target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch

   1 From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Fri, 1 Jun 2018 02:41:15 +0200
   4 Subject: [PATCH] arm: ox820: remove left-overs
   5
   6 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
   7 ---
   8  drivers/clk/clk-oxnas.c                  |  2 --
   9  include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
  10  2 files changed, 14 insertions(+), 20 deletions(-)
  11
  12 diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
  13 index e51e0023fc6e..da6af71649de 100644
  14 --- a/drivers/clk/clk-oxnas.c
  15 +++ b/drivers/clk/clk-oxnas.c
  16 @@ -40,8 +40,6 @@ struct oxnas_stdclk_data {
  17         struct clk_hw_onecell_data *onecell_data;
  18         struct clk_oxnas_gate **gates;
  19         unsigned int ngates;
  20 -       struct clk_oxnas_pll **plls;
  21 -       unsigned int nplls;
  22  };
  23
  24  /* Regmap offsets */
  25 diff --git a/include/dt-bindings/clock/oxsemi,ox820.h b/include/dt-bindings/clock/oxsemi,ox820.h
  26 index f661ecc8d760..35b44ca1b104 100644
  27 --- a/include/dt-bindings/clock/oxsemi,ox820.h
  28 +++ b/include/dt-bindings/clock/oxsemi,ox820.h
  29 @@ -17,24 +17,20 @@
  30  #ifndef DT_CLOCK_OXSEMI_OX820_H
  31  #define DT_CLOCK_OXSEMI_OX820_H
  32
  33 -/* PLLs */
  34 -#define CLK_820_PLLA           0
  35 -#define CLK_820_PLLB           1
  36 -
  37  /* Gate Clocks */
  38 -#define CLK_820_LEON           2
  39 -#define CLK_820_DMA_SGDMA      3
  40 -#define CLK_820_CIPHER         4
  41 -#define CLK_820_SD             5
  42 -#define CLK_820_SATA           6
  43 -#define CLK_820_AUDIO          7
  44 -#define CLK_820_USBMPH         8
  45 -#define CLK_820_ETHA           9
  46 -#define CLK_820_PCIEA          10
  47 -#define CLK_820_NAND           11
  48 -#define CLK_820_PCIEB          12
  49 -#define CLK_820_ETHB           13
  50 -#define CLK_820_REF600         14
  51 -#define CLK_820_USBDEV         15
  52 +#define CLK_820_LEON           0
  53 +#define CLK_820_DMA_SGDMA      1
  54 +#define CLK_820_CIPHER         2
  55 +#define CLK_820_SD             3
  56 +#define CLK_820_SATA           4
  57 +#define CLK_820_AUDIO          5
  58 +#define CLK_820_USBMPH         6
  59 +#define CLK_820_ETHA           7
  60 +#define CLK_820_PCIEA          8
  61 +#define CLK_820_NAND           9
  62 +#define CLK_820_PCIEB          10
  63 +#define CLK_820_ETHB           11
  64 +#define CLK_820_REF600         12
  65 +#define CLK_820_USBDEV         13
  66
  67  #endif /* DT_CLOCK_OXSEMI_OX820_H */
  68 --
  69 2.17.1
  70