target/linux/mediatek/patches-5.4/0600-4-6-net-dsa-mt7530-Add-the-support-of-MT7531-switch.patch

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  50 From: Landen Chao <landen.chao@mediatek.com>
  51 To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
  52  <vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
  53  <robh+dt@kernel.org>, <mark.rutland@arm.com>
  54 CC: <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,
  55  <linux-kernel@vger.kernel.org>,
  56  <linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,
  57  <sean.wang@mediatek.com>, <opensource@vdorst.com>,
  58  <frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>
  59 Subject: [PATCH net-next 4/6] net: dsa: mt7530: Add the support of MT7531
  60  switch
  61 Date: Tue, 10 Dec 2019 16:14:40 +0800
  62 Message-ID: <6d608dd024edc90b09ba4fe35417b693847f973c.1575914275.git.landen.chao@mediatek.com>
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  72
  73 Add new support for MT7531:
  74
  75 MT7531 is the next generation of MT7530. It is also a 7-ports switch with
  76 5 giga embedded phys, 2 cpu ports, and the same MAC logic of MT7530. Cpu
  77 port 6 only supports HSGMII interface. Cpu port 5 supports either RGMII
  78 or HSGMII in different HW sku. Due to HSGMII interface support, pll, and
  79 pad setting are different from MT7530. This patch adds different initial
  80 setting of MT7531.
  81
  82 Signed-off-by: Landen Chao <landen.chao@mediatek.com>
  83 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  84 ---
  85  drivers/net/dsa/Kconfig  |   6 +-
  86  drivers/net/dsa/mt7530.c | 643 ++++++++++++++++++++++++++++++++++++++-
  87  drivers/net/dsa/mt7530.h | 144 +++++++++
  88  3 files changed, 784 insertions(+), 9 deletions(-)
  89
  90 Index: linux-5.4.43/drivers/net/dsa/Kconfig
  91 ===================================================================
  92 --- linux-5.4.43.orig/drivers/net/dsa/Kconfig
  93 +++ linux-5.4.43/drivers/net/dsa/Kconfig
  94 @@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
  95           the xrx200 / VR9 SoC.
  96
  97  config NET_DSA_MT7530
  98 -       tristate "MediaTek MT7530 and MT7621 Ethernet switch support"
  99 +       tristate "MediaTek MT753x and MT7621 Ethernet switch support"
 100         depends on NET_DSA
 101         select NET_DSA_TAG_MTK
 102         ---help---
 103 -         This enables support for the MediaTek MT7530 and MT7621 Ethernet
 104 -         switch chip.
 105 +         This enables support for the MediaTek MT7530, MT7531 and MT7621
 106 +         Ethernet switch chip.
 107
 108  config NET_DSA_MV88E6060
 109         tristate "Marvell 88E6060 ethernet switch chip support"
 110 Index: linux-5.4.43/drivers/net/dsa/mt7530.c
 111 ===================================================================
 112 --- linux-5.4.43.orig/drivers/net/dsa/mt7530.c
 113 +++ linux-5.4.43/drivers/net/dsa/mt7530.c
 114 @@ -234,6 +234,12 @@ mt7530_write(struct mt7530_priv *priv, u
 115  }
 116
 117  static u32
 118 +_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
 119 +{
 120 +       return mt7530_mii_read(p->priv, p->reg);
 121 +}
 122 +
 123 +static u32
 124  _mt7530_read(struct mt7530_dummy_poll *p)
 125  {
 126         struct mii_bus          *bus = p->priv->bus;
 127 @@ -287,6 +293,102 @@ mt7530_clear(struct mt7530_priv *priv, u
 128  }
 129
 130  static int
 131 +mt7531_ind_mmd_phy_read(struct mt7530_priv *priv, int port, int devad,
 132 +                       int regnum)
 133 +{
 134 +       struct mii_bus *bus = priv->bus;
 135 +       struct mt7530_dummy_poll p;
 136 +       u32 reg, val;
 137 +       int ret;
 138 +
 139 +       INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 140 +
 141 +       mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 142 +
 143 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 144 +                                !(val & PHY_ACS_ST), 20, 100000);
 145 +       if (ret < 0) {
 146 +               dev_err(priv->dev, "poll timeout\n");
 147 +               goto out;
 148 +       }
 149 +
 150 +       reg = MDIO_CL45_ADDR | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad) |
 151 +             regnum;
 152 +       mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
 153 +
 154 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 155 +                                !(val & PHY_ACS_ST), 20, 100000);
 156 +       if (ret < 0) {
 157 +               dev_err(priv->dev, "poll timeout\n");
 158 +               goto out;
 159 +       }
 160 +
 161 +       reg = MDIO_CL45_READ | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad);
 162 +       mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
 163 +
 164 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 165 +                                !(val & PHY_ACS_ST), 20, 100000);
 166 +       if (ret < 0) {
 167 +               dev_err(priv->dev, "poll timeout\n");
 168 +               goto out;
 169 +       }
 170 +
 171 +       ret = val & MDIO_RW_DATA_MASK;
 172 +out:
 173 +       mutex_unlock(&bus->mdio_lock);
 174 +
 175 +       return ret;
 176 +}
 177 +
 178 +static int
 179 +mt7531_ind_mmd_phy_write(struct mt7530_priv *priv, int port, int devad,
 180 +                        int regnum, u32 data)
 181 +{
 182 +       struct mii_bus *bus = priv->bus;
 183 +       struct mt7530_dummy_poll p;
 184 +       u32 val, reg;
 185 +       int ret;
 186 +
 187 +       INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 188 +
 189 +       mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 190 +
 191 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 192 +                                !(val & PHY_ACS_ST), 20, 100000);
 193 +       if (ret < 0) {
 194 +               dev_err(priv->dev, "poll timeout\n");
 195 +               goto out;
 196 +       }
 197 +
 198 +       reg = MDIO_CL45_ADDR | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad) |
 199 +             regnum;
 200 +       mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
 201 +
 202 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 203 +                                !(val & PHY_ACS_ST), 20, 100000);
 204 +       if (ret < 0) {
 205 +               dev_err(priv->dev, "poll timeout\n");
 206 +               goto out;
 207 +       }
 208 +
 209 +       reg = MDIO_CL45_WRITE | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad) |
 210 +             data;
 211 +       mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
 212 +
 213 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 214 +                                !(val & PHY_ACS_ST), 20, 100000);
 215 +       if (ret < 0) {
 216 +               dev_err(priv->dev, "poll timeout\n");
 217 +               goto out;
 218 +       }
 219 +
 220 +out:
 221 +       mutex_unlock(&bus->mdio_lock);
 222 +
 223 +       return ret;
 224 +}
 225 +
 226 +static int
 227  mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
 228  {
 229         u32 val;
 230 @@ -516,6 +618,83 @@ static int mt7530_phy_write(struct dsa_s
 231         return mdiobus_write_nested(priv->bus, port, regnum, val);
 232  }
 233
 234 +static int
 235 +mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
 236 +{
 237 +       struct mt7530_priv *priv = ds->priv;
 238 +       struct mii_bus *bus = priv->bus;
 239 +       struct mt7530_dummy_poll p;
 240 +       int ret;
 241 +       u32 val;
 242 +
 243 +       INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 244 +
 245 +       mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 246 +
 247 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 248 +                                !(val & PHY_ACS_ST), 20, 100000);
 249 +       if (ret < 0) {
 250 +               dev_err(priv->dev, "poll timeout\n");
 251 +               goto out;
 252 +       }
 253 +
 254 +       val = MDIO_CL22_READ | MDIO_PHY_ADDR(port) | MDIO_REG_ADDR(regnum);
 255 +
 256 +       mt7530_mii_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
 257 +
 258 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 259 +                                !(val & PHY_ACS_ST), 20, 100000);
 260 +       if (ret < 0) {
 261 +               dev_err(priv->dev, "poll timeout\n");
 262 +               goto out;
 263 +       }
 264 +
 265 +       ret = val & MDIO_RW_DATA_MASK;
 266 +out:
 267 +       mutex_unlock(&bus->mdio_lock);
 268 +
 269 +       return ret;
 270 +}
 271 +
 272 +static int
 273 +mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
 274 +                    u16 data)
 275 +{
 276 +       struct mt7530_priv *priv = ds->priv;
 277 +       struct mii_bus *bus = priv->bus;
 278 +       struct mt7530_dummy_poll p;
 279 +       int ret;
 280 +       u32 reg;
 281 +
 282 +       INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 283 +
 284 +       mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 285 +
 286 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
 287 +                                !(reg & PHY_ACS_ST), 20, 100000);
 288 +       if (ret < 0) {
 289 +               dev_err(priv->dev, "poll timeout\n");
 290 +               goto out;
 291 +       }
 292 +
 293 +       reg = MDIO_CL22_WRITE | MDIO_PHY_ADDR(port) | MDIO_REG_ADDR(regnum) |
 294 +             data;
 295 +
 296 +       mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
 297 +
 298 +       ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
 299 +                                !(reg & PHY_ACS_ST), 20, 100000);
 300 +       if (ret < 0) {
 301 +               dev_err(priv->dev, "poll timeout\n");
 302 +               goto out;
 303 +       }
 304 +
 305 +out:
 306 +       mutex_unlock(&bus->mdio_lock);
 307 +
 308 +       return ret;
 309 +}
 310 +
 311  static void
 312  mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 313                    uint8_t *data)
 314 @@ -1355,6 +1534,86 @@ mt7530_setup(struct dsa_switch *ds)
 315         return 0;
 316  }
 317
 318 +static int mt7531_setup(struct dsa_switch *ds)
 319 +{
 320 +       struct mt7530_priv *priv = ds->priv;
 321 +       struct mt7530_dummy_poll p;
 322 +       u32 val, id;
 323 +       int ret, i;
 324 +
 325 +       /* Reset whole chip through gpio pin or memory-mapped registers for
 326 +        * different type of hardware
 327 +        */
 328 +       if (priv->mcm) {
 329 +               reset_control_assert(priv->rstc);
 330 +               usleep_range(1000, 1100);
 331 +               reset_control_deassert(priv->rstc);
 332 +       } else {
 333 +               gpiod_set_value_cansleep(priv->reset, 0);
 334 +               usleep_range(1000, 1100);
 335 +               gpiod_set_value_cansleep(priv->reset, 1);
 336 +       }
 337 +
 338 +       /* Waiting for MT7530 got to stable */
 339 +       INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
 340 +       ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
 341 +                                20, 1000000);
 342 +       if (ret < 0) {
 343 +               dev_err(priv->dev, "reset timeout\n");
 344 +               return ret;
 345 +       }
 346 +
 347 +       id = mt7530_read(priv, MT7531_CREV);
 348 +       id >>= CHIP_NAME_SHIFT;
 349 +
 350 +       if (id != MT7531_ID) {
 351 +               dev_err(priv->dev, "chip %x can't be supported\n", id);
 352 +               return -ENODEV;
 353 +       }
 354 +
 355 +       /* Reset the switch through internal reset */
 356 +       mt7530_write(priv, MT7530_SYS_CTRL,
 357 +                    SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
 358 +                    SYS_CTRL_REG_RST);
 359 +
 360 +       priv->p6_interface = PHY_INTERFACE_MODE_NA;
 361 +
 362 +       /* Enable PHY power, since phy_device has not yet been created
 363 +        * provided for phy_[read,write]_mmd_indirect is called, we provide
 364 +        * our own mt7531_ind_mmd_phy_[read,write] to complete this
 365 +        * function.
 366 +        */
 367 +       val = mt7531_ind_mmd_phy_read(priv, 0, PHY_DEV1F,
 368 +                                     MT7531_PHY_DEV1F_REG_403);
 369 +       val |= MT7531_PHY_EN_BYPASS_MODE;
 370 +       val &= ~MT7531_PHY_POWER_OFF;
 371 +       mt7531_ind_mmd_phy_write(priv, 0, PHY_DEV1F,
 372 +                                MT7531_PHY_DEV1F_REG_403, val);
 373 +
 374 +       /* Enable and reset MIB counters */
 375 +       mt7530_mib_reset(ds);
 376 +
 377 +       mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
 378 +
 379 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
 380 +               /* Disable forwarding by default on all ports */
 381 +               mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
 382 +                          PCR_MATRIX_CLR);
 383 +
 384 +               if (dsa_is_cpu_port(ds, i))
 385 +                       mt7530_cpu_port_enable(priv, i);
 386 +               else
 387 +                       mt7530_port_disable(ds, i);
 388 +       }
 389 +
 390 +       /* Flush the FDB table */
 391 +       ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
 392 +       if (ret < 0)
 393 +               return ret;
 394 +
 395 +       return 0;
 396 +}
 397 +
 398  static bool mt7530_phy_supported(struct dsa_switch *ds, int port,
 399                                  const struct phylink_link_state *state)
 400  {
 401 @@ -1392,6 +1651,49 @@ unsupported:
 402         return false;
 403  }
 404
 405 +static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
 406 +{
 407 +       u32 val;
 408 +
 409 +       val = mt7530_read(priv, MT7531_TOP_SIG_SR);
 410 +       return ((val & PAD_DUAL_SGMII_EN) != 0);
 411 +}
 412 +
 413 +static bool mt7531_phy_supported(struct dsa_switch *ds, int port,
 414 +                                const struct phylink_link_state *state)
 415 +{
 416 +       struct mt7530_priv *priv = ds->priv;
 417 +
 418 +       switch (port) {
 419 +       case 0: /* Internal phy */
 420 +       case 1:
 421 +       case 2:
 422 +       case 3:
 423 +       case 4:
 424 +               if (state->interface != PHY_INTERFACE_MODE_GMII)
 425 +                       goto unsupported;
 426 +               break;
 427 +       case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
 428 +               if (!mt7531_dual_sgmii_supported(priv))
 429 +                       return phy_interface_mode_is_rgmii(state->interface);
 430 +               /* fall through */
 431 +       case 6: /* 1st cpu port supports sgmii/8023z only */
 432 +               if (state->interface != PHY_INTERFACE_MODE_SGMII &&
 433 +                   !phy_interface_mode_is_8023z(state->interface))
 434 +                       goto unsupported;
 435 +               break;
 436 +       default:
 437 +               dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
 438 +                       port);
 439 +               goto unsupported;
 440 +       }
 441 +
 442 +       return true;
 443 +
 444 +unsupported:
 445 +       return false;
 446 +}
 447 +
 448  static bool mt753x_phy_supported(struct dsa_switch *ds, int port,
 449                                  const struct phylink_link_state *state)
 450  {
 451 @@ -1413,7 +1715,144 @@ mt7530_pad_setup(struct dsa_switch *ds,
 452                  * host which must be placed after the setup on the
 453                  * device side is all finished.
 454                  */
 455 -               mt7623_pad_clk_setup(ds);
 456 +               //mt7623_pad_clk_setup(ds);
 457 +       }
 458 +
 459 +       return 0;
 460 +}
 461 +
 462 +static int
 463 +mt7531_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
 464 +{
 465 +       struct mt7530_priv *priv = ds->priv;
 466 +       u32 xtal, val;
 467 +
 468 +       if (mt7531_dual_sgmii_supported(priv))
 469 +               return 0;
 470 +
 471 +       xtal = mt7530_read(priv, MT7531_HWTRAP) & HWTRAP_XTAL_FSEL_MASK;
 472 +
 473 +       switch (xtal) {
 474 +       case HWTRAP_XTAL_FSEL_25MHZ:
 475 +               /* Step 1 : Disable MT7531 COREPLL */
 476 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 477 +               val &= ~EN_COREPLL;
 478 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 479 +
 480 +               /* Step 2: switch to XTAL output */
 481 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 482 +               val |= SW_CLKSW;
 483 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 484 +
 485 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 486 +               val &= ~RG_COREPLL_EN;
 487 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 488 +
 489 +               /* Step 3: disable PLLGP and enable program PLLGP */
 490 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 491 +               val |= SW_PLLGP;
 492 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 493 +
 494 +               /* Step 4: program COREPLL output frequency to 500MHz */
 495 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 496 +               val &= ~RG_COREPLL_POSDIV_M;
 497 +               val |= 2 << RG_COREPLL_POSDIV_S;
 498 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 499 +               usleep_range(25, 35);
 500 +
 501 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 502 +               val &= ~RG_COREPLL_SDM_PCW_M;
 503 +               val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
 504 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 505 +
 506 +               /* Set feedback divide ratio update signal to high */
 507 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 508 +               val |= RG_COREPLL_SDM_PCW_CHG;
 509 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 510 +               /* Wait for at least 16 XTAL clocks */
 511 +               usleep_range(10, 20);
 512 +
 513 +               /* Step 5: set feedback divide ratio update signal to low */
 514 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 515 +               val &= ~RG_COREPLL_SDM_PCW_CHG;
 516 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 517 +
 518 +               /* Enable 325M clock for SGMII */
 519 +               mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
 520 +
 521 +               /* Enable 250SSC clock for RGMII */
 522 +               mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
 523 +
 524 +               /* Step 6: Enable MT7531 PLL */
 525 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 526 +               val |= RG_COREPLL_EN;
 527 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 528 +
 529 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 530 +               val |= EN_COREPLL;
 531 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 532 +               usleep_range(25, 35);
 533 +               break;
 534 +       case HWTRAP_XTAL_FSEL_40MHZ:
 535 +               /* Step 1 : Disable MT7531 COREPLL */
 536 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 537 +               val &= ~EN_COREPLL;
 538 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 539 +
 540 +               /* Step 2: switch to XTAL output */
 541 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 542 +               val |= SW_CLKSW;
 543 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 544 +
 545 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 546 +               val &= ~RG_COREPLL_EN;
 547 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 548 +
 549 +               /* Step 3: disable PLLGP and enable program PLLGP */
 550 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 551 +               val |= SW_PLLGP;
 552 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 553 +
 554 +               /* Step 4: program COREPLL output frequency to 500MHz */
 555 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 556 +               val &= ~RG_COREPLL_POSDIV_M;
 557 +               val |= 2 << RG_COREPLL_POSDIV_S;
 558 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 559 +               usleep_range(25, 35);
 560 +
 561 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 562 +               val &= ~RG_COREPLL_SDM_PCW_M;
 563 +               val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
 564 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 565 +
 566 +               /* Set feedback divide ratio update signal to high */
 567 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 568 +               val |= RG_COREPLL_SDM_PCW_CHG;
 569 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 570 +               /* Wait for at least 16 XTAL clocks */
 571 +               usleep_range(10, 20);
 572 +
 573 +               /* Step 5: set feedback divide ratio update signal to low */
 574 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 575 +               val &= ~RG_COREPLL_SDM_PCW_CHG;
 576 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 577 +
 578 +               /* Enable 325M clock for SGMII */
 579 +               mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
 580 +
 581 +               /* Enable 250SSC clock for RGMII */
 582 +               mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
 583 +
 584 +               /* Step 6: Enable MT7531 PLL */
 585 +               val = mt7530_read(priv, MT7531_PLLGP_CR0);
 586 +               val |= RG_COREPLL_EN;
 587 +               mt7530_write(priv, MT7531_PLLGP_CR0, val);
 588 +
 589 +               val = mt7530_read(priv, MT7531_PLLGP_EN);
 590 +               val |= EN_COREPLL;
 591 +               mt7530_write(priv, MT7531_PLLGP_EN, val);
 592 +               usleep_range(25, 35);
 593 +               break;
 594         }
 595
 596         return 0;
 597 @@ -1442,6 +1881,149 @@ mt7530_mac_setup(struct dsa_switch *ds,
 598         return 0;
 599  }
 600
 601 +static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port)
 602 +{
 603 +       u32 val;
 604 +
 605 +       if (port != 5) {
 606 +               dev_err(priv->dev, "RGMII mode is not available for port %d\n",
 607 +                       port);
 608 +               return -EINVAL;
 609 +       }
 610 +
 611 +       val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
 612 +       val |= GP_CLK_EN;
 613 +       val &= ~GP_MODE_MASK;
 614 +       val |= GP_MODE(MT7531_GP_MODE_RGMII);
 615 +       val |= TXCLK_NO_REVERSE;
 616 +       val |= RXCLK_NO_DELAY;
 617 +       val &= ~CLK_SKEW_IN_MASK;
 618 +       val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
 619 +       val &= ~CLK_SKEW_OUT_MASK;
 620 +       val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
 621 +       mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
 622 +
 623 +       return 0;
 624 +}
 625 +
 626 +static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
 627 +                                        const struct phylink_link_state *state)
 628 +{
 629 +       u32 val;
 630 +
 631 +       if (port != 5 && port != 6)
 632 +               return -EINVAL;
 633 +
 634 +       val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
 635 +       val |= MT7531_SGMII_PHYA_PWD;
 636 +       mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
 637 +
 638 +       val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
 639 +       val &= ~MT7531_RG_TPHY_SPEED_MASK;
 640 +       if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
 641 +               val |= MT7531_RG_TPHY_SPEED_3_125G;
 642 +       mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
 643 +
 644 +       val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
 645 +       val &= ~MT7531_SGMII_AN_ENABLE;
 646 +       mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
 647 +
 648 +       val = mt7530_read(priv, MT7531_SGMII_MODE(port));
 649 +       val &= ~MT7531_SGMII_IF_MODE_MASK;
 650 +
 651 +       switch (state->speed) {
 652 +       case SPEED_10:
 653 +               val |= MT7531_SGMII_FORCE_SPEED_10;
 654 +               break;
 655 +       case SPEED_100:
 656 +               val |= MT7531_SGMII_FORCE_SPEED_100;
 657 +               break;
 658 +       case SPEED_2500:
 659 +       case SPEED_1000:
 660 +               val |= MT7531_SGMII_FORCE_SPEED_1000;
 661 +               break;
 662 +       };
 663 +
 664 +       val &= ~MT7531_SGMII_FORCE_DUPLEX;
 665 +       /* For sgmii force mode, 0 is full duplex and 1 is half duplex */
 666 +       if (state->duplex == DUPLEX_HALF)
 667 +               val |= MT7531_SGMII_FORCE_DUPLEX;
 668 +
 669 +       mt7530_write(priv, MT7531_SGMII_MODE(port), val);
 670 +
 671 +       val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
 672 +       val &= ~MT7531_SGMII_PHYA_PWD;
 673 +       mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
 674 +
 675 +       return 0;
 676 +}
 677 +
 678 +static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
 679 +                                     const struct phylink_link_state *state)
 680 +{
 681 +       u32 val;
 682 +
 683 +       if (port != 5 && port != 6)
 684 +               return -EINVAL;
 685 +
 686 +       val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
 687 +       val |= MT7531_SGMII_PHYA_PWD;
 688 +       mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
 689 +
 690 +       switch (state->speed) {
 691 +       case SPEED_10:
 692 +       case SPEED_100:
 693 +       case SPEED_1000:
 694 +               val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
 695 +               val &= ~MT7531_RG_TPHY_SPEED_MASK;
 696 +               mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
 697 +               break;
 698 +       default:
 699 +               dev_info(priv->dev, "invalid SGMII speed idx %d for port %d\n",
 700 +                        state->speed, port);
 701 +
 702 +               return -EINVAL;
 703 +       }
 704 +
 705 +       val = mt7530_read(priv, MT7531_SGMII_MODE(port));
 706 +       val |= MT7531_SGMII_REMOTE_FAULT_DIS;
 707 +       mt7530_write(priv, MT7531_SGMII_MODE(port), val);
 708 +
 709 +       val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
 710 +       val |= MT7531_SGMII_AN_RESTART;
 711 +       mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
 712 +
 713 +       val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
 714 +       val &= ~MT7531_SGMII_PHYA_PWD;
 715 +       mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
 716 +
 717 +       return 0;
 718 +}
 719 +
 720 +static int
 721 +mt7531_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,
 722 +                const struct phylink_link_state *state)
 723 +{
 724 +       struct mt7530_priv *priv = ds->priv;
 725 +
 726 +       if (port < 5 || port >= MT7530_NUM_PORTS) {
 727 +               dev_err(priv->dev, "port %d is not a MAC port\n", port);
 728 +               return -EINVAL;
 729 +       }
 730 +
 731 +       switch (state->interface) {
 732 +       case PHY_INTERFACE_MODE_RGMII:
 733 +               return mt7531_rgmii_setup(priv, port);
 734 +       case PHY_INTERFACE_MODE_1000BASEX:
 735 +       case PHY_INTERFACE_MODE_2500BASEX:
 736 +               return mt7531_sgmii_setup_mode_force(priv, port, state);
 737 +       case PHY_INTERFACE_MODE_SGMII:
 738 +               return mt7531_sgmii_setup_mode_an(priv, port, state);
 739 +       default:
 740 +               return -EINVAL;
 741 +       }
 742 +}
 743 +
 744  static int mt753x_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,
 745                             const struct phylink_link_state *state)
 746  {
 747 @@ -1473,22 +2055,23 @@ static void mt753x_phylink_mac_config(st
 748                 if (priv->p5_interface == state->interface)
 749                         break;
 750                 if (mt753x_mac_setup(ds, port, mode, state) < 0)
 751 -                       goto unsupported;
 752 +                       break;
 753 +               priv->p5_interface = state->interface;
 754                 break;
 755         case 6: /* 1st cpu port */
 756                 if (priv->p6_interface == state->interface)
 757                         break;
 758                 mt753x_pad_setup(ds, state);
 759                 if (mt753x_mac_setup(ds, port, mode, state) < 0)
 760 -                       goto unsupported;
 761 +                       break;
 762                 priv->p6_interface = state->interface;
 763                 break;
 764         default:
 765 -               dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
 766                 return;
 767         }
 768
 769 -       if (phylink_autoneg_inband(mode)) {
 770 +       if (phylink_autoneg_inband(mode) &&
 771 +           state->interface != PHY_INTERFACE_MODE_SGMII) {
 772                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
 773                         __func__);
 774                 return;
 775 @@ -1499,13 +2082,15 @@ static void mt753x_phylink_mac_config(st
 776         mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
 777                      PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
 778         mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
 779 -                  PMCR_BACKPR_EN | PMCR_FORCE_MODE;
 780 +                  PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id) |
 781 +                  PMCR_FORCE_LNK;
 782
 783         /* Are we connected to external phy */
 784         if (port == 5 && dsa_is_user_port(ds, 5))
 785                 mcr_new |= PMCR_EXT_PHY;
 786
 787         switch (state->speed) {
 788 +       case SPEED_2500:
 789         case SPEED_1000:
 790                 mcr_new |= PMCR_FORCE_SPEED_1000;
 791                 if (priv->eee_enable & BIT(port))
 792 @@ -1529,6 +2114,27 @@ static void mt753x_phylink_mac_config(st
 793                 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
 794  }
 795
 796 +void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
 797 +{
 798 +       struct mt7530_priv *priv = ds->priv;
 799 +       u32 val;
 800 +
 801 +       val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
 802 +       val |= MT7531_SGMII_AN_RESTART;
 803 +       mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
 804 +}
 805 +
 806 +static void
 807 +mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
 808 +{
 809 +       struct mt7530_priv *priv = ds->priv;
 810 +
 811 +       if (!priv->info->port_an_restart)
 812 +               return;
 813 +
 814 +       priv->info->port_an_restart(ds, port);
 815 +}
 816 +
 817  static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
 818                                          unsigned int mode,
 819                                          phy_interface_t interface)
 820 @@ -1563,9 +2169,20 @@ static void mt753x_phylink_validate(stru
 821         phylink_set_port_modes(mask);
 822         phylink_set(mask, Autoneg);
 823
 824 -       if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
 825 +       switch (state->interface) {
 826 +       case PHY_INTERFACE_MODE_TRGMII:
 827                 phylink_set(mask, 1000baseT_Full);
 828 -       } else {
 829 +               break;
 830 +       case PHY_INTERFACE_MODE_1000BASEX:
 831 +       case PHY_INTERFACE_MODE_2500BASEX:
 832 +               phylink_set(mask, 1000baseX_Full);
 833 +               phylink_set(mask, 2500baseX_Full);
 834 +               break;
 835 +       case PHY_INTERFACE_MODE_SGMII:
 836 +               phylink_set(mask, 1000baseT_Full);
 837 +               phylink_set(mask, 1000baseX_Full);
 838 +               /* fall through */
 839 +       default:
 840                 phylink_set(mask, 10baseT_Half);
 841                 phylink_set(mask, 10baseT_Full);
 842                 phylink_set(mask, 100baseT_Half);
 843 @@ -1577,6 +2194,7 @@ static void mt753x_phylink_validate(stru
 844                         if (port == 5)
 845                                 phylink_set(mask, 1000baseX_Full);
 846                 }
 847 +               break;
 848         }
 849
 850         phylink_set(mask, Pause);
 851 @@ -1721,8 +2339,9 @@ static const struct dsa_switch_ops mt753
 852         .port_mirror_add        = mt7530_port_mirror_add,
 853         .port_mirror_del        = mt7530_port_mirror_del,
 854         .phylink_validate       = mt753x_phylink_validate,
 855 -       .phylink_mac_link_state = mt7530_phylink_mac_link_state,
 856 +       .phylink_mac_link_state = mt7530_phylink_mac_link_state,
 857         .phylink_mac_config     = mt753x_phylink_mac_config,
 858 +       .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
 859         .phylink_mac_link_down  = mt7530_phylink_mac_link_down,
 860         .phylink_mac_link_up    = mt7530_phylink_mac_link_up,
 861         .get_mac_eee            = mt7530_get_mac_eee,
 862 @@ -1748,11 +2367,22 @@ static const struct mt753x_info mt753x_t
 863                 .pad_setup = mt7530_pad_setup,
 864                 .mac_setup = mt7530_mac_setup,
 865         },
 866 +       [ID_MT7531] = {
 867 +               .id = ID_MT7531,
 868 +               .setup = mt7531_setup,
 869 +               .phy_read = mt7531_ind_phy_read,
 870 +               .phy_write = mt7531_ind_phy_write,
 871 +               .phy_supported = mt7531_phy_supported,
 872 +               .pad_setup = mt7531_pad_setup,
 873 +               .mac_setup = mt7531_mac_setup,
 874 +               .port_an_restart = mt7531_sgmii_restart_an,
 875 +       },
 876  };
 877
 878   static const struct of_device_id mt7530_of_match[] = {
 879         { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
 880         { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
 881 +       { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
 882         { /* sentinel */ },
 883  };
 884  MODULE_DEVICE_TABLE(of, mt7530_of_match);
 885 Index: linux-5.4.43/drivers/net/dsa/mt7530.h
 886 ===================================================================
 887 --- linux-5.4.43.orig/drivers/net/dsa/mt7530.h
 888 +++ linux-5.4.43/drivers/net/dsa/mt7530.h
 889 @@ -14,6 +14,7 @@
 890  enum mt753x_id {
 891         ID_MT7530 = 0,
 892         ID_MT7621 = 1,
 893 +       ID_MT7531 = 2,
 894  };
 895
 896  #define        NUM_TRGMII_CTRL                 5
 897 @@ -222,6 +223,19 @@ enum mt7530_vlan_port_attr {
 898  #define  PMCR_FORCE_LNK                        BIT(0)
 899  #define  PMCR_SPEED_MASK               (PMCR_FORCE_SPEED_100 | \
 900                                          PMCR_FORCE_SPEED_1000)
 901 +#define  MT7531_FORCE_LNK              BIT(31)
 902 +#define  MT7531_FORCE_SPD              BIT(30)
 903 +#define  MT7531_FORCE_DPX              BIT(29)
 904 +#define  MT7531_FORCE_RX_FC            BIT(28)
 905 +#define  MT7531_FORCE_TX_FC            BIT(27)
 906 +#define  MT7531_FORCE_MODE             (MT7531_FORCE_LNK | \
 907 +                                        MT7531_FORCE_SPD | \
 908 +                                        MT7531_FORCE_DPX | \
 909 +                                        MT7531_FORCE_RX_FC | \
 910 +                                        MT7531_FORCE_TX_FC)
 911 +#define  PMCR_FORCE_MODE_ID(id)                (((id) == ID_MT7531) ? \
 912 +                                        MT7531_FORCE_MODE : \
 913 +                                        PMCR_FORCE_MODE)
 914
 915  #define MT7530_PMSR_P(x)               (0x3008 + (x) * 0x100)
 916  #define  PMSR_EEE1G                    BIT(7)
 917 @@ -258,12 +272,111 @@ enum mt7530_vlan_port_attr {
 918                                          CCR_RX_OCT_CNT_BAD | \
 919                                          CCR_TX_OCT_CNT_GOOD | \
 920                                          CCR_TX_OCT_CNT_BAD)
 921 +
 922 +/* SGMII registers */
 923 +#define MT7531_SGMII_REG_BASE          0x5000
 924 +#define MT7531_SGMII_REG(p, r)         (MT7531_SGMII_REG_BASE + \
 925 +                                       ((p) - 5) * 0x1000 + (r))
 926 +
 927 +/* SGMII PCS_CONTROL_1 */
 928 +#define MT7531_PCS_CONTROL_1(p)                MT7531_SGMII_REG(p, 0x00)
 929 +#define  MT7531_SGMII_LINK_STATUS      BIT(18)
 930 +#define  MT7531_SGMII_AN_ENABLE                BIT(12)
 931 +#define  MT7531_SGMII_AN_RESTART       BIT(9)
 932 +
 933 +/* Fields of SGMII_MODE */
 934 +#define MT7531_SGMII_MODE(p)           MT7531_SGMII_REG(p, 0x20)
 935 +#define  MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
 936 +#define  MT7531_SGMII_FORCE_DUPLEX     BIT(4)
 937 +#define  MT7531_SGMII_IF_MODE_MASK     GENMASK(5, 1)
 938 +#define  MT7531_SGMII_FORCE_SPEED_10   0x0
 939 +#define  MT7531_SGMII_FORCE_SPEED_100  BIT(2)
 940 +#define  MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
 941 +
 942 +/* Fields of QPHY_PWR_STATE_CTRL */
 943 +#define MT7531_QPHY_PWR_STATE_CTRL(p)  MT7531_SGMII_REG(p, 0xe8)
 944 +#define  MT7531_SGMII_PHYA_PWD         BIT(4)
 945 +
 946 +/* Values of SGMII SPEED */
 947 +#define MT7531_PHYA_CTRL_SIGNAL3(p)    MT7531_SGMII_REG(p, 0x128)
 948 +#define  MT7531_RG_TPHY_SPEED_MASK     (BIT(2) | BIT(3))
 949 +#define  MT7531_RG_TPHY_SPEED_1_25G    0x0
 950 +#define  MT7531_RG_TPHY_SPEED_3_125G   BIT(2)
 951 +
 952  /* Register for system reset */
 953  #define MT7530_SYS_CTRL                        0x7000
 954  #define  SYS_CTRL_PHY_RST              BIT(2)
 955  #define  SYS_CTRL_SW_RST               BIT(1)
 956  #define  SYS_CTRL_REG_RST              BIT(0)
 957
 958 +/* Register for PHY Indirect Access Control */
 959 +#define MT7531_PHY_IAC                 0x701C
 960 +#define  PHY_ACS_ST                    BIT(31)
 961 +#define  MDIO_REG_ADDR_MASK            (0x1f << 25)
 962 +#define  MDIO_PHY_ADDR_MASK            (0x1f << 20)
 963 +#define  MDIO_CMD_MASK                 (0x3 << 18)
 964 +#define  MDIO_ST_MASK                  (0x3 << 16)
 965 +#define  MDIO_RW_DATA_MASK             (0xffff)
 966 +#define  MDIO_REG_ADDR(x)              (((x) & 0x1f) << 25)
 967 +#define  MDIO_DEV_ADDR(x)              (((x) & 0x1f) << 25)
 968 +#define  MDIO_PHY_ADDR(x)              (((x) & 0x1f) << 20)
 969 +#define  MDIO_CMD(x)                   (((x) & 0x3) << 18)
 970 +#define  MDIO_ST(x)                    (((x) & 0x3) << 16)
 971 +
 972 +enum mt7531_phy_iac_cmd {
 973 +       MT7531_MDIO_ADDR = 0,
 974 +       MT7531_MDIO_WRITE = 1,
 975 +       MT7531_MDIO_READ = 2,
 976 +       MT7531_MDIO_READ_CL45 = 3,
 977 +};
 978 +
 979 +/* MDIO_ST: MDIO start field */
 980 +enum mt7531_mdio_st {
 981 +       MT7531_MDIO_ST_CL45 = 0,
 982 +       MT7531_MDIO_ST_CL22 = 1,
 983 +};
 984 +
 985 +#define  MDIO_CL22_READ                        (MDIO_ST(MT7531_MDIO_ST_CL22) | \
 986 +                                        MDIO_CMD(MT7531_MDIO_READ))
 987 +#define  MDIO_CL22_WRITE               (MDIO_ST(MT7531_MDIO_ST_CL22) | \
 988 +                                        MDIO_CMD(MT7531_MDIO_WRITE))
 989 +#define  MDIO_CL45_ADDR                        (MDIO_ST(MT7531_MDIO_ST_CL45) | \
 990 +                                        MDIO_CMD(MT7531_MDIO_ADDR))
 991 +#define  MDIO_CL45_READ                        (MDIO_ST(MT7531_MDIO_ST_CL45) | \
 992 +                                        MDIO_CMD(MT7531_MDIO_READ))
 993 +#define  MDIO_CL45_WRITE               (MDIO_ST(MT7531_MDIO_ST_CL45) | \
 994 +                                        MDIO_CMD(MT7531_MDIO_WRITE))
 995 +
 996 +#define MT7531_CLKGEN_CTRL             0x7500
 997 +#define  CLK_SKEW_OUT(x)               (((x) & 0x3) << 8)
 998 +#define  CLK_SKEW_OUT_MASK             (0x3 << 8)
 999 +#define  CLK_SKEW_IN(x)                        (((x) & 0x3) << 6)
1000 +#define  CLK_SKEW_IN_MASK              (0x3 << 6)
1001 +#define  RXCLK_NO_DELAY                        BIT(5)
1002 +#define  TXCLK_NO_REVERSE              BIT(4)
1003 +#define  GP_MODE(x)                    (((x) & 0x3) << 1)
1004 +#define  GP_MODE_MASK                  (0x3 << 1)
1005 +#define  GP_CLK_EN                     BIT(0)
1006 +
1007 +#define PHY_DEV1F                      0x1f
1008 +#define MT7531_PHY_DEV1F_REG_403       0x403
1009 +
1010 +#define MT7531_PHY_EN_BYPASS_MODE      BIT(4)
1011 +#define MT7531_PHY_POWER_OFF           BIT(5)
1012 +
1013 +enum mt7531_gp_mode {
1014 +       MT7531_GP_MODE_RGMII = 0,
1015 +       MT7531_GP_MODE_MII = 1,
1016 +       MT7531_GP_MODE_REV_MII = 2
1017 +};
1018 +
1019 +enum mt7531_clk_skew {
1020 +       MT7531_CLK_SKEW_NO_CHG = 0,
1021 +       MT7531_CLK_SKEW_DLY_100PPS = 1,
1022 +       MT7531_CLK_SKEW_DLY_200PPS = 2,
1023 +       MT7531_CLK_SKEW_REVERSE = 3,
1024 +};
1025 +
1026  /* Register for hw trap status */
1027  #define MT7530_HWTRAP                  0x7800
1028  #define  HWTRAP_XTAL_MASK              (BIT(10) | BIT(9))
1029 @@ -271,6 +384,11 @@ enum mt7530_vlan_port_attr {
1030  #define  HWTRAP_XTAL_40MHZ             (BIT(10))
1031  #define  HWTRAP_XTAL_20MHZ             (BIT(9))
1032
1033 +#define MT7531_HWTRAP                  0x7800
1034 +#define  HWTRAP_XTAL_FSEL_MASK         BIT(7)
1035 +#define  HWTRAP_XTAL_FSEL_25MHZ                BIT(7)
1036 +#define  HWTRAP_XTAL_FSEL_40MHZ                0
1037 +
1038  /* Register for hw trap modification */
1039  #define MT7530_MHWTRAP                 0x7804
1040  #define  MHWTRAP_PHY0_SEL              BIT(20)
1041 @@ -285,14 +403,34 @@ enum mt7530_vlan_port_attr {
1042  #define MT7530_TOP_SIG_CTRL            0x7808
1043  #define  TOP_SIG_CTRL_NORMAL           (BIT(17) | BIT(16))
1044
1045 +#define MT7531_TOP_SIG_SR              0x780c
1046 +#define  PAD_DUAL_SGMII_EN             BIT(1)
1047 +
1048  #define MT7530_IO_DRV_CR               0x7810
1049  #define  P5_IO_CLK_DRV(x)              ((x) & 0x3)
1050  #define  P5_IO_DATA_DRV(x)             (((x) & 0x3) << 4)
1051
1052 +#define MT7531_PLLGP_EN                        0x7820
1053 +#define  EN_COREPLL                    BIT(2)
1054 +#define  SW_CLKSW                      BIT(1)
1055 +#define  SW_PLLGP                      BIT(0)
1056 +
1057 +#define MT7531_PLLGP_CR0               0x78a8
1058 +#define  RG_COREPLL_EN                 BIT(22)
1059 +#define  RG_COREPLL_POSDIV_S           23
1060 +#define  RG_COREPLL_POSDIV_M           0x3800000
1061 +#define  RG_COREPLL_SDM_PCW_S          1
1062 +#define  RG_COREPLL_SDM_PCW_M          0x3ffffe
1063 +#define  RG_COREPLL_SDM_PCW_CHG                BIT(0)
1064 +
1065  #define MT7530_P6ECR                   0x7830
1066  #define  P6_INTF_MODE_MASK             0x3
1067  #define  P6_INTF_MODE(x)               ((x) & 0x3)
1068
1069 +/* RGMII and SGMII PLL clock */
1070 +#define MT7531_ANA_PLLGP_CR2           0x78b0
1071 +#define MT7531_ANA_PLLGP_CR5           0x78bc
1072 +
1073  /* Registers for TRGMII on the both side */
1074  #define MT7530_TRGMII_RCK_CTRL         0x7a00
1075  #define  RX_RST                                BIT(31)
1076 @@ -335,6 +473,9 @@ enum mt7530_vlan_port_attr {
1077  #define  CHIP_NAME_SHIFT               16
1078  #define  MT7530_ID                     0x7530
1079
1080 +#define MT7531_CREV                    0x781C
1081 +#define  MT7531_ID                     0x7531
1082 +
1083  /* Registers for core PLL access through mmd indirect */
1084  #define CORE_PLL_GROUP2                        0x401
1085  #define  RG_SYSPLL_EN_NORMAL           BIT(15)
1086 @@ -458,6 +599,8 @@ static const char *p5_intf_modes(unsigne
1087   *                     port
1088   * @mac_setup:         Holding the way setting up the PHY attribute for a
1089   *                     certain MAC port
1090 + * @port_an_restart    Holding the way restarting 802.3z BaseX autonegotiation
1091 + *                     for a certain MAC port
1092   */
1093  struct mt753x_info {
1094         enum mt753x_id id;
1095 @@ -471,6 +614,7 @@ struct mt753x_info {
1096                          const struct phylink_link_state *state);
1097         int (*mac_setup)(struct dsa_switch *ds, int port, unsigned int mode,
1098                          const struct phylink_link_state *state);
1099 +       void (*port_an_restart)(struct dsa_switch *ds, int port);
1100  };
1101
1102  /* struct mt7530_priv -        This is the main data structure for holding the state