target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch

   1 From ec5192303a3938d0972fde3b1f2526d8d6dd02d7 Mon Sep 17 00:00:00 2001
   2 From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
   3 Date: Mon, 23 Oct 2017 12:10:34 +0800
   4 Subject: [PATCH 146/224] clk: mediatek: Add MT2712 clock support
   5
   6 Add MT2712 clock support, include topckgen, apmixedsys,
   7 infracfg, pericfg, mcucfg and subsystem clocks.
   8
   9 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
  10 [sboyd@codeaurora.org: Static on top_clk_data]
  11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  12 ---
  13  drivers/clk/mediatek/Kconfig             |   50 ++
  14  drivers/clk/mediatek/Makefile            |    8 +
  15  drivers/clk/mediatek/clk-mt2712-bdp.c    |  102 +++
  16  drivers/clk/mediatek/clk-mt2712-img.c    |   80 ++
  17  drivers/clk/mediatek/clk-mt2712-jpgdec.c |   76 ++
  18  drivers/clk/mediatek/clk-mt2712-mfg.c    |   75 ++
  19  drivers/clk/mediatek/clk-mt2712-mm.c     |  170 ++++
  20  drivers/clk/mediatek/clk-mt2712-vdec.c   |   94 ++
  21  drivers/clk/mediatek/clk-mt2712-venc.c   |   77 ++
  22  drivers/clk/mediatek/clk-mt2712.c        | 1435 ++++++++++++++++++++++++++++++
  23  drivers/clk/mediatek/clk-mtk.h           |    2 +
  24  drivers/clk/mediatek/clk-pll.c           |   13 +-
  25  12 files changed, 2180 insertions(+), 2 deletions(-)
  26  create mode 100644 drivers/clk/mediatek/clk-mt2712-bdp.c
  27  create mode 100644 drivers/clk/mediatek/clk-mt2712-img.c
  28  create mode 100644 drivers/clk/mediatek/clk-mt2712-jpgdec.c
  29  create mode 100644 drivers/clk/mediatek/clk-mt2712-mfg.c
  30  create mode 100644 drivers/clk/mediatek/clk-mt2712-mm.c
  31  create mode 100644 drivers/clk/mediatek/clk-mt2712-vdec.c
  32  create mode 100644 drivers/clk/mediatek/clk-mt2712-venc.c
  33  create mode 100644 drivers/clk/mediatek/clk-mt2712.c
  34
  35 diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
  36 index 28739a9a6e37..300dbb551bf7 100644
  37 --- a/drivers/clk/mediatek/Kconfig
  38 +++ b/drivers/clk/mediatek/Kconfig
  39 @@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
  40         ---help---
  41           This driver supports Mediatek MT2701 bdpsys clocks.
  42
  43 +config COMMON_CLK_MT2712
  44 +       bool "Clock driver for Mediatek MT2712"
  45 +       depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
  46 +       select COMMON_CLK_MEDIATEK
  47 +       default ARCH_MEDIATEK && ARM64
  48 +       ---help---
  49 +         This driver supports Mediatek MT2712 basic clocks.
  50 +
  51 +config COMMON_CLK_MT2712_BDPSYS
  52 +       bool "Clock driver for Mediatek MT2712 bdpsys"
  53 +       depends on COMMON_CLK_MT2712
  54 +       ---help---
  55 +         This driver supports Mediatek MT2712 bdpsys clocks.
  56 +
  57 +config COMMON_CLK_MT2712_IMGSYS
  58 +       bool "Clock driver for Mediatek MT2712 imgsys"
  59 +       depends on COMMON_CLK_MT2712
  60 +       ---help---
  61 +         This driver supports Mediatek MT2712 imgsys clocks.
  62 +
  63 +config COMMON_CLK_MT2712_JPGDECSYS
  64 +       bool "Clock driver for Mediatek MT2712 jpgdecsys"
  65 +       depends on COMMON_CLK_MT2712
  66 +       ---help---
  67 +         This driver supports Mediatek MT2712 jpgdecsys clocks.
  68 +
  69 +config COMMON_CLK_MT2712_MFGCFG
  70 +       bool "Clock driver for Mediatek MT2712 mfgcfg"
  71 +       depends on COMMON_CLK_MT2712
  72 +       ---help---
  73 +         This driver supports Mediatek MT2712 mfgcfg clocks.
  74 +
  75 +config COMMON_CLK_MT2712_MMSYS
  76 +       bool "Clock driver for Mediatek MT2712 mmsys"
  77 +       depends on COMMON_CLK_MT2712
  78 +       ---help---
  79 +         This driver supports Mediatek MT2712 mmsys clocks.
  80 +
  81 +config COMMON_CLK_MT2712_VDECSYS
  82 +       bool "Clock driver for Mediatek MT2712 vdecsys"
  83 +       depends on COMMON_CLK_MT2712
  84 +       ---help---
  85 +         This driver supports Mediatek MT2712 vdecsys clocks.
  86 +
  87 +config COMMON_CLK_MT2712_VENCSYS
  88 +       bool "Clock driver for Mediatek MT2712 vencsys"
  89 +       depends on COMMON_CLK_MT2712
  90 +       ---help---
  91 +         This driver supports Mediatek MT2712 vencsys clocks.
  92 +
  93  config COMMON_CLK_MT6797
  94         bool "Clock driver for Mediatek MT6797"
  95         depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
  96 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
  97 index 2a755b5fb51b..a4e5c47c73a4 100644
  98 --- a/drivers/clk/mediatek/Makefile
  99 +++ b/drivers/clk/mediatek/Makefile
 100 @@ -12,5 +12,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
 101  obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
 102  obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
 103  obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
 104 +obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
 105 +obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
 106 +obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
 107 +obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
 108 +obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
 109 +obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
 110 +obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
 111 +obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
 112  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 113  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
 114 diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/clk-mt2712-bdp.c
 115 new file mode 100644
 116 index 000000000000..5fe4728c076e
 117 --- /dev/null
 118 +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c
 119 @@ -0,0 +1,102 @@
 120 +/*
 121 + * Copyright (c) 2017 MediaTek Inc.
 122 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 123 + *
 124 + * This program is free software; you can redistribute it and/or modify
 125 + * it under the terms of the GNU General Public License version 2 as
 126 + * published by the Free Software Foundation.
 127 + *
 128 + * This program is distributed in the hope that it will be useful,
 129 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 130 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 131 + * GNU General Public License for more details.
 132 + */
 133 +
 134 +#include <linux/clk-provider.h>
 135 +#include <linux/platform_device.h>
 136 +
 137 +#include "clk-mtk.h"
 138 +#include "clk-gate.h"
 139 +
 140 +#include <dt-bindings/clock/mt2712-clk.h>
 141 +
 142 +static const struct mtk_gate_regs bdp_cg_regs = {
 143 +       .set_ofs = 0x100,
 144 +       .clr_ofs = 0x100,
 145 +       .sta_ofs = 0x100,
 146 +};
 147 +
 148 +#define GATE_BDP(_id, _name, _parent, _shift) {        \
 149 +               .id = _id,                              \
 150 +               .name = _name,                          \
 151 +               .parent_name = _parent,                 \
 152 +               .regs = &bdp_cg_regs,                   \
 153 +               .shift = _shift,                        \
 154 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 155 +       }
 156 +
 157 +static const struct mtk_gate bdp_clks[] = {
 158 +       GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
 159 +       GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
 160 +       GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
 161 +       GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
 162 +       GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
 163 +       GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
 164 +       GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
 165 +       GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
 166 +       GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
 167 +       GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
 168 +       GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
 169 +       GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
 170 +       GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
 171 +       GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
 172 +       GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
 173 +       GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
 174 +       GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
 175 +       GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
 176 +       GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
 177 +       GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
 178 +       GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
 179 +       GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
 180 +       GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
 181 +       GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
 182 +       GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
 183 +       GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
 184 +       GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
 185 +       GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
 186 +};
 187 +
 188 +static int clk_mt2712_bdp_probe(struct platform_device *pdev)
 189 +{
 190 +       struct clk_onecell_data *clk_data;
 191 +       int r;
 192 +       struct device_node *node = pdev->dev.of_node;
 193 +
 194 +       clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
 195 +
 196 +       mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
 197 +                       clk_data);
 198 +
 199 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 200 +
 201 +       if (r != 0)
 202 +               pr_err("%s(): could not register clock provider: %d\n",
 203 +                       __func__, r);
 204 +
 205 +       return r;
 206 +}
 207 +
 208 +static const struct of_device_id of_match_clk_mt2712_bdp[] = {
 209 +       { .compatible = "mediatek,mt2712-bdpsys", },
 210 +       {}
 211 +};
 212 +
 213 +static struct platform_driver clk_mt2712_bdp_drv = {
 214 +       .probe = clk_mt2712_bdp_probe,
 215 +       .driver = {
 216 +               .name = "clk-mt2712-bdp",
 217 +               .of_match_table = of_match_clk_mt2712_bdp,
 218 +       },
 219 +};
 220 +
 221 +builtin_platform_driver(clk_mt2712_bdp_drv);
 222 diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/clk-mt2712-img.c
 223 new file mode 100644
 224 index 000000000000..139ff55d495e
 225 --- /dev/null
 226 +++ b/drivers/clk/mediatek/clk-mt2712-img.c
 227 @@ -0,0 +1,80 @@
 228 +/*
 229 + * Copyright (c) 2017 MediaTek Inc.
 230 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 231 + *
 232 + * This program is free software; you can redistribute it and/or modify
 233 + * it under the terms of the GNU General Public License version 2 as
 234 + * published by the Free Software Foundation.
 235 + *
 236 + * This program is distributed in the hope that it will be useful,
 237 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 238 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 239 + * GNU General Public License for more details.
 240 + */
 241 +
 242 +#include <linux/clk-provider.h>
 243 +#include <linux/platform_device.h>
 244 +
 245 +#include "clk-mtk.h"
 246 +#include "clk-gate.h"
 247 +
 248 +#include <dt-bindings/clock/mt2712-clk.h>
 249 +
 250 +static const struct mtk_gate_regs img_cg_regs = {
 251 +       .set_ofs = 0x0,
 252 +       .clr_ofs = 0x0,
 253 +       .sta_ofs = 0x0,
 254 +};
 255 +
 256 +#define GATE_IMG(_id, _name, _parent, _shift) {        \
 257 +               .id = _id,                              \
 258 +               .name = _name,                          \
 259 +               .parent_name = _parent,                 \
 260 +               .regs = &img_cg_regs,                   \
 261 +               .shift = _shift,                        \
 262 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 263 +       }
 264 +
 265 +static const struct mtk_gate img_clks[] = {
 266 +       GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
 267 +       GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
 268 +       GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
 269 +       GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
 270 +       GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
 271 +       GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
 272 +};
 273 +
 274 +static int clk_mt2712_img_probe(struct platform_device *pdev)
 275 +{
 276 +       struct clk_onecell_data *clk_data;
 277 +       int r;
 278 +       struct device_node *node = pdev->dev.of_node;
 279 +
 280 +       clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
 281 +
 282 +       mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
 283 +                       clk_data);
 284 +
 285 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 286 +
 287 +       if (r != 0)
 288 +               pr_err("%s(): could not register clock provider: %d\n",
 289 +                       __func__, r);
 290 +
 291 +       return r;
 292 +}
 293 +
 294 +static const struct of_device_id of_match_clk_mt2712_img[] = {
 295 +       { .compatible = "mediatek,mt2712-imgsys", },
 296 +       {}
 297 +};
 298 +
 299 +static struct platform_driver clk_mt2712_img_drv = {
 300 +       .probe = clk_mt2712_img_probe,
 301 +       .driver = {
 302 +               .name = "clk-mt2712-img",
 303 +               .of_match_table = of_match_clk_mt2712_img,
 304 +       },
 305 +};
 306 +
 307 +builtin_platform_driver(clk_mt2712_img_drv);
 308 diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
 309 new file mode 100644
 310 index 000000000000..c7d4aada4892
 311 --- /dev/null
 312 +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
 313 @@ -0,0 +1,76 @@
 314 +/*
 315 + * Copyright (c) 2017 MediaTek Inc.
 316 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 317 + *
 318 + * This program is free software; you can redistribute it and/or modify
 319 + * it under the terms of the GNU General Public License version 2 as
 320 + * published by the Free Software Foundation.
 321 + *
 322 + * This program is distributed in the hope that it will be useful,
 323 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 324 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 325 + * GNU General Public License for more details.
 326 + */
 327 +
 328 +#include <linux/clk-provider.h>
 329 +#include <linux/platform_device.h>
 330 +
 331 +#include "clk-mtk.h"
 332 +#include "clk-gate.h"
 333 +
 334 +#include <dt-bindings/clock/mt2712-clk.h>
 335 +
 336 +static const struct mtk_gate_regs jpgdec_cg_regs = {
 337 +       .set_ofs = 0x4,
 338 +       .clr_ofs = 0x8,
 339 +       .sta_ofs = 0x0,
 340 +};
 341 +
 342 +#define GATE_JPGDEC(_id, _name, _parent, _shift) {     \
 343 +               .id = _id,                              \
 344 +               .name = _name,                          \
 345 +               .parent_name = _parent,                 \
 346 +               .regs = &jpgdec_cg_regs,                        \
 347 +               .shift = _shift,                        \
 348 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
 349 +       }
 350 +
 351 +static const struct mtk_gate jpgdec_clks[] = {
 352 +       GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
 353 +       GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
 354 +};
 355 +
 356 +static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
 357 +{
 358 +       struct clk_onecell_data *clk_data;
 359 +       int r;
 360 +       struct device_node *node = pdev->dev.of_node;
 361 +
 362 +       clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
 363 +
 364 +       mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
 365 +                       clk_data);
 366 +
 367 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 368 +
 369 +       if (r != 0)
 370 +               pr_err("%s(): could not register clock provider: %d\n",
 371 +                       __func__, r);
 372 +
 373 +       return r;
 374 +}
 375 +
 376 +static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
 377 +       { .compatible = "mediatek,mt2712-jpgdecsys", },
 378 +       {}
 379 +};
 380 +
 381 +static struct platform_driver clk_mt2712_jpgdec_drv = {
 382 +       .probe = clk_mt2712_jpgdec_probe,
 383 +       .driver = {
 384 +               .name = "clk-mt2712-jpgdec",
 385 +               .of_match_table = of_match_clk_mt2712_jpgdec,
 386 +       },
 387 +};
 388 +
 389 +builtin_platform_driver(clk_mt2712_jpgdec_drv);
 390 diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/clk-mt2712-mfg.c
 391 new file mode 100644
 392 index 000000000000..570f72d48d4d
 393 --- /dev/null
 394 +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c
 395 @@ -0,0 +1,75 @@
 396 +/*
 397 + * Copyright (c) 2017 MediaTek Inc.
 398 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 399 + *
 400 + * This program is free software; you can redistribute it and/or modify
 401 + * it under the terms of the GNU General Public License version 2 as
 402 + * published by the Free Software Foundation.
 403 + *
 404 + * This program is distributed in the hope that it will be useful,
 405 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 406 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 407 + * GNU General Public License for more details.
 408 + */
 409 +
 410 +#include <linux/clk-provider.h>
 411 +#include <linux/platform_device.h>
 412 +
 413 +#include "clk-mtk.h"
 414 +#include "clk-gate.h"
 415 +
 416 +#include <dt-bindings/clock/mt2712-clk.h>
 417 +
 418 +static const struct mtk_gate_regs mfg_cg_regs = {
 419 +       .set_ofs = 0x4,
 420 +       .clr_ofs = 0x8,
 421 +       .sta_ofs = 0x0,
 422 +};
 423 +
 424 +#define GATE_MFG(_id, _name, _parent, _shift) {        \
 425 +               .id = _id,                              \
 426 +               .name = _name,                          \
 427 +               .parent_name = _parent,                 \
 428 +               .regs = &mfg_cg_regs,                   \
 429 +               .shift = _shift,                        \
 430 +               .ops = &mtk_clk_gate_ops_setclr,        \
 431 +       }
 432 +
 433 +static const struct mtk_gate mfg_clks[] = {
 434 +       GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
 435 +};
 436 +
 437 +static int clk_mt2712_mfg_probe(struct platform_device *pdev)
 438 +{
 439 +       struct clk_onecell_data *clk_data;
 440 +       int r;
 441 +       struct device_node *node = pdev->dev.of_node;
 442 +
 443 +       clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
 444 +
 445 +       mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
 446 +                       clk_data);
 447 +
 448 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 449 +
 450 +       if (r != 0)
 451 +               pr_err("%s(): could not register clock provider: %d\n",
 452 +                       __func__, r);
 453 +
 454 +       return r;
 455 +}
 456 +
 457 +static const struct of_device_id of_match_clk_mt2712_mfg[] = {
 458 +       { .compatible = "mediatek,mt2712-mfgcfg", },
 459 +       {}
 460 +};
 461 +
 462 +static struct platform_driver clk_mt2712_mfg_drv = {
 463 +       .probe = clk_mt2712_mfg_probe,
 464 +       .driver = {
 465 +               .name = "clk-mt2712-mfg",
 466 +               .of_match_table = of_match_clk_mt2712_mfg,
 467 +       },
 468 +};
 469 +
 470 +builtin_platform_driver(clk_mt2712_mfg_drv);
 471 diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c
 472 new file mode 100644
 473 index 000000000000..a8b4b6d42488
 474 --- /dev/null
 475 +++ b/drivers/clk/mediatek/clk-mt2712-mm.c
 476 @@ -0,0 +1,170 @@
 477 +/*
 478 + * Copyright (c) 2017 MediaTek Inc.
 479 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 480 + *
 481 + * This program is free software; you can redistribute it and/or modify
 482 + * it under the terms of the GNU General Public License version 2 as
 483 + * published by the Free Software Foundation.
 484 + *
 485 + * This program is distributed in the hope that it will be useful,
 486 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 487 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 488 + * GNU General Public License for more details.
 489 + */
 490 +
 491 +#include <linux/clk-provider.h>
 492 +#include <linux/platform_device.h>
 493 +
 494 +#include "clk-mtk.h"
 495 +#include "clk-gate.h"
 496 +
 497 +#include <dt-bindings/clock/mt2712-clk.h>
 498 +
 499 +static const struct mtk_gate_regs mm0_cg_regs = {
 500 +       .set_ofs = 0x104,
 501 +       .clr_ofs = 0x108,
 502 +       .sta_ofs = 0x100,
 503 +};
 504 +
 505 +static const struct mtk_gate_regs mm1_cg_regs = {
 506 +       .set_ofs = 0x114,
 507 +       .clr_ofs = 0x118,
 508 +       .sta_ofs = 0x110,
 509 +};
 510 +
 511 +static const struct mtk_gate_regs mm2_cg_regs = {
 512 +       .set_ofs = 0x224,
 513 +       .clr_ofs = 0x228,
 514 +       .sta_ofs = 0x220,
 515 +};
 516 +
 517 +#define GATE_MM0(_id, _name, _parent, _shift) {        \
 518 +               .id = _id,                              \
 519 +               .name = _name,                          \
 520 +               .parent_name = _parent,                 \
 521 +               .regs = &mm0_cg_regs,                   \
 522 +               .shift = _shift,                        \
 523 +               .ops = &mtk_clk_gate_ops_setclr,        \
 524 +       }
 525 +
 526 +#define GATE_MM1(_id, _name, _parent, _shift) {        \
 527 +               .id = _id,                              \
 528 +               .name = _name,                          \
 529 +               .parent_name = _parent,                 \
 530 +               .regs = &mm1_cg_regs,                   \
 531 +               .shift = _shift,                        \
 532 +               .ops = &mtk_clk_gate_ops_setclr,        \
 533 +       }
 534 +
 535 +#define GATE_MM2(_id, _name, _parent, _shift) {        \
 536 +               .id = _id,                              \
 537 +               .name = _name,                          \
 538 +               .parent_name = _parent,                 \
 539 +               .regs = &mm2_cg_regs,                   \
 540 +               .shift = _shift,                        \
 541 +               .ops = &mtk_clk_gate_ops_setclr,        \
 542 +       }
 543 +
 544 +static const struct mtk_gate mm_clks[] = {
 545 +       /* MM0 */
 546 +       GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
 547 +       GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
 548 +       GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
 549 +       GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
 550 +       GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
 551 +       GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
 552 +       GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
 553 +       GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
 554 +       GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
 555 +       GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
 556 +       GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
 557 +       GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
 558 +       GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
 559 +       GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
 560 +       GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
 561 +       GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
 562 +       GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
 563 +       GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
 564 +       GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
 565 +       GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
 566 +       GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
 567 +       GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
 568 +       GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
 569 +       GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
 570 +       GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
 571 +       GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
 572 +       GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
 573 +       GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
 574 +       GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
 575 +       GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
 576 +       /* MM1 */
 577 +       GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
 578 +       GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
 579 +       GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
 580 +       GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
 581 +       GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
 582 +       GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
 583 +       GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
 584 +       GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
 585 +       GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
 586 +       GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
 587 +       GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
 588 +       GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
 589 +       GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
 590 +       GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
 591 +       GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
 592 +       GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
 593 +       GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
 594 +       GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
 595 +       GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
 596 +       GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
 597 +       GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
 598 +       GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
 599 +       GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
 600 +       GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
 601 +       GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
 602 +       GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
 603 +       /* MM2 */
 604 +       GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
 605 +       GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
 606 +       GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
 607 +       GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
 608 +       GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
 609 +       GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
 610 +       GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
 611 +};
 612 +
 613 +static int clk_mt2712_mm_probe(struct platform_device *pdev)
 614 +{
 615 +       struct clk_onecell_data *clk_data;
 616 +       int r;
 617 +       struct device_node *node = pdev->dev.of_node;
 618 +
 619 +       clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
 620 +
 621 +       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
 622 +                       clk_data);
 623 +
 624 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 625 +
 626 +       if (r != 0)
 627 +               pr_err("%s(): could not register clock provider: %d\n",
 628 +                       __func__, r);
 629 +
 630 +       return r;
 631 +}
 632 +
 633 +static const struct of_device_id of_match_clk_mt2712_mm[] = {
 634 +       { .compatible = "mediatek,mt2712-mmsys", },
 635 +       {}
 636 +};
 637 +
 638 +static struct platform_driver clk_mt2712_mm_drv = {
 639 +       .probe = clk_mt2712_mm_probe,
 640 +       .driver = {
 641 +               .name = "clk-mt2712-mm",
 642 +               .of_match_table = of_match_clk_mt2712_mm,
 643 +       },
 644 +};
 645 +
 646 +builtin_platform_driver(clk_mt2712_mm_drv);
 647 diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/clk-mt2712-vdec.c
 648 new file mode 100644
 649 index 000000000000..55c64ee8cc91
 650 --- /dev/null
 651 +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c
 652 @@ -0,0 +1,94 @@
 653 +/*
 654 + * Copyright (c) 2017 MediaTek Inc.
 655 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 656 + *
 657 + * This program is free software; you can redistribute it and/or modify
 658 + * it under the terms of the GNU General Public License version 2 as
 659 + * published by the Free Software Foundation.
 660 + *
 661 + * This program is distributed in the hope that it will be useful,
 662 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 663 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 664 + * GNU General Public License for more details.
 665 + */
 666 +
 667 +#include <linux/clk-provider.h>
 668 +#include <linux/platform_device.h>
 669 +
 670 +#include "clk-mtk.h"
 671 +#include "clk-gate.h"
 672 +
 673 +#include <dt-bindings/clock/mt2712-clk.h>
 674 +
 675 +static const struct mtk_gate_regs vdec0_cg_regs = {
 676 +       .set_ofs = 0x0,
 677 +       .clr_ofs = 0x4,
 678 +       .sta_ofs = 0x0,
 679 +};
 680 +
 681 +static const struct mtk_gate_regs vdec1_cg_regs = {
 682 +       .set_ofs = 0x8,
 683 +       .clr_ofs = 0xc,
 684 +       .sta_ofs = 0x8,
 685 +};
 686 +
 687 +#define GATE_VDEC0(_id, _name, _parent, _shift) {      \
 688 +               .id = _id,                              \
 689 +               .name = _name,                          \
 690 +               .parent_name = _parent,                 \
 691 +               .regs = &vdec0_cg_regs,                 \
 692 +               .shift = _shift,                        \
 693 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
 694 +       }
 695 +
 696 +#define GATE_VDEC1(_id, _name, _parent, _shift) {      \
 697 +               .id = _id,                              \
 698 +               .name = _name,                          \
 699 +               .parent_name = _parent,                 \
 700 +               .regs = &vdec1_cg_regs,                 \
 701 +               .shift = _shift,                        \
 702 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
 703 +       }
 704 +
 705 +static const struct mtk_gate vdec_clks[] = {
 706 +       /* VDEC0 */
 707 +       GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
 708 +       /* VDEC1 */
 709 +       GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
 710 +       GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
 711 +};
 712 +
 713 +static int clk_mt2712_vdec_probe(struct platform_device *pdev)
 714 +{
 715 +       struct clk_onecell_data *clk_data;
 716 +       int r;
 717 +       struct device_node *node = pdev->dev.of_node;
 718 +
 719 +       clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
 720 +
 721 +       mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
 722 +                       clk_data);
 723 +
 724 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 725 +
 726 +       if (r != 0)
 727 +               pr_err("%s(): could not register clock provider: %d\n",
 728 +                       __func__, r);
 729 +
 730 +       return r;
 731 +}
 732 +
 733 +static const struct of_device_id of_match_clk_mt2712_vdec[] = {
 734 +       { .compatible = "mediatek,mt2712-vdecsys", },
 735 +       {}
 736 +};
 737 +
 738 +static struct platform_driver clk_mt2712_vdec_drv = {
 739 +       .probe = clk_mt2712_vdec_probe,
 740 +       .driver = {
 741 +               .name = "clk-mt2712-vdec",
 742 +               .of_match_table = of_match_clk_mt2712_vdec,
 743 +       },
 744 +};
 745 +
 746 +builtin_platform_driver(clk_mt2712_vdec_drv);
 747 diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/clk-mt2712-venc.c
 748 new file mode 100644
 749 index 000000000000..ccbfe98777c8
 750 --- /dev/null
 751 +++ b/drivers/clk/mediatek/clk-mt2712-venc.c
 752 @@ -0,0 +1,77 @@
 753 +/*
 754 + * Copyright (c) 2017 MediaTek Inc.
 755 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 756 + *
 757 + * This program is free software; you can redistribute it and/or modify
 758 + * it under the terms of the GNU General Public License version 2 as
 759 + * published by the Free Software Foundation.
 760 + *
 761 + * This program is distributed in the hope that it will be useful,
 762 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 763 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 764 + * GNU General Public License for more details.
 765 + */
 766 +
 767 +#include <linux/clk-provider.h>
 768 +#include <linux/platform_device.h>
 769 +
 770 +#include "clk-mtk.h"
 771 +#include "clk-gate.h"
 772 +
 773 +#include <dt-bindings/clock/mt2712-clk.h>
 774 +
 775 +static const struct mtk_gate_regs venc_cg_regs = {
 776 +       .set_ofs = 0x4,
 777 +       .clr_ofs = 0x8,
 778 +       .sta_ofs = 0x0,
 779 +};
 780 +
 781 +#define GATE_VENC(_id, _name, _parent, _shift) {       \
 782 +               .id = _id,                              \
 783 +               .name = _name,                          \
 784 +               .parent_name = _parent,                 \
 785 +               .regs = &venc_cg_regs,                  \
 786 +               .shift = _shift,                        \
 787 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
 788 +       }
 789 +
 790 +static const struct mtk_gate venc_clks[] = {
 791 +       GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
 792 +       GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
 793 +       GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
 794 +};
 795 +
 796 +static int clk_mt2712_venc_probe(struct platform_device *pdev)
 797 +{
 798 +       struct clk_onecell_data *clk_data;
 799 +       int r;
 800 +       struct device_node *node = pdev->dev.of_node;
 801 +
 802 +       clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
 803 +
 804 +       mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
 805 +                       clk_data);
 806 +
 807 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 808 +
 809 +       if (r != 0)
 810 +               pr_err("%s(): could not register clock provider: %d\n",
 811 +                       __func__, r);
 812 +
 813 +       return r;
 814 +}
 815 +
 816 +static const struct of_device_id of_match_clk_mt2712_venc[] = {
 817 +       { .compatible = "mediatek,mt2712-vencsys", },
 818 +       {}
 819 +};
 820 +
 821 +static struct platform_driver clk_mt2712_venc_drv = {
 822 +       .probe = clk_mt2712_venc_probe,
 823 +       .driver = {
 824 +               .name = "clk-mt2712-venc",
 825 +               .of_match_table = of_match_clk_mt2712_venc,
 826 +       },
 827 +};
 828 +
 829 +builtin_platform_driver(clk_mt2712_venc_drv);
 830 diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
 831 new file mode 100644
 832 index 000000000000..498d13799388
 833 --- /dev/null
 834 +++ b/drivers/clk/mediatek/clk-mt2712.c
 835 @@ -0,0 +1,1435 @@
 836 +/*
 837 + * Copyright (c) 2017 MediaTek Inc.
 838 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 839 + *
 840 + * This program is free software; you can redistribute it and/or modify
 841 + * it under the terms of the GNU General Public License version 2 as
 842 + * published by the Free Software Foundation.
 843 + *
 844 + * This program is distributed in the hope that it will be useful,
 845 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 846 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 847 + * GNU General Public License for more details.
 848 + */
 849 +
 850 +#include <linux/clk.h>
 851 +#include <linux/delay.h>
 852 +#include <linux/mfd/syscon.h>
 853 +#include <linux/of.h>
 854 +#include <linux/of_address.h>
 855 +#include <linux/of_device.h>
 856 +#include <linux/platform_device.h>
 857 +#include <linux/slab.h>
 858 +
 859 +#include "clk-mtk.h"
 860 +#include "clk-gate.h"
 861 +
 862 +#include <dt-bindings/clock/mt2712-clk.h>
 863 +
 864 +static DEFINE_SPINLOCK(mt2712_clk_lock);
 865 +
 866 +static const struct mtk_fixed_clk top_fixed_clks[] = {
 867 +       FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
 868 +       FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
 869 +       FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
 870 +       FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
 871 +       FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
 872 +       FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
 873 +       FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
 874 +       FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
 875 +       FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
 876 +       FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
 877 +       FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
 878 +       FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
 879 +};
 880 +
 881 +static const struct mtk_fixed_factor top_early_divs[] = {
 882 +       FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
 883 +               1),
 884 +       FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
 885 +               2),
 886 +};
 887 +
 888 +static const struct mtk_fixed_factor top_divs[] = {
 889 +       FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
 890 +               1),
 891 +       FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
 892 +               2),
 893 +       FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
 894 +               3),
 895 +       FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
 896 +               1),
 897 +       FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
 898 +               1),
 899 +       FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
 900 +               2),
 901 +       FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
 902 +               2),
 903 +       FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
 904 +               4),
 905 +       FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
 906 +               8),
 907 +       FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
 908 +               16),
 909 +       FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
 910 +               3),
 911 +       FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
 912 +               2),
 913 +       FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
 914 +               4),
 915 +       FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
 916 +               5),
 917 +       FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
 918 +               2),
 919 +       FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
 920 +               4),
 921 +       FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
 922 +               7),
 923 +       FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
 924 +               2),
 925 +       FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
 926 +               4),
 927 +       FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
 928 +               1),
 929 +       FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
 930 +               7),
 931 +       FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
 932 +               26),
 933 +       FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
 934 +               52),
 935 +       FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
 936 +               104),
 937 +       FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
 938 +               208),
 939 +       FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
 940 +               2),
 941 +       FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
 942 +               2),
 943 +       FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
 944 +               4),
 945 +       FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
 946 +               8),
 947 +       FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
 948 +               3),
 949 +       FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
 950 +               2),
 951 +       FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
 952 +               4),
 953 +       FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
 954 +               8),
 955 +       FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
 956 +               5),
 957 +       FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
 958 +               2),
 959 +       FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
 960 +               4),
 961 +       FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
 962 +               8),
 963 +       FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
 964 +               1),
 965 +       FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
 966 +               1),
 967 +       FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
 968 +               1),
 969 +       FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
 970 +               1),
 971 +       FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
 972 +               1),
 973 +       FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
 974 +               1),
 975 +       FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
 976 +               1),
 977 +       FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
 978 +               2),
 979 +       FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
 980 +               4),
 981 +       FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
 982 +               8),
 983 +       FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
 984 +               16),
 985 +       FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
 986 +               1),
 987 +       FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
 988 +               2),
 989 +       FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
 990 +               4),
 991 +       FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
 992 +               8),
 993 +       FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
 994 +               16),
 995 +       FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
 996 +               1),
 997 +       FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
 998 +               2),
 999 +       FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
1000 +               4),
1001 +       FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
1002 +               8),
1003 +       FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
1004 +               1),
1005 +       FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
1006 +               2),
1007 +       FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
1008 +               4),
1009 +       FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
1010 +               8),
1011 +       FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
1012 +               1),
1013 +       FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
1014 +               1),
1015 +       FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
1016 +               1),
1017 +       FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
1018 +               2),
1019 +       FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
1020 +               1),
1021 +       FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
1022 +               2),
1023 +       FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
1024 +               1),
1025 +       FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
1026 +               2),
1027 +       FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
1028 +               1),
1029 +       FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
1030 +               2),
1031 +       FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
1032 +               1),
1033 +       FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
1034 +               2),
1035 +       FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
1036 +               4),
1037 +       FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
1038 +               8),
1039 +       FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
1040 +               1),
1041 +       FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
1042 +               2),
1043 +       FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
1044 +               4),
1045 +       FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
1046 +               1),
1047 +       FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
1048 +               2),
1049 +       FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
1050 +               4),
1051 +       FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
1052 +               1),
1053 +       FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
1054 +               2),
1055 +       FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
1056 +               4),
1057 +       FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
1058 +               4),
1059 +};
1060 +
1061 +static const char * const axi_parents[] = {
1062 +       "clk26m",
1063 +       "syspll1_d2",
1064 +       "syspll_d5",
1065 +       "syspll1_d4",
1066 +       "univpll_d5",
1067 +       "univpll2_d2",
1068 +       "msdcpll2_ck"
1069 +};
1070 +
1071 +static const char * const mem_parents[] = {
1072 +       "clk26m",
1073 +       "dmpll_ck"
1074 +};
1075 +
1076 +static const char * const mm_parents[] = {
1077 +       "clk26m",
1078 +       "vencpll_ck",
1079 +       "syspll_d3",
1080 +       "syspll1_d2",
1081 +       "syspll_d5",
1082 +       "syspll1_d4",
1083 +       "univpll1_d2",
1084 +       "univpll2_d2"
1085 +};
1086 +
1087 +static const char * const pwm_parents[] = {
1088 +       "clk26m",
1089 +       "univpll2_d4",
1090 +       "univpll3_d2",
1091 +       "univpll1_d4"
1092 +};
1093 +
1094 +static const char * const vdec_parents[] = {
1095 +       "clk26m",
1096 +       "vcodecpll_ck",
1097 +       "tvdpll_429m",
1098 +       "univpll_d3",
1099 +       "vencpll_ck",
1100 +       "syspll_d3",
1101 +       "univpll1_d2",
1102 +       "mmpll_d2",
1103 +       "syspll3_d2",
1104 +       "tvdpll_ck"
1105 +};
1106 +
1107 +static const char * const venc_parents[] = {
1108 +       "clk26m",
1109 +       "univpll1_d2",
1110 +       "mmpll_d2",
1111 +       "tvdpll_d2",
1112 +       "syspll1_d2",
1113 +       "univpll_d5",
1114 +       "vcodecpll_d2",
1115 +       "univpll2_d2",
1116 +       "syspll3_d2"
1117 +};
1118 +
1119 +static const char * const mfg_parents[] = {
1120 +       "clk26m",
1121 +       "mmpll_ck",
1122 +       "univpll_d3",
1123 +       "clk26m",
1124 +       "clk26m",
1125 +       "clk26m",
1126 +       "clk26m",
1127 +       "clk26m",
1128 +       "clk26m",
1129 +       "syspll_d3",
1130 +       "syspll1_d2",
1131 +       "syspll_d5",
1132 +       "univpll_d3",
1133 +       "univpll1_d2",
1134 +       "univpll_d5",
1135 +       "univpll2_d2"
1136 +};
1137 +
1138 +static const char * const camtg_parents[] = {
1139 +       "clk26m",
1140 +       "univpll_d52",
1141 +       "univpll_d208",
1142 +       "univpll_d104",
1143 +       "clk26m_d2",
1144 +       "univpll_d26",
1145 +       "univpll2_d8",
1146 +       "syspll3_d4",
1147 +       "syspll3_d2",
1148 +       "univpll1_d4",
1149 +       "univpll2_d2"
1150 +};
1151 +
1152 +static const char * const uart_parents[] = {
1153 +       "clk26m",
1154 +       "univpll2_d8"
1155 +};
1156 +
1157 +static const char * const spi_parents[] = {
1158 +       "clk26m",
1159 +       "univpll2_d4",
1160 +       "univpll1_d4",
1161 +       "univpll2_d2",
1162 +       "univpll3_d2",
1163 +       "univpll1_d8"
1164 +};
1165 +
1166 +static const char * const usb20_parents[] = {
1167 +       "clk26m",
1168 +       "univpll1_d8",
1169 +       "univpll3_d4"
1170 +};
1171 +
1172 +static const char * const usb30_parents[] = {
1173 +       "clk26m",
1174 +       "univpll3_d2",
1175 +       "univpll3_d4",
1176 +       "univpll2_d4"
1177 +};
1178 +
1179 +static const char * const msdc50_0_h_parents[] = {
1180 +       "clk26m",
1181 +       "syspll1_d2",
1182 +       "syspll2_d2",
1183 +       "syspll4_d2",
1184 +       "univpll_d5",
1185 +       "univpll1_d4"
1186 +};
1187 +
1188 +static const char * const msdc50_0_parents[] = {
1189 +       "clk26m",
1190 +       "msdcpll_ck",
1191 +       "msdcpll_d2",
1192 +       "univpll1_d4",
1193 +       "syspll2_d2",
1194 +       "msdcpll_d4",
1195 +       "vencpll_d2",
1196 +       "univpll1_d2",
1197 +       "msdcpll2_ck",
1198 +       "msdcpll2_d2",
1199 +       "msdcpll2_d4"
1200 +};
1201 +
1202 +static const char * const msdc30_1_parents[] = {
1203 +       "clk26m",
1204 +       "univpll2_d2",
1205 +       "msdcpll_d2",
1206 +       "univpll1_d4",
1207 +       "syspll2_d2",
1208 +       "univpll_d7",
1209 +       "vencpll_d2"
1210 +};
1211 +
1212 +static const char * const msdc30_3_parents[] = {
1213 +       "clk26m",
1214 +       "msdcpll2_ck",
1215 +       "msdcpll2_d2",
1216 +       "univpll2_d2",
1217 +       "msdcpll2_d4",
1218 +       "univpll1_d4",
1219 +       "syspll2_d2",
1220 +       "syspll_d7",
1221 +       "univpll_d7",
1222 +       "vencpll_d2",
1223 +       "msdcpll_ck",
1224 +       "msdcpll_d2",
1225 +       "msdcpll_d4"
1226 +};
1227 +
1228 +static const char * const audio_parents[] = {
1229 +       "clk26m",
1230 +       "syspll3_d4",
1231 +       "syspll4_d4",
1232 +       "syspll1_d16"
1233 +};
1234 +
1235 +static const char * const aud_intbus_parents[] = {
1236 +       "clk26m",
1237 +       "syspll1_d4",
1238 +       "syspll4_d2",
1239 +       "univpll3_d2",
1240 +       "univpll2_d8",
1241 +       "syspll3_d2",
1242 +       "syspll3_d4"
1243 +};
1244 +
1245 +static const char * const pmicspi_parents[] = {
1246 +       "clk26m",
1247 +       "syspll1_d8",
1248 +       "syspll3_d4",
1249 +       "syspll1_d16",
1250 +       "univpll3_d4",
1251 +       "univpll_d26",
1252 +       "syspll3_d4"
1253 +};
1254 +
1255 +static const char * const dpilvds1_parents[] = {
1256 +       "clk26m",
1257 +       "lvdspll2_ck",
1258 +       "lvdspll2_d2",
1259 +       "lvdspll2_d4",
1260 +       "lvdspll2_d8",
1261 +       "clkfpc"
1262 +};
1263 +
1264 +static const char * const atb_parents[] = {
1265 +       "clk26m",
1266 +       "syspll1_d2",
1267 +       "univpll_d5",
1268 +       "syspll_d5"
1269 +};
1270 +
1271 +static const char * const nr_parents[] = {
1272 +       "clk26m",
1273 +       "univpll1_d4",
1274 +       "syspll2_d2",
1275 +       "syspll1_d4",
1276 +       "univpll1_d8",
1277 +       "univpll3_d2",
1278 +       "univpll2_d2",
1279 +       "syspll_d5"
1280 +};
1281 +
1282 +static const char * const nfi2x_parents[] = {
1283 +       "clk26m",
1284 +       "syspll4_d4",
1285 +       "univpll3_d4",
1286 +       "univpll1_d8",
1287 +       "syspll2_d4",
1288 +       "univpll3_d2",
1289 +       "syspll_d7",
1290 +       "syspll2_d2",
1291 +       "univpll2_d2",
1292 +       "syspll_d5",
1293 +       "syspll1_d2"
1294 +};
1295 +
1296 +static const char * const irda_parents[] = {
1297 +       "clk26m",
1298 +       "univpll2_d4",
1299 +       "syspll2_d4",
1300 +       "univpll2_d8"
1301 +};
1302 +
1303 +static const char * const cci400_parents[] = {
1304 +       "clk26m",
1305 +       "vencpll_ck",
1306 +       "armca35pll_600m",
1307 +       "armca35pll_400m",
1308 +       "univpll_d2",
1309 +       "syspll_d2",
1310 +       "msdcpll_ck",
1311 +       "univpll_d3"
1312 +};
1313 +
1314 +static const char * const aud_1_parents[] = {
1315 +       "clk26m",
1316 +       "apll1_ck",
1317 +       "univpll2_d4",
1318 +       "univpll2_d8"
1319 +};
1320 +
1321 +static const char * const aud_2_parents[] = {
1322 +       "clk26m",
1323 +       "apll2_ck",
1324 +       "univpll2_d4",
1325 +       "univpll2_d8"
1326 +};
1327 +
1328 +static const char * const mem_mfg_parents[] = {
1329 +       "clk26m",
1330 +       "mmpll_ck",
1331 +       "univpll_d3"
1332 +};
1333 +
1334 +static const char * const axi_mfg_parents[] = {
1335 +       "clk26m",
1336 +       "axi_sel",
1337 +       "univpll_d5"
1338 +};
1339 +
1340 +static const char * const scam_parents[] = {
1341 +       "clk26m",
1342 +       "syspll3_d2",
1343 +       "univpll2_d4",
1344 +       "syspll2_d4"
1345 +};
1346 +
1347 +static const char * const nfiecc_parents[] = {
1348 +       "clk26m",
1349 +       "nfi2x_sel",
1350 +       "syspll_d7",
1351 +       "syspll2_d2",
1352 +       "univpll2_d2",
1353 +       "univpll_d5",
1354 +       "syspll1_d2"
1355 +};
1356 +
1357 +static const char * const pe2_mac_p0_parents[] = {
1358 +       "clk26m",
1359 +       "syspll1_d8",
1360 +       "syspll4_d2",
1361 +       "syspll2_d4",
1362 +       "univpll2_d4",
1363 +       "syspll3_d2"
1364 +};
1365 +
1366 +static const char * const dpilvds_parents[] = {
1367 +       "clk26m",
1368 +       "lvdspll_ck",
1369 +       "lvdspll_d2",
1370 +       "lvdspll_d4",
1371 +       "lvdspll_d8",
1372 +       "clkfpc"
1373 +};
1374 +
1375 +static const char * const hdcp_parents[] = {
1376 +       "clk26m",
1377 +       "syspll4_d2",
1378 +       "syspll3_d4",
1379 +       "univpll2_d4"
1380 +};
1381 +
1382 +static const char * const hdcp_24m_parents[] = {
1383 +       "clk26m",
1384 +       "univpll_d26",
1385 +       "univpll_d52",
1386 +       "univpll2_d8"
1387 +};
1388 +
1389 +static const char * const rtc_parents[] = {
1390 +       "clkrtc_int",
1391 +       "clkrtc_ext",
1392 +       "clk26m",
1393 +       "univpll3_d8"
1394 +};
1395 +
1396 +static const char * const spinor_parents[] = {
1397 +       "clk26m",
1398 +       "clk26m_d2",
1399 +       "syspll4_d4",
1400 +       "univpll2_d8",
1401 +       "univpll3_d4",
1402 +       "syspll4_d2",
1403 +       "syspll2_d4",
1404 +       "univpll2_d4",
1405 +       "etherpll_125m",
1406 +       "syspll1_d4"
1407 +};
1408 +
1409 +static const char * const apll_parents[] = {
1410 +       "clk26m",
1411 +       "apll1_ck",
1412 +       "apll1_d2",
1413 +       "apll1_d4",
1414 +       "apll1_d8",
1415 +       "apll1_d16",
1416 +       "apll2_ck",
1417 +       "apll2_d2",
1418 +       "apll2_d4",
1419 +       "apll2_d8",
1420 +       "apll2_d16",
1421 +       "clk26m",
1422 +       "clk26m"
1423 +};
1424 +
1425 +static const char * const a1sys_hp_parents[] = {
1426 +       "clk26m",
1427 +       "apll1_ck",
1428 +       "apll1_d2",
1429 +       "apll1_d4",
1430 +       "apll1_d8"
1431 +};
1432 +
1433 +static const char * const a2sys_hp_parents[] = {
1434 +       "clk26m",
1435 +       "apll2_ck",
1436 +       "apll2_d2",
1437 +       "apll2_d4",
1438 +       "apll2_d8"
1439 +};
1440 +
1441 +static const char * const asm_l_parents[] = {
1442 +       "clk26m",
1443 +       "univpll2_d4",
1444 +       "univpll2_d2",
1445 +       "syspll_d5"
1446 +};
1447 +
1448 +static const char * const i2so1_parents[] = {
1449 +       "clk26m",
1450 +       "apll1_ck",
1451 +       "apll2_ck"
1452 +};
1453 +
1454 +static const char * const ether_125m_parents[] = {
1455 +       "clk26m",
1456 +       "etherpll_125m",
1457 +       "univpll3_d2"
1458 +};
1459 +
1460 +static const char * const ether_50m_parents[] = {
1461 +       "clk26m",
1462 +       "etherpll_50m",
1463 +       "univpll_d26",
1464 +       "univpll3_d4"
1465 +};
1466 +
1467 +static const char * const jpgdec_parents[] = {
1468 +       "clk26m",
1469 +       "univpll_d3",
1470 +       "tvdpll_429m",
1471 +       "vencpll_ck",
1472 +       "syspll_d3",
1473 +       "vcodecpll_ck",
1474 +       "univpll1_d2",
1475 +       "armca35pll_400m",
1476 +       "tvdpll_429m_d2",
1477 +       "tvdpll_429m_d4"
1478 +};
1479 +
1480 +static const char * const spislv_parents[] = {
1481 +       "clk26m",
1482 +       "univpll2_d4",
1483 +       "univpll1_d4",
1484 +       "univpll2_d2",
1485 +       "univpll3_d2",
1486 +       "univpll1_d8",
1487 +       "univpll1_d2",
1488 +       "univpll_d5"
1489 +};
1490 +
1491 +static const char * const ether_parents[] = {
1492 +       "clk26m",
1493 +       "etherpll_50m",
1494 +       "univpll_d26"
1495 +};
1496 +
1497 +static const char * const di_parents[] = {
1498 +       "clk26m",
1499 +       "tvdpll_d2",
1500 +       "tvdpll_d4",
1501 +       "tvdpll_d8",
1502 +       "vencpll_ck",
1503 +       "vencpll_d2",
1504 +       "cvbs",
1505 +       "cvbs_d2"
1506 +};
1507 +
1508 +static const char * const tvd_parents[] = {
1509 +       "clk26m",
1510 +       "cvbs_d2",
1511 +       "univpll2_d8"
1512 +};
1513 +
1514 +static const char * const i2c_parents[] = {
1515 +       "clk26m",
1516 +       "univpll_d26",
1517 +       "univpll2_d4",
1518 +       "univpll3_d2",
1519 +       "univpll1_d4"
1520 +};
1521 +
1522 +static const char * const msdc0p_aes_parents[] = {
1523 +       "clk26m",
1524 +       "msdcpll_ck",
1525 +       "univpll_d3",
1526 +       "vcodecpll_ck"
1527 +};
1528 +
1529 +static const char * const cmsys_parents[] = {
1530 +       "clk26m",
1531 +       "univpll_d3",
1532 +       "syspll_d3",
1533 +       "syspll1_d2",
1534 +       "syspll2_d2"
1535 +};
1536 +
1537 +static const char * const gcpu_parents[] = {
1538 +       "clk26m",
1539 +       "syspll_d3",
1540 +       "syspll1_d2",
1541 +       "univpll1_d2",
1542 +       "univpll_d5",
1543 +       "univpll3_d2",
1544 +       "univpll_d3"
1545 +};
1546 +
1547 +static const char * const aud_apll1_parents[] = {
1548 +       "apll1",
1549 +       "clkaud_ext_i_1"
1550 +};
1551 +
1552 +static const char * const aud_apll2_parents[] = {
1553 +       "apll2",
1554 +       "clkaud_ext_i_2"
1555 +};
1556 +
1557 +static const char * const audull_vtx_parents[] = {
1558 +       "d2a_ulclk_6p5m",
1559 +       "clkaud_ext_i_0"
1560 +};
1561 +
1562 +static struct mtk_composite top_muxes[] = {
1563 +       /* CLK_CFG_0 */
1564 +       MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
1565 +               7, CLK_IS_CRITICAL),
1566 +       MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
1567 +               15, CLK_IS_CRITICAL),
1568 +       MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
1569 +               mm_parents, 0x040, 24, 3, 31),
1570 +       /* CLK_CFG_1 */
1571 +       MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
1572 +               pwm_parents, 0x050, 0, 2, 7),
1573 +       MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
1574 +               vdec_parents, 0x050, 8, 4, 15),
1575 +       MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
1576 +               venc_parents, 0x050, 16, 4, 23),
1577 +       MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
1578 +               mfg_parents, 0x050, 24, 4, 31),
1579 +       /* CLK_CFG_2 */
1580 +       MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
1581 +               camtg_parents, 0x060, 0, 4, 7),
1582 +       MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
1583 +               uart_parents, 0x060, 8, 1, 15),
1584 +       MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
1585 +               spi_parents, 0x060, 16, 3, 23),
1586 +       MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
1587 +               usb20_parents, 0x060, 24, 2, 31),
1588 +       /* CLK_CFG_3 */
1589 +       MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
1590 +               usb30_parents, 0x070, 0, 2, 7),
1591 +       MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
1592 +               msdc50_0_h_parents, 0x070, 8, 3, 15),
1593 +       MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
1594 +               msdc50_0_parents, 0x070, 16, 4, 23),
1595 +       MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
1596 +               msdc30_1_parents, 0x070, 24, 3, 31),
1597 +       /* CLK_CFG_4 */
1598 +       MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
1599 +               msdc30_1_parents, 0x080, 0, 3, 7),
1600 +       MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
1601 +               msdc30_3_parents, 0x080, 8, 4, 15),
1602 +       MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
1603 +               audio_parents, 0x080, 16, 2, 23),
1604 +       MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
1605 +               aud_intbus_parents, 0x080, 24, 3, 31),
1606 +       /* CLK_CFG_5 */
1607 +       MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
1608 +               pmicspi_parents, 0x090, 0, 3, 7),
1609 +       MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
1610 +               dpilvds1_parents, 0x090, 8, 3, 15),
1611 +       MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
1612 +               atb_parents, 0x090, 16, 2, 23),
1613 +       MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
1614 +               nr_parents, 0x090, 24, 3, 31),
1615 +       /* CLK_CFG_6 */
1616 +       MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
1617 +               nfi2x_parents, 0x0a0, 0, 4, 7),
1618 +       MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
1619 +               irda_parents, 0x0a0, 8, 2, 15),
1620 +       MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
1621 +               cci400_parents, 0x0a0, 16, 3, 23),
1622 +       MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
1623 +               aud_1_parents, 0x0a0, 24, 2, 31),
1624 +       /* CLK_CFG_7 */
1625 +       MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
1626 +               aud_2_parents, 0x0b0, 0, 2, 7),
1627 +       MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
1628 +               mem_mfg_parents, 0x0b0, 8, 2, 15),
1629 +       MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
1630 +               axi_mfg_parents, 0x0b0, 16, 2, 23),
1631 +       MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
1632 +               scam_parents, 0x0b0, 24, 2, 31),
1633 +       /* CLK_CFG_8 */
1634 +       MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
1635 +               nfiecc_parents, 0x0c0, 0, 3, 7),
1636 +       MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
1637 +               pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
1638 +       MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
1639 +               pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
1640 +       MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
1641 +               dpilvds_parents, 0x0c0, 24, 3, 31),
1642 +       /* CLK_CFG_9 */
1643 +       MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
1644 +               msdc50_0_h_parents, 0x0d0, 0, 3, 7),
1645 +       MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
1646 +               hdcp_parents, 0x0d0, 8, 2, 15),
1647 +       MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
1648 +               hdcp_24m_parents, 0x0d0, 16, 2, 23),
1649 +       MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
1650 +               31, CLK_IS_CRITICAL),
1651 +       /* CLK_CFG_10 */
1652 +       MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
1653 +               spinor_parents, 0x500, 0, 4, 7),
1654 +       MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
1655 +               apll_parents, 0x500, 8, 4, 15),
1656 +       MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
1657 +               apll_parents, 0x500, 16, 4, 23),
1658 +       MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
1659 +               a1sys_hp_parents, 0x500, 24, 3, 31),
1660 +       /* CLK_CFG_11 */
1661 +       MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
1662 +               a2sys_hp_parents, 0x510, 0, 3, 7),
1663 +       MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
1664 +               asm_l_parents, 0x510, 8, 2, 15),
1665 +       MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
1666 +               asm_l_parents, 0x510, 16, 2, 23),
1667 +       MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
1668 +               asm_l_parents, 0x510, 24, 2, 31),
1669 +       /* CLK_CFG_12 */
1670 +       MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
1671 +               i2so1_parents, 0x520, 0, 2, 7),
1672 +       MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
1673 +               i2so1_parents, 0x520, 8, 2, 15),
1674 +       MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
1675 +               i2so1_parents, 0x520, 16, 2, 23),
1676 +       MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
1677 +               i2so1_parents, 0x520, 24, 2, 31),
1678 +       /* CLK_CFG_13 */
1679 +       MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
1680 +               i2so1_parents, 0x530, 0, 2, 7),
1681 +       MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
1682 +               i2so1_parents, 0x530, 8, 2, 15),
1683 +       MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
1684 +               i2so1_parents, 0x530, 16, 2, 23),
1685 +       MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
1686 +               i2so1_parents, 0x530, 24, 2, 31),
1687 +       /* CLK_CFG_14 */
1688 +       MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
1689 +               ether_125m_parents, 0x540, 0, 2, 7),
1690 +       MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
1691 +               ether_50m_parents, 0x540, 8, 2, 15),
1692 +       MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
1693 +               jpgdec_parents, 0x540, 16, 4, 23),
1694 +       MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
1695 +               spislv_parents, 0x540, 24, 3, 31),
1696 +       /* CLK_CFG_15 */
1697 +       MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
1698 +               ether_parents, 0x550, 0, 2, 7),
1699 +       MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
1700 +               camtg_parents, 0x550, 8, 4, 15),
1701 +       MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
1702 +               di_parents, 0x550, 16, 3, 23),
1703 +       MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
1704 +               tvd_parents, 0x550, 24, 2, 31),
1705 +       /* CLK_CFG_16 */
1706 +       MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
1707 +               i2c_parents, 0x560, 0, 3, 7),
1708 +       MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
1709 +               pwm_parents, 0x560, 8, 2, 15),
1710 +       MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
1711 +               msdc0p_aes_parents, 0x560, 16, 2, 23),
1712 +       MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
1713 +               cmsys_parents, 0x560, 24, 3, 31),
1714 +       /* CLK_CFG_17 */
1715 +       MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
1716 +               gcpu_parents, 0x570, 0, 3, 7),
1717 +       /* CLK_AUDDIV_4 */
1718 +       MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
1719 +               aud_apll1_parents, 0x134, 0, 1),
1720 +       MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
1721 +               aud_apll2_parents, 0x134, 1, 1),
1722 +       MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
1723 +               audull_vtx_parents, 0x134, 31, 1),
1724 +};
1725 +
1726 +static const char * const mcu_mp0_parents[] = {
1727 +       "clk26m",
1728 +       "armca35pll_ck",
1729 +       "f_mp0_pll1_ck",
1730 +       "f_mp0_pll2_ck"
1731 +};
1732 +
1733 +static const char * const mcu_mp2_parents[] = {
1734 +       "clk26m",
1735 +       "armca72pll_ck",
1736 +       "f_big_pll1_ck",
1737 +       "f_big_pll2_ck"
1738 +};
1739 +
1740 +static const char * const mcu_bus_parents[] = {
1741 +       "clk26m",
1742 +       "cci400_sel",
1743 +       "f_bus_pll1_ck",
1744 +       "f_bus_pll2_ck"
1745 +};
1746 +
1747 +static struct mtk_composite mcu_muxes[] = {
1748 +       /* mp0_pll_divider_cfg */
1749 +       MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
1750 +               9, 2, -1, CLK_IS_CRITICAL),
1751 +       /* mp2_pll_divider_cfg */
1752 +       MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
1753 +               9, 2, -1, CLK_IS_CRITICAL),
1754 +       /* bus_pll_divider_cfg */
1755 +       MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
1756 +               9, 2, -1, CLK_IS_CRITICAL),
1757 +};
1758 +
1759 +static const struct mtk_clk_divider top_adj_divs[] = {
1760 +       DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
1761 +       DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
1762 +       DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
1763 +       DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
1764 +       DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
1765 +       DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
1766 +       DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
1767 +       DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
1768 +};
1769 +
1770 +static const struct mtk_gate_regs top_cg_regs = {
1771 +       .set_ofs = 0x120,
1772 +       .clr_ofs = 0x120,
1773 +       .sta_ofs = 0x120,
1774 +};
1775 +
1776 +#define GATE_TOP(_id, _name, _parent, _shift) {        \
1777 +               .id = _id,                              \
1778 +               .name = _name,                          \
1779 +               .parent_name = _parent,                 \
1780 +               .regs = &top_cg_regs,                   \
1781 +               .shift = _shift,                        \
1782 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
1783 +       }
1784 +
1785 +static const struct mtk_gate top_clks[] = {
1786 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
1787 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
1788 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
1789 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
1790 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
1791 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
1792 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
1793 +       GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
1794 +};
1795 +
1796 +static const struct mtk_gate_regs infra_cg_regs = {
1797 +       .set_ofs = 0x40,
1798 +       .clr_ofs = 0x44,
1799 +       .sta_ofs = 0x40,
1800 +};
1801 +
1802 +#define GATE_INFRA(_id, _name, _parent, _shift) {      \
1803 +               .id = _id,                              \
1804 +               .name = _name,                          \
1805 +               .parent_name = _parent,                 \
1806 +               .regs = &infra_cg_regs,                 \
1807 +               .shift = _shift,                        \
1808 +               .ops = &mtk_clk_gate_ops_setclr,        \
1809 +       }
1810 +
1811 +static const struct mtk_gate infra_clks[] = {
1812 +       GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
1813 +       GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
1814 +       GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
1815 +       GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
1816 +       GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
1817 +       GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
1818 +       GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
1819 +};
1820 +
1821 +static const struct mtk_gate_regs peri0_cg_regs = {
1822 +       .set_ofs = 0x8,
1823 +       .clr_ofs = 0x10,
1824 +       .sta_ofs = 0x18,
1825 +};
1826 +
1827 +static const struct mtk_gate_regs peri1_cg_regs = {
1828 +       .set_ofs = 0xc,
1829 +       .clr_ofs = 0x14,
1830 +       .sta_ofs = 0x1c,
1831 +};
1832 +
1833 +static const struct mtk_gate_regs peri2_cg_regs = {
1834 +       .set_ofs = 0x42c,
1835 +       .clr_ofs = 0x42c,
1836 +       .sta_ofs = 0x42c,
1837 +};
1838 +
1839 +#define GATE_PERI0(_id, _name, _parent, _shift) {      \
1840 +               .id = _id,                              \
1841 +               .name = _name,                          \
1842 +               .parent_name = _parent,                 \
1843 +               .regs = &peri0_cg_regs,                 \
1844 +               .shift = _shift,                        \
1845 +               .ops = &mtk_clk_gate_ops_setclr,        \
1846 +       }
1847 +
1848 +#define GATE_PERI1(_id, _name, _parent, _shift) {      \
1849 +               .id = _id,                              \
1850 +               .name = _name,                          \
1851 +               .parent_name = _parent,                 \
1852 +               .regs = &peri1_cg_regs,                 \
1853 +               .shift = _shift,                        \
1854 +               .ops = &mtk_clk_gate_ops_setclr,        \
1855 +       }
1856 +
1857 +#define GATE_PERI2(_id, _name, _parent, _shift) {      \
1858 +               .id = _id,                              \
1859 +               .name = _name,                          \
1860 +               .parent_name = _parent,                 \
1861 +               .regs = &peri2_cg_regs,                 \
1862 +               .shift = _shift,                        \
1863 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1864 +       }
1865 +
1866 +static const struct mtk_gate peri_clks[] = {
1867 +       /* PERI0 */
1868 +       GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1869 +               "axi_sel", 0),
1870 +       GATE_PERI0(CLK_PERI_THERM, "per_therm",
1871 +               "axi_sel", 1),
1872 +       GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1873 +               "pwm_sel", 2),
1874 +       GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1875 +               "pwm_sel", 3),
1876 +       GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1877 +               "pwm_sel", 4),
1878 +       GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1879 +               "pwm_sel", 5),
1880 +       GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1881 +               "pwm_sel", 6),
1882 +       GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1883 +               "pwm_sel", 7),
1884 +       GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1885 +               "pwm_sel", 8),
1886 +       GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1887 +               "pwm_sel", 9),
1888 +       GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1889 +               "pwm_sel", 10),
1890 +       GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1891 +               "axi_sel", 13),
1892 +       GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1893 +               "msdc50_0_sel", 14),
1894 +       GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1895 +               "msdc30_1_sel", 15),
1896 +       GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1897 +               "msdc30_2_sel", 16),
1898 +       GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1899 +               "msdc30_3_sel", 17),
1900 +       GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1901 +               "uart_sel", 20),
1902 +       GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1903 +               "uart_sel", 21),
1904 +       GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1905 +               "uart_sel", 22),
1906 +       GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1907 +               "uart_sel", 23),
1908 +       GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1909 +               "axi_sel", 24),
1910 +       GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1911 +               "axi_sel", 25),
1912 +       GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1913 +               "axi_sel", 26),
1914 +       GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1915 +               "axi_sel", 27),
1916 +       GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1917 +               "axi_sel", 28),
1918 +       GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1919 +               "ltepll_fs26m", 29),
1920 +       GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1921 +               "spi_sel", 30),
1922 +       /* PERI1 */
1923 +       GATE_PERI1(CLK_PERI_SPI, "per_spi",
1924 +               "spinor_sel", 1),
1925 +       GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1926 +               "axi_sel", 3),
1927 +       GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1928 +               "spi_sel", 5),
1929 +       GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1930 +               "spi_sel", 6),
1931 +       GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1932 +               "spi_sel", 8),
1933 +       GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1934 +               "uart_sel", 9),
1935 +       GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1936 +               "uart_sel", 11),
1937 +       GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1938 +               "uart_sel", 12),
1939 +       GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1940 +               "uart_sel", 14),
1941 +       GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1942 +               "uart_sel", 15),
1943 +       GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1944 +               "uart_sel", 16),
1945 +       /* PERI2 */
1946 +       GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1947 +               "msdc50_0_sel", 0),
1948 +       GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1949 +               "msdc30_1_sel", 1),
1950 +       GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1951 +               "msdc30_2_sel", 2),
1952 +       GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1953 +               "msdc30_3_sel", 3),
1954 +       GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1955 +               "msdc50_0_h_sel", 4),
1956 +       GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1957 +               "msdc50_3_h_sel", 5),
1958 +};
1959 +
1960 +#define MT2712_PLL_FMAX                (3000UL * MHZ)
1961 +
1962 +#define CON0_MT2712_RST_BAR    BIT(24)
1963 +
1964 +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,  \
1965 +                       _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
1966 +                       _tuner_en_bit, _pcw_reg, _pcw_shift,            \
1967 +                       _div_table) {                                   \
1968 +               .id = _id,                                              \
1969 +               .name = _name,                                          \
1970 +               .reg = _reg,                                            \
1971 +               .pwr_reg = _pwr_reg,                                    \
1972 +               .en_mask = _en_mask,                                    \
1973 +               .flags = _flags,                                        \
1974 +               .rst_bar_mask = CON0_MT2712_RST_BAR,                    \
1975 +               .fmax = MT2712_PLL_FMAX,                                \
1976 +               .pcwbits = _pcwbits,                                    \
1977 +               .pd_reg = _pd_reg,                                      \
1978 +               .pd_shift = _pd_shift,                                  \
1979 +               .tuner_reg = _tuner_reg,                                \
1980 +               .tuner_en_reg = _tuner_en_reg,                          \
1981 +               .tuner_en_bit = _tuner_en_bit,                          \
1982 +               .pcw_reg = _pcw_reg,                                    \
1983 +               .pcw_shift = _pcw_shift,                                \
1984 +               .div_table = _div_table,                                \
1985 +       }
1986 +
1987 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,    \
1988 +                       _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
1989 +                       _tuner_en_bit, _pcw_reg, _pcw_shift)            \
1990 +               PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
1991 +                       _pcwbits, _pd_reg, _pd_shift, _tuner_reg,       \
1992 +                       _tuner_en_reg, _tuner_en_bit, _pcw_reg,         \
1993 +                       _pcw_shift, NULL)
1994 +
1995 +static const struct mtk_pll_div_table armca35pll_div_table[] = {
1996 +       { .div = 0, .freq = MT2712_PLL_FMAX },
1997 +       { .div = 1, .freq = 1202500000 },
1998 +       { .div = 2, .freq = 500500000 },
1999 +       { .div = 3, .freq = 315250000 },
2000 +       { .div = 4, .freq = 157625000 },
2001 +       { } /* sentinel */
2002 +};
2003 +
2004 +static const struct mtk_pll_div_table armca72pll_div_table[] = {
2005 +       { .div = 0, .freq = MT2712_PLL_FMAX },
2006 +       { .div = 1, .freq = 994500000 },
2007 +       { .div = 2, .freq = 520000000 },
2008 +       { .div = 3, .freq = 315250000 },
2009 +       { .div = 4, .freq = 157625000 },
2010 +       { } /* sentinel */
2011 +};
2012 +
2013 +static const struct mtk_pll_div_table mmpll_div_table[] = {
2014 +       { .div = 0, .freq = MT2712_PLL_FMAX },
2015 +       { .div = 1, .freq = 1001000000 },
2016 +       { .div = 2, .freq = 601250000 },
2017 +       { .div = 3, .freq = 250250000 },
2018 +       { .div = 4, .freq = 125125000 },
2019 +       { } /* sentinel */
2020 +};
2021 +
2022 +static const struct mtk_pll_data plls[] = {
2023 +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
2024 +               HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
2025 +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
2026 +               HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
2027 +       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
2028 +               0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
2029 +       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
2030 +               0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
2031 +       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
2032 +               0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
2033 +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
2034 +               0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
2035 +       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
2036 +               0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
2037 +       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
2038 +               0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
2039 +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
2040 +               0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
2041 +       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
2042 +               0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
2043 +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
2044 +               0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
2045 +       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
2046 +               0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
2047 +               mmpll_div_table),
2048 +       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
2049 +               HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
2050 +               armca35pll_div_table),
2051 +       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
2052 +               0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
2053 +               armca72pll_div_table),
2054 +       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
2055 +               0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
2056 +};
2057 +
2058 +static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
2059 +{
2060 +       struct clk_onecell_data *clk_data;
2061 +       int r;
2062 +       struct device_node *node = pdev->dev.of_node;
2063 +
2064 +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
2065 +
2066 +       mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
2067 +
2068 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2069 +
2070 +       if (r != 0)
2071 +               pr_err("%s(): could not register clock provider: %d\n",
2072 +                       __func__, r);
2073 +
2074 +       return r;
2075 +}
2076 +
2077 +static struct clk_onecell_data *top_clk_data;
2078 +
2079 +static void clk_mt2712_top_init_early(struct device_node *node)
2080 +{
2081 +       int r, i;
2082 +
2083 +       if (!top_clk_data) {
2084 +               top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
2085 +
2086 +               for (i = 0; i < CLK_TOP_NR_CLK; i++)
2087 +                       top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
2088 +       }
2089 +
2090 +       mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
2091 +                       top_clk_data);
2092 +
2093 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
2094 +       if (r)
2095 +               pr_err("%s(): could not register clock provider: %d\n",
2096 +                       __func__, r);
2097 +}
2098 +
2099 +CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
2100 +                       clk_mt2712_top_init_early);
2101 +
2102 +static int clk_mt2712_top_probe(struct platform_device *pdev)
2103 +{
2104 +       int r, i;
2105 +       struct device_node *node = pdev->dev.of_node;
2106 +       void __iomem *base;
2107 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2108 +
2109 +       base = devm_ioremap_resource(&pdev->dev, res);
2110 +       if (IS_ERR(base)) {
2111 +               pr_err("%s(): ioremap failed\n", __func__);
2112 +               return PTR_ERR(base);
2113 +       }
2114 +
2115 +       if (!top_clk_data) {
2116 +               top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
2117 +       } else {
2118 +               for (i = 0; i < CLK_TOP_NR_CLK; i++) {
2119 +                       if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
2120 +                               top_clk_data->clks[i] = ERR_PTR(-ENOENT);
2121 +               }
2122 +       }
2123 +
2124 +       mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
2125 +                       top_clk_data);
2126 +       mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
2127 +                       top_clk_data);
2128 +       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
2129 +       mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
2130 +                       &mt2712_clk_lock, top_clk_data);
2131 +       mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
2132 +                       &mt2712_clk_lock, top_clk_data);
2133 +       mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
2134 +                       top_clk_data);
2135 +
2136 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
2137 +
2138 +       if (r != 0)
2139 +               pr_err("%s(): could not register clock provider: %d\n",
2140 +                       __func__, r);
2141 +
2142 +       return r;
2143 +}
2144 +
2145 +static int clk_mt2712_infra_probe(struct platform_device *pdev)
2146 +{
2147 +       struct clk_onecell_data *clk_data;
2148 +       int r;
2149 +       struct device_node *node = pdev->dev.of_node;
2150 +
2151 +       clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
2152 +
2153 +       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
2154 +                       clk_data);
2155 +
2156 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2157 +
2158 +       if (r != 0)
2159 +               pr_err("%s(): could not register clock provider: %d\n",
2160 +                       __func__, r);
2161 +
2162 +       mtk_register_reset_controller(node, 2, 0x30);
2163 +
2164 +       return r;
2165 +}
2166 +
2167 +static int clk_mt2712_peri_probe(struct platform_device *pdev)
2168 +{
2169 +       struct clk_onecell_data *clk_data;
2170 +       int r;
2171 +       struct device_node *node = pdev->dev.of_node;
2172 +
2173 +       clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
2174 +
2175 +       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
2176 +                       clk_data);
2177 +
2178 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2179 +
2180 +       if (r != 0)
2181 +               pr_err("%s(): could not register clock provider: %d\n",
2182 +                       __func__, r);
2183 +
2184 +       mtk_register_reset_controller(node, 2, 0);
2185 +
2186 +       return r;
2187 +}
2188 +
2189 +static int clk_mt2712_mcu_probe(struct platform_device *pdev)
2190 +{
2191 +       struct clk_onecell_data *clk_data;
2192 +       int r;
2193 +       struct device_node *node = pdev->dev.of_node;
2194 +       void __iomem *base;
2195 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2196 +
2197 +       base = devm_ioremap_resource(&pdev->dev, res);
2198 +       if (IS_ERR(base)) {
2199 +               pr_err("%s(): ioremap failed\n", __func__);
2200 +               return PTR_ERR(base);
2201 +       }
2202 +
2203 +       clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
2204 +
2205 +       mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
2206 +                       &mt2712_clk_lock, clk_data);
2207 +
2208 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2209 +
2210 +       if (r != 0)
2211 +               pr_err("%s(): could not register clock provider: %d\n",
2212 +                       __func__, r);
2213 +
2214 +       return r;
2215 +}
2216 +
2217 +static const struct of_device_id of_match_clk_mt2712[] = {
2218 +       {
2219 +               .compatible = "mediatek,mt2712-apmixedsys",
2220 +               .data = clk_mt2712_apmixed_probe,
2221 +       }, {
2222 +               .compatible = "mediatek,mt2712-topckgen",
2223 +               .data = clk_mt2712_top_probe,
2224 +       }, {
2225 +               .compatible = "mediatek,mt2712-infracfg",
2226 +               .data = clk_mt2712_infra_probe,
2227 +       }, {
2228 +               .compatible = "mediatek,mt2712-pericfg",
2229 +               .data = clk_mt2712_peri_probe,
2230 +       }, {
2231 +               .compatible = "mediatek,mt2712-mcucfg",
2232 +               .data = clk_mt2712_mcu_probe,
2233 +       }, {
2234 +               /* sentinel */
2235 +       }
2236 +};
2237 +
2238 +static int clk_mt2712_probe(struct platform_device *pdev)
2239 +{
2240 +       int (*clk_probe)(struct platform_device *);
2241 +       int r;
2242 +
2243 +       clk_probe = of_device_get_match_data(&pdev->dev);
2244 +       if (!clk_probe)
2245 +               return -EINVAL;
2246 +
2247 +       r = clk_probe(pdev);
2248 +       if (r != 0)
2249 +               dev_err(&pdev->dev,
2250 +                       "could not register clock provider: %s: %d\n",
2251 +                       pdev->name, r);
2252 +
2253 +       return r;
2254 +}
2255 +
2256 +static struct platform_driver clk_mt2712_drv = {
2257 +       .probe = clk_mt2712_probe,
2258 +       .driver = {
2259 +               .name = "clk-mt2712",
2260 +               .owner = THIS_MODULE,
2261 +               .of_match_table = of_match_clk_mt2712,
2262 +       },
2263 +};
2264 +
2265 +static int __init clk_mt2712_init(void)
2266 +{
2267 +       return platform_driver_register(&clk_mt2712_drv);
2268 +}
2269 +
2270 +arch_initcall(clk_mt2712_init);
2271 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
2272 index f5d6b70ce189..f48df75cc901 100644
2273 --- a/drivers/clk/mediatek/clk-mtk.h
2274 +++ b/drivers/clk/mediatek/clk-mtk.h
2275 @@ -207,6 +207,8 @@ struct mtk_pll_data {
2276         uint32_t en_mask;
2277         uint32_t pd_reg;
2278         uint32_t tuner_reg;
2279 +       uint32_t tuner_en_reg;
2280 +       uint8_t tuner_en_bit;
2281         int pd_shift;
2282         unsigned int flags;
2283         const struct clk_ops *ops;
2284 diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
2285 index a409142e9346..3c546bae6955 100644
2286 --- a/drivers/clk/mediatek/clk-pll.c
2287 +++ b/drivers/clk/mediatek/clk-pll.c
2288 @@ -47,6 +47,7 @@ struct mtk_clk_pll {
2289         void __iomem    *pd_addr;
2290         void __iomem    *pwr_addr;
2291         void __iomem    *tuner_addr;
2292 +       void __iomem    *tuner_en_addr;
2293         void __iomem    *pcw_addr;
2294         const struct mtk_pll_data *data;
2295  };
2296 @@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
2297         r |= pll->data->en_mask;
2298         writel(r, pll->base_addr + REG_CON0);
2299
2300 -       if (pll->tuner_addr) {
2301 +       if (pll->tuner_en_addr) {
2302 +               r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
2303 +               writel(r, pll->tuner_en_addr);
2304 +       } else if (pll->tuner_addr) {
2305                 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
2306                 writel(r, pll->tuner_addr);
2307         }
2308 @@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
2309                 writel(r, pll->base_addr + REG_CON0);
2310         }
2311
2312 -       if (pll->tuner_addr) {
2313 +       if (pll->tuner_en_addr) {
2314 +               r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
2315 +               writel(r, pll->tuner_en_addr);
2316 +       } else if (pll->tuner_addr) {
2317                 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
2318                 writel(r, pll->tuner_addr);
2319         }
2320 @@ -297,6 +304,8 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
2321         pll->pcw_addr = base + data->pcw_reg;
2322         if (data->tuner_reg)
2323                 pll->tuner_addr = base + data->tuner_reg;
2324 +       if (data->tuner_en_reg)
2325 +               pll->tuner_en_addr = base + data->tuner_en_reg;
2326         pll->hw.init = &init;
2327         pll->data = data;
2328
2329 --
2330 2.11.0
2331