2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "mt7622.dtsi"
13 #include "mt6380.dtsi"
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
36 sram-supply = <&mt6380_vm_reg>;
41 compatible = "gpio-keys";
46 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
51 linux,code = <KEY_WPS_BUTTON>;
52 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
57 compatible = "mediatek,mt753x";
58 mediatek,ethsys = <ðsys>;
64 compatible = "gpio-leds";
67 label = "bpi-r64:pio:green";
68 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
69 default-state = "off";
73 label = "bpi-r64:pio:red";
74 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
75 default-state = "off";
80 reg = <0 0x40000000 0 0x40000000>;
83 reg_1p8v: regulator-1p8v {
84 compatible = "regulator-fixed";
85 regulator-name = "fixed-1.8V";
86 regulator-min-microvolt = <1800000>;
87 regulator-max-microvolt = <1800000>;
91 reg_3p3v: regulator-3p3v {
92 compatible = "regulator-fixed";
93 regulator-name = "fixed-3.3V";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
100 reg_5v: regulator-5v {
101 compatible = "regulator-fixed";
102 regulator-name = "fixed-5V";
103 regulator-min-microvolt = <5000000>;
104 regulator-max-microvolt = <5000000>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&irrx_pins>;
127 compatible = "mediatek,eth-mac";
129 phy-mode = "2500base-x";
139 compatible = "mediatek,eth-mac";
151 #address-cells = <1>;
157 mediatek,mdio = <&mdio>;
158 mediatek,portmap = "wllll";
159 mediatek,mdio_master_pinmux = <0>;
160 reset-gpios = <&pio 54 0>;
161 interrupt-parent = <&pio>;
162 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
166 compatible = "mediatek,mt753x-port";
176 compatible = "mediatek,mt753x-port";
187 pinctrl-names = "default";
188 pinctrl-0 = <&i2c1_pins>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&i2c2_pins>;
199 pinctrl-names = "default", "state_uhs";
200 pinctrl-0 = <&emmc_pins_default>;
201 pinctrl-1 = <&emmc_pins_uhs>;
204 max-frequency = <50000000>;
207 vmmc-supply = <®_3p3v>;
208 vqmmc-supply = <®_1p8v>;
209 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
210 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
215 pinctrl-names = "default", "state_uhs";
216 pinctrl-0 = <&sd0_pins_default>;
217 pinctrl-1 = <&sd0_pins_uhs>;
220 max-frequency = <50000000>;
223 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
224 vmmc-supply = <®_3p3v>;
225 vqmmc-supply = <®_3p3v>;
226 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
227 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
231 pinctrl-names = "default";
232 pinctrl-0 = <¶llel_nand_pins>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&spi_nor_pins>;
242 compatible = "jedec,spi-nor";
248 pinctrl-names = "default";
249 pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
262 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
263 * SATA functions. i.e. output-high: PCIe, output-low: SATA
267 gpios = <90 GPIO_ACTIVE_HIGH>;
271 /* eMMC is shared pin with parallel NAND */
272 emmc_pins_default: emmc-pins-default {
274 function = "emmc", "emmc_rst";
278 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
279 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
280 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
283 pins = "NDL0", "NDL1", "NDL2",
284 "NDL3", "NDL4", "NDL5",
285 "NDL6", "NDL7", "NRB";
296 emmc_pins_uhs: emmc-pins-uhs {
303 pins = "NDL0", "NDL1", "NDL2",
304 "NDL3", "NDL4", "NDL5",
305 "NDL6", "NDL7", "NRB";
307 drive-strength = <4>;
313 drive-strength = <4>;
321 groups = "mdc_mdio", "rgmii_via_gmac2";
325 i2c1_pins: i2c1-pins {
332 i2c2_pins: i2c2-pins {
339 i2s1_pins: i2s1-pins {
342 groups = "i2s_out_mclk_bclk_ws",
348 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
349 "I2S_WS", "I2S_MCLK";
350 drive-strength = <12>;
355 irrx_pins: irrx-pins {
362 irtx_pins: irtx-pins {
369 /* Parallel nand is shared pin with eMMC */
370 parallel_nand_pins: parallel-nand-pins {
377 pcie0_pins: pcie0-pins {
380 groups = "pcie0_pad_perst",
386 pcie1_pins: pcie1-pins {
389 groups = "pcie1_pad_perst",
395 pmic_bus_pins: pmic-bus-pins {
402 pwm7_pins: pwm1-2-pins {
405 groups = "pwm_ch7_2";
409 wled_pins: wled-pins {
416 sd0_pins_default: sd0-pins-default {
422 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
423 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
424 * DAT2, DAT3, CMD, CLK for SD respectively.
427 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
428 "I2S2_IN","I2S4_OUT";
430 drive-strength = <8>;
435 drive-strength = <12>;
444 sd0_pins_uhs: sd0-pins-uhs {
451 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
452 "I2S2_IN","I2S4_OUT";
463 /* Serial NAND is shared pin with SPI-NOR */
464 serial_nand_pins: serial-nand-pins {
471 spic0_pins: spic0-pins {
478 spic1_pins: spic1-pins {
485 /* SPI-NOR is shared pin with serial NAND */
486 spi_nor_pins: spi-nor-pins {
493 /* serial NAND is shared pin with SPI-NOR */
494 serial_nand_pins: serial-nand-pins {
501 uart0_pins: uart0-pins {
504 groups = "uart0_0_tx_rx" ;
508 uart2_pins: uart2-pins {
511 groups = "uart2_1_tx_rx" ;
515 watchdog_pins: watchdog-pins {
517 function = "watchdog";
524 pinctrl-names = "default";
525 pinctrl-0 = <&pwm7_pins>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pmic_bus_pins>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&spic0_pins>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&spic1_pins>;
557 vusb33-supply = <®_3p3v>;
558 vbus-supply = <®_5v>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&uart0_pins>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&uart2_pins>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&watchdog_pins>;