target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch

   1 From 62e7f0b553038e3a1a1b2b067dd1fbdacd634e37 Mon Sep 17 00:00:00 2001
   2 From: Robert Jones <rjones@gateworks.com>
   3 Date: Fri, 14 Feb 2020 13:02:41 -0800
   4 Subject: [PATCH] ARM: dts: imx6qdl-gw553x: add lsm9ds1 iio imu/magn support
   5
   6 Add one node for the accel/gyro i2c device and another for the separate
   7 magnetometer device in the lsm9ds1.
   8
   9 Signed-off-by: Robert Jones <rjones@gateworks.com>
  10 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  11 ---
  12  arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 31 +++++++++++++++++++++++++++++++
  13  1 file changed, 31 insertions(+)
  14
  15 diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
  16 index a106689..ee85031 100644
  17 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
  18 +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
  19 @@ -173,6 +173,25 @@
  20         pinctrl-0 = <&pinctrl_i2c2>;
  21         status = "okay";
  22
  23 +       magn@1c {
  24 +               compatible = "st,lsm9ds1-magn";
  25 +               reg = <0x1c>;
  26 +               pinctrl-names = "default";
  27 +               pinctrl-0 = <&pinctrl_mag>;
  28 +               interrupt-parent = <&gpio1>;
  29 +               interrupts = <2 IRQ_TYPE_EDGE_RISING>;
  30 +       };
  31 +
  32 +       imu@6a {
  33 +               compatible = "st,lsm9ds1-imu";
  34 +               reg = <0x6a>;
  35 +               st,drdy-int-pin = <1>;
  36 +               pinctrl-names = "default";
  37 +               pinctrl-0 = <&pinctrl_imu>;
  38 +               interrupt-parent = <&gpio7>;
  39 +               interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
  40 +       };
  41 +
  42         ltc3676: pmic@3c {
  43                 compatible = "lltc,ltc3676";
  44                 reg = <0x3c>;
  45 @@ -426,6 +445,12 @@
  46                 >;
  47         };
  48
  49 +       pinctrl_imu: imugrp {
  50 +               fsl,pins = <
  51 +                       MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
  52 +               >;
  53 +       };
  54 +
  55         pinctrl_ipu1_csi0: ipu1csi0grp {
  56                 fsl,pins = <
  57                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
  58 @@ -449,6 +474,12 @@
  59                 >;
  60         };
  61
  62 +       pinctrl_mag: maggrp {
  63 +               fsl,pins = <
  64 +                       MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
  65 +               >;
  66 +       };
  67 +
  68         pinctrl_pcie: pciegrp {
  69                 fsl,pins = <
  70                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
  71 --
  72 2.7.4
  73