target/linux/generic/pending-4.9/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch

   1 From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Sun, 23 Dec 2018 18:06:53 +0100
   4 Subject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo
   5
   6 Many MIPS CPUs have optional CPU features which are not activates for
   7 all CPU cores. Print the CPU options which are implemented in the core
   8 in /proc/cpuinfo. This makes it possible to see what features are
   9 supported and which are not supported. This should cover all standard
  10 MIPS extensions, before it only printed information about the main MIPS
  11 ASEs.
  12
  13 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  14 ---
  15  arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++
  16  1 file changed, 116 insertions(+)
  17
  18 --- a/arch/mips/kernel/proc.c
  19 +++ b/arch/mips/kernel/proc.c
  20 @@ -128,6 +128,114 @@ static int show_cpuinfo(struct seq_file
  21                 seq_printf(m, "micromips kernel\t: %s\n",
  22                       (read_c0_config3() & MIPS_CONF3_ISA_OE) ?  "yes" : "no");
  23         }
  24 +
  25 +       seq_printf(m, "Options implemented\t:");
  26 +       if (cpu_has_tlb)
  27 +               seq_printf(m, "%s", " tlb");
  28 +       if (cpu_has_ftlb)
  29 +               seq_printf(m, "%s", " ftlb");
  30 +       if (cpu_has_tlbinv)
  31 +               seq_printf(m, "%s", " tlbinv");
  32 +       if (cpu_has_segments)
  33 +               seq_printf(m, "%s", " segments");
  34 +       if (cpu_has_rixiex)
  35 +               seq_printf(m, "%s", " rixiex");
  36 +       if (cpu_has_ldpte)
  37 +               seq_printf(m, "%s", " ldpte");
  38 +       if (cpu_has_maar)
  39 +               seq_printf(m, "%s", " maar");
  40 +       if (cpu_has_rw_llb)
  41 +               seq_printf(m, "%s", " rw_llb");
  42 +       if (cpu_has_4kex)
  43 +               seq_printf(m, "%s", " 4kex");
  44 +       if (cpu_has_3k_cache)
  45 +               seq_printf(m, "%s", " 3k_cache");
  46 +       if (cpu_has_4k_cache)
  47 +               seq_printf(m, "%s", " 4k_cache");
  48 +       if (cpu_has_6k_cache)
  49 +               seq_printf(m, "%s", " 6k_cache");
  50 +       if (cpu_has_8k_cache)
  51 +               seq_printf(m, "%s", " 8k_cache");
  52 +       if (cpu_has_tx39_cache)
  53 +               seq_printf(m, "%s", " tx39_cache");
  54 +       if (cpu_has_octeon_cache)
  55 +               seq_printf(m, "%s", " octeon_cache");
  56 +       if (cpu_has_fpu)
  57 +               seq_printf(m, "%s", " fpu");
  58 +       if (cpu_has_32fpr)
  59 +               seq_printf(m, "%s", " 32fpr");
  60 +       if (cpu_has_cache_cdex_p)
  61 +               seq_printf(m, "%s", " cache_cdex_p");
  62 +       if (cpu_has_cache_cdex_s)
  63 +               seq_printf(m, "%s", " cache_cdex_s");
  64 +       if (cpu_has_prefetch)
  65 +               seq_printf(m, "%s", " prefetch");
  66 +       if (cpu_has_mcheck)
  67 +               seq_printf(m, "%s", " mcheck");
  68 +       if (cpu_has_ejtag)
  69 +               seq_printf(m, "%s", " ejtag");
  70 +       if (cpu_has_llsc)
  71 +               seq_printf(m, "%s", " llsc");
  72 +       if (cpu_has_bp_ghist)
  73 +               seq_printf(m, "%s", " bp_ghist");
  74 +       if (cpu_has_guestctl0ext)
  75 +               seq_printf(m, "%s", " guestctl0ext");
  76 +       if (cpu_has_guestctl1)
  77 +               seq_printf(m, "%s", " guestctl1");
  78 +       if (cpu_has_guestctl2)
  79 +               seq_printf(m, "%s", " guestctl2");
  80 +       if (cpu_has_guestid)
  81 +               seq_printf(m, "%s", " guestid");
  82 +       if (cpu_has_drg)
  83 +               seq_printf(m, "%s", " drg");
  84 +       if (cpu_has_rixi)
  85 +               seq_printf(m, "%s", " rixi");
  86 +       if (cpu_has_lpa)
  87 +               seq_printf(m, "%s", " lpa");
  88 +       if (cpu_has_mvh)
  89 +               seq_printf(m, "%s", " mvh");
  90 +       if (cpu_has_vtag_icache)
  91 +               seq_printf(m, "%s", " vtag_icache");
  92 +       if (cpu_has_dc_aliases)
  93 +               seq_printf(m, "%s", " dc_aliases");
  94 +       if (cpu_has_ic_fills_f_dc)
  95 +               seq_printf(m, "%s", " ic_fills_f_dc");
  96 +       if (cpu_has_pindexed_dcache)
  97 +               seq_printf(m, "%s", " pindexed_dcache");
  98 +       if (cpu_has_userlocal)
  99 +               seq_printf(m, "%s", " userlocal");
 100 +       if (cpu_has_nofpuex)
 101 +               seq_printf(m, "%s", " nofpuex");
 102 +       if (cpu_has_vint)
 103 +               seq_printf(m, "%s", " vint");
 104 +       if (cpu_has_veic)
 105 +               seq_printf(m, "%s", " veic");
 106 +       if (cpu_has_inclusive_pcaches)
 107 +               seq_printf(m, "%s", " inclusive_pcaches");
 108 +       if (cpu_has_perf_cntr_intr_bit)
 109 +               seq_printf(m, "%s", " perf_cntr_intr_bit");
 110 +       if (cpu_has_fre)
 111 +               seq_printf(m, "%s", " fre");
 112 +       if (cpu_has_cdmm)
 113 +               seq_printf(m, "%s", " cdmm");
 114 +       if (cpu_has_small_pages)
 115 +               seq_printf(m, "%s", " small_pages");
 116 +       if (cpu_has_nan_legacy)
 117 +               seq_printf(m, "%s", " nan_legacy");
 118 +       if (cpu_has_nan_2008)
 119 +               seq_printf(m, "%s", " nan_2008");
 120 +       if (cpu_has_ebase_wg)
 121 +               seq_printf(m, "%s", " ebase_wg");
 122 +       if (cpu_has_badinstr)
 123 +               seq_printf(m, "%s", " badinstr");
 124 +       if (cpu_has_badinstrp)
 125 +               seq_printf(m, "%s", " badinstrp");
 126 +       if (cpu_has_contextconfig)
 127 +               seq_printf(m, "%s", " contextconfig");
 128 +       if (cpu_has_perf)
 129 +               seq_printf(m, "%s", " perf");
 130 +       seq_printf(m, "\n");
 131 +
 132         seq_printf(m, "shadow register sets\t: %d\n",
 133                       cpu_data[n].srsets);
 134         seq_printf(m, "kscratch registers\t: %d\n",