target/linux/brcm2708/patches-4.19/950-0296-usb-dwc_otg-Clean-up-build-warnings-on-64bit-kernels.patch

   1 From d2536830d8f1ef06afdc84c5ac6e1a70b3a2bc40 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.org>
   3 Date: Fri, 25 Jan 2019 16:03:31 +0000
   4 Subject: [PATCH] usb: dwc_otg: Clean up build warnings on 64bit
   5  kernels
   6
   7 No functional changes. Almost all are changes to logging lines.
   8
   9 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
  10 ---
  11  drivers/usb/host/dwc_otg/dwc_otg_driver.c    |  3 +--
  12  drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c   |  2 +-
  13  drivers/usb/host/dwc_otg/dwc_otg_hcd.c       | 19 ++++++++++++++-----
  14  drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 10 ++++------
  15  4 files changed, 20 insertions(+), 14 deletions(-)
  16
  17 --- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c
  18 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
  19 @@ -837,8 +837,7 @@ static int dwc_otg_driver_probe(
  20                 retval = -ENOMEM;
  21                 goto fail;
  22         }
  23 -       dev_info(&_dev->dev, "base=0x%08x\n",
  24 -                (unsigned)dwc_otg_device->os_dep.base);
  25 +       dev_info(&_dev->dev, "base=%p\n", dwc_otg_device->os_dep.base);
  26  #endif
  27
  28         /*
  29 --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  30 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  31 @@ -301,7 +301,7 @@ static int notrace fiq_iso_out_advance(s
  32                 last = 1;
  33
  34         /* New DMA address - address of bounce buffer referred to in index */
  35 -       hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
  36 +       hcdma.d32 = (dma_addr_t) blob->channel[n].index[i].buf;
  37         //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
  38         //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
  39         fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
  40 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
  41 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
  42 @@ -1041,8 +1041,8 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd
  43                  * moderately readable array casts.
  44                  */
  45                 hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
  46 -               DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
  47 -                               (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
  48 +               DWC_WARN("FIQ DMA bounce buffers: virt = %px dma = %pad len=%zu",
  49 +                               hcd->fiq_dmab, &hcd->fiq_state->dma_base,
  50                                 sizeof(struct fiq_dma_channel) * num_channels);
  51
  52                 DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
  53 @@ -1522,9 +1522,12 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
  54                 /*
  55                  * Set dma_regs to bounce buffer. FIQ will update the
  56                  * state depending on transaction progress.
  57 +                * Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)
  58 +                * to point it to the correct offset in the allocated buffers.
  59                  */
  60                 blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
  61 -               st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
  62 +               st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
  63 +
  64                 /* Calculate the max number of CSPLITS such that the FIQ can time out
  65                  * a transaction if it fails.
  66                  */
  67 @@ -1571,9 +1574,15 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
  68                                 st->nrpackets = i;
  69                         }
  70                         ptr = qtd->urb->buf + frame_desc->offset;
  71 -                       /* Point the HC at the DMA address of the bounce buffers */
  72 +                       /*
  73 +                        * Point the HC at the DMA address of the bounce buffers
  74 +                        *
  75 +                        * Pointer arithmetic on hcd->fiq_state->dma_base (a
  76 +                        * dma_addr_t) to point it to the correct offset in the
  77 +                        * allocated buffers.
  78 +                        */
  79                         blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
  80 -                       st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
  81 +                       st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
  82
  83                         /* fixup xfersize to the actual packet size */
  84                         st->hctsiz_copy.b.pid = 0;
  85 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
  86 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
  87 @@ -454,11 +454,9 @@ static void hcd_init_fiq(void *cookie)
  88                 DWC_ERROR("Can't claim FIQ");
  89                 BUG();
  90         }
  91 -       DWC_WARN("FIQ on core %d at 0x%08x",
  92 -                               smp_processor_id(),
  93 -                               (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
  94 -       DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
  95 -               set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
  96 +       DWC_WARN("FIQ on core %d", smp_processor_id());
  97 +       DWC_WARN("FIQ ASM at %px length %d", &_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
  98 +       set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
  99         memset(&regs,0,sizeof(regs));
 100
 101         regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
 102 @@ -483,7 +481,7 @@ static void hcd_init_fiq(void *cookie)
 103         dwc_otg_hcd->fiq_state->mphi_regs.outddb  = otg_dev->os_dep.mphi_base + 0x2c;
 104         dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
 105         dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
 106 -       DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
 107 +       DWC_WARN("MPHI regs_base at %px", dwc_otg_hcd->fiq_state->mphi_regs.base);
 108         //Enable mphi peripheral
 109         writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
 110  #ifdef DEBUG