target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/input/input.h>
   5
   6 #include "ar9344.dtsi"
   7
   8 / {
   9         keys {
  10                 compatible = "gpio-keys";
  11
  12                 reset {
  13                         linux,code = <KEY_RESTART>;
  14                         gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  15                         debounce-interval = <60>;
  16                 };
  17
  18                 wps {
  19                         linux,code = <KEY_WPS_BUTTON>;
  20                         gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
  21                         debounce-interval = <60>;
  22                 };
  23         };
  24 };
  25
  26 &eth0 {
  27         status = "okay";
  28
  29         /* default for ar934x, except for 1000M */
  30         pll-data = <0x06000000 0x00000101 0x00001616>;
  31
  32         phy-mode = "rgmii";
  33         phy-handle = <&phy0>;
  34 };
  35
  36 &mdio0 {
  37         status = "okay";
  38
  39         phy-mask = <0>;
  40
  41         phy0: ethernet-phy@0 {
  42                 reg = <0>;
  43                 qca,ar8327-initvals = <
  44                         /* GPL code drop (bsp.h & athrs17_phy.c) */
  45                         0x10 0xc1000000 /* PWS_REG_VALUE */
  46                         0x04 0x07600000 /* PORT0 PAD Mode */
  47                         0x0c 0x01000000 /* PORT6 PAD Mode */
  48                         0x7c 0x0000007e /* PORT0_STATUS */
  49                         0x94 0x0000007e /* PORT6_STATUS */
  50                 >;
  51         };
  52 };
  53
  54 &pcie {
  55         status = "okay";
  56
  57         ath9k: wifi@0,0 {
  58                 compatible = "pci168c,0030";
  59                 reg = <0x0000 0 0 0 0>;
  60                 qca,no-eeprom;
  61                 gpio-controller;
  62                 #gpio-cells = <2>;
  63         };
  64 };
  65
  66 &ref {
  67         clock-frequency = <40000000>;
  68 };
  69
  70 &spi {
  71         status = "okay";
  72         num-cs = <1>;
  73
  74         flash@0 {
  75                 compatible = "jedec,spi-nor";
  76                 reg = <0>;
  77                 spi-max-frequency = <25000000>;
  78
  79                 partitions {
  80                         compatible = "fixed-partitions";
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83
  84                         partition@0 {
  85                                 label = "uboot";
  86                                 reg = <0x000000 0x010000>;
  87                                 read-only;
  88                         };
  89
  90                         partition@10000 {
  91                                 label = "nvram";
  92                                 reg = <0x010000 0x010000>;
  93                                 read-only;
  94                         };
  95
  96                         partition@20000 {
  97                                 label = "firmware";
  98                                 reg = <0x020000 0xF90000>;
  99                                 compatible = "denx,uimage";
 100                         };
 101
 102                         partition@fb0000 {
 103                                 label = "lang";
 104                                 reg = <0xfb0000 0x030000>;
 105                                 read-only;
 106                         };
 107
 108                         partition@fe0000 {
 109                                 label = "mac";
 110                                 reg = <0xfe0000 0x010000>;
 111                                 read-only;
 112                         };
 113
 114                         partition@ff0000 {
 115                                 label = "art";
 116                                 reg = <0xff0000 0x010000>;
 117                                 read-only;
 118                         };
 119                 };
 120         };
 121 };
 122
 123 &uart {
 124         status = "okay";
 125 };
 126
 127 &usb {
 128         status = "okay";
 129         #address-cells = <1>;
 130         #size-cells = <0>;
 131
 132         hub_port1: port@1 {
 133                 reg = <1>;
 134                 #trigger-source-cells = <0>;
 135         };
 136 };
 137
 138 &usb_phy {
 139         status = "okay";
 140 };
 141
 142 &wmac {
 143         status = "okay";
 144         qca,no-eeprom;
 145 };