2 * NAND flash driver for the MikroTik RouterBOARD 91x series
4 * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/spinlock.h>
13 #include <linux/module.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/gpio.h>
21 #include <linux/platform_data/rb91x_nand.h>
22 #include <linux/version.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/ath79.h>
27 #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
29 #define RB91X_NAND_NRWE BIT(12)
31 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
32 BIT(13) | BIT(14) | BIT(15))
34 #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
35 #define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
37 #define RB91X_NAND_LOW_DATA_MASK 0x1f
38 #define RB91X_NAND_HIGH_DATA_MASK 0xe0
39 #define RB91X_NAND_HIGH_DATA_SHIFT 8
41 struct rb91x_nand_info {
42 struct nand_chip chip;
43 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
57 static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
59 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
60 return container_of(mtd, struct rb91x_nand_info, mtd);
62 struct nand_chip *chip = mtd_to_nand(mtd);
64 return container_of(chip, struct rb91x_nand_info, chip);
68 static struct mtd_info *rbinfo_to_mtd(struct rb91x_nand_info *nfc)
70 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
73 return nand_to_mtd(&nfc->chip);
78 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
80 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
81 * will not be able to find the kernel that we load.
83 static struct nand_ecclayout rb91x_nand_ecclayout = {
85 .eccpos = { 8, 9, 10, 13, 14, 15 },
87 .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
92 static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
93 struct mtd_oob_region *oobregion)
97 oobregion->offset = 8;
98 oobregion->length = 3;
101 oobregion->offset = 13;
102 oobregion->length = 3;
109 static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
110 struct mtd_oob_region *oobregion)
114 oobregion->offset = 0;
115 oobregion->length = 4;
118 oobregion->offset = 4;
119 oobregion->length = 1;
122 oobregion->offset = 6;
123 oobregion->length = 2;
126 oobregion->offset = 11;
127 oobregion->length = 2;
134 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
135 .ecc = rb91x_ooblayout_ecc,
136 .free = rb91x_ooblayout_free,
140 static struct mtd_partition rb91x_nand_partitions[] = {
144 .size = (256 * 1024),
145 .mask_flags = MTD_WRITEABLE,
148 .offset = (256 * 1024),
149 .size = (4 * 1024 * 1024) - (256 * 1024),
152 .offset = MTDPART_OFS_NXTBLK,
153 .size = MTDPART_SIZ_FULL,
157 static void rb91x_nand_write(struct rb91x_nand_info *rbni,
161 void __iomem *base = ath79_gpio_base;
167 /* enable the latch */
168 gpio_set_value_cansleep(rbni->gpio_nle, 0);
170 oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
171 out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
173 /* set data lines to output mode */
174 __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
175 base + AR71XX_GPIO_REG_OE);
177 out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
178 for (i = 0; i != len; i++) {
181 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
182 RB91X_NAND_HIGH_DATA_SHIFT;
183 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
185 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
187 /* deactivate WE line */
188 data |= RB91X_NAND_NRWE;
189 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
191 __raw_readl(base + AR71XX_GPIO_REG_OUT);
194 /* restore registers */
195 __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
196 __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
198 __raw_readl(base + AR71XX_GPIO_REG_OUT);
200 /* disable the latch */
201 gpio_set_value_cansleep(rbni->gpio_nle, 1);
204 static void rb91x_nand_read(struct rb91x_nand_info *rbni,
208 void __iomem *base = ath79_gpio_base;
213 /* enable read mode */
214 gpio_set_value_cansleep(rbni->gpio_read, 1);
217 gpio_set_value_cansleep(rbni->gpio_nle, 0);
220 oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
221 out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
223 /* set data lines to input mode */
224 __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
225 base + AR71XX_GPIO_REG_OE);
227 for (i = 0; i < len; i++) {
231 /* activate RE line */
232 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
234 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
236 /* read input lines */
237 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
239 /* deactivate RE line */
240 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
242 data = (in & RB91X_NAND_LOW_DATA_MASK);
243 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
244 RB91X_NAND_HIGH_DATA_MASK;
249 /* restore registers */
250 __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
251 __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
253 __raw_readl(base + AR71XX_GPIO_REG_OUT);
256 gpio_set_value_cansleep(rbni->gpio_nle, 1);
258 /* disable read mode */
259 gpio_set_value_cansleep(rbni->gpio_read, 0);
262 static int rb91x_nand_dev_ready(struct mtd_info *mtd)
264 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
266 return gpio_get_value_cansleep(rbni->gpio_rdy);
269 static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
272 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
274 if (ctrl & NAND_CTRL_CHANGE) {
275 gpio_set_value_cansleep(rbni->gpio_cle,
276 (ctrl & NAND_CLE) ? 1 : 0);
277 gpio_set_value_cansleep(rbni->gpio_ale,
278 (ctrl & NAND_ALE) ? 1 : 0);
279 gpio_set_value_cansleep(rbni->gpio_nce,
280 (ctrl & NAND_NCE) ? 0 : 1);
283 if (cmd != NAND_CMD_NONE) {
286 rb91x_nand_write(rbni, &t, 1);
290 static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
292 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
295 rb91x_nand_read(rbni, &data, 1);
300 static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
302 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
304 rb91x_nand_read(rbni, buf, len);
307 static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
309 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
311 rb91x_nand_write(rbni, buf, len);
314 static int rb91x_nand_gpio_init(struct rb91x_nand_info *info)
319 * Ensure that the LATCH is disabled before initializing
322 ret = devm_gpio_request_one(info->dev, info->gpio_nle,
323 GPIOF_OUT_INIT_HIGH, "LATCH enable");
327 ret = devm_gpio_request_one(info->dev, info->gpio_nce,
328 GPIOF_OUT_INIT_HIGH, "NAND nCE");
332 ret = devm_gpio_request_one(info->dev, info->gpio_nrw,
333 GPIOF_OUT_INIT_HIGH, "NAND nRW");
337 ret = devm_gpio_request_one(info->dev, info->gpio_cle,
338 GPIOF_OUT_INIT_LOW, "NAND CLE");
342 ret = devm_gpio_request_one(info->dev, info->gpio_ale,
343 GPIOF_OUT_INIT_LOW, "NAND ALE");
347 ret = devm_gpio_request_one(info->dev, info->gpio_read,
348 GPIOF_OUT_INIT_LOW, "NAND READ");
352 ret = devm_gpio_request_one(info->dev, info->gpio_rdy,
353 GPIOF_IN, "NAND RDY");
357 static int rb91x_nand_probe(struct platform_device *pdev)
359 struct rb91x_nand_info *rbni;
360 struct rb91x_nand_platform_data *pdata;
361 struct mtd_info *mtd;
364 pr_info(DRV_DESC "\n");
366 pdata = dev_get_platdata(&pdev->dev);
370 rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL);
374 rbni->dev = &pdev->dev;
375 rbni->gpio_nce = pdata->gpio_nce;
376 rbni->gpio_ale = pdata->gpio_ale;
377 rbni->gpio_cle = pdata->gpio_cle;
378 rbni->gpio_read = pdata->gpio_read;
379 rbni->gpio_nrw = pdata->gpio_nrw;
380 rbni->gpio_rdy = pdata->gpio_rdy;
381 rbni->gpio_nle = pdata->gpio_nle;
383 rbni->chip.priv = &rbni;
384 mtd = rbinfo_to_mtd(rbni);
386 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
387 mtd->priv = &rbni->chip;
389 mtd->owner = THIS_MODULE;
391 rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl;
392 rbni->chip.dev_ready = rb91x_nand_dev_ready;
393 rbni->chip.read_byte = rb91x_nand_read_byte;
394 rbni->chip.write_buf = rb91x_nand_write_buf;
395 rbni->chip.read_buf = rb91x_nand_read_buf;
397 rbni->chip.chip_delay = 25;
398 rbni->chip.ecc.mode = NAND_ECC_SOFT;
399 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
400 rbni->chip.ecc.algo = NAND_ECC_HAMMING;
402 rbni->chip.options = NAND_NO_SUBPAGE_WRITE;
404 platform_set_drvdata(pdev, rbni);
406 ret = rb91x_nand_gpio_init(rbni);
410 ret = nand_scan_ident(mtd, 1, NULL);
414 if (mtd->writesize == 512)
415 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
416 rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
418 mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
421 ret = nand_scan_tail(mtd);
425 ret = mtd_device_register(mtd, rb91x_nand_partitions,
426 ARRAY_SIZE(rb91x_nand_partitions));
428 goto err_release_nand;
437 static int rb91x_nand_remove(struct platform_device *pdev)
439 struct rb91x_nand_info *info = platform_get_drvdata(pdev);
441 nand_release(rbinfo_to_mtd(info));
446 static struct platform_driver rb91x_nand_driver = {
447 .probe = rb91x_nand_probe,
448 .remove = rb91x_nand_remove,
450 .name = RB91X_NAND_DRIVER_NAME,
451 .owner = THIS_MODULE,
455 module_platform_driver(rb91x_nand_driver);
457 MODULE_DESCRIPTION(DRV_DESC);
458 MODULE_VERSION(DRV_VERSION);
459 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
460 MODULE_LICENSE("GPL v2");