Assumptions made on source code:
-* looks like USB block is [FUSB200](http://www.faraday-tech.com/techDocument/FUSB200_ProductBrief_v1_2.pdf).
-* We have 15 Enddpoints and 15 FIFO buffers.
-* **FIFO0 - FIFO13, 512 Byte each? FIFO14 - FIFO15 - 64 Byte each?**
+* looks like USB block is Faraday [FUSB200](http://www.faraday-tech.com/techDocument/FUSB200_ProductBrief_v1_2.pdf).
+* We have 15 Endpoints and 15 FIFO buffers.
+* **FIFO0 - FIFO13, 512 Byte each. FIFO14 - FIFO15 - 64 Byte each.**
+* location of usb descriptor target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.c
+
+# EP layout vs software/reg layout
+Default
+* EP 1 OUT; Bulk; = LP (Low priority downstream); RX0;
+* EP 2 IN; Bulk; = US (upstream)
+* EP 3 IN; Interrupt;
+* EP 4 OUT; Interrupt;
+* EP 5 OUT; Bulk; = HP (High priority downstream); RX1;
+* EP 6 OUT; Bulk; = MP (Medium priority downstream); RX2;
+
# 0x00 ZM_MAIN_CTRL_OFFSET
-* BIT7
+* BIT7 - Forced to be Full-Speed Mod?
* BIT6 - 1 = HighSpeed is set (read only?)
-* BIT5
-* BIT4
-* BIT3
-* BIT2 - 1 = enable global Int
-* BIT1
-* BIT0 - 1 = set Remote Wake Up;
+* BIT5 - Chip Enable
+* BIT4 - Chip Software Rese
+* BIT3 - Enter Suspend Mode
+* BIT2 - Enable global Int
+* BIT1 - Half speed mode for FPGA test
+* BIT0 - Enable remote wake-up;
# 0x01 ZM_DEVICE_ADDRESS_OFFSET
-* BIT7 - usb config? (r/w)
+* BIT7 - SET_CONFIGURATION has been executed
* BIT6
* BIT5
* BIT4
* BIT0
# 0x02 ZM_TEST_OFFSET
-* BIT0 - 1 ?? set on usb 2.0 init
+* BIT6 - Do not generate SOF
+* BIT5 - Enter Test Mode
+* BIT4 - Do not toggle sequence
+* BIT3 - Do not append CRC
+* BIT2 - Clear External Side Address
+* BIT1 - EP0 loopback test
+* BIT0 - 1 ?? set on usb 2.0 init. Clear FIFO
# 0x08 ZM_PHY_TEST_SELECT_OFFSET
* BIT7
* BIT6
* BIT5
* BIT4 - TEST_PKY - Test packed.
-* BIT3 - TEST_SE0_NAK
-* BIT2 - TEST_K
-* BIT1 - TEST_J
-* BIT0
+* BIT3 - TEST_SE0_NAK. High-Speed quiescent state.
+* BIT2 - TEST_K, High-Speed K state
+* BIT1 - TEST_J, High-Speed J state
+* BIT0 - Enable soft-detachment
According to FUSB200 doc:
DM(D-) DP(D+) Description
# 0x0B ZM_CX_CONFIG_STATUS_OFFSET
* BIT7
-* BIT6 - EP0 tx stall
-* BIT5 - indicator that frame was transmitted.
-* BIT4
-* BIT3 - set to drom the fram?
-* BIT2 - set CX_STL to stall Endpoint0 & will also clear FIFO0
-* BIT1 -
-* BIT0 - set CX_DONE to indicate the transmistion of control frame
+* BIT6 -
+* BIT5 - CX FIFO empty
+* BIT4 - CX FIFO full
+* BIT3 - CX FIFO clear
+* BIT2 - set CX_STL, CX data stalled
+* BIT1 - Test packet data transfer finished
+* BIT0 - set CX_DONE, CX data transfer finished
# 0x0C ZM_EP0_DATA_OFFSET
* Write 32bit data to fifo
# 0x21 ZM_INTR_SOURCE_0_OFFSET
* BIT7 - abort interrupt? should be cleared first?
* BIT6 -
-* BIT5 -
-* BIT4 - ep0 CMD_FAIL
-* BIT3 - ep0 CMD_END
-* BIT2 - USB EP0 OUT/rx interrupt
-* BIT1 - USB EP0 IN/tx interrupt
-* BIT0 - ep0 SETUP
-
-# 0x22 ZM_INTR_SOURCE_1_OFFSET
-# 0x23 ZM_INTR_SOURCE_2_OFFSET
-# 0x24 ZM_INTR_SOURCE_3_OFFSET
-# 0x25 ZM_INTR_SOURCE_4_OFFSET
-* BIT7 - End of data.
-* BIT6 - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out.
-Comments: we can read only 64bytes per time. If pending data is less then 64bytes or it is end of packet, then BIT6 and BIT7 will be set. If not, then only BIT6 is set.
-
-# 0x26 ZM_INTR_SOURCE_5_OFFSET
-these endpoints are handled by DMA
-
-# 0x27 ZM_INTR_SOURCE_6_OFFSET
-* BIT6 - vUsb_Status_In()?
+* BIT5 - (abort int on fotg210, may be here too?)
+* BIT4 - ep0 CMD_FAIL (error)
+* BIT3 - ep0 CMD_END
+* BIT2 - EP0-OUT packet
+* BIT1 - EP0-IN packet
+* BIT0 - EP0-SETUP packet
+
+# 0x22 - 0x25 ZM_INTR_SOURCE_1_OFFSET (FIFOx OUT)
+....
+* BIT1 - FIFO0 OUT - short packet
+* BIT0 - FIFO0 OUT - data
+
+### 0x25 ZM_INTR_SOURCE_4_OFFSET
+* BIT7 - FIFO15 OUT - short packet.
+* BIT6 - FIFO15 OUT - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out.
+* BIT4 - FIFO14 OUT
+* BIT2 - FIFO13 OUT
+* BIT0 - FIFO12 OUT
+
+# 0x26 - 0x27 ZM_INTR_SOURCE_5_OFFSET (FIFOx IN)
+* BIT1 - FIFO1 IN
+* BIT0 - FIFO0 IN
+
+### 0x27 ZM_INTR_SOURCE_6_OFFSET
+* BIT6 - FIFO14 IN - vUsb_Status_In()
# 0x28 ZM_INTR_SOURCE_7_OFFSET
-* BIT7
-* BIT6
-* BIT5
-* BIT4
+* BIT11 - device wake up
+* BIT10 - device idle
+* BIT9 - DMA error
+* BIT8 - DMA finnished
+* BIT7 - RX0BTYE_INT - Zero-Length-Packet Rx
+* BIT6 - TX0BTYE_INT - Zero-Length-Packet Tx
+* BIT5 - ISO seq abort
+* BIT4 - ISO seq error
* BIT3 - USB resume
* BIT2 - USB suspend
* BIT1 - USB reset interrupt.
-* BIT0
+
+comment: not matching layout with fotg210.. some thing wrong?
# 0x2F mUsbEPMap EP0
code use: ZM_FUSB_BASE+0x30+(EPn-1)
(0x0F | FIFOn << 4) = OUT
-(0xF0 | FIFOn) = IN
+(0xF0 | FIFOn) = IN
+**probably incorrect interpretation. It should be FUSB_REG_IDLE_CNT
+ set suspend delay in ms**
for FIFOn see mUsbFIFOMap registers.
* 0x3b 0x00
* 0x3c 0x00
* 0x3d 0x00
-* 0x3e 0x00
# 0x30 mUsbEPMap EP1
# 0x31 mUsbEPMap EP2
# 0x3b mUsbEPMap EP12
# 0x3c mUsbEPMap EP13
# 0x3d mUsbEPMap EP14
-# 0x3e mUsbEPMap EP15
# 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP0
* BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)
+Current configuration:
+* 0x3e 0x00
+* 0x40 0x00
+* 0x42 0x00
+* 0x44 0x40
+* 0x46 0x00
+* 0x48 0x00
+* 0x4a 0x00
+* 0x4c 0x00
+* 0x4e 0x00
+* 0x50 0x00
+* 0x52 0x00
+* 0x54 0x00
+* 0x56 0x00
+* 0x58 0x00
+* 0x5a 0x00
+* 0x5c 0x00
+
+
# 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET EP0
* BIT7
* BIT6
These offset + 2 Byte step for each endpoint.
For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
+* 0x3f 0x00
+* 0x41 0x02
+* 0x43 0x22
+* 0x45 0x20
+* 0x47 0x02
+* 0x49 0x02
+* 0x4b 0x02
+* 0x4d 0x00
+* 0x4f 0x00
+* 0x51 0x00
+* 0x53 0x00
+* 0x55 0x00
+* 0x57 0x00
+* 0x59 0x00
+* 0x5b 0x00
+* 0x5d 0x00
# 0x40 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP1
# 0x42 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP2
# 0x9e mUsbFIFOConfig FIFO14
# 0x9f mUsbFIFOConfig FIFO15
-# 0xAE ZM_EP3_BYTE_COUNT_HIGH_OFFSET
+# 0xa0 FUSB_REG_FIFO0_INS
+* BIT0 - BIT2 - high offset of byte count in fifo.
+
+# 0xa1 FUSB_REG_FIFO1_INS
+# 0xa2 FUSB_REG_FIFO2_INS
+# 0xa3 FUSB_REG_FIFO3_INS
+# 0xa4 FUSB_REG_FIFO4_INS
+# 0xa5 FUSB_REG_FIFO5_INS
+# 0xa6 FUSB_REG_FIFO6_INS
+# 0xa7 FUSB_REG_FIFO7_INS
+# 0xa8 FUSB_REG_FIFO8_INS
+# 0xa9 FUSB_REG_FIFO9_INS
+# 0xaa FUSB_REG_FIFO10_INS
+# 0xab FUSB_REG_FIFO11_INS
+# 0xac FUSB_REG_FIFO12_INS
+# 0xad FUSB_REG_FIFO13_INS
+# 0xae FUSB_REG_FIFO14_INS
+or known as ZM_EP3_BYTE_COUNT_HIGH_OFFSET
BIT3 - 1 xfer done?
comments: after sending data from target to host, set BIT3
-# 0xAF ZM_EP4_BYTE_COUNT_HIGH_OFFSET
+# 0xaf FUSB_REG_FIFO15_INS
+or known ZM_EP4_BYTE_COUNT_HIGH_OFFSET
BIT4 - 1 - reset fifo; 0 - disable reset?
comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET.
**These name reg do not fit to pattern!!!** Compare with 0x3e, 0x3f and 0x5e, 0x5f.
If we have 0x3e, 0x3f and 0x5e, 0x5f, why do we need this register?
-# 0xBE ZM_EP3_BYTE_COUNT_LOW_OFFSET
+# 0xb0 FUSB_REG_FIFO0_BCNT
+# 0xb1 FUSB_REG_FIFO1_BCNT
+# 0xb2 FUSB_REG_FIFO2_BCNT
+# 0xb3 FUSB_REG_FIFO3_BCNT
+# 0xb4 FUSB_REG_FIFO4_BCNT
+# 0xb5 FUSB_REG_FIFO5_BCNT
+# 0xb6 FUSB_REG_FIFO6_BCNT
+# 0xb7 FUSB_REG_FIFO7_BCNT
+# 0xb8 FUSB_REG_FIFO8_BCNT
+# 0xb9 FUSB_REG_FIFO9_BCNT
+# 0xba FUSB_REG_FIFO10_BCNT
+# 0xbb FUSB_REG_FIFO11_BCNT
+# 0xbc FUSB_REG_FIFO12_BCNT
+# 0xbd FUSB_REG_FIFO13_BCNT
+# 0xbe FUSB_REG_FIFO14_BCNT
+or known as ZM_EP3_BYTE_COUNT_LOW_OFFSET
size of data in fifo buffer? never used?
-# 0xBF ZM_EP4_BYTE_COUNT_LOW_OFFSET
+# 0xbf FUSB_REG_FIFO15_BCNT
+or known as ZM_EP4_BYTE_COUNT_LOW_OFFSET
size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.
# 0xc0 FIFO0 DATA OFFSET?
+or known as FUSB_REG_FIFO0_DP
+
# 0xc4 FIFO1 DATA OFFSET?
# 0xc8 FIFO2 DATA OFFSET?
# 0xcc FIFO3 DATA OFFSET?
# 0x114 ZM_SOC_USB_TIME_CTRL_OFFSET
set stream mode timeout critirea. the unit is 32 USB (30Mhz) clock cycles.
+# 0x118 ZM_SOC_USB_DMA_RESET_OFFSET
+ BIT0 - reset usb dma.
+
# 0x1f0 ZM_CBUS_CTRL_REG
projects / librecmc / open-ath9k-htc-firmware.wiki.git / blobdiff