Updated usb regs (markdown)

[librecmc/open-ath9k-htc-firmware.wiki.git] / usb-regs.md

diff --git a/usb-regs.md b/usb-regs.md
index 48a0e042d2e8bf15294e92bcb63da292a14034b0..1886c81f02e3b23b62c1554c474c6c688fab69d9 100644 (file)
--- a/usb-regs.md
+++ b/usb-regs.md
@@ -62,6 +62,8 @@ DM(D-) DP(D+) Description
 * Write 32bit data to fifo
 
 # 0x11 ZM_INTR_MASK_BYTE_0_OFFSET
+Theoretically INTR_MASK_BYTE should control INTR_SOURCE. Is it correct?
+
 # 0x12 ZM_INTR_MASK_BYTE_1_OFFSET
 USB OUT FIFO
 
@@ -116,7 +118,9 @@ These bits indicate if fallowing groups got some interrupt.
 # 0x23 ZM_INTR_SOURCE_2_OFFSET
 # 0x24 ZM_INTR_SOURCE_3_OFFSET
 # 0x25 ZM_INTR_SOURCE_4_OFFSET
-* BIT6 - vUsb_Reg_Out()?
+* BIT7 - End of data.
+* BIT6 - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out.
+Comments: we can read only 64bytes per time. If pending data is less then 64bytes or it is end of packet, then BIT6 and BIT7 will be set. If not, then only BIT6 is set. 
 
 # 0x26 ZM_INTR_SOURCE_5_OFFSET
 these endpoints are handled by DMA  
@@ -146,7 +150,7 @@ these endpoints are handled by DMA
 * BIT1
 * BIT0  
 These offset + 2 Byte step for each endpoint.  
-For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1).
+For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
 
 # 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET
 
@@ -160,7 +164,7 @@ For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1).
 * BIT1
 * BIT0  
 These offset + 2 Byte step for each endpoint.  
-For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1).
+For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
 
 # 0xAE ZM_EP3_BYTE_COUNT_HIGH_OFFSET
     BIT3 - 1 xfer done?
@@ -168,15 +172,24 @@ For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1).
 
 # 0xAF ZM_EP4_BYTE_COUNT_HIGH_OFFSET
     BIT4 - 1 - reset fifo; 0 - disable reset?
-    comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET
+    comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET.  
+**These name reg do not fit to pattern!!!** Compare with 0x3e, 0x3f and 0x5e, 0x5f.
+If we have 0x3e, 0x3f and 0x5e, 0x5f, why do we need this register?
 
 # 0xBE ZM_EP3_BYTE_COUNT_LOW_OFFSET
+    size of data in fifo buffer? never used?
 
 # 0xBF ZM_EP4_BYTE_COUNT_LOW_OFFSET
-    size of data in fifo buffer
+    size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.
 
 # 0xF8 ZM_EP3_DATA_OFFSET
+32bit data.  
+
 # 0xFC ZM_EP4_DATA_OFFSET
+32bit data.  
+
+# 0x100 what is here?
+**we miss 8 bytes here**
 
 # 0x108 ZM_SOC_USB_MODE_CTRL_OFFSET
     BIT10 - 1 - enable MP (EP6) downstream stream mode