Assumptions made on source code:
* looks like USB block is [FUSB200](http://www.faraday-tech.com/techDocument/FUSB200_ProductBrief_v1_2.pdf).
-* According to docs FUSB200 has 15 endpoints, but according to the source 10.
+* We have 15 Enddpoints and 15 FIFO buffers.
+* **FIFO0 - FIFO13, 512 Byte each? FIFO14 - FIFO15 - 64 Byte each?**
# 0x00 ZM_MAIN_CTRL_OFFSET
* BIT7
* BIT7
* BIT6
* BIT5
-* BIT4 - TEST_PKY
+* BIT4 - TEST_PKY - Test packed.
* BIT3 - TEST_SE0_NAK
* BIT2 - TEST_K
* BIT1 - TEST_J
1 1 3: SE1
0: Control PHY to turn off 1.5K Ohm pull-up resistor
1: Control PHY to turn on 1.5K Ohm pull-up resistor
-
+If TEST_PKY is set, the test packet must be filled into FIFO by DMA first.
# 0x0A ZM_VDR_SPECIFIC_MODE_OFFSET
* BIT1 - USB reset interrupt.
* BIT0
-# 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET
-
-# 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET
+# 0x2F mUsbEPMap EP0
+code use: ZM_FUSB_BASE+0x30+(EPn-1)
+(0x0F | FIFOn << 4) = OUT
+(0xF0 | FIFOn) = IN
+
+for FIFOn see mUsbFIFOMap registers.
+
+Current configuration:
+* 0x2f 0x00
+* 0x30 0x0f <- EP1 = OUT + Start FIFO0
+* 0x31 0xf2 <- EP2 = IN + Start FIFO2
+* 0x32 0xfe <- EP3 = IN + Start FIFO14
+* 0x33 0xff <- EP4 = OUT + Start FIFO15
+* 0x34 0x4f
+* 0x35 0x6f
+* 0x36 0x00
+* 0x37 0x00
+* 0x38 0x00
+* 0x39 0x00
+* 0x3a 0x00
+* 0x3b 0x00
+* 0x3c 0x00
+* 0x3d 0x00
+* 0x3e 0x00
+
+# 0x30 mUsbEPMap EP1
+# 0x31 mUsbEPMap EP2
+# 0x32 mUsbEPMap EP3
+# 0x33 mUsbEPMap EP4
+# 0x34 mUsbEPMap EP5
+# 0x35 mUsbEPMap EP6
+# 0x36 mUsbEPMap EP7
+# 0x37 mUsbEPMap EP8
+# 0x38 mUsbEPMap EP9
+# 0x39 mUsbEPMap EP10
+# 0x3a mUsbEPMap EP11
+# 0x3b mUsbEPMap EP12
+# 0x3c mUsbEPMap EP13
+# 0x3d mUsbEPMap EP14
+# 0x3e mUsbEPMap EP15
+
+# 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP0
+* BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)
+
+# 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET EP0
* BIT7
* BIT6
* BIT5
* BIT4 - mUsbEPinRsTgSet
* BIT3 - mUsbEPinStallSet
-* BIT2
-* BIT1
-* BIT0
+* BIT0 - BIT2; High size regs
These offset + 2 Byte step for each endpoint.
For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
-# 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET
-# 0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET
+# 0x40 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP1
+# 0x42 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP2
+# 0x44 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP3
+# 0x46 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP4
+# 0x48 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP5
+# 0x4A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP6
+# 0x4C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP7
+# 0x4E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP8
+# 0x50 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP9
+# 0x52 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP10
+# 0x54 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP11
+# 0x56 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP12
+# 0x58 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP13
+# 0x5A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP14
+# 0x5C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP15
+
+# 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP0
+* BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_OUT_MAX_SIZE_LOW_OFFSET + ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET)
+
+# 0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET EP0
* BIT7
* BIT6
* BIT5
* BIT4 - mUsbEPoutRsTgSet
* BIT3 - mUsbEPoutStallSet
-* BIT2
-* BIT1
-* BIT0
+* BIT0 - BIT2; High size regs
+
These offset + 2 Byte step for each endpoint.
For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
+# 0x60 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP1
+# 0x62 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP2
+# 0x64 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP3
+# 0x66 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP4
+# 0x68 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP5
+# 0x6A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP6
+# 0x6C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP7
+# 0x6E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP8
+# 0x70 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP9
+# 0x72 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP10
+# 0x74 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP11
+# 0x76 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP12
+# 0x78 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP13
+# 0x7A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP14
+# 0x7C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP15
+
+# 0x80 mUsbFIFOMap FIFO0
+* BIT7
+* BIT6
+* BIT5
+* BIT4 - Direction: 0 - OUT; 1 - IN.
+* BIT0 - BIT3: assigned EP number.
+
+Current layout:
+* 0x80 0x01 - EP1 OUT
+* 0x81 0x01 - EP1 OUT
+* 0x82 0x12 - EP2 IN
+* 0x83 0x12 - EP2 IN
+* 0x84 0x05
+* 0x85 0x05
+* 0x86 0x06
+* 0x87 0x06
+* 0x88 0x00
+* 0x89 0x00
+* 0x8a 0x00
+* 0x8b 0x00
+* 0x8c 0x00
+* 0x8d 0x00
+* 0x8e 0x13
+* 0x8f 0x04
+
+# 0x81 mUsbFIFOMap FIFO1
+# 0x82 mUsbFIFOMap FIFO2
+# 0x83 mUsbFIFOMap FIFO3
+# 0x84 mUsbFIFOMap FIFO4
+# 0x85 mUsbFIFOMap FIFO5
+# 0x86 mUsbFIFOMap FIFO6
+# 0x87 mUsbFIFOMap FIFO7
+# 0x88 mUsbFIFOMap FIFO8
+# 0x89 mUsbFIFOMap FIFO9
+# 0x8a mUsbFIFOMap FIFO10
+# 0x8b mUsbFIFOMap FIFO11
+# 0x8c mUsbFIFOMap FIFO12
+# 0x8d mUsbFIFOMap FIFO13
+# 0x8e mUsbFIFOMap FIFO14
+# 0x8f mUsbFIFOMap FIFO15
+
+# 0x90 mUsbFIFOConfig FIFO0
+* BIT7 - If EPn use more then one FIFO, then this bit should be on the first
+* BIT6
+* BIT5
+* BIT4 - Block size: 0 - 64/512; 1 - 128/1024. It depends on initial FIFO size.
+* BIT2 - BIT3; number of FIFO blocks or better to say extra blocks? 0 - no more blocks; 1 - one block; 2 - two blocks.
+* BIT0 - BIT1; EP type: 0x1 - Iso; 0x2 - Bulk, 0x3 - Intr;
+
+* 0x90 0x86 <- FIFO0: Bulk | + one block (0x91) | size 512
+* 0x91 0x06
+* 0x92 0x86
+* 0x93 0x06
+* 0x94 0x86
+* 0x95 0x06
+* 0x96 0x86
+* 0x97 0x06
+* 0x98 0x00
+* 0x99 0x00
+* 0x9a 0x00
+* 0x9b 0x00
+* 0x9c 0x00
+* 0x9d 0x00
+* 0x9e 0x83
+* 0x9f 0x83
+
+# 0x91 mUsbFIFOConfig FIFO1
+# 0x92 mUsbFIFOConfig FIFO2
+# 0x93 mUsbFIFOConfig FIFO3
+# 0x94 mUsbFIFOConfig FIFO4
+# 0x95 mUsbFIFOConfig FIFO5
+# 0x96 mUsbFIFOConfig FIFO6
+# 0x97 mUsbFIFOConfig FIFO7
+# 0x98 mUsbFIFOConfig FIFO8
+# 0x99 mUsbFIFOConfig FIFO9
+# 0x9a mUsbFIFOConfig FIFO10
+# 0x9b mUsbFIFOConfig FIFO11
+# 0x9c mUsbFIFOConfig FIFO12
+# 0x9d mUsbFIFOConfig FIFO13
+# 0x9e mUsbFIFOConfig FIFO14
+# 0x9f mUsbFIFOConfig FIFO15
+
# 0xAE ZM_EP3_BYTE_COUNT_HIGH_OFFSET
BIT3 - 1 xfer done?
comments: after sending data from target to host, set BIT3
# 0xBF ZM_EP4_BYTE_COUNT_LOW_OFFSET
size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.
+# 0xc0 FIFO0 DATA OFFSET?
+# 0xc4 FIFO1 DATA OFFSET?
+# 0xc8 FIFO2 DATA OFFSET?
+# 0xcc FIFO3 DATA OFFSET?
+# 0xd0 FIFO4 DATA OFFSET?
+# 0xd4 FIFO5 DATA OFFSET?
+# 0xd8 FIFO6 DATA OFFSET?
+# 0xdc FIFO7 DATA OFFSET?
+# 0xe0 FIFO8 DATA OFFSET?
+# 0xe4 FIFO9 DATA OFFSET?
+# 0xe8 FIFO10 DATA OFFSET?
+# 0xec FIFO11 DATA OFFSET?
+# 0xf0 FIFO12 DATA OFFSET?
+# 0xf4 FIFO13 DATA OFFSET?
+# 0xf8 FIFO14 DATA OFFSET?
+# 0xfc FIFO15 DATA OFFSET?
+
# 0xF8 ZM_EP3_DATA_OFFSET
-32bit data.
+32bit data. Probably FIFO14 offset.. not EP
# 0xFC ZM_EP4_DATA_OFFSET
-32bit data.
+32bit data. Probably FIFO15 offset.. not EP
# 0x100 ZM_CBUS_FIFO_SIZE_REG
0x1 - 1 Byte, 0x3 - 2 Byte, 0x7 - 3 Byte; 0xf - 4 Byte.
projects / librecmc / open-ath9k-htc-firmware.wiki.git / blobdiff