target_firmware/wlan/if_ath.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <adf_os_types.h>
  37 #include <adf_os_pci.h>
  38 #include <adf_os_dma.h>
  39 #include <adf_os_timer.h>
  40 #include <adf_os_lock.h>
  41 #include <adf_os_io.h>
  42 #include <adf_os_mem.h>
  43 #include <adf_os_util.h>
  44 #include <adf_os_stdtypes.h>
  45 #include <adf_os_defer.h>
  46 #include <adf_os_atomic.h>
  47 #include <adf_nbuf.h>
  48 #include <adf_net.h>
  49 #include <adf_net_wcmd.h>
  50 #include <adf_os_irq.h>
  51
  52 #include <if_ath_pci.h>
  53 #include "if_llc.h"
  54 #include "ieee80211_var.h"
  55 #include "if_athrate.h"
  56 #include "if_athvar.h"
  57 #include "ah_desc.h"
  58 #include "ah.h"
  59 #include "ratectrl.h"
  60 #include "ah_internal.h"
  61
  62 static a_int32_t ath_numrxbufs = -1;
  63 static a_int32_t ath_numrxdescs = -1;
  64
  65 #if defined(PROJECT_MAGPIE)
  66 uint32_t *init_htc_handle = 0;
  67 #endif
  68
  69 #define RX_ENDPOINT_ID 3
  70 #define ATH_CABQ_HANDLING_THRESHOLD 9000
  71 #define UAPSDQ_NUM   9
  72 #define CABQ_NUM     8
  73
  74 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
  75 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
  76 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  77 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  78 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
  79 extern void  ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
  80 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
  81 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,  owl_txq_state_t txqstate);
  82 void owl_tgt_node_init(struct ath_node_target * an);
  83 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
  84 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
  85
  86 /*
  87  * Extend a 32 bit TSF to nearest 64 bit TSF value.
  88  * When the adapter is a STATION, its local TSF is periodically modified by
  89  * the hardware to match the BSS TSF (as received in beacon packets), and
  90  * rstamp may appear to be from the future or from the past (with reference
  91  * to the current local TSF) because of jitter. This is mostly noticable in
  92  * highly congested channels. The code uses signed modulo arithmetic to
  93  * handle both past/future cases and signed-extension to avoid branches.
  94  * Test cases:
  95  * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006
  96  * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002
  97  * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe  ! tsfhigh--
  98  * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002
  99  * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe
 100  * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe
 101  * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa
 102  * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002  ! tsfhigh++
 103  */
 104 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
 105 {
 106         struct ath_hal *ah = sc->sc_ah;
 107         u_int64_t tsf;
 108         u_int32_t tsf_low;
 109         a_int64_t tsf_delta;  /* signed int64 */
 110
 111         tsf = ah->ah_getTsf64(ah);
 112         tsf_low = tsf & 0xffffffffUL;
 113
 114         tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL);
 115
 116         return (tsf + (u_int64_t)tsf_delta);
 117 }
 118
 119 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
 120 {
 121         struct ath_hal *ah = sc->sc_ah;
 122         const HAL_RATE_TABLE *rt;
 123
 124         switch (mode) {
 125         case IEEE80211_MODE_11NA:
 126                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
 127                 break;
 128         case IEEE80211_MODE_11NG:
 129                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
 130                 break;
 131         default:
 132                 return 0;
 133         }
 134         rt = sc->sc_rates[mode];
 135         if (rt == NULL)
 136                 return 0;
 137
 138         return 1;
 139 }
 140
 141 static void ath_setcurmode(struct ath_softc_tgt *sc,
 142                            enum ieee80211_phymode mode)
 143 {
 144         const HAL_RATE_TABLE *rt;
 145         a_int32_t i;
 146
 147         adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 148
 149         rt = sc->sc_rates[mode];
 150         adf_os_assert(rt != NULL);
 151
 152         for (i = 0; i < rt->rateCount; i++) {
 153                 sc->sc_rixmap[rt->info[i].rateCode] = i;
 154         }
 155
 156         sc->sc_currates = rt;
 157         sc->sc_curmode = mode;
 158         sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
 159
 160 }
 161
 162 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
 163                void *buffer, a_int32_t Length)
 164 {
 165         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 166         a_uint8_t *pData;
 167
 168         netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
 169                                 sizeof(WMI_CMD_HDR) + Length);
 170
 171         if (netbuf == ADF_NBUF_NULL) {
 172                 adf_os_print("Buf null\n");
 173                 return;
 174         }
 175
 176         if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
 177                 pData = adf_nbuf_put_tail(netbuf, Length);
 178                 adf_os_mem_copy(pData, buffer, Length);
 179         }
 180
 181         WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
 182 }
 183
 184 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
 185                  void *buffer, a_int32_t Length)
 186 {
 187         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 188         A_UINT8 *pData;
 189
 190         netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
 191                                 sizeof(WMI_CMD_HDR) + Length);
 192
 193         if (netbuf == ADF_NBUF_NULL) {
 194                 adf_os_assert(0);
 195                 return;
 196         }
 197
 198         if (Length != 0 && buffer != NULL) {
 199                 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
 200                 adf_os_mem_copy(pData, buffer, Length);
 201         }
 202
 203         WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
 204 }
 205
 206 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
 207 {
 208         a_int32_t i;
 209
 210         for (i = 0; i < TARGET_NODE_MAX; i++) {
 211                 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
 212                         sc->sc_sta[i].an_valid = 0;
 213         }
 214 }
 215
 216 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
 217 {
 218         if (sc->sc_curmode == IEEE80211_MODE_11NG)
 219                 return avp->av_minrateidx[0];
 220         else if (sc->sc_curmode == IEEE80211_MODE_11NA)
 221                 return avp->av_minrateidx[1];
 222
 223         return 0;
 224 }
 225
 226 /******/
 227 /* RX */
 228 /******/
 229
 230 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
 231                                       a_uint32_t size, a_uint32_t align)
 232 {
 233         adf_nbuf_t skb;
 234
 235         skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
 236                                        RX_HEADER_SPACE, align);
 237         return skb;
 238 }
 239
 240 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
 241 {
 242         struct ath_hal *ah = sc->sc_ah;
 243         struct ath_rx_desc *ds_held;
 244         a_uint8_t *anbdata;
 245         a_uint32_t anblen;
 246
 247         if (!sc->sc_rxdesc_held) {
 248                 sc->sc_rxdesc_held = ds;
 249                 return 0;
 250         }
 251
 252         ds_held = sc->sc_rxdesc_held;
 253         sc->sc_rxdesc_held = ds;
 254         ds = ds_held;
 255
 256         if (ds->ds_nbuf == ADF_NBUF_NULL) {
 257                 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
 258                 if (ds->ds_nbuf == ADF_NBUF_NULL) {
 259                         sc->sc_rxdesc_held = ds;
 260                         sc->sc_rx_stats.ast_rx_nobuf++;
 261                         return ENOMEM;
 262                 }
 263                 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
 264                 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
 265                 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
 266         }
 267
 268         ds->ds_link = 0;
 269         adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 270
 271         ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
 272
 273         if (sc->sc_rxlink == NULL) {
 274                 ah->ah_setRxDP(ah, ds->ds_daddr);
 275         }
 276         else {
 277                 *sc->sc_rxlink = ds->ds_daddr;
 278         }
 279         sc->sc_rxlink = &ds->ds_link;
 280         ah->ah_enableReceive(ah);
 281
 282         return 0;
 283 }
 284
 285 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
 286 {
 287         struct ath_rx_desc *ds;
 288         adf_nbuf_t buf_tmp;
 289         adf_nbuf_queue_t nbuf_head;
 290
 291         adf_nbuf_split_to_frag(buf, &nbuf_head);
 292         ds = asf_tailq_first(&sc->sc_rxdesc_idle);
 293
 294         while (ds) {
 295                 struct ath_rx_desc *ds_tmp;
 296                 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
 297
 298                 if (buf_tmp == NULL) {
 299                         break;
 300                 }
 301
 302                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
 303
 304                 ds_tmp = ds;
 305                 ds = asf_tailq_next(ds, ds_list);
 306
 307                 ath_rxdesc_init(sc, ds_tmp);
 308
 309                 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
 310                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
 311         }
 312 }
 313
 314 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
 315 {
 316         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 317
 318         if (Endpt == RX_ENDPOINT_ID) {
 319                 sc->sc_rx_stats.ast_rx_done++;
 320                 ath_rx_complete(sc, buf);
 321         }
 322 }
 323
 324 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
 325 {
 326         struct ath_hal *ah = sc->sc_ah;
 327         struct ath_rx_buf *bf = NULL;
 328         struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
 329         a_int32_t retval;
 330         a_uint32_t cnt = 0;
 331         a_uint16_t frame_len = 0;
 332
 333 #define PA2DESC(_sc, _pa)                                               \
 334         ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc +         \
 335                              ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
 336
 337         bf = asf_tailq_first(&sc->sc_rxbuf);
 338
 339         ds = asf_tailq_first(&sc->sc_rxdesc);
 340         ds_head = ds;
 341
 342         while(ds) {
 343                 ++cnt;
 344
 345                 if (cnt == ath_numrxbufs - 1) {
 346                         adf_os_print("VERY LONG PACKET!!!!!\n");
 347                         ds_tail = ds;
 348                         ds_tmp = ds_head;
 349                         while (ds_tmp) {
 350                                 struct ath_rx_desc *ds_rmv;
 351                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 352                                 ds_rmv = ds_tmp;
 353                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 354
 355                                 if (ds_tmp == NULL) {
 356                                         adf_os_print("ds_tmp is NULL\n");
 357                                         adf_os_assert(0);
 358                                 }
 359
 360                                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
 361                                 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
 362
 363                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 364                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 365                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 366                                 }
 367                                 else {
 368                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 369                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 370                                 }
 371
 372                                 if (ds_rmv == ds_tail) {
 373                                         break;
 374                                 }
 375                         }
 376                         break;
 377                 }
 378
 379                 if (ds->ds_link == 0) {
 380                         break;
 381                 }
 382
 383                 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
 384                         continue;
 385                 }
 386
 387                 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
 388                                                 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
 389                 if (HAL_EINPROGRESS == retval) {
 390                         break;
 391                 }
 392
 393                 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
 394                         adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
 395                 }
 396
 397                 frame_len += bf->bf_rx_status.rs_datalen;
 398
 399                 if (bf->bf_rx_status.rs_more == 0) {
 400                         adf_nbuf_queue_t nbuf_head;
 401                         adf_nbuf_queue_init(&nbuf_head);
 402
 403                         cnt = 0;
 404
 405                         ds_tail = ds;
 406                         ds = asf_tailq_next(ds, ds_list);
 407
 408                         ds_tmp = ds_head;
 409                         ds_head = asf_tailq_next(ds_tail, ds_list);
 410
 411                         while (ds_tmp) {
 412                                 struct ath_rx_desc *ds_rmv;
 413
 414                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 415                                 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
 416                                 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
 417
 418                                 ds_rmv = ds_tmp;
 419                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 420                                 if (ds_tmp == NULL) {
 421                                         adf_os_assert(0);
 422                                 }
 423
 424                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 425                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 426                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 427                                 }  else {
 428                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 429                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 430                                 }
 431
 432                                 if (ds_rmv == ds_tail) {
 433                                         break;
 434                                 }
 435                         }
 436
 437
 438                         bf->bf_rx_status.rs_datalen = frame_len;
 439                         frame_len = 0;
 440
 441                         bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
 442
 443                         bf->bf_status |= ATH_BUFSTATUS_DONE;
 444
 445                         bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
 446                 }
 447                 else {
 448                         ds = asf_tailq_next(ds, ds_list);
 449                 }
 450         }
 451
 452 #undef PA2DESC
 453 }
 454
 455 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
 456 {
 457         struct ath_hal *ah = sc->sc_ah;
 458         struct ath_rx_desc *ds;
 459
 460         sc->sc_rxbufsize = 1024+512+128;
 461         sc->sc_rxlink = NULL;
 462
 463         sc->sc_rxdesc_held = NULL;
 464
 465         asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
 466                 a_int32_t error = ath_rxdesc_init(sc, ds);
 467                 if (error != 0) {
 468                         return error;
 469                 }
 470         }
 471
 472         ds = asf_tailq_first(&sc->sc_rxdesc);
 473         ah->ah_setRxDP(ah, ds->ds_daddr);
 474
 475         return 0;
 476 }
 477
 478 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
 479 {
 480         struct ath_softc_tgt *sc  = (struct ath_softc_tgt *)data;
 481         struct ath_rx_buf *bf = NULL;
 482         struct ath_hal *ah = sc->sc_ah;
 483         struct rx_frame_header *rxhdr;
 484         struct ath_rx_status *rxstats;
 485         adf_nbuf_t skb = ADF_NBUF_NULL;
 486
 487         do {
 488                 bf = asf_tailq_first(&sc->sc_rxbuf);
 489                 if (bf == NULL) {
 490                         break;
 491                 }
 492
 493                 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
 494                         break;
 495                 }
 496
 497                 skb = bf->bf_skb;
 498                 if (skb == NULL) {
 499                         continue;
 500                 }
 501
 502                 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
 503
 504                 bf->bf_skb = NULL;
 505
 506                 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
 507                                                      sizeof(struct rx_frame_header));
 508                 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
 509                 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
 510                                 sizeof(struct ath_rx_status));
 511
 512                 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
 513
 514                 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
 515                 sc->sc_rx_stats.ast_rx_send++;
 516
 517                 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
 518                 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
 519
 520         } while(1);
 521
 522         sc->sc_imask |= HAL_INT_RX;
 523         ah->ah_setInterrupts(ah, sc->sc_imask);
 524 }
 525
 526 /*******************/
 527 /* Beacon Handling */
 528 /*******************/
 529
 530 /*
 531  * Setup the beacon frame for transmit.
 532  * FIXME: Short Preamble.
 533  */
 534 static void ath_beacon_setup(struct ath_softc_tgt *sc,
 535                              struct ath_tx_buf *bf,
 536                              struct ath_vap_target *avp)
 537 {
 538         adf_nbuf_t skb = bf->bf_skb;
 539         struct ath_hal *ah = sc->sc_ah;
 540         struct ath_tx_desc *ds;
 541         a_int32_t flags;
 542         const HAL_RATE_TABLE *rt;
 543         a_uint8_t rix, rate;
 544         HAL_11N_RATE_SERIES series[4] = {{ 0 }};
 545
 546         flags = HAL_TXDESC_NOACK;
 547
 548         ds = bf->bf_desc;
 549         ds->ds_link = 0;
 550         ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
 551
 552         rix = ath_get_minrateidx(sc, avp);
 553         rt  = sc->sc_currates;
 554         rate = rt->info[rix].rateCode;
 555
 556         ah->ah_setupTxDesc(ds
 557                             , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 558                             , sizeof(struct ieee80211_frame)
 559                             , HAL_PKT_TYPE_BEACON
 560                             , MAX_RATE_POWER
 561                             , rate, 1
 562                             , HAL_TXKEYIX_INVALID
 563                             , flags
 564                             , 0
 565                             , 0);
 566
 567         ah->ah_fillTxDesc(ds
 568                            , asf_roundup(adf_nbuf_len(skb), 4)
 569                            , AH_TRUE
 570                            , AH_TRUE
 571                            , ds);
 572
 573         series[0].Tries = 1;
 574         series[0].Rate = rate;
 575         series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 576         series[0].RateFlags = 0;
 577         ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
 578 }
 579
 580 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
 581                                 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
 582 {
 583         struct ath_hal *ah = sc->sc_ah;
 584         struct ath_tx_buf *bf;
 585         a_uint8_t vap_index, *anbdata;
 586         ath_beacon_hdr_t *bhdr;
 587         a_uint32_t anblen;
 588
 589         if (!bc_hdr) {
 590                 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
 591                 bhdr = (ath_beacon_hdr_t *)anbdata;
 592         } else {
 593                 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
 594         }
 595
 596         vap_index = bhdr->vap_index;
 597         adf_os_assert(vap_index < TARGET_VAP_MAX);
 598
 599         adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t));
 600
 601         bf = sc->sc_vap[vap_index].av_bcbuf;
 602         adf_os_assert(bf);
 603         bf->bf_endpt = EndPt;
 604
 605         if (bf->bf_skb) {
 606                 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
 607                 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
 608                 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
 609         }
 610
 611         bf->bf_skb = nbuf;
 612
 613         adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
 614         adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
 615
 616         ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
 617         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 618         ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 619         ah->ah_startTxDma(ah, sc->sc_bhalq);
 620 }
 621
 622 /******/
 623 /* TX */
 624 /******/
 625
 626 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
 627 {
 628         struct ath_hal *ah = sc->sc_ah;
 629
 630         ah->ah_stopTxDma(ah, txq->axq_qnum);
 631 }
 632
 633 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
 634 {
 635         owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
 636 }
 637
 638 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
 639 {
 640         owltgt_txq_drain(sc, txq);
 641 }
 642
 643 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
 644 {
 645         struct ath_hal *ah = sc->sc_ah;
 646         a_uint16_t i;
 647         struct ath_txq *txq = NULL;
 648         struct ath_atx_tid *tid = NULL;
 649
 650         ath_tx_status_clear(sc);
 651         sc->sc_tx_draining = 1;
 652
 653         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 654
 655         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 656                 if (ATH_TXQ_SETUP(sc, i))
 657                         ath_tx_stopdma(sc, ATH_TXQ(sc, i));
 658
 659         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 660                 if (ATH_TXQ_SETUP(sc, i)) {
 661                         owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
 662
 663                         txq = ATH_TXQ(sc,i);
 664                         while (!asf_tailq_empty(&txq->axq_tidq)){
 665                                 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
 666                                 if(tid == NULL)
 667                                         break;
 668                                 tid->sched = AH_FALSE;
 669                                 ath_tgt_tid_drain(sc,tid);
 670                         }
 671                 }
 672
 673         sc->sc_tx_draining = 0;
 674 }
 675
 676 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
 677 {
 678         a_int32_t qnum;
 679         struct ath_txq *txq;
 680
 681         sc->sc_txqsetup=0;
 682
 683         for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
 684                 txq= &sc->sc_txq[qnum];
 685                 txq->axq_qnum = qnum;
 686                 txq->axq_link = NULL;
 687                 asf_tailq_init(&txq->axq_q);
 688                 txq->axq_depth = 0;
 689                 txq->axq_linkbuf = NULL;
 690                 asf_tailq_init(&txq->axq_tidq);
 691                 sc->sc_txqsetup |= 1<<qnum;
 692         }
 693
 694         sc->sc_uapsdq  = &sc->sc_txq[UAPSDQ_NUM];
 695         sc->sc_cabq    = &sc->sc_txq[CABQ_NUM];
 696
 697         sc->sc_ac2q[WME_AC_BE]  = &sc->sc_txq[0];
 698         sc->sc_ac2q[WME_AC_BK]  = &sc->sc_txq[1];
 699         sc->sc_ac2q[WME_AC_VI]  = &sc->sc_txq[2];
 700         sc->sc_ac2q[WME_AC_VO]  = &sc->sc_txq[3];
 701
 702         return;
 703 #undef N
 704 }
 705
 706 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 707                                       adf_nbuf_t buf, void *ServiceCtx)
 708 {
 709         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 710
 711         ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
 712 }
 713
 714 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 715                                      adf_nbuf_t buf, void *ServiceCtx)
 716 {
 717 }
 718
 719 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 720                                     adf_nbuf_t buf, void *ServiceCtx)
 721 {
 722         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 723
 724         ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
 725 }
 726
 727 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
 728                                       adf_nbuf_t hdr_buf, adf_nbuf_t buf,
 729                                       void *ServiceCtx)
 730 {
 731         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 732         struct ath_tx_buf *bf;
 733         a_uint8_t *data;
 734         a_uint32_t len;
 735         ath_data_hdr_t *dh;
 736         struct ath_node_target *an;
 737         struct ath_atx_tid *tid;
 738
 739         if (!hdr_buf) {
 740                 adf_nbuf_peek_header(buf, &data, &len);
 741                 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
 742         } else {
 743                 adf_nbuf_peek_header(hdr_buf, &data, &len);
 744         }
 745
 746         adf_os_assert(len >= sizeof(ath_data_hdr_t));
 747         dh = (ath_data_hdr_t *)data;
 748
 749         an = &sc->sc_sta[dh->ni_index];
 750         tid = ATH_AN_2_TID(an, dh->tidno);
 751
 752         sc->sc_tx_stats.tx_tgt++;
 753
 754         bf = ath_tgt_tx_prepare(sc, buf, dh);
 755         if (!bf) {
 756                 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
 757                 return;
 758         }
 759
 760         bf->bf_endpt = EndPt;
 761         bf->bf_cookie = dh->cookie;
 762
 763         if (tid->flag & TID_AGGR_ENABLED)
 764                 ath_tgt_handle_aggr(sc, bf);
 765         else
 766                 ath_tgt_handle_normal(sc, bf);
 767 }
 768
 769 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 770                                    adf_nbuf_t buf, void *ServiceCtx)
 771 {
 772         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 773         struct ath_hal *ah = sc->sc_ah;
 774         a_uint64_t tsf;
 775         a_uint32_t tmp;
 776
 777 #ifdef ATH_ENABLE_CABQ
 778         tsf = ah->ah_getTsf64(ah);
 779         tmp = tsf - sc->sc_swba_tsf;
 780
 781         if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
 782                 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
 783                 return;
 784         }
 785
 786         tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
 787 #endif
 788 }
 789
 790 /***********************/
 791 /* Descriptor Handling */
 792 /***********************/
 793
 794 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
 795                                    struct ath_descdma *dd, ath_bufhead *head,
 796                                    const char *name, a_int32_t nbuf, a_int32_t ndesc,
 797                                    a_uint32_t bfSize, a_uint32_t descSize)
 798 {
 799 #define DS2PHYS(_dd, _ds)                                               \
 800         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 801
 802         struct ath_desc *ds;
 803         struct ath_buf *bf;
 804         a_int32_t i, bsize, error;
 805         a_uint8_t *bf_addr;
 806         a_uint8_t *ds_addr;
 807
 808         dd->dd_name = name;
 809         dd->dd_desc_len = descSize * nbuf * ndesc;
 810
 811         dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
 812                                   dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
 813         dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
 814         if (dd->dd_desc == NULL) {
 815                 error = -ENOMEM;
 816                 goto fail;
 817         }
 818         ds = dd->dd_desc;
 819
 820         bsize = bfSize * nbuf;
 821         bf = adf_os_mem_alloc(bsize);
 822         if (bf == NULL) {
 823                 error = -ENOMEM;
 824                 goto fail2;
 825         }
 826         adf_os_mem_set(bf, 0, bsize);
 827         dd->dd_bufptr = bf;
 828
 829         bf_addr = (a_uint8_t *)bf;
 830         ds_addr = (a_uint8_t *)ds;
 831
 832         asf_tailq_init(head);
 833
 834         for (i = 0; i < nbuf; i++) {
 835                 a_int32_t j;
 836
 837                 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
 838                         goto fail2;
 839                 }
 840
 841                 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
 842                 for (j = 0; j < ndesc; j++)
 843                         ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
 844
 845                 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
 846
 847                 adf_nbuf_queue_init(&bf->bf_skbhead);
 848                 asf_tailq_insert_tail(head, bf, bf_list);
 849
 850                 bf_addr += bfSize;
 851                 ds_addr += (ndesc * descSize);
 852                 bf = (struct ath_buf *)bf_addr;
 853                 ds = (struct ath_desc *)ds_addr;
 854         }
 855
 856         return 0;
 857 fail2:
 858         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 859                            1, dd->dd_desc, dd->dd_desc_dmamap);
 860 fail:
 861         adf_os_mem_set(dd, 0, sizeof(*dd));
 862         adf_os_assert(0);
 863         return error;
 864
 865 #undef DS2PHYS
 866 }
 867
 868 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
 869                                 struct ath_descdma *dd,
 870                                 ath_bufhead *head, a_int32_t dir)
 871 {
 872         struct ath_buf *bf;
 873
 874         asf_tailq_foreach(bf, head, bf_list) {
 875                 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 876                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
 877                         while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 878                                 ath_free_rx_skb(sc,
 879                                         adf_nbuf_queue_remove(&bf->bf_skbhead));
 880                         }
 881                         bf->bf_skb = NULL;
 882                 } else if (bf->bf_skb != NULL) {
 883                         adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
 884                         ath_free_rx_skb(sc, bf->bf_skb);
 885                         bf->bf_skb = NULL;
 886                 }
 887
 888                 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
 889
 890                 bf->bf_node = NULL;
 891         }
 892
 893         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 894                            1, dd->dd_desc, dd->dd_desc_dmamap);
 895
 896         asf_tailq_init(head);
 897         adf_os_mem_free(dd->dd_bufptr);
 898         adf_os_mem_set(dd, 0, sizeof(*dd));
 899 }
 900
 901 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
 902 {
 903 #define DS2PHYS(_dd, _ds)                                               \
 904         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 905
 906         a_int32_t error;
 907         struct ath_tx_buf *bf;
 908
 909         if(ath_numrxbufs == -1)
 910                 ath_numrxbufs = ATH_RXBUF;
 911
 912         if (ath_numrxdescs == -1)
 913                 ath_numrxdescs = ATH_RXDESC;
 914
 915         error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 916                                   "rx", ath_numrxdescs, 1,
 917                                   sizeof(struct ath_rx_buf),
 918                                   sizeof(struct ath_rx_desc));
 919         if (error != 0)
 920                 return error;
 921
 922         a_uint32_t i;
 923         struct ath_descdma *dd = &sc->sc_rxdma;
 924         struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
 925         struct ath_rx_desc *ds_prev = NULL;
 926
 927         asf_tailq_init(&sc->sc_rxdesc);
 928         asf_tailq_init(&sc->sc_rxdesc_idle);
 929
 930         for (i = 0; i < ath_numrxdescs; i++, ds++) {
 931
 932                 if (ds->ds_nbuf != ADF_NBUF_NULL) {
 933                         ds->ds_nbuf = ADF_NBUF_NULL;
 934                 }
 935
 936                 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
 937                         adf_os_assert(0);
 938                 }
 939
 940                 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
 941
 942                 if (ds_prev) {
 943                         ds_prev->ds_link = ds->ds_daddr;
 944                 }
 945
 946                 ds->ds_link = 0;
 947                 ds_prev = ds;
 948
 949                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
 950         }
 951
 952         error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 953                                   "tx", ATH_TXBUF + 1, ATH_TXDESC,
 954                                   sizeof(struct ath_tx_buf),
 955                                   sizeof(struct ath_tx_desc));
 956         if (error != 0) {
 957                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 958                                     ADF_OS_DMA_FROM_DEVICE);
 959                 return error;
 960         }
 961
 962         error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
 963                                   "beacon", ATH_BCBUF, 1,
 964                                   sizeof(struct ath_tx_buf),
 965                                   sizeof(struct ath_tx_desc));
 966         if (error != 0) {
 967                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 968                                     ADF_OS_DMA_TO_DEVICE);
 969                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 970                                     ADF_OS_DMA_FROM_DEVICE);
 971                 return error;
 972         }
 973
 974         bf = asf_tailq_first(&sc->sc_txbuf);
 975         bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
 976         asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
 977
 978         sc->sc_txbuf_held = bf;
 979
 980         return 0;
 981
 982 #undef DS2PHYS
 983 }
 984
 985 static void ath_desc_free(struct ath_softc_tgt *sc)
 986 {
 987         asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
 988
 989         sc->sc_txbuf_held = NULL;
 990
 991         if (sc->sc_txdma.dd_desc_len != 0)
 992                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 993                                     ADF_OS_DMA_TO_DEVICE);
 994         if (sc->sc_rxdma.dd_desc_len != 0)
 995                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 996                                     ADF_OS_DMA_FROM_DEVICE);
 997 }
 998
 999 /**********************/
1000 /* Interrupt Handling */
1001 /**********************/
1002
1003 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1004 {
1005         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1006         struct ath_hal *ah = sc->sc_ah;
1007         HAL_INT status;
1008
1009         if (sc->sc_invalid)
1010                 return ADF_OS_IRQ_NONE;
1011
1012         if (!ah->ah_isInterruptPending(ah))
1013                 return ADF_OS_IRQ_NONE;
1014
1015         ah->ah_getPendingInterrupts(ah, &status);
1016
1017         status &= sc->sc_imask;
1018
1019         if (status & HAL_INT_FATAL) {
1020                 ah->ah_setInterrupts(ah, 0);
1021                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1022         } else {
1023                 if (status & HAL_INT_SWBA) {
1024                         WMI_SWBA_EVENT swbaEvt;
1025                         struct ath_txq *txq = ATH_TXQ(sc, 8);
1026
1027                         swbaEvt.tsf = ah->ah_getTsf64(ah);
1028                         swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1029                         sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1030
1031                         wmi_event(sc->tgt_wmi_handle,
1032                                   WMI_SWBA_EVENTID,
1033                                   &swbaEvt,
1034                                   sizeof(WMI_SWBA_EVENT));
1035
1036                         ath_tx_draintxq(sc, txq);
1037                 }
1038
1039                 if (status & HAL_INT_RXORN)
1040                         sc->sc_int_stats.ast_rxorn++;
1041
1042                 if (status & HAL_INT_RXEOL)
1043                         sc->sc_int_stats.ast_rxeol++;
1044
1045                 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1046                         if (status & HAL_INT_RX)
1047                                 sc->sc_int_stats.ast_rx++;
1048
1049                         ath_uapsd_processtriggers(sc);
1050
1051                         sc->sc_imask &= ~HAL_INT_RX;
1052                         ah->ah_setInterrupts(ah, sc->sc_imask);
1053
1054                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1055                 }
1056
1057                 if (status & HAL_INT_TXURN) {
1058                         sc->sc_int_stats.ast_txurn++;
1059                         ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1060                 }
1061
1062                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1063
1064                 if (status & HAL_INT_BMISS) {
1065                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1066                 }
1067
1068                 if (status & HAL_INT_GTT)
1069                         sc->sc_int_stats.ast_txto++;
1070
1071                 if (status & HAL_INT_CST)
1072                         sc->sc_int_stats.ast_cst++;
1073         }
1074
1075         return ADF_OS_IRQ_HANDLED;
1076 }
1077
1078 static void ath_fatal_tasklet(TQUEUE_ARG data )
1079 {
1080         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1081
1082         wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1083 }
1084
1085 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1086 {
1087         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1088
1089         wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1090 }
1091
1092 /****************/
1093 /* WMI Commands */
1094 /****************/
1095
1096 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1097                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1098 {
1099         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1100         struct ath_hal *ah = sc->sc_ah;
1101         a_uint32_t intr = 0;
1102
1103         if (datalen == 4)
1104                 intr = (*(a_uint32_t *)data);
1105
1106         intr = adf_os_ntohl(intr);
1107
1108         if (intr & HAL_INT_SWBA) {
1109                 sc->sc_imask |= HAL_INT_SWBA;
1110         } else {
1111                 sc->sc_imask &= ~HAL_INT_SWBA;
1112         }
1113
1114         if (intr & HAL_INT_BMISS) {
1115                 sc->sc_imask |= HAL_INT_BMISS;
1116         }
1117
1118         ah->ah_setInterrupts(ah, sc->sc_imask);
1119         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1120 }
1121
1122 static void ath_init_tgt(void *Context, A_UINT16 Command,
1123                          A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1124 {
1125         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1126         struct ath_hal *ah = sc->sc_ah;
1127
1128         sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1129                 | HAL_INT_RXEOL | HAL_INT_RXORN
1130                 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1131
1132         sc->sc_imask |= HAL_INT_GTT;
1133
1134         if (ath_hal_getcapability(ah, HAL_CAP_HT))
1135                 sc->sc_imask |= HAL_INT_CST;
1136
1137         adf_os_setup_intr(sc->sc_dev, ath_intr);
1138         ah->ah_setInterrupts(ah, sc->sc_imask);
1139
1140         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1141 }
1142
1143 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1144                               A_UINT8 *data, a_int32_t datalen)
1145 {
1146         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1147
1148         struct fusion_stats {
1149                 a_uint32_t ast_rx;
1150                 a_uint32_t ast_rxorn;
1151                 a_uint32_t ast_rxeol;
1152                 a_uint32_t ast_txurn;
1153                 a_uint32_t ast_txto;
1154                 a_uint32_t ast_cst;
1155         };
1156
1157         struct fusion_stats stats;
1158
1159         stats.ast_rx = sc->sc_int_stats.ast_rx;
1160         stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1161         stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1162         stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1163         stats.ast_txto = sc->sc_int_stats.ast_txto;
1164         stats.ast_cst = sc->sc_int_stats.ast_cst;
1165
1166         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1167 }
1168
1169 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1170                              A_UINT8 *data, a_int32_t datalen)
1171 {
1172         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1173
1174         struct fusion_stats {
1175                 a_uint32_t   ast_tx_xretries;
1176                 a_uint32_t   ast_tx_fifoerr;
1177                 a_uint32_t   ast_tx_filtered;
1178                 a_uint32_t   ast_tx_timer_exp;
1179                 a_uint32_t   ast_tx_shortretry;
1180                 a_uint32_t   ast_tx_longretry;
1181
1182                 a_uint32_t   tx_qnull;
1183                 a_uint32_t   tx_noskbs;
1184                 a_uint32_t   tx_nobufs;
1185         };
1186
1187         struct fusion_stats stats;
1188
1189         stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1190         stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1191         stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1192         stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1193         stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1194         stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1195         stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1196         stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1197         stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1198
1199         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1200 }
1201
1202 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1203                              A_UINT8 *data, a_int32_t datalen)
1204 {
1205         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1206
1207         struct fusion_stats {
1208                 a_uint32_t   ast_rx_nobuf;
1209                 a_uint32_t   ast_rx_send;
1210                 a_uint32_t   ast_rx_done;
1211         };
1212
1213         struct fusion_stats stats;
1214
1215         stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1216         stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1217         stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1218
1219         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1220 }
1221
1222 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1223                                 A_UINT8 *data, a_int32_t datalen)
1224 {
1225         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1226         struct wmi_fw_version ver;
1227
1228         ver.major = ATH_VERSION_MAJOR;
1229         ver.minor = ATH_VERSION_MINOR;
1230
1231         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1232 }
1233
1234 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1235                                 A_UINT8 *data, a_int32_t datalen)
1236 {
1237         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1238         struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1239         a_uint8_t nodeindex = aggr->nodeindex;
1240         a_uint8_t tidno = aggr->tidno;
1241         struct ath_node_target *an = NULL ;
1242         struct ath_atx_tid  *tid = NULL;
1243
1244         if (nodeindex >= TARGET_NODE_MAX) {
1245                 goto done;
1246         }
1247
1248         an = &sc->sc_sta[nodeindex];
1249         if (!an->an_valid) {
1250                 goto done;
1251         }
1252
1253         if (tidno >= WME_NUM_TID) {
1254                 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1255                              __FUNCTION__, tidno, nodeindex);
1256                 goto done;
1257         }
1258
1259         tid = ATH_AN_2_TID(an, tidno);
1260
1261         if (aggr->aggr_enable) {
1262                 tid->flag |= TID_AGGR_ENABLED;
1263         } else if ( tid->flag & TID_AGGR_ENABLED ) {
1264                 tid->flag &= ~TID_AGGR_ENABLED;
1265                 ath_tgt_tx_cleanup(sc, an, tid, 1);
1266         }
1267 done:
1268         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1269 }
1270
1271 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1272                               A_UINT8 *data, a_int32_t datalen)
1273 {
1274         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1275         struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1276         struct ieee80211com_target *ictgt = &sc->sc_ic ;
1277
1278         adf_os_mem_copy(ictgt, ic, sizeof(struct  ieee80211com_target));
1279
1280         ictgt->ic_ampdu_limit         = adf_os_ntohl(ic->ic_ampdu_limit);
1281
1282         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1283 }
1284
1285 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1286                                A_UINT8 *data, a_int32_t datalen)
1287 {
1288         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1289         struct ieee80211vap_target *vap;
1290         a_uint8_t vap_index;
1291
1292         vap = (struct ieee80211vap_target *)data;
1293
1294         vap->iv_rtsthreshold    = adf_os_ntohs(vap->iv_rtsthreshold);
1295         vap->iv_opmode          = adf_os_ntohl(vap->iv_opmode);
1296
1297         vap_index = vap->iv_vapindex;
1298
1299         adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1300
1301         adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1302                         VAP_TARGET_SIZE);
1303
1304         sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1305         sc->sc_vap[vap_index].av_valid = 1;
1306
1307         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1308 }
1309
1310 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1311                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1312 {
1313         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1314         struct ieee80211_node_target *node;
1315         a_uint8_t vap_index;
1316         a_uint8_t node_index;
1317
1318         node = (struct ieee80211_node_target *)data;
1319
1320         node_index = node->ni_nodeindex;
1321
1322         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1323         node->ni_flags = adf_os_ntohs(node->ni_flags);
1324         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1325
1326         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1327                         NODE_TARGET_SIZE);
1328
1329         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1330         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1331         if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1332                 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1333
1334         sc->sc_sta[node_index].an_valid = 1;
1335         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1336         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1337         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1338
1339         owl_tgt_node_init(&sc->sc_sta[node_index]);
1340
1341         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1342 }
1343
1344 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1345                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1346 {
1347         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1348         a_uint8_t node_index;
1349         a_uint8_t *nodedata;
1350
1351         nodedata = (a_uint8_t *)data;
1352         node_index = *nodedata;
1353         sc->sc_sta[node_index].an_valid = 0;
1354
1355         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1356 }
1357
1358 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1359                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1360 {
1361         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1362         struct ieee80211_node_target *node;
1363         a_uint8_t vap_index;
1364         a_uint8_t node_index;
1365
1366         node = (struct ieee80211_node_target *)data;
1367
1368         node_index = node->ni_nodeindex;
1369
1370         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1371         node->ni_flags = adf_os_ntohs(node->ni_flags);
1372         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1373
1374         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1375                         NODE_TARGET_SIZE);
1376
1377         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1378         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1379
1380         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1381         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1382         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1383
1384         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1385 }
1386
1387 static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
1388 {
1389         if ((addr & 0xffffe000) == 0x2000) {
1390                 /* SEEPROM registers */
1391                 ioread32_mac(addr);
1392                 if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
1393                         adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1394
1395                 return ioread32_mac(0x407c) & 0x0000ffff;
1396         } else if (addr > 0xffff)
1397                 /* SoC registers */
1398                 return ioread32(addr);
1399         else
1400                 /* MAC registers */
1401                 return ioread32_mac(addr);
1402 }
1403
1404 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1405                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1406 {
1407         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1408         struct ath_hal *ah = sc->sc_ah;
1409         a_uint32_t addr;
1410         a_uint32_t val[32];
1411         int i;
1412
1413         for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1414                 addr = *(a_uint32_t *)(data + i);
1415                 addr = adf_os_ntohl(addr);
1416
1417                 val[i/sizeof(a_int32_t)] =
1418                         adf_os_ntohl(ath_reg_read_filter(ah, addr));
1419         }
1420
1421         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1422 }
1423
1424 static void ath_pll_reset_ones(struct ath_hal *ah)
1425 {
1426         static uint8_t reset_pll = 0;
1427
1428         if(reset_pll == 0) {
1429 #if defined(PROJECT_K2)
1430                 /* here we write to core register */
1431                 iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
1432                 /* and here to mac register */
1433                 iowrite32_mac(0x786c,
1434                          ioread32_mac(0x786c) | 0x6000000);
1435                 iowrite32_mac(0x786c,
1436                          ioread32_mac(0x786c) & (~0x6000000));
1437
1438                 iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
1439
1440 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1441                 iowrite32_mac(0x7890,
1442                          ioread32_mac(0x7890) | 0x1800000);
1443                 iowrite32_mac(0x7890,
1444                          ioread32_mac(0x7890) & (~0x1800000));
1445 #endif
1446                 reset_pll = 1;
1447         }
1448 }
1449
1450 static void ath_hal_reg_write_filter(struct ath_hal *ah,
1451                         a_uint32_t reg, a_uint32_t val)
1452 {
1453         if(reg > 0xffff) {
1454                 iowrite32(reg, val);
1455 #if defined(PROJECT_K2)
1456                 if(reg == 0x50040) {
1457                         static uint8_t flg=0;
1458
1459                         if(flg == 0) {
1460                                 /* reinit clock and uart.
1461                                  * TODO: Independent on what host will
1462                                  * here set. We do our own decision. Why? */
1463                                 A_CLOCK_INIT(117);
1464                                 A_UART_HWINIT(117*1000*1000, 19200);
1465                                 flg = 1;
1466                         }
1467                 }
1468 #endif
1469         } else {
1470                 if(reg == 0x7014)
1471                         ath_pll_reset_ones(ah);
1472
1473                 iowrite32_mac(reg, val);
1474         }
1475 }
1476
1477 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1478                                   A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1479 {
1480         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1481         struct ath_hal *ah = sc->sc_ah;
1482         int i;
1483         struct registerWrite {
1484                 a_uint32_t reg;
1485                 a_uint32_t val;
1486         }*t;
1487
1488         for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1489                 t = (struct registerWrite *)(data+i);
1490
1491                 ath_hal_reg_write_filter(ah, t->reg, t->val);
1492         }
1493
1494         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1495 }
1496
1497 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
1498                                 A_UINT16 SeqNo, A_UINT8 *data,
1499                                 a_int32_t datalen)
1500 {
1501         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1502         struct ath_hal *ah = sc->sc_ah;
1503         struct register_rmw *buf = (struct register_rmw *)data;
1504         int i;
1505
1506         for (i = 0; i < datalen;
1507              i += sizeof(struct register_rmw)) {
1508                 a_uint32_t val;
1509                 buf = (struct register_rmw *)(data + i);
1510
1511                 val = ath_reg_read_filter(ah, buf->reg);
1512                 val &= ~buf->clr;
1513                 val |= buf->set;
1514                 ath_hal_reg_write_filter(ah, buf->reg, val);
1515         }
1516         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1517 }
1518
1519 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1520                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1521 {
1522         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1523         a_uint8_t vap_index;
1524
1525         vap_index = *(a_uint8_t *)data;
1526
1527         sc->sc_vap[vap_index].av_valid = 0;
1528         sc->sc_vap[vap_index].av_bcbuf = NULL;
1529         ath_node_vdelete_tgt(sc, vap_index);
1530         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1531 }
1532
1533 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1534                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1535 {
1536         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1537         struct ath_hal *ah = sc->sc_ah;
1538
1539         ah->ah_setInterrupts(ah, 0);
1540         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1541 }
1542
1543 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1544                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1545 {
1546         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1547         struct ath_rx_buf *bf;
1548
1549         asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1550                 if (bf->bf_skb != NULL) {
1551                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1552                                        ADF_OS_DMA_FROM_DEVICE);
1553                         ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1554                         bf->bf_skb = NULL;
1555                 }
1556
1557         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1558 }
1559
1560 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1561                                 A_UINT8 *data, a_int32_t datalen)
1562 {
1563         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1564         a_uint32_t q = *(a_uint32_t *)data;
1565         struct ath_txq *txq = NULL;
1566
1567         q = adf_os_ntohl(q);
1568         txq = ATH_TXQ(sc, q);
1569
1570         ath_tx_draintxq(sc, txq);
1571         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1572 }
1573
1574 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1575                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1576 {
1577         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1578         HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1579
1580         ath_draintxq(Context, b);
1581         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1582 }
1583
1584 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1585                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1586 {
1587         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1588         struct ath_hal *ah = sc->sc_ah;
1589
1590         ah->ah_abortTxDma(sc->sc_ah);
1591         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1592 }
1593
1594 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1595                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1596 {
1597
1598         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1599         a_uint16_t i;
1600
1601         for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1602                 if (ATH_TXQ_SETUP(sc, i))
1603                         ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1604         }
1605
1606         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1607 }
1608
1609 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1610                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1611 {
1612         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1613         struct ath_hal *ah = sc->sc_ah;
1614         a_uint32_t q;
1615
1616         if (!datalen)
1617                 goto done;
1618
1619         q = *(a_uint32_t *)data;
1620
1621         q = adf_os_ntohl(q);
1622         ah->ah_stopTxDma(ah, q);
1623 done:
1624         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1625 }
1626
1627 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1628                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1629 {
1630
1631         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1632
1633         ath_startrecv(sc);
1634         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1635 }
1636
1637 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1638                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1639 {
1640         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1641         struct ath_hal *ah = sc->sc_ah;
1642
1643         ah->ah_stopPcuReceive(ah);
1644         ah->ah_setRxFilter(ah, 0);
1645         ah->ah_stopDmaReceive(ah);
1646
1647         sc->sc_rxlink = NULL;
1648         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1649 }
1650
1651 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1652                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1653 {
1654         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1655         a_uint16_t mode;
1656
1657         mode= *((a_uint16_t *)data);
1658         mode = adf_os_ntohs(mode);
1659
1660         ath_setcurmode(sc, mode);
1661
1662         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1663 }
1664
1665 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1666                                  A_UINT8 *data, a_int32_t datalen)
1667 {
1668         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1669         struct ath_hal *ah = sc->sc_ah;
1670
1671         ath_desc_free(sc);
1672         ah->ah_detach(ah);
1673         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1674         adf_os_mem_free(sc);
1675 }
1676
1677 static void handle_echo_command(void *pContext, A_UINT16 Command,
1678                                 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1679 {
1680         wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1681 }
1682
1683 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1684                                        A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1685
1686 {
1687         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1688         struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1689
1690         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1691
1692         ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1693                           wmi_data->vap_state,
1694                           capflag,
1695                           &wmi_data->rs);
1696
1697         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1698 }
1699
1700 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1701                                       A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1702 {
1703         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1704         struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1705
1706         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1707
1708         ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1709                              wmi_data->isNew,
1710                              capflag,
1711                              &wmi_data->rs);
1712
1713         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1714 }
1715
1716 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1717                                      A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1718 {
1719         adf_os_assert(0);
1720 }
1721
1722 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1723                             A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1724 {
1725         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1726         struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1727         int idx, band, i;
1728
1729         idx = wmi_data->vap_index;
1730         band = wmi_data->band;
1731
1732         sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1733
1734         if (sc->sc_vap[idx].av_rate_mask[band]) {
1735                 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1736                         if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1737                                 sc->sc_vap[idx].av_minrateidx[band] = i;
1738                                 break;
1739                         }
1740                 }
1741         } else {
1742                 sc->sc_vap[idx].av_minrateidx[band] = 0;
1743         }
1744
1745         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1746 }
1747
1748 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1749 {
1750         {handle_echo_command,         WMI_ECHO_CMDID,               0},
1751         {dispatch_magpie_sys_cmds,    WMI_ACCESS_MEMORY_CMDID,      0},
1752         {ath_get_tgt_version,         WMI_GET_FW_VERSION,           0},
1753         {ath_disable_intr_tgt,        WMI_DISABLE_INTR_CMDID,       0},
1754         {ath_enable_intr_tgt,         WMI_ENABLE_INTR_CMDID,        0},
1755         {ath_init_tgt,                WMI_ATH_INIT_CMDID,           0},
1756         {ath_aborttxq_tgt,            WMI_ABORT_TXQ_CMDID,          0},
1757         {ath_stop_tx_dma_tgt,         WMI_STOP_TX_DMA_CMDID,        0},
1758         {ath_aborttx_dma_tgt,         WMI_ABORT_TX_DMA_CMDID,       0},
1759         {ath_tx_draintxq_tgt,         WMI_DRAIN_TXQ_CMDID,          0},
1760         {ath_draintxq_tgt,            WMI_DRAIN_TXQ_ALL_CMDID,      0},
1761         {ath_startrecv_tgt,           WMI_START_RECV_CMDID,         0},
1762         {ath_stoprecv_tgt,            WMI_STOP_RECV_CMDID,          0},
1763         {ath_flushrecv_tgt,           WMI_FLUSH_RECV_CMDID,         0},
1764         {ath_setcurmode_tgt,          WMI_SET_MODE_CMDID,           0},
1765         {ath_node_create_tgt,         WMI_NODE_CREATE_CMDID,        0},
1766         {ath_node_cleanup_tgt,        WMI_NODE_REMOVE_CMDID,        0},
1767         {ath_vap_delete_tgt,          WMI_VAP_REMOVE_CMDID,         0},
1768         {ath_vap_create_tgt,          WMI_VAP_CREATE_CMDID,         0},
1769         {ath_hal_reg_read_tgt,        WMI_REG_READ_CMDID,           0},
1770         {ath_hal_reg_write_tgt,       WMI_REG_WRITE_CMDID,          0},
1771         {handle_rc_state_change_cmd,  WMI_RC_STATE_CHANGE_CMDID,    0},
1772         {handle_rc_rate_update_cmd,   WMI_RC_RATE_UPDATE_CMDID,     0},
1773         {ath_ic_update_tgt,           WMI_TARGET_IC_UPDATE_CMDID,   0},
1774         {ath_enable_aggr_tgt,         WMI_TX_AGGR_ENABLE_CMDID,     0},
1775         {ath_detach_tgt,              WMI_TGT_DETACH_CMDID,         0},
1776         {ath_node_update_tgt,         WMI_NODE_UPDATE_CMDID,        0},
1777         {ath_int_stats_tgt,           WMI_INT_STATS_CMDID,          0},
1778         {ath_tx_stats_tgt,            WMI_TX_STATS_CMDID,           0},
1779         {ath_rx_stats_tgt,            WMI_RX_STATS_CMDID,           0},
1780         {ath_rc_mask_tgt,             WMI_BITRATE_MASK_CMDID,       0},
1781         {ath_hal_reg_rmw_tgt,         WMI_REG_RMW_CMDID,            0},
1782 };
1783
1784 /*****************/
1785 /* Init / Deinit */
1786 /*****************/
1787
1788 static void htc_setup_comp(void)
1789 {
1790 }
1791
1792 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1793                                   HTC_ENDPOINT_ID eid,
1794                                   A_UINT8 *pDataIn,
1795                                   a_int32_t LengthIn,
1796                                   A_UINT8 *pDataOut,
1797                                   a_int32_t *pLengthOut)
1798 {
1799         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1800
1801         switch(pService->ServiceID) {
1802         case WMI_CONTROL_SVC:
1803                 sc->wmi_command_ep= eid;
1804                 break;
1805         case WMI_BEACON_SVC:
1806                 sc->beacon_ep= eid;
1807                 break;
1808         case WMI_CAB_SVC:
1809                 sc->cab_ep= eid;
1810                 break;
1811         case WMI_UAPSD_SVC:
1812                 sc->uapsd_ep= eid;
1813                 break;
1814         case WMI_MGMT_SVC:
1815                 sc->mgmt_ep= eid;
1816                 break;
1817         case WMI_DATA_VO_SVC:
1818                 sc->data_VO_ep = eid;
1819                 break;
1820         case WMI_DATA_VI_SVC:
1821                 sc->data_VI_ep = eid;
1822                 break;
1823         case WMI_DATA_BE_SVC:
1824                 sc->data_BE_ep = eid;
1825                 break;
1826         case WMI_DATA_BK_SVC:
1827                 sc->data_BK_ep = eid;
1828                 break;
1829         default:
1830                 adf_os_assert(0);
1831         }
1832
1833         return HTC_SERVICE_SUCCESS;
1834 }
1835
1836 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1837                             int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1838 {
1839         svc->ProcessRecvMsg = recvMsg;
1840         svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1841         svc->ProcessConnect = tgt_ServiceConnect;
1842         svc->MaxSvcMsgSize = 1600;
1843         svc->TrailerSpcCheckLimit = 0;
1844         svc->ServiceID = svcId;
1845         svc->ServiceCtx = sc;
1846         HTC_RegisterService(sc->tgt_htc_handle, svc);
1847 }
1848
1849 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1850 {
1851         HTC_CONFIG htc_conf;
1852         WMI_SVC_CONFIG wmiConfig;
1853         WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1854
1855         /* Init dynamic buf pool */
1856         sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1857
1858         /* Init target-side HIF */
1859         sc->tgt_hif_handle = HIF_init(0);
1860
1861         /* Init target-side HTC */
1862         htc_conf.HIFHandle = sc->tgt_hif_handle;
1863         htc_conf.CreditSize = 320;
1864         htc_conf.CreditNumber = ATH_TXBUF;
1865         htc_conf.OSHandle = sc->sc_hdl;
1866         htc_conf.PoolHandle = sc->pool_handle;
1867         sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1868 #if defined(PROJECT_MAGPIE)
1869         init_htc_handle = sc->tgt_htc_handle;
1870 #endif
1871
1872         tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1873         tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1874         tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1875         tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1876         tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1877         tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1878         tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1879         tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1880
1881         /* Init target-side WMI */
1882         Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1883         adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1884         Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1885         Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1886
1887         adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1888         wmiConfig.HtcHandle = sc->tgt_htc_handle;
1889         wmiConfig.PoolHandle = sc->pool_handle;
1890         wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1891         wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1892
1893         sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1894         Magpie_Sys_Commands_Tbl->pContext = sc;
1895         WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1896
1897         HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1898
1899         /* Start HTC messages exchange */
1900         HTC_Ready(sc->tgt_htc_handle);
1901 }
1902
1903 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1904 {
1905         struct ath_hal *ah;
1906         HAL_STATUS status;
1907         a_int32_t error = 0, i, flags = 0;
1908         a_uint8_t csz;
1909
1910         adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1911
1912         if (csz == 0)
1913                 csz = 16;
1914         sc->sc_cachelsz = csz << 2;
1915
1916         sc->sc_dev = osdev;
1917         sc->sc_hdl = osdev;
1918
1919         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1920         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1921         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1922         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1923
1924         flags |= AH_USE_EEPROM;
1925         ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1926         if (ah == NULL) {
1927                 error = ENXIO;
1928                 goto bad;
1929         }
1930         sc->sc_ah = ah;
1931
1932         tgt_hif_htc_wmi_init(sc);
1933
1934         sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1935
1936         ath_rate_setup(sc, IEEE80211_MODE_11NA);
1937         ath_rate_setup(sc, IEEE80211_MODE_11NG);
1938
1939         sc->sc_rc = ath_rate_attach(sc);
1940         if (sc->sc_rc == NULL) {
1941                 error = EIO;
1942                 goto bad2;
1943         }
1944
1945         for (i=0; i < TARGET_NODE_MAX; i++) {
1946                 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1947         }
1948
1949         error = ath_desc_alloc(sc);
1950         if (error != 0) {
1951                 goto bad;
1952         }
1953
1954         BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1955
1956         ath_tgt_txq_setup(sc);
1957         sc->sc_imask =0;
1958         ah->ah_setInterrupts(ah, 0);
1959
1960         return 0;
1961 bad:
1962 bad2:
1963         ath_desc_free(sc);
1964         if (ah)
1965                 ah->ah_detach(ah);
1966 }
1967
1968 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1969 {
1970         HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1971
1972         WMI_Shutdown(sc->tgt_wmi_handle);
1973         HTC_Shutdown(sc->tgt_htc_handle);
1974         HIF_shutdown(sc->tgt_hif_handle);
1975         BUF_Pool_shutdown(sc->pool_handle);
1976 }
1977
1978 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1979 {
1980         tgt_hif_htc_wmi_shutdown(sc);
1981 }