virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 /*
  26  * Call this function to convert a u64 value to an unsigned long * bitmask
  27  * in a way that works on both 32-bit and 64-bit LE and BE platforms.
  28  *
  29  * Warning: Calling this function may modify *val.
  30  */
  31 static unsigned long *u64_to_bitmask(u64 *val)
  32 {
  33 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
  34         *val = (*val >> 32) | (*val << 32);
  35 #endif
  36         return (unsigned long *)val;
  37 }
  38
  39 void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
  40 {
  41         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  42
  43         if (cpuif->vgic_misr & GICH_MISR_EOI) {
  44                 u64 eisr = cpuif->vgic_eisr;
  45                 unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
  46                 int lr;
  47
  48                 for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
  49                         u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
  50
  51                         WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
  52
  53                         /* Only SPIs require notification */
  54                         if (vgic_valid_spi(vcpu->kvm, intid))
  55                                 kvm_notify_acked_irq(vcpu->kvm, 0,
  56                                                      intid - VGIC_NR_PRIVATE_IRQS);
  57                 }
  58         }
  59
  60         /* check and disable underflow maintenance IRQ */
  61         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  62
  63         /*
  64          * In the next iterations of the vcpu loop, if we sync the
  65          * vgic state after flushing it, but before entering the guest
  66          * (this happens for pending signals and vmid rollovers), then
  67          * make sure we don't pick up any old maintenance interrupts
  68          * here.
  69          */
  70         cpuif->vgic_eisr = 0;
  71 }
  72
  73 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  74 {
  75         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  76
  77         cpuif->vgic_hcr |= GICH_HCR_UIE;
  78 }
  79
  80 /*
  81  * transfer the content of the LRs back into the corresponding ap_list:
  82  * - active bit is transferred as is
  83  * - pending bit is
  84  *   - transferred as is in case of edge sensitive IRQs
  85  *   - set to the line-level (resample time) for level sensitive IRQs
  86  */
  87 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  88 {
  89         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  90         int lr;
  91
  92         for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
  93                 u32 val = cpuif->vgic_lr[lr];
  94                 u32 intid = val & GICH_LR_VIRTUALID;
  95                 struct vgic_irq *irq;
  96
  97                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  98
  99                 spin_lock(&irq->irq_lock);
 100
 101                 /* Always preserve the active bit */
 102                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
 103
 104                 /* Edge is the only case where we preserve the pending bit */
 105                 if (irq->config == VGIC_CONFIG_EDGE &&
 106                     (val & GICH_LR_PENDING_BIT)) {
 107                         irq->pending = true;
 108
 109                         if (vgic_irq_is_sgi(intid)) {
 110                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
 111
 112                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
 113                                 irq->source |= (1 << cpuid);
 114                         }
 115                 }
 116
 117                 /*
 118                  * Clear soft pending state when level irqs have been acked.
 119                  * Always regenerate the pending state.
 120                  */
 121                 if (irq->config == VGIC_CONFIG_LEVEL) {
 122                         if (!(val & GICH_LR_PENDING_BIT))
 123                                 irq->soft_pending = false;
 124
 125                         irq->pending = irq->line_level || irq->soft_pending;
 126                 }
 127
 128                 spin_unlock(&irq->irq_lock);
 129                 vgic_put_irq(vcpu->kvm, irq);
 130         }
 131 }
 132
 133 /*
 134  * Populates the particular LR with the state of a given IRQ:
 135  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 136  * - for a level sensitive IRQ the pending state value is unchanged;
 137  *   it is dictated directly by the input level
 138  *
 139  * If @irq describes an SGI with multiple sources, we choose the
 140  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 141  *
 142  * The irq_lock must be held by the caller.
 143  */
 144 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 145 {
 146         u32 val = irq->intid;
 147
 148         if (irq->pending) {
 149                 val |= GICH_LR_PENDING_BIT;
 150
 151                 if (irq->config == VGIC_CONFIG_EDGE)
 152                         irq->pending = false;
 153
 154                 if (vgic_irq_is_sgi(irq->intid)) {
 155                         u32 src = ffs(irq->source);
 156
 157                         BUG_ON(!src);
 158                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 159                         irq->source &= ~(1 << (src - 1));
 160                         if (irq->source)
 161                                 irq->pending = true;
 162                 }
 163         }
 164
 165         if (irq->active)
 166                 val |= GICH_LR_ACTIVE_BIT;
 167
 168         if (irq->hw) {
 169                 val |= GICH_LR_HW;
 170                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 171         } else {
 172                 if (irq->config == VGIC_CONFIG_LEVEL)
 173                         val |= GICH_LR_EOI;
 174         }
 175
 176         /* The GICv2 LR only holds five bits of priority. */
 177         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 178
 179         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 180 }
 181
 182 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 183 {
 184         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 185 }
 186
 187 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 188 {
 189         u32 vmcr;
 190
 191         vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
 192         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 193                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 194         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 195                 GICH_VMCR_BINPOINT_MASK;
 196         vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &
 197                 GICH_VMCR_PRIMASK_MASK;
 198
 199         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
 200 }
 201
 202 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 203 {
 204         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
 205
 206         vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
 207                         GICH_VMCR_CTRL_SHIFT;
 208         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 209                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 210         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 211                         GICH_VMCR_BINPOINT_SHIFT;
 212         vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >>
 213                         GICH_VMCR_PRIMASK_SHIFT;
 214 }
 215
 216 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 217 {
 218         /*
 219          * By forcing VMCR to zero, the GIC will restore the binary
 220          * points to their reset values. Anything else resets to zero
 221          * anyway.
 222          */
 223         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 224         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 225
 226         /* Get the show on the road... */
 227         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 228 }
 229
 230 /* check for overlapping regions and for regions crossing the end of memory */
 231 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 232 {
 233         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 234                 return false;
 235         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 236                 return false;
 237
 238         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 239                 return true;
 240         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 241                 return true;
 242
 243         return false;
 244 }
 245
 246 int vgic_v2_map_resources(struct kvm *kvm)
 247 {
 248         struct vgic_dist *dist = &kvm->arch.vgic;
 249         int ret = 0;
 250
 251         if (vgic_ready(kvm))
 252                 goto out;
 253
 254         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 255             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 256                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 257                 ret = -ENXIO;
 258                 goto out;
 259         }
 260
 261         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 262                 kvm_err("VGIC CPU and dist frames overlap\n");
 263                 ret = -EINVAL;
 264                 goto out;
 265         }
 266
 267         /*
 268          * Initialize the vgic if this hasn't already been done on demand by
 269          * accessing the vgic state from userspace.
 270          */
 271         ret = vgic_init(kvm);
 272         if (ret) {
 273                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 274                 goto out;
 275         }
 276
 277         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 278         if (ret) {
 279                 kvm_err("Unable to register VGIC MMIO regions\n");
 280                 goto out;
 281         }
 282
 283         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 284                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 285                                             kvm_vgic_global_state.vcpu_base,
 286                                             KVM_VGIC_V2_CPU_SIZE, true);
 287                 if (ret) {
 288                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 289                         goto out;
 290                 }
 291         }
 292
 293         dist->ready = true;
 294
 295 out:
 296         return ret;
 297 }
 298
 299 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 300
 301 /**
 302  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 303  * @node:       pointer to the DT node
 304  *
 305  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 306  */
 307 int vgic_v2_probe(const struct gic_kvm_info *info)
 308 {
 309         int ret;
 310         u32 vtr;
 311
 312         if (!info->vctrl.start) {
 313                 kvm_err("GICH not present in the firmware table\n");
 314                 return -ENXIO;
 315         }
 316
 317         if (!PAGE_ALIGNED(info->vcpu.start) ||
 318             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 319                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 320                 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
 321                                                              resource_size(&info->vcpu));
 322                 if (!kvm_vgic_global_state.vcpu_base_va) {
 323                         kvm_err("Cannot ioremap GICV\n");
 324                         return -ENOMEM;
 325                 }
 326
 327                 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
 328                                              kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
 329                                              info->vcpu.start);
 330                 if (ret) {
 331                         kvm_err("Cannot map GICV into hyp\n");
 332                         goto out;
 333                 }
 334
 335                 static_branch_enable(&vgic_v2_cpuif_trap);
 336         }
 337
 338         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 339                                                    resource_size(&info->vctrl));
 340         if (!kvm_vgic_global_state.vctrl_base) {
 341                 kvm_err("Cannot ioremap GICH\n");
 342                 ret = -ENOMEM;
 343                 goto out;
 344         }
 345
 346         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 347         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 348
 349         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 350                                      kvm_vgic_global_state.vctrl_base +
 351                                          resource_size(&info->vctrl),
 352                                      info->vctrl.start);
 353         if (ret) {
 354                 kvm_err("Cannot map VCTRL into hyp\n");
 355                 goto out;
 356         }
 357
 358         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 359         if (ret) {
 360                 kvm_err("Cannot register GICv2 KVM device\n");
 361                 goto out;
 362         }
 363
 364         kvm_vgic_global_state.can_emulate_gicv2 = true;
 365         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 366         kvm_vgic_global_state.type = VGIC_V2;
 367         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 368
 369         kvm_info("vgic-v2@%llx\n", info->vctrl.start);
 370
 371         return 0;
 372 out:
 373         if (kvm_vgic_global_state.vctrl_base)
 374                 iounmap(kvm_vgic_global_state.vctrl_base);
 375         if (kvm_vgic_global_state.vcpu_base_va)
 376                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 377
 378         return ret;
 379 }