tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json

   1 [
   2     {
   3         "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
   4         "EventCode": "0x08",
   5         "Counter": "0,1,2,3",
   6         "UMask": "0x1",
   7         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
   8         "SampleAfterValue": "100003",
   9         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
  10         "CounterHTOff": "0,1,2,3,4,5,6,7"
  11     },
  12     {
  13         "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
  14         "EventCode": "0x08",
  15         "Counter": "0,1,2,3",
  16         "UMask": "0x2",
  17         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
  18         "SampleAfterValue": "2000003",
  19         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
  20         "CounterHTOff": "0,1,2,3,4,5,6,7"
  21     },
  22     {
  23         "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
  24         "EventCode": "0x08",
  25         "Counter": "0,1,2,3",
  26         "UMask": "0x4",
  27         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
  28         "SampleAfterValue": "2000003",
  29         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
  30         "CounterHTOff": "0,1,2,3,4,5,6,7"
  31     },
  32     {
  33         "EventCode": "0x08",
  34         "Counter": "0,1,2,3",
  35         "UMask": "0x8",
  36         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
  37         "SampleAfterValue": "2000003",
  38         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
  39         "CounterHTOff": "0,1,2,3,4,5,6,7"
  40     },
  41     {
  42         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
  43         "EventCode": "0x08",
  44         "Counter": "0,1,2,3",
  45         "UMask": "0x10",
  46         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
  47         "SampleAfterValue": "2000003",
  48         "BriefDescription": "Cycles when PMH is busy with page walks",
  49         "CounterHTOff": "0,1,2,3,4,5,6,7"
  50     },
  51     {
  52         "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
  53         "EventCode": "0x08",
  54         "Counter": "0,1,2,3",
  55         "UMask": "0x20",
  56         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
  57         "SampleAfterValue": "2000003",
  58         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
  59         "CounterHTOff": "0,1,2,3,4,5,6,7"
  60     },
  61     {
  62         "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
  63         "EventCode": "0x08",
  64         "Counter": "0,1,2,3",
  65         "UMask": "0x40",
  66         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
  67         "SampleAfterValue": "2000003",
  68         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",
  69         "CounterHTOff": "0,1,2,3,4,5,6,7"
  70     },
  71     {
  72         "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
  73         "EventCode": "0x08",
  74         "Counter": "0,1,2,3",
  75         "UMask": "0x80",
  76         "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
  77         "SampleAfterValue": "100003",
  78         "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
  79         "CounterHTOff": "0,1,2,3,4,5,6,7"
  80     },
  81     {
  82         "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
  83         "EventCode": "0x49",
  84         "Counter": "0,1,2,3",
  85         "UMask": "0x1",
  86         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
  87         "SampleAfterValue": "100003",
  88         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
  89         "CounterHTOff": "0,1,2,3,4,5,6,7"
  90     },
  91     {
  92         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
  93         "EventCode": "0x49",
  94         "Counter": "0,1,2,3",
  95         "UMask": "0x2",
  96         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
  97         "SampleAfterValue": "100003",
  98         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
  99         "CounterHTOff": "0,1,2,3,4,5,6,7"
 100     },
 101     {
 102         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
 103         "EventCode": "0x49",
 104         "Counter": "0,1,2,3",
 105         "UMask": "0x4",
 106         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
 107         "SampleAfterValue": "100003",
 108         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
 109         "CounterHTOff": "0,1,2,3,4,5,6,7"
 110     },
 111     {
 112         "EventCode": "0x49",
 113         "Counter": "0,1,2,3",
 114         "UMask": "0x8",
 115         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
 116         "SampleAfterValue": "100003",
 117         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
 118         "CounterHTOff": "0,1,2,3,4,5,6,7"
 119     },
 120     {
 121         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
 122         "EventCode": "0x49",
 123         "Counter": "0,1,2,3",
 124         "UMask": "0x10",
 125         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
 126         "SampleAfterValue": "100003",
 127         "BriefDescription": "Cycles when PMH is busy with page walks",
 128         "CounterHTOff": "0,1,2,3,4,5,6,7"
 129     },
 130     {
 131         "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
 132         "EventCode": "0x49",
 133         "Counter": "0,1,2,3",
 134         "UMask": "0x20",
 135         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
 136         "SampleAfterValue": "100003",
 137         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
 138         "CounterHTOff": "0,1,2,3,4,5,6,7"
 139     },
 140     {
 141         "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
 142         "EventCode": "0x49",
 143         "Counter": "0,1,2,3",
 144         "UMask": "0x40",
 145         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
 146         "SampleAfterValue": "100003",
 147         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M)",
 148         "CounterHTOff": "0,1,2,3,4,5,6,7"
 149     },
 150     {
 151         "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
 152         "EventCode": "0x49",
 153         "Counter": "0,1,2,3",
 154         "UMask": "0x80",
 155         "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
 156         "SampleAfterValue": "100003",
 157         "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
 158         "CounterHTOff": "0,1,2,3,4,5,6,7"
 159     },
 160     {
 161         "EventCode": "0x4f",
 162         "Counter": "0,1,2,3",
 163         "UMask": "0x10",
 164         "EventName": "EPT.WALK_CYCLES",
 165         "SampleAfterValue": "2000003",
 166         "BriefDescription": "Cycle count for an Extended Page table walk.",
 167         "CounterHTOff": "0,1,2,3,4,5,6,7"
 168     },
 169     {
 170         "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
 171         "EventCode": "0x85",
 172         "Counter": "0,1,2,3",
 173         "UMask": "0x1",
 174         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
 175         "SampleAfterValue": "100003",
 176         "BriefDescription": "Misses at all ITLB levels that cause page walks",
 177         "CounterHTOff": "0,1,2,3,4,5,6,7"
 178     },
 179     {
 180         "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
 181         "EventCode": "0x85",
 182         "Counter": "0,1,2,3",
 183         "UMask": "0x2",
 184         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
 185         "SampleAfterValue": "100003",
 186         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
 187         "CounterHTOff": "0,1,2,3,4,5,6,7"
 188     },
 189     {
 190         "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
 191         "EventCode": "0x85",
 192         "Counter": "0,1,2,3",
 193         "UMask": "0x4",
 194         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
 195         "SampleAfterValue": "100003",
 196         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
 197         "CounterHTOff": "0,1,2,3,4,5,6,7"
 198     },
 199     {
 200         "EventCode": "0x85",
 201         "Counter": "0,1,2,3",
 202         "UMask": "0x8",
 203         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
 204         "SampleAfterValue": "100003",
 205         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
 206         "CounterHTOff": "0,1,2,3,4,5,6,7"
 207     },
 208     {
 209         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses.",
 210         "EventCode": "0x85",
 211         "Counter": "0,1,2,3",
 212         "UMask": "0x10",
 213         "EventName": "ITLB_MISSES.WALK_DURATION",
 214         "SampleAfterValue": "100003",
 215         "BriefDescription": "Cycles when PMH is busy with page walks",
 216         "CounterHTOff": "0,1,2,3,4,5,6,7"
 217     },
 218     {
 219         "PublicDescription": "ITLB misses that hit STLB (4K).",
 220         "EventCode": "0x85",
 221         "Counter": "0,1,2,3",
 222         "UMask": "0x20",
 223         "EventName": "ITLB_MISSES.STLB_HIT_4K",
 224         "SampleAfterValue": "100003",
 225         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
 226         "CounterHTOff": "0,1,2,3,4,5,6,7"
 227     },
 228     {
 229         "PublicDescription": "ITLB misses that hit STLB (2M).",
 230         "EventCode": "0x85",
 231         "Counter": "0,1,2,3",
 232         "UMask": "0x40",
 233         "EventName": "ITLB_MISSES.STLB_HIT_2M",
 234         "SampleAfterValue": "100003",
 235         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",
 236         "CounterHTOff": "0,1,2,3,4,5,6,7"
 237     },
 238     {
 239         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
 240         "EventCode": "0xae",
 241         "Counter": "0,1,2,3",
 242         "UMask": "0x1",
 243         "EventName": "ITLB.ITLB_FLUSH",
 244         "SampleAfterValue": "100003",
 245         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
 246         "CounterHTOff": "0,1,2,3,4,5,6,7"
 247     },
 248     {
 249         "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
 250         "EventCode": "0xBC",
 251         "Counter": "0,1,2,3",
 252         "UMask": "0x11",
 253         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
 254         "SampleAfterValue": "2000003",
 255         "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
 256         "CounterHTOff": "0,1,2,3"
 257     },
 258     {
 259         "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
 260         "EventCode": "0xBC",
 261         "Counter": "0,1,2,3",
 262         "UMask": "0x21",
 263         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
 264         "SampleAfterValue": "2000003",
 265         "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
 266         "CounterHTOff": "0,1,2,3"
 267     },
 268     {
 269         "EventCode": "0xBC",
 270         "Counter": "0,1,2,3",
 271         "UMask": "0x41",
 272         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
 273         "SampleAfterValue": "2000003",
 274         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
 275         "CounterHTOff": "0,1,2,3"
 276     },
 277     {
 278         "EventCode": "0xBC",
 279         "Counter": "0,1,2,3",
 280         "UMask": "0x81",
 281         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
 282         "SampleAfterValue": "2000003",
 283         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
 284         "CounterHTOff": "0,1,2,3"
 285     },
 286     {
 287         "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
 288         "EventCode": "0xBC",
 289         "Counter": "0,1,2,3",
 290         "UMask": "0x12",
 291         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
 292         "SampleAfterValue": "2000003",
 293         "BriefDescription": "Number of DTLB page walker hits in the L2",
 294         "CounterHTOff": "0,1,2,3"
 295     },
 296     {
 297         "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
 298         "EventCode": "0xBC",
 299         "Counter": "0,1,2,3",
 300         "UMask": "0x22",
 301         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
 302         "SampleAfterValue": "2000003",
 303         "BriefDescription": "Number of ITLB page walker hits in the L2",
 304         "CounterHTOff": "0,1,2,3"
 305     },
 306     {
 307         "EventCode": "0xBC",
 308         "Counter": "0,1,2,3",
 309         "UMask": "0x42",
 310         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
 311         "SampleAfterValue": "2000003",
 312         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
 313         "CounterHTOff": "0,1,2,3"
 314     },
 315     {
 316         "EventCode": "0xBC",
 317         "Counter": "0,1,2,3",
 318         "UMask": "0x82",
 319         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
 320         "SampleAfterValue": "2000003",
 321         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
 322         "CounterHTOff": "0,1,2,3"
 323     },
 324     {
 325         "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
 326         "EventCode": "0xBC",
 327         "Counter": "0,1,2,3",
 328         "UMask": "0x14",
 329         "Errata": "HSD25",
 330         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
 331         "SampleAfterValue": "2000003",
 332         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
 333         "CounterHTOff": "0,1,2,3"
 334     },
 335     {
 336         "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
 337         "EventCode": "0xBC",
 338         "Counter": "0,1,2,3",
 339         "UMask": "0x24",
 340         "Errata": "HSD25",
 341         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
 342         "SampleAfterValue": "2000003",
 343         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
 344         "CounterHTOff": "0,1,2,3"
 345     },
 346     {
 347         "EventCode": "0xBC",
 348         "Counter": "0,1,2,3",
 349         "UMask": "0x44",
 350         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
 351         "SampleAfterValue": "2000003",
 352         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
 353         "CounterHTOff": "0,1,2,3"
 354     },
 355     {
 356         "EventCode": "0xBC",
 357         "Counter": "0,1,2,3",
 358         "UMask": "0x84",
 359         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
 360         "SampleAfterValue": "2000003",
 361         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
 362         "CounterHTOff": "0,1,2,3"
 363     },
 364     {
 365         "PublicDescription": "Number of DTLB page walker loads from memory.",
 366         "EventCode": "0xBC",
 367         "Counter": "0,1,2,3",
 368         "UMask": "0x18",
 369         "Errata": "HSD25",
 370         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
 371         "SampleAfterValue": "2000003",
 372         "BriefDescription": "Number of DTLB page walker hits in Memory",
 373         "CounterHTOff": "0,1,2,3"
 374     },
 375     {
 376         "PublicDescription": "Number of ITLB page walker loads from memory.",
 377         "EventCode": "0xBC",
 378         "Counter": "0,1,2,3",
 379         "UMask": "0x28",
 380         "Errata": "HSD25",
 381         "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
 382         "SampleAfterValue": "2000003",
 383         "BriefDescription": "Number of ITLB page walker hits in Memory",
 384         "CounterHTOff": "0,1,2,3"
 385     },
 386     {
 387         "EventCode": "0xBC",
 388         "Counter": "0,1,2,3",
 389         "UMask": "0x48",
 390         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
 391         "SampleAfterValue": "2000003",
 392         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
 393         "CounterHTOff": "0,1,2,3"
 394     },
 395     {
 396         "EventCode": "0xBC",
 397         "Counter": "0,1,2,3",
 398         "UMask": "0x88",
 399         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
 400         "SampleAfterValue": "2000003",
 401         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
 402         "CounterHTOff": "0,1,2,3"
 403     },
 404     {
 405         "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
 406         "EventCode": "0xBD",
 407         "Counter": "0,1,2,3",
 408         "UMask": "0x1",
 409         "EventName": "TLB_FLUSH.DTLB_THREAD",
 410         "SampleAfterValue": "100003",
 411         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
 412         "CounterHTOff": "0,1,2,3,4,5,6,7"
 413     },
 414     {
 415         "PublicDescription": "Count number of STLB flush attempts.",
 416         "EventCode": "0xBD",
 417         "Counter": "0,1,2,3",
 418         "UMask": "0x20",
 419         "EventName": "TLB_FLUSH.STLB_ANY",
 420         "SampleAfterValue": "100003",
 421         "BriefDescription": "STLB flush attempts",
 422         "CounterHTOff": "0,1,2,3,4,5,6,7"
 423     },
 424     {
 425         "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
 426         "EventCode": "0x08",
 427         "Counter": "0,1,2,3",
 428         "UMask": "0xe",
 429         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
 430         "SampleAfterValue": "100003",
 431         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
 432         "CounterHTOff": "0,1,2,3,4,5,6,7"
 433     },
 434     {
 435         "PublicDescription": "Number of cache load STLB hits. No page walk.",
 436         "EventCode": "0x08",
 437         "Counter": "0,1,2,3",
 438         "UMask": "0x60",
 439         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
 440         "SampleAfterValue": "2000003",
 441         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
 442         "CounterHTOff": "0,1,2,3,4,5,6,7"
 443     },
 444     {
 445         "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
 446         "EventCode": "0x49",
 447         "Counter": "0,1,2,3",
 448         "UMask": "0xe",
 449         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
 450         "SampleAfterValue": "100003",
 451         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
 452         "CounterHTOff": "0,1,2,3,4,5,6,7"
 453     },
 454     {
 455         "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
 456         "EventCode": "0x49",
 457         "Counter": "0,1,2,3",
 458         "UMask": "0x60",
 459         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
 460         "SampleAfterValue": "100003",
 461         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
 462         "CounterHTOff": "0,1,2,3,4,5,6,7"
 463     },
 464     {
 465         "PublicDescription": "Completed page walks in ITLB of any page size.",
 466         "EventCode": "0x85",
 467         "Counter": "0,1,2,3",
 468         "UMask": "0xe",
 469         "EventName": "ITLB_MISSES.WALK_COMPLETED",
 470         "SampleAfterValue": "100003",
 471         "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
 472         "CounterHTOff": "0,1,2,3,4,5,6,7"
 473     },
 474     {
 475         "PublicDescription": "ITLB misses that hit STLB. No page walk.",
 476         "EventCode": "0x85",
 477         "Counter": "0,1,2,3",
 478         "UMask": "0x60",
 479         "EventName": "ITLB_MISSES.STLB_HIT",
 480         "SampleAfterValue": "100003",
 481         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
 482         "CounterHTOff": "0,1,2,3,4,5,6,7"
 483     }
 484 ]