sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = codec->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110                 return 1;
 111         default:
 112                 return 0;
 113         }
 114 }
 115
 116 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 117         unsigned int value)
 118 {
 119         int ret;
 120
 121         BUG_ON(reg > WM8994_MAX_REGISTER);
 122
 123         if (!wm8994_volatile(codec, reg)) {
 124                 ret = snd_soc_cache_write(codec, reg, value);
 125                 if (ret != 0)
 126                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 127                                 reg, ret);
 128         }
 129
 130         return wm8994_reg_write(codec->control_data, reg, value);
 131 }
 132
 133 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 134                                 unsigned int reg)
 135 {
 136         unsigned int val;
 137         int ret;
 138
 139         BUG_ON(reg > WM8994_MAX_REGISTER);
 140
 141         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 142             reg < codec->driver->reg_cache_size) {
 143                 ret = snd_soc_cache_read(codec, reg, &val);
 144                 if (ret >= 0)
 145                         return val;
 146                 else
 147                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 148                                 reg, ret);
 149         }
 150
 151         return wm8994_reg_read(codec->control_data, reg);
 152 }
 153
 154 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 155 {
 156         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 157         int rate;
 158         int reg1 = 0;
 159         int offset;
 160
 161         if (aif)
 162                 offset = 4;
 163         else
 164                 offset = 0;
 165
 166         switch (wm8994->sysclk[aif]) {
 167         case WM8994_SYSCLK_MCLK1:
 168                 rate = wm8994->mclk[0];
 169                 break;
 170
 171         case WM8994_SYSCLK_MCLK2:
 172                 reg1 |= 0x8;
 173                 rate = wm8994->mclk[1];
 174                 break;
 175
 176         case WM8994_SYSCLK_FLL1:
 177                 reg1 |= 0x10;
 178                 rate = wm8994->fll[0].out;
 179                 break;
 180
 181         case WM8994_SYSCLK_FLL2:
 182                 reg1 |= 0x18;
 183                 rate = wm8994->fll[1].out;
 184                 break;
 185
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         if (rate >= 13500000) {
 191                 rate /= 2;
 192                 reg1 |= WM8994_AIF1CLK_DIV;
 193
 194                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 195                         aif + 1, rate);
 196         }
 197
 198         if (rate && rate < 3000000)
 199                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 200                          aif + 1, rate);
 201
 202         wm8994->aifclk[aif] = rate;
 203
 204         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 205                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 206                             reg1);
 207
 208         return 0;
 209 }
 210
 211 static int configure_clock(struct snd_soc_codec *codec)
 212 {
 213         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 214         int old, new;
 215
 216         /* Bring up the AIF clocks first */
 217         configure_aif_clock(codec, 0);
 218         configure_aif_clock(codec, 1);
 219
 220         /* Then switch CLK_SYS over to the higher of them; a change
 221          * can only happen as a result of a clocking change which can
 222          * only be made outside of DAPM so we can safely redo the
 223          * clocking.
 224          */
 225
 226         /* If they're equal it doesn't matter which is used */
 227         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 228                 return 0;
 229
 230         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 231                 new = WM8994_SYSCLK_SRC;
 232         else
 233                 new = 0;
 234
 235         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 236
 237         /* If there's no change then we're done. */
 238         if (old == new)
 239                 return 0;
 240
 241         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 242
 243         snd_soc_dapm_sync(&codec->dapm);
 244
 245         return 0;
 246 }
 247
 248 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 249                          struct snd_soc_dapm_widget *sink)
 250 {
 251         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 252         const char *clk;
 253
 254         /* Check what we're currently using for CLK_SYS */
 255         if (reg & WM8994_SYSCLK_SRC)
 256                 clk = "AIF2CLK";
 257         else
 258                 clk = "AIF1CLK";
 259
 260         return strcmp(source->name, clk) == 0;
 261 }
 262
 263 static const char *sidetone_hpf_text[] = {
 264         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 265 };
 266
 267 static const struct soc_enum sidetone_hpf =
 268         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 269
 270 static const char *adc_hpf_text[] = {
 271         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 272 };
 273
 274 static const struct soc_enum aif1adc1_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const struct soc_enum aif1adc2_hpf =
 278         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 279
 280 static const struct soc_enum aif2adc_hpf =
 281         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 282
 283 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 284 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 285 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 287 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 288
 289 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 290 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 291         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 292         .put = wm8994_put_drc_sw, \
 293         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 294
 295 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 296                              struct snd_ctl_elem_value *ucontrol)
 297 {
 298         struct soc_mixer_control *mc =
 299                 (struct soc_mixer_control *)kcontrol->private_value;
 300         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 301         int mask, ret;
 302
 303         /* Can't enable both ADC and DAC paths simultaneously */
 304         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 305                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 306                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 307         else
 308                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 309
 310         ret = snd_soc_read(codec, mc->reg);
 311         if (ret < 0)
 312                 return ret;
 313         if (ret & mask)
 314                 return -EINVAL;
 315
 316         return snd_soc_put_volsw(kcontrol, ucontrol);
 317 }
 318
 319 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 320 {
 321         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 322         struct wm8994_pdata *pdata = wm8994->pdata;
 323         int base = wm8994_drc_base[drc];
 324         int cfg = wm8994->drc_cfg[drc];
 325         int save, i;
 326
 327         /* Save any enables; the configuration should clear them. */
 328         save = snd_soc_read(codec, base);
 329         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 330                 WM8994_AIF1ADC1R_DRC_ENA;
 331
 332         for (i = 0; i < WM8994_DRC_REGS; i++)
 333                 snd_soc_update_bits(codec, base + i, 0xffff,
 334                                     pdata->drc_cfgs[cfg].regs[i]);
 335
 336         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 337                              WM8994_AIF1ADC1L_DRC_ENA |
 338                              WM8994_AIF1ADC1R_DRC_ENA, save);
 339 }
 340
 341 /* Icky as hell but saves code duplication */
 342 static int wm8994_get_drc(const char *name)
 343 {
 344         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 345                 return 0;
 346         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 347                 return 1;
 348         if (strcmp(name, "AIF2DRC Mode") == 0)
 349                 return 2;
 350         return -EINVAL;
 351 }
 352
 353 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 354                                struct snd_ctl_elem_value *ucontrol)
 355 {
 356         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 357         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 358         struct wm8994_pdata *pdata = wm8994->pdata;
 359         int drc = wm8994_get_drc(kcontrol->id.name);
 360         int value = ucontrol->value.integer.value[0];
 361
 362         if (drc < 0)
 363                 return drc;
 364
 365         if (value >= pdata->num_drc_cfgs)
 366                 return -EINVAL;
 367
 368         wm8994->drc_cfg[drc] = value;
 369
 370         wm8994_set_drc(codec, drc);
 371
 372         return 0;
 373 }
 374
 375 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 376                                struct snd_ctl_elem_value *ucontrol)
 377 {
 378         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 379         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 380         int drc = wm8994_get_drc(kcontrol->id.name);
 381
 382         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 383
 384         return 0;
 385 }
 386
 387 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 388 {
 389         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 390         struct wm8994_pdata *pdata = wm8994->pdata;
 391         int base = wm8994_retune_mobile_base[block];
 392         int iface, best, best_val, save, i, cfg;
 393
 394         if (!pdata || !wm8994->num_retune_mobile_texts)
 395                 return;
 396
 397         switch (block) {
 398         case 0:
 399         case 1:
 400                 iface = 0;
 401                 break;
 402         case 2:
 403                 iface = 1;
 404                 break;
 405         default:
 406                 return;
 407         }
 408
 409         /* Find the version of the currently selected configuration
 410          * with the nearest sample rate. */
 411         cfg = wm8994->retune_mobile_cfg[block];
 412         best = 0;
 413         best_val = INT_MAX;
 414         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 415                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 416                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 417                     abs(pdata->retune_mobile_cfgs[i].rate
 418                         - wm8994->dac_rates[iface]) < best_val) {
 419                         best = i;
 420                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 421                                        - wm8994->dac_rates[iface]);
 422                 }
 423         }
 424
 425         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 426                 block,
 427                 pdata->retune_mobile_cfgs[best].name,
 428                 pdata->retune_mobile_cfgs[best].rate,
 429                 wm8994->dac_rates[iface]);
 430
 431         /* The EQ will be disabled while reconfiguring it, remember the
 432          * current configuration.
 433          */
 434         save = snd_soc_read(codec, base);
 435         save &= WM8994_AIF1DAC1_EQ_ENA;
 436
 437         for (i = 0; i < WM8994_EQ_REGS; i++)
 438                 snd_soc_update_bits(codec, base + i, 0xffff,
 439                                 pdata->retune_mobile_cfgs[best].regs[i]);
 440
 441         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 442 }
 443
 444 /* Icky as hell but saves code duplication */
 445 static int wm8994_get_retune_mobile_block(const char *name)
 446 {
 447         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 448                 return 0;
 449         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 450                 return 1;
 451         if (strcmp(name, "AIF2 EQ Mode") == 0)
 452                 return 2;
 453         return -EINVAL;
 454 }
 455
 456 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 457                                          struct snd_ctl_elem_value *ucontrol)
 458 {
 459         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 460         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 461         struct wm8994_pdata *pdata = wm8994->pdata;
 462         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 463         int value = ucontrol->value.integer.value[0];
 464
 465         if (block < 0)
 466                 return block;
 467
 468         if (value >= pdata->num_retune_mobile_cfgs)
 469                 return -EINVAL;
 470
 471         wm8994->retune_mobile_cfg[block] = value;
 472
 473         wm8994_set_retune_mobile(codec, block);
 474
 475         return 0;
 476 }
 477
 478 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 479                                          struct snd_ctl_elem_value *ucontrol)
 480 {
 481         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 482         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 483         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 484
 485         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 486
 487         return 0;
 488 }
 489
 490 static const char *aif_chan_src_text[] = {
 491         "Left", "Right"
 492 };
 493
 494 static const struct soc_enum aif1adcl_src =
 495         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 496
 497 static const struct soc_enum aif1adcr_src =
 498         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 499
 500 static const struct soc_enum aif2adcl_src =
 501         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 502
 503 static const struct soc_enum aif2adcr_src =
 504         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 505
 506 static const struct soc_enum aif1dacl_src =
 507         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 508
 509 static const struct soc_enum aif1dacr_src =
 510         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 511
 512 static const struct soc_enum aif2dacl_src =
 513         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 514
 515 static const struct soc_enum aif2dacr_src =
 516         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 517
 518 static const char *osr_text[] = {
 519         "Low Power", "High Performance",
 520 };
 521
 522 static const struct soc_enum dac_osr =
 523         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 524
 525 static const struct soc_enum adc_osr =
 526         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 527
 528 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 529 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 530                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 531                  1, 119, 0, digital_tlv),
 532 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 533                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 534                  1, 119, 0, digital_tlv),
 535 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 536                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 537                  1, 119, 0, digital_tlv),
 538
 539 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 540 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 541 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 542 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 543
 544 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 545 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 546 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 547 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 548
 549 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 550                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 552                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 553 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 554                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 555
 556 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 557 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 558
 559 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 560 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 561 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 568 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 569 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 570
 571 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 572 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 573 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 574
 575 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 580                5, 12, 0, st_tlv),
 581 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 582                0, 12, 0, st_tlv),
 583 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 584 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 585
 586 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 587 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 588
 589 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 590 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 591
 592 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 593 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 594
 595 SOC_ENUM("ADC OSR", adc_osr),
 596 SOC_ENUM("DAC OSR", dac_osr),
 597
 598 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 599                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 600 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 601              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 602
 603 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 604                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 605 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 606              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 607
 608 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 609                6, 1, 1, wm_hubs_spkmix_tlv),
 610 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 611                2, 1, 1, wm_hubs_spkmix_tlv),
 612
 613 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 614                6, 1, 1, wm_hubs_spkmix_tlv),
 615 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 616                2, 1, 1, wm_hubs_spkmix_tlv),
 617
 618 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 625            8, 1, 0),
 626 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 627                10, 15, 0, wm8994_3d_tlv),
 628 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 629            8, 1, 0),
 630 };
 631
 632 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 638                eq_tlv),
 639 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 640                eq_tlv),
 641 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 642                eq_tlv),
 643
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 649                eq_tlv),
 650 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 651                eq_tlv),
 652 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 653                eq_tlv),
 654
 655 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 660                eq_tlv),
 661 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 662                eq_tlv),
 663 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 664                eq_tlv),
 665 };
 666
 667 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 668 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 669 };
 670
 671 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 672                          struct snd_kcontrol *kcontrol, int event)
 673 {
 674         struct snd_soc_codec *codec = w->codec;
 675
 676         switch (event) {
 677         case SND_SOC_DAPM_PRE_PMU:
 678                 return configure_clock(codec);
 679
 680         case SND_SOC_DAPM_POST_PMD:
 681                 configure_clock(codec);
 682                 break;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 689 {
 690         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 691         int enable = 1;
 692         int source = 0;  /* GCC flow analysis can't track enable */
 693         int reg, reg_r;
 694
 695         /* Only support direct DAC->headphone paths */
 696         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 697         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 698                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 699                 enable = 0;
 700         }
 701
 702         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 703         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 704                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 705                 enable = 0;
 706         }
 707
 708         /* We also need the same setting for L/R and only one path */
 709         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 710         switch (reg) {
 711         case WM8994_AIF2DACL_TO_DAC1L:
 712                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 713                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 714                 break;
 715         case WM8994_AIF1DAC2L_TO_DAC1L:
 716                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 717                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 718                 break;
 719         case WM8994_AIF1DAC1L_TO_DAC1L:
 720                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 721                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 722                 break;
 723         default:
 724                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 725                 enable = 0;
 726                 break;
 727         }
 728
 729         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 730         if (reg_r != reg) {
 731                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 732                 enable = 0;
 733         }
 734
 735         if (enable) {
 736                 dev_dbg(codec->dev, "Class W enabled\n");
 737                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 738                                     WM8994_CP_DYN_PWR |
 739                                     WM8994_CP_DYN_SRC_SEL_MASK,
 740                                     source | WM8994_CP_DYN_PWR);
 741                 wm8994->hubs.class_w = true;
 742
 743         } else {
 744                 dev_dbg(codec->dev, "Class W disabled\n");
 745                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 746                                     WM8994_CP_DYN_PWR, 0);
 747                 wm8994->hubs.class_w = false;
 748         }
 749 }
 750
 751 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 752                           struct snd_kcontrol *kcontrol, int event)
 753 {
 754         struct snd_soc_codec *codec = w->codec;
 755         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 if (wm8994->aif1clk_enable) {
 760                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 761                                             WM8994_AIF1CLK_ENA_MASK,
 762                                             WM8994_AIF1CLK_ENA);
 763                         wm8994->aif1clk_enable = 0;
 764                 }
 765                 if (wm8994->aif2clk_enable) {
 766                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 767                                             WM8994_AIF2CLK_ENA_MASK,
 768                                             WM8994_AIF2CLK_ENA);
 769                         wm8994->aif2clk_enable = 0;
 770                 }
 771                 break;
 772         }
 773
 774         /* We may also have postponed startup of DSP, handle that. */
 775         wm8958_aif_ev(w, kcontrol, event);
 776
 777         return 0;
 778 }
 779
 780 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 781                            struct snd_kcontrol *kcontrol, int event)
 782 {
 783         struct snd_soc_codec *codec = w->codec;
 784         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 785
 786         switch (event) {
 787         case SND_SOC_DAPM_POST_PMD:
 788                 if (wm8994->aif1clk_disable) {
 789                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 790                                             WM8994_AIF1CLK_ENA_MASK, 0);
 791                         wm8994->aif1clk_disable = 0;
 792                 }
 793                 if (wm8994->aif2clk_disable) {
 794                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 795                                             WM8994_AIF2CLK_ENA_MASK, 0);
 796                         wm8994->aif2clk_disable = 0;
 797                 }
 798                 break;
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 805                       struct snd_kcontrol *kcontrol, int event)
 806 {
 807         struct snd_soc_codec *codec = w->codec;
 808         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 809
 810         switch (event) {
 811         case SND_SOC_DAPM_PRE_PMU:
 812                 wm8994->aif1clk_enable = 1;
 813                 break;
 814         case SND_SOC_DAPM_POST_PMD:
 815                 wm8994->aif1clk_disable = 1;
 816                 break;
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 823                       struct snd_kcontrol *kcontrol, int event)
 824 {
 825         struct snd_soc_codec *codec = w->codec;
 826         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 827
 828         switch (event) {
 829         case SND_SOC_DAPM_PRE_PMU:
 830                 wm8994->aif2clk_enable = 1;
 831                 break;
 832         case SND_SOC_DAPM_POST_PMD:
 833                 wm8994->aif2clk_disable = 1;
 834                 break;
 835         }
 836
 837         return 0;
 838 }
 839
 840 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 841                       struct snd_kcontrol *kcontrol, int event)
 842 {
 843         late_enable_ev(w, kcontrol, event);
 844         return 0;
 845 }
 846
 847 static int micbias_ev(struct snd_soc_dapm_widget *w,
 848                       struct snd_kcontrol *kcontrol, int event)
 849 {
 850         late_enable_ev(w, kcontrol, event);
 851         return 0;
 852 }
 853
 854 static int dac_ev(struct snd_soc_dapm_widget *w,
 855                   struct snd_kcontrol *kcontrol, int event)
 856 {
 857         struct snd_soc_codec *codec = w->codec;
 858         unsigned int mask = 1 << w->shift;
 859
 860         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 861                             mask, mask);
 862         return 0;
 863 }
 864
 865 static const char *hp_mux_text[] = {
 866         "Mixer",
 867         "DAC",
 868 };
 869
 870 #define WM8994_HP_ENUM(xname, xenum) \
 871 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 872         .info = snd_soc_info_enum_double, \
 873         .get = snd_soc_dapm_get_enum_double, \
 874         .put = wm8994_put_hp_enum, \
 875         .private_value = (unsigned long)&xenum }
 876
 877 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 878                               struct snd_ctl_elem_value *ucontrol)
 879 {
 880         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
 881         struct snd_soc_dapm_widget *w = wlist->widgets[0];
 882         struct snd_soc_codec *codec = w->codec;
 883         int ret;
 884
 885         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 886
 887         wm8994_update_class_w(codec);
 888
 889         return ret;
 890 }
 891
 892 static const struct soc_enum hpl_enum =
 893         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 894
 895 static const struct snd_kcontrol_new hpl_mux =
 896         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
 897
 898 static const struct soc_enum hpr_enum =
 899         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
 900
 901 static const struct snd_kcontrol_new hpr_mux =
 902         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
 903
 904 static const char *adc_mux_text[] = {
 905         "ADC",
 906         "DMIC",
 907 };
 908
 909 static const struct soc_enum adc_enum =
 910         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
 911
 912 static const struct snd_kcontrol_new adcl_mux =
 913         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
 914
 915 static const struct snd_kcontrol_new adcr_mux =
 916         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
 917
 918 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 919 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
 920 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
 921 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
 922 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
 923 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
 924 };
 925
 926 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 927 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
 928 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
 929 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
 930 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
 931 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
 932 };
 933
 934 /* Debugging; dump chip status after DAPM transitions */
 935 static int post_ev(struct snd_soc_dapm_widget *w,
 936             struct snd_kcontrol *kcontrol, int event)
 937 {
 938         struct snd_soc_codec *codec = w->codec;
 939         dev_dbg(codec->dev, "SRC status: %x\n",
 940                 snd_soc_read(codec,
 941                              WM8994_RATE_STATUS));
 942         return 0;
 943 }
 944
 945 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
 946 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 947                 1, 1, 0),
 948 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 949                 0, 1, 0),
 950 };
 951
 952 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
 953 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 954                 1, 1, 0),
 955 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 956                 0, 1, 0),
 957 };
 958
 959 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
 960 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 961                 1, 1, 0),
 962 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 963                 0, 1, 0),
 964 };
 965
 966 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
 967 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 968                 1, 1, 0),
 969 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 970                 0, 1, 0),
 971 };
 972
 973 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
 974 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 975                 5, 1, 0),
 976 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 977                 4, 1, 0),
 978 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 979                 2, 1, 0),
 980 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 981                 1, 1, 0),
 982 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 983                 0, 1, 0),
 984 };
 985
 986 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
 987 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 988                 5, 1, 0),
 989 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 990                 4, 1, 0),
 991 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 992                 2, 1, 0),
 993 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 994                 1, 1, 0),
 995 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 996                 0, 1, 0),
 997 };
 998
 999 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1000 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1001         .info = snd_soc_info_volsw, \
1002         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1003         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1004
1005 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1006                               struct snd_ctl_elem_value *ucontrol)
1007 {
1008         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1009         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1010         struct snd_soc_codec *codec = w->codec;
1011         int ret;
1012
1013         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1014
1015         wm8994_update_class_w(codec);
1016
1017         return ret;
1018 }
1019
1020 static const struct snd_kcontrol_new dac1l_mix[] = {
1021 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022                       5, 1, 0),
1023 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024                       4, 1, 0),
1025 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026                       2, 1, 0),
1027 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1028                       1, 1, 0),
1029 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1030                       0, 1, 0),
1031 };
1032
1033 static const struct snd_kcontrol_new dac1r_mix[] = {
1034 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035                       5, 1, 0),
1036 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037                       4, 1, 0),
1038 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039                       2, 1, 0),
1040 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1041                       1, 1, 0),
1042 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1043                       0, 1, 0),
1044 };
1045
1046 static const char *sidetone_text[] = {
1047         "ADC/DMIC1", "DMIC2",
1048 };
1049
1050 static const struct soc_enum sidetone1_enum =
1051         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1052
1053 static const struct snd_kcontrol_new sidetone1_mux =
1054         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1055
1056 static const struct soc_enum sidetone2_enum =
1057         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1058
1059 static const struct snd_kcontrol_new sidetone2_mux =
1060         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1061
1062 static const char *aif1dac_text[] = {
1063         "AIF1DACDAT", "AIF3DACDAT",
1064 };
1065
1066 static const struct soc_enum aif1dac_enum =
1067         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1068
1069 static const struct snd_kcontrol_new aif1dac_mux =
1070         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1071
1072 static const char *aif2dac_text[] = {
1073         "AIF2DACDAT", "AIF3DACDAT",
1074 };
1075
1076 static const struct soc_enum aif2dac_enum =
1077         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1078
1079 static const struct snd_kcontrol_new aif2dac_mux =
1080         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1081
1082 static const char *aif2adc_text[] = {
1083         "AIF2ADCDAT", "AIF3DACDAT",
1084 };
1085
1086 static const struct soc_enum aif2adc_enum =
1087         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1088
1089 static const struct snd_kcontrol_new aif2adc_mux =
1090         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1091
1092 static const char *aif3adc_text[] = {
1093         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1094 };
1095
1096 static const struct soc_enum wm8994_aif3adc_enum =
1097         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1098
1099 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1100         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1101
1102 static const struct soc_enum wm8958_aif3adc_enum =
1103         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1104
1105 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1106         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1107
1108 static const char *mono_pcm_out_text[] = {
1109         "None", "AIF2ADCL", "AIF2ADCR",
1110 };
1111
1112 static const struct soc_enum mono_pcm_out_enum =
1113         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1114
1115 static const struct snd_kcontrol_new mono_pcm_out_mux =
1116         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1117
1118 static const char *aif2dac_src_text[] = {
1119         "AIF2", "AIF3",
1120 };
1121
1122 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1123 static const struct soc_enum aif2dacl_src_enum =
1124         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1125
1126 static const struct snd_kcontrol_new aif2dacl_src_mux =
1127         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1128
1129 static const struct soc_enum aif2dacr_src_enum =
1130         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1131
1132 static const struct snd_kcontrol_new aif2dacr_src_mux =
1133         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1134
1135 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1136 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1137         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1139         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1140
1141 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1146         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1148         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1149
1150 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1151 };
1152
1153 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1154 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1155 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1156 };
1157
1158 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1159 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1160         dac_ev, SND_SOC_DAPM_PRE_PMU),
1161 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1162         dac_ev, SND_SOC_DAPM_PRE_PMU),
1163 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1164         dac_ev, SND_SOC_DAPM_PRE_PMU),
1165 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1166         dac_ev, SND_SOC_DAPM_PRE_PMU),
1167 };
1168
1169 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1170 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1171 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1172 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1173 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1174 };
1175
1176 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1177 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1178                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1179 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1180                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1181 };
1182
1183 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1184 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1185 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1186 };
1187
1188 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1189 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1190 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1191 SND_SOC_DAPM_INPUT("Clock"),
1192
1193 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1194                       SND_SOC_DAPM_PRE_PMU),
1195
1196 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1197                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1198
1199 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1200 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1201 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1202
1203 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1204                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1205 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1206                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1207 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1208                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1209                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1210 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1211                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1212                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1213
1214 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1215                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1216 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1217                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1218 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1219                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1220                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1221 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1222                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1223                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1224
1225 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1226                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1227 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1228                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1229
1230 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1231                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1232 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1233                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1234
1235 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1236                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1237 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1238                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1239
1240 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1241 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1242
1243 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1244                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1245 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1246                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1247
1248 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1249                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1250 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1251                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1252 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1253                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1254                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1255 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1256                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1257                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1258
1259 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1260 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1261 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1262 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1263
1264 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1265 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1266 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1267
1268 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1269 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1270
1271 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1272
1273 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1274 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1275 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1276 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1277
1278 /* Power is done with the muxes since the ADC power also controls the
1279  * downsampling chain, the chip will automatically manage the analogue
1280  * specific portions.
1281  */
1282 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1283 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1284
1285 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1286 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1287
1288 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1289                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1290 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1291                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1292
1293 SND_SOC_DAPM_POST("Debug log", post_ev),
1294 };
1295
1296 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1297 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1298 };
1299
1300 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1301 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1302 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1303 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1304 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1305 };
1306
1307 static const struct snd_soc_dapm_route intercon[] = {
1308         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1309         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1310
1311         { "DSP1CLK", NULL, "CLK_SYS" },
1312         { "DSP2CLK", NULL, "CLK_SYS" },
1313         { "DSPINTCLK", NULL, "CLK_SYS" },
1314
1315         { "AIF1ADC1L", NULL, "AIF1CLK" },
1316         { "AIF1ADC1L", NULL, "DSP1CLK" },
1317         { "AIF1ADC1R", NULL, "AIF1CLK" },
1318         { "AIF1ADC1R", NULL, "DSP1CLK" },
1319         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1320
1321         { "AIF1DAC1L", NULL, "AIF1CLK" },
1322         { "AIF1DAC1L", NULL, "DSP1CLK" },
1323         { "AIF1DAC1R", NULL, "AIF1CLK" },
1324         { "AIF1DAC1R", NULL, "DSP1CLK" },
1325         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1326
1327         { "AIF1ADC2L", NULL, "AIF1CLK" },
1328         { "AIF1ADC2L", NULL, "DSP1CLK" },
1329         { "AIF1ADC2R", NULL, "AIF1CLK" },
1330         { "AIF1ADC2R", NULL, "DSP1CLK" },
1331         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1332
1333         { "AIF1DAC2L", NULL, "AIF1CLK" },
1334         { "AIF1DAC2L", NULL, "DSP1CLK" },
1335         { "AIF1DAC2R", NULL, "AIF1CLK" },
1336         { "AIF1DAC2R", NULL, "DSP1CLK" },
1337         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1338
1339         { "AIF2ADCL", NULL, "AIF2CLK" },
1340         { "AIF2ADCL", NULL, "DSP2CLK" },
1341         { "AIF2ADCR", NULL, "AIF2CLK" },
1342         { "AIF2ADCR", NULL, "DSP2CLK" },
1343         { "AIF2ADCR", NULL, "DSPINTCLK" },
1344
1345         { "AIF2DACL", NULL, "AIF2CLK" },
1346         { "AIF2DACL", NULL, "DSP2CLK" },
1347         { "AIF2DACR", NULL, "AIF2CLK" },
1348         { "AIF2DACR", NULL, "DSP2CLK" },
1349         { "AIF2DACR", NULL, "DSPINTCLK" },
1350
1351         { "DMIC1L", NULL, "DMIC1DAT" },
1352         { "DMIC1L", NULL, "CLK_SYS" },
1353         { "DMIC1R", NULL, "DMIC1DAT" },
1354         { "DMIC1R", NULL, "CLK_SYS" },
1355         { "DMIC2L", NULL, "DMIC2DAT" },
1356         { "DMIC2L", NULL, "CLK_SYS" },
1357         { "DMIC2R", NULL, "DMIC2DAT" },
1358         { "DMIC2R", NULL, "CLK_SYS" },
1359
1360         { "ADCL", NULL, "AIF1CLK" },
1361         { "ADCL", NULL, "DSP1CLK" },
1362         { "ADCL", NULL, "DSPINTCLK" },
1363
1364         { "ADCR", NULL, "AIF1CLK" },
1365         { "ADCR", NULL, "DSP1CLK" },
1366         { "ADCR", NULL, "DSPINTCLK" },
1367
1368         { "ADCL Mux", "ADC", "ADCL" },
1369         { "ADCL Mux", "DMIC", "DMIC1L" },
1370         { "ADCR Mux", "ADC", "ADCR" },
1371         { "ADCR Mux", "DMIC", "DMIC1R" },
1372
1373         { "DAC1L", NULL, "AIF1CLK" },
1374         { "DAC1L", NULL, "DSP1CLK" },
1375         { "DAC1L", NULL, "DSPINTCLK" },
1376
1377         { "DAC1R", NULL, "AIF1CLK" },
1378         { "DAC1R", NULL, "DSP1CLK" },
1379         { "DAC1R", NULL, "DSPINTCLK" },
1380
1381         { "DAC2L", NULL, "AIF2CLK" },
1382         { "DAC2L", NULL, "DSP2CLK" },
1383         { "DAC2L", NULL, "DSPINTCLK" },
1384
1385         { "DAC2R", NULL, "AIF2DACR" },
1386         { "DAC2R", NULL, "AIF2CLK" },
1387         { "DAC2R", NULL, "DSP2CLK" },
1388         { "DAC2R", NULL, "DSPINTCLK" },
1389
1390         { "TOCLK", NULL, "CLK_SYS" },
1391
1392         /* AIF1 outputs */
1393         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1394         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1395         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1396
1397         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1398         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1399         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1400
1401         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1402         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1403         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1404
1405         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1406         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1407         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1408
1409         /* Pin level routing for AIF3 */
1410         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1411         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1412         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1413         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1414
1415         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1416         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1417         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1418         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1419         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1420         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1421         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1422
1423         /* DAC1 inputs */
1424         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1425         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1426         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1427         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1428         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1429
1430         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1431         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1432         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1433         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1434         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1435
1436         /* DAC2/AIF2 outputs  */
1437         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1438         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1439         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1440         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1441         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1442         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1443
1444         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1445         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1446         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1447         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1448         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1449         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1450
1451         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1452         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1453         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1454         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1455
1456         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1457
1458         /* AIF3 output */
1459         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1460         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1461         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1462         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1463         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1464         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1465         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1466         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1467
1468         /* Sidetone */
1469         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1470         { "Left Sidetone", "DMIC2", "DMIC2L" },
1471         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1472         { "Right Sidetone", "DMIC2", "DMIC2R" },
1473
1474         /* Output stages */
1475         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1476         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1477
1478         { "SPKL", "DAC1 Switch", "DAC1L" },
1479         { "SPKL", "DAC2 Switch", "DAC2L" },
1480
1481         { "SPKR", "DAC1 Switch", "DAC1R" },
1482         { "SPKR", "DAC2 Switch", "DAC2R" },
1483
1484         { "Left Headphone Mux", "DAC", "DAC1L" },
1485         { "Right Headphone Mux", "DAC", "DAC1R" },
1486 };
1487
1488 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1489         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1490         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1491         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1492         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1493         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1494         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1495         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1496         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1497 };
1498
1499 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1500         { "DAC1L", NULL, "DAC1L Mixer" },
1501         { "DAC1R", NULL, "DAC1R Mixer" },
1502         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1503         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1504 };
1505
1506 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1507         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1508         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1509         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1510         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1511         { "MICBIAS1", NULL, "CLK_SYS" },
1512         { "MICBIAS1", NULL, "MICBIAS Supply" },
1513         { "MICBIAS2", NULL, "CLK_SYS" },
1514         { "MICBIAS2", NULL, "MICBIAS Supply" },
1515 };
1516
1517 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1518         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1519         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1520 };
1521
1522 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1523         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1524         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1525
1526         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1527         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1528         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1529         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1530
1531         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1532         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1533
1534         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1535 };
1536
1537 /* The size in bits of the FLL divide multiplied by 10
1538  * to allow rounding later */
1539 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1540
1541 struct fll_div {
1542         u16 outdiv;
1543         u16 n;
1544         u16 k;
1545         u16 clk_ref_div;
1546         u16 fll_fratio;
1547 };
1548
1549 static int wm8994_get_fll_config(struct fll_div *fll,
1550                                  int freq_in, int freq_out)
1551 {
1552         u64 Kpart;
1553         unsigned int K, Ndiv, Nmod;
1554
1555         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1556
1557         /* Scale the input frequency down to <= 13.5MHz */
1558         fll->clk_ref_div = 0;
1559         while (freq_in > 13500000) {
1560                 fll->clk_ref_div++;
1561                 freq_in /= 2;
1562
1563                 if (fll->clk_ref_div > 3)
1564                         return -EINVAL;
1565         }
1566         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1567
1568         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1569         fll->outdiv = 3;
1570         while (freq_out * (fll->outdiv + 1) < 90000000) {
1571                 fll->outdiv++;
1572                 if (fll->outdiv > 63)
1573                         return -EINVAL;
1574         }
1575         freq_out *= fll->outdiv + 1;
1576         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1577
1578         if (freq_in > 1000000) {
1579                 fll->fll_fratio = 0;
1580         } else if (freq_in > 256000) {
1581                 fll->fll_fratio = 1;
1582                 freq_in *= 2;
1583         } else if (freq_in > 128000) {
1584                 fll->fll_fratio = 2;
1585                 freq_in *= 4;
1586         } else if (freq_in > 64000) {
1587                 fll->fll_fratio = 3;
1588                 freq_in *= 8;
1589         } else {
1590                 fll->fll_fratio = 4;
1591                 freq_in *= 16;
1592         }
1593         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1594
1595         /* Now, calculate N.K */
1596         Ndiv = freq_out / freq_in;
1597
1598         fll->n = Ndiv;
1599         Nmod = freq_out % freq_in;
1600         pr_debug("Nmod=%d\n", Nmod);
1601
1602         /* Calculate fractional part - scale up so we can round. */
1603         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1604
1605         do_div(Kpart, freq_in);
1606
1607         K = Kpart & 0xFFFFFFFF;
1608
1609         if ((K % 10) >= 5)
1610                 K += 5;
1611
1612         /* Move down to proper range now rounding is done */
1613         fll->k = K / 10;
1614
1615         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1616
1617         return 0;
1618 }
1619
1620 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1621                           unsigned int freq_in, unsigned int freq_out)
1622 {
1623         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1624         int reg_offset, ret;
1625         struct fll_div fll;
1626         u16 reg, aif1, aif2;
1627
1628         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1629                 & WM8994_AIF1CLK_ENA;
1630
1631         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1632                 & WM8994_AIF2CLK_ENA;
1633
1634         switch (id) {
1635         case WM8994_FLL1:
1636                 reg_offset = 0;
1637                 id = 0;
1638                 break;
1639         case WM8994_FLL2:
1640                 reg_offset = 0x20;
1641                 id = 1;
1642                 break;
1643         default:
1644                 return -EINVAL;
1645         }
1646
1647         switch (src) {
1648         case 0:
1649                 /* Allow no source specification when stopping */
1650                 if (freq_out)
1651                         return -EINVAL;
1652                 src = wm8994->fll[id].src;
1653                 break;
1654         case WM8994_FLL_SRC_MCLK1:
1655         case WM8994_FLL_SRC_MCLK2:
1656         case WM8994_FLL_SRC_LRCLK:
1657         case WM8994_FLL_SRC_BCLK:
1658                 break;
1659         default:
1660                 return -EINVAL;
1661         }
1662
1663         /* Are we changing anything? */
1664         if (wm8994->fll[id].src == src &&
1665             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1666                 return 0;
1667
1668         /* If we're stopping the FLL redo the old config - no
1669          * registers will actually be written but we avoid GCC flow
1670          * analysis bugs spewing warnings.
1671          */
1672         if (freq_out)
1673                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1674         else
1675                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1676                                             wm8994->fll[id].out);
1677         if (ret < 0)
1678                 return ret;
1679
1680         /* Gate the AIF clocks while we reclock */
1681         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1682                             WM8994_AIF1CLK_ENA, 0);
1683         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1684                             WM8994_AIF2CLK_ENA, 0);
1685
1686         /* We always need to disable the FLL while reconfiguring */
1687         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1688                             WM8994_FLL1_ENA, 0);
1689
1690         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1691                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1692         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1693                             WM8994_FLL1_OUTDIV_MASK |
1694                             WM8994_FLL1_FRATIO_MASK, reg);
1695
1696         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1697
1698         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1699                             WM8994_FLL1_N_MASK,
1700                                     fll.n << WM8994_FLL1_N_SHIFT);
1701
1702         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1703                             WM8994_FLL1_REFCLK_DIV_MASK |
1704                             WM8994_FLL1_REFCLK_SRC_MASK,
1705                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1706                             (src - 1));
1707
1708         /* Enable (with fractional mode if required) */
1709         if (freq_out) {
1710                 if (fll.k)
1711                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1712                 else
1713                         reg = WM8994_FLL1_ENA;
1714                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1715                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1716                                     reg);
1717
1718                 msleep(5);
1719         }
1720
1721         wm8994->fll[id].in = freq_in;
1722         wm8994->fll[id].out = freq_out;
1723         wm8994->fll[id].src = src;
1724
1725         /* Enable any gated AIF clocks */
1726         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1727                             WM8994_AIF1CLK_ENA, aif1);
1728         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1729                             WM8994_AIF2CLK_ENA, aif2);
1730
1731         configure_clock(codec);
1732
1733         return 0;
1734 }
1735
1736
1737 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1738
1739 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1740                           unsigned int freq_in, unsigned int freq_out)
1741 {
1742         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1743 }
1744
1745 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1746                 int clk_id, unsigned int freq, int dir)
1747 {
1748         struct snd_soc_codec *codec = dai->codec;
1749         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1750         int i;
1751
1752         switch (dai->id) {
1753         case 1:
1754         case 2:
1755                 break;
1756
1757         default:
1758                 /* AIF3 shares clocking with AIF1/2 */
1759                 return -EINVAL;
1760         }
1761
1762         switch (clk_id) {
1763         case WM8994_SYSCLK_MCLK1:
1764                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1765                 wm8994->mclk[0] = freq;
1766                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1767                         dai->id, freq);
1768                 break;
1769
1770         case WM8994_SYSCLK_MCLK2:
1771                 /* TODO: Set GPIO AF */
1772                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1773                 wm8994->mclk[1] = freq;
1774                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1775                         dai->id, freq);
1776                 break;
1777
1778         case WM8994_SYSCLK_FLL1:
1779                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1780                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1781                 break;
1782
1783         case WM8994_SYSCLK_FLL2:
1784                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1785                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1786                 break;
1787
1788         case WM8994_SYSCLK_OPCLK:
1789                 /* Special case - a division (times 10) is given and
1790                  * no effect on main clocking.
1791                  */
1792                 if (freq) {
1793                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1794                                 if (opclk_divs[i] == freq)
1795                                         break;
1796                         if (i == ARRAY_SIZE(opclk_divs))
1797                                 return -EINVAL;
1798                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1799                                             WM8994_OPCLK_DIV_MASK, i);
1800                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1801                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1802                 } else {
1803                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1804                                             WM8994_OPCLK_ENA, 0);
1805                 }
1806
1807         default:
1808                 return -EINVAL;
1809         }
1810
1811         configure_clock(codec);
1812
1813         return 0;
1814 }
1815
1816 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1817                                  enum snd_soc_bias_level level)
1818 {
1819         struct wm8994 *control = codec->control_data;
1820         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1821
1822         switch (level) {
1823         case SND_SOC_BIAS_ON:
1824                 break;
1825
1826         case SND_SOC_BIAS_PREPARE:
1827                 /* VMID=2x40k */
1828                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1829                                     WM8994_VMID_SEL_MASK, 0x2);
1830                 break;
1831
1832         case SND_SOC_BIAS_STANDBY:
1833                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1834                         pm_runtime_get_sync(codec->dev);
1835
1836                         switch (control->type) {
1837                         case WM8994:
1838                                 if (wm8994->revision < 4) {
1839                                         /* Tweak DC servo and DSP
1840                                          * configuration for improved
1841                                          * performance. */
1842                                         snd_soc_write(codec, 0x102, 0x3);
1843                                         snd_soc_write(codec, 0x56, 0x3);
1844                                         snd_soc_write(codec, 0x817, 0);
1845                                         snd_soc_write(codec, 0x102, 0);
1846                                 }
1847                                 break;
1848
1849                         case WM8958:
1850                                 if (wm8994->revision == 0) {
1851                                         /* Optimise performance for rev A */
1852                                         snd_soc_write(codec, 0x102, 0x3);
1853                                         snd_soc_write(codec, 0xcb, 0x81);
1854                                         snd_soc_write(codec, 0x817, 0);
1855                                         snd_soc_write(codec, 0x102, 0);
1856
1857                                         snd_soc_update_bits(codec,
1858                                                             WM8958_CHARGE_PUMP_2,
1859                                                             WM8958_CP_DISCH,
1860                                                             WM8958_CP_DISCH);
1861                                 }
1862                                 break;
1863                         }
1864
1865                         /* Discharge LINEOUT1 & 2 */
1866                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1867                                             WM8994_LINEOUT1_DISCH |
1868                                             WM8994_LINEOUT2_DISCH,
1869                                             WM8994_LINEOUT1_DISCH |
1870                                             WM8994_LINEOUT2_DISCH);
1871
1872                         /* Startup bias, VMID ramp & buffer */
1873                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1874                                             WM8994_STARTUP_BIAS_ENA |
1875                                             WM8994_VMID_BUF_ENA |
1876                                             WM8994_VMID_RAMP_MASK,
1877                                             WM8994_STARTUP_BIAS_ENA |
1878                                             WM8994_VMID_BUF_ENA |
1879                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1880
1881                         /* Main bias enable, VMID=2x40k */
1882                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1883                                             WM8994_BIAS_ENA |
1884                                             WM8994_VMID_SEL_MASK,
1885                                             WM8994_BIAS_ENA | 0x2);
1886
1887                         msleep(20);
1888                 }
1889
1890                 /* VMID=2x500k */
1891                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1892                                     WM8994_VMID_SEL_MASK, 0x4);
1893
1894                 break;
1895
1896         case SND_SOC_BIAS_OFF:
1897                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1898                         /* Switch over to startup biases */
1899                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1900                                             WM8994_BIAS_SRC |
1901                                             WM8994_STARTUP_BIAS_ENA |
1902                                             WM8994_VMID_BUF_ENA |
1903                                             WM8994_VMID_RAMP_MASK,
1904                                             WM8994_BIAS_SRC |
1905                                             WM8994_STARTUP_BIAS_ENA |
1906                                             WM8994_VMID_BUF_ENA |
1907                                             (1 << WM8994_VMID_RAMP_SHIFT));
1908
1909                         /* Disable main biases */
1910                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1911                                             WM8994_BIAS_ENA |
1912                                             WM8994_VMID_SEL_MASK, 0);
1913
1914                         /* Discharge line */
1915                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1916                                             WM8994_LINEOUT1_DISCH |
1917                                             WM8994_LINEOUT2_DISCH,
1918                                             WM8994_LINEOUT1_DISCH |
1919                                             WM8994_LINEOUT2_DISCH);
1920
1921                         msleep(5);
1922
1923                         /* Switch off startup biases */
1924                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1925                                             WM8994_BIAS_SRC |
1926                                             WM8994_STARTUP_BIAS_ENA |
1927                                             WM8994_VMID_BUF_ENA |
1928                                             WM8994_VMID_RAMP_MASK, 0);
1929
1930                         wm8994->cur_fw = NULL;
1931
1932                         pm_runtime_put(codec->dev);
1933                 }
1934                 break;
1935         }
1936         codec->dapm.bias_level = level;
1937         return 0;
1938 }
1939
1940 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1941 {
1942         struct snd_soc_codec *codec = dai->codec;
1943         struct wm8994 *control = codec->control_data;
1944         int ms_reg;
1945         int aif1_reg;
1946         int ms = 0;
1947         int aif1 = 0;
1948
1949         switch (dai->id) {
1950         case 1:
1951                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1952                 aif1_reg = WM8994_AIF1_CONTROL_1;
1953                 break;
1954         case 2:
1955                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1956                 aif1_reg = WM8994_AIF2_CONTROL_1;
1957                 break;
1958         default:
1959                 return -EINVAL;
1960         }
1961
1962         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1963         case SND_SOC_DAIFMT_CBS_CFS:
1964                 break;
1965         case SND_SOC_DAIFMT_CBM_CFM:
1966                 ms = WM8994_AIF1_MSTR;
1967                 break;
1968         default:
1969                 return -EINVAL;
1970         }
1971
1972         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1973         case SND_SOC_DAIFMT_DSP_B:
1974                 aif1 |= WM8994_AIF1_LRCLK_INV;
1975         case SND_SOC_DAIFMT_DSP_A:
1976                 aif1 |= 0x18;
1977                 break;
1978         case SND_SOC_DAIFMT_I2S:
1979                 aif1 |= 0x10;
1980                 break;
1981         case SND_SOC_DAIFMT_RIGHT_J:
1982                 break;
1983         case SND_SOC_DAIFMT_LEFT_J:
1984                 aif1 |= 0x8;
1985                 break;
1986         default:
1987                 return -EINVAL;
1988         }
1989
1990         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1991         case SND_SOC_DAIFMT_DSP_A:
1992         case SND_SOC_DAIFMT_DSP_B:
1993                 /* frame inversion not valid for DSP modes */
1994                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1995                 case SND_SOC_DAIFMT_NB_NF:
1996                         break;
1997                 case SND_SOC_DAIFMT_IB_NF:
1998                         aif1 |= WM8994_AIF1_BCLK_INV;
1999                         break;
2000                 default:
2001                         return -EINVAL;
2002                 }
2003                 break;
2004
2005         case SND_SOC_DAIFMT_I2S:
2006         case SND_SOC_DAIFMT_RIGHT_J:
2007         case SND_SOC_DAIFMT_LEFT_J:
2008                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2009                 case SND_SOC_DAIFMT_NB_NF:
2010                         break;
2011                 case SND_SOC_DAIFMT_IB_IF:
2012                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2013                         break;
2014                 case SND_SOC_DAIFMT_IB_NF:
2015                         aif1 |= WM8994_AIF1_BCLK_INV;
2016                         break;
2017                 case SND_SOC_DAIFMT_NB_IF:
2018                         aif1 |= WM8994_AIF1_LRCLK_INV;
2019                         break;
2020                 default:
2021                         return -EINVAL;
2022                 }
2023                 break;
2024         default:
2025                 return -EINVAL;
2026         }
2027
2028         /* The AIF2 format configuration needs to be mirrored to AIF3
2029          * on WM8958 if it's in use so just do it all the time. */
2030         if (control->type == WM8958 && dai->id == 2)
2031                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2032                                     WM8994_AIF1_LRCLK_INV |
2033                                     WM8958_AIF3_FMT_MASK, aif1);
2034
2035         snd_soc_update_bits(codec, aif1_reg,
2036                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2037                             WM8994_AIF1_FMT_MASK,
2038                             aif1);
2039         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2040                             ms);
2041
2042         return 0;
2043 }
2044
2045 static struct {
2046         int val, rate;
2047 } srs[] = {
2048         { 0,   8000 },
2049         { 1,  11025 },
2050         { 2,  12000 },
2051         { 3,  16000 },
2052         { 4,  22050 },
2053         { 5,  24000 },
2054         { 6,  32000 },
2055         { 7,  44100 },
2056         { 8,  48000 },
2057         { 9,  88200 },
2058         { 10, 96000 },
2059 };
2060
2061 static int fs_ratios[] = {
2062         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2063 };
2064
2065 static int bclk_divs[] = {
2066         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2067         640, 880, 960, 1280, 1760, 1920
2068 };
2069
2070 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2071                             struct snd_pcm_hw_params *params,
2072                             struct snd_soc_dai *dai)
2073 {
2074         struct snd_soc_codec *codec = dai->codec;
2075         struct wm8994 *control = codec->control_data;
2076         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2077         int aif1_reg;
2078         int aif2_reg;
2079         int bclk_reg;
2080         int lrclk_reg;
2081         int rate_reg;
2082         int aif1 = 0;
2083         int aif2 = 0;
2084         int bclk = 0;
2085         int lrclk = 0;
2086         int rate_val = 0;
2087         int id = dai->id - 1;
2088
2089         int i, cur_val, best_val, bclk_rate, best;
2090
2091         switch (dai->id) {
2092         case 1:
2093                 aif1_reg = WM8994_AIF1_CONTROL_1;
2094                 aif2_reg = WM8994_AIF1_CONTROL_2;
2095                 bclk_reg = WM8994_AIF1_BCLK;
2096                 rate_reg = WM8994_AIF1_RATE;
2097                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2098                     wm8994->lrclk_shared[0]) {
2099                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2100                 } else {
2101                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2102                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2103                 }
2104                 break;
2105         case 2:
2106                 aif1_reg = WM8994_AIF2_CONTROL_1;
2107                 aif2_reg = WM8994_AIF2_CONTROL_2;
2108                 bclk_reg = WM8994_AIF2_BCLK;
2109                 rate_reg = WM8994_AIF2_RATE;
2110                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2111                     wm8994->lrclk_shared[1]) {
2112                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2113                 } else {
2114                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2115                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2116                 }
2117                 break;
2118         case 3:
2119                 switch (control->type) {
2120                 case WM8958:
2121                         aif1_reg = WM8958_AIF3_CONTROL_1;
2122                         break;
2123                 default:
2124                         return 0;
2125                 }
2126         default:
2127                 return -EINVAL;
2128         }
2129
2130         bclk_rate = params_rate(params) * 4;
2131         switch (params_format(params)) {
2132         case SNDRV_PCM_FORMAT_S16_LE:
2133                 bclk_rate *= 16;
2134                 break;
2135         case SNDRV_PCM_FORMAT_S20_3LE:
2136                 bclk_rate *= 20;
2137                 aif1 |= 0x20;
2138                 break;
2139         case SNDRV_PCM_FORMAT_S24_LE:
2140                 bclk_rate *= 24;
2141                 aif1 |= 0x40;
2142                 break;
2143         case SNDRV_PCM_FORMAT_S32_LE:
2144                 bclk_rate *= 32;
2145                 aif1 |= 0x60;
2146                 break;
2147         default:
2148                 return -EINVAL;
2149         }
2150
2151         /* Try to find an appropriate sample rate; look for an exact match. */
2152         for (i = 0; i < ARRAY_SIZE(srs); i++)
2153                 if (srs[i].rate == params_rate(params))
2154                         break;
2155         if (i == ARRAY_SIZE(srs))
2156                 return -EINVAL;
2157         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2158
2159         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2160         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2161                 dai->id, wm8994->aifclk[id], bclk_rate);
2162
2163         if (params_channels(params) == 1 &&
2164             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2165                 aif2 |= WM8994_AIF1_MONO;
2166
2167         if (wm8994->aifclk[id] == 0) {
2168                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2169                 return -EINVAL;
2170         }
2171
2172         /* AIFCLK/fs ratio; look for a close match in either direction */
2173         best = 0;
2174         best_val = abs((fs_ratios[0] * params_rate(params))
2175                        - wm8994->aifclk[id]);
2176         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2177                 cur_val = abs((fs_ratios[i] * params_rate(params))
2178                               - wm8994->aifclk[id]);
2179                 if (cur_val >= best_val)
2180                         continue;
2181                 best = i;
2182                 best_val = cur_val;
2183         }
2184         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2185                 dai->id, fs_ratios[best]);
2186         rate_val |= best;
2187
2188         /* We may not get quite the right frequency if using
2189          * approximate clocks so look for the closest match that is
2190          * higher than the target (we need to ensure that there enough
2191          * BCLKs to clock out the samples).
2192          */
2193         best = 0;
2194         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2195                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2196                 if (cur_val < 0) /* BCLK table is sorted */
2197                         break;
2198                 best = i;
2199         }
2200         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2201         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2202                 bclk_divs[best], bclk_rate);
2203         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2204
2205         lrclk = bclk_rate / params_rate(params);
2206         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2207                 lrclk, bclk_rate / lrclk);
2208
2209         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2210         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2211         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2212         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2213                             lrclk);
2214         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2215                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2216
2217         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2218                 switch (dai->id) {
2219                 case 1:
2220                         wm8994->dac_rates[0] = params_rate(params);
2221                         wm8994_set_retune_mobile(codec, 0);
2222                         wm8994_set_retune_mobile(codec, 1);
2223                         break;
2224                 case 2:
2225                         wm8994->dac_rates[1] = params_rate(params);
2226                         wm8994_set_retune_mobile(codec, 2);
2227                         break;
2228                 }
2229         }
2230
2231         return 0;
2232 }
2233
2234 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2235                                  struct snd_pcm_hw_params *params,
2236                                  struct snd_soc_dai *dai)
2237 {
2238         struct snd_soc_codec *codec = dai->codec;
2239         struct wm8994 *control = codec->control_data;
2240         int aif1_reg;
2241         int aif1 = 0;
2242
2243         switch (dai->id) {
2244         case 3:
2245                 switch (control->type) {
2246                 case WM8958:
2247                         aif1_reg = WM8958_AIF3_CONTROL_1;
2248                         break;
2249                 default:
2250                         return 0;
2251                 }
2252         default:
2253                 return 0;
2254         }
2255
2256         switch (params_format(params)) {
2257         case SNDRV_PCM_FORMAT_S16_LE:
2258                 break;
2259         case SNDRV_PCM_FORMAT_S20_3LE:
2260                 aif1 |= 0x20;
2261                 break;
2262         case SNDRV_PCM_FORMAT_S24_LE:
2263                 aif1 |= 0x40;
2264                 break;
2265         case SNDRV_PCM_FORMAT_S32_LE:
2266                 aif1 |= 0x60;
2267                 break;
2268         default:
2269                 return -EINVAL;
2270         }
2271
2272         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2273 }
2274
2275 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2276 {
2277         struct snd_soc_codec *codec = codec_dai->codec;
2278         int mute_reg;
2279         int reg;
2280
2281         switch (codec_dai->id) {
2282         case 1:
2283                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2284                 break;
2285         case 2:
2286                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2287                 break;
2288         default:
2289                 return -EINVAL;
2290         }
2291
2292         if (mute)
2293                 reg = WM8994_AIF1DAC1_MUTE;
2294         else
2295                 reg = 0;
2296
2297         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2298
2299         return 0;
2300 }
2301
2302 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2303 {
2304         struct snd_soc_codec *codec = codec_dai->codec;
2305         int reg, val, mask;
2306
2307         switch (codec_dai->id) {
2308         case 1:
2309                 reg = WM8994_AIF1_MASTER_SLAVE;
2310                 mask = WM8994_AIF1_TRI;
2311                 break;
2312         case 2:
2313                 reg = WM8994_AIF2_MASTER_SLAVE;
2314                 mask = WM8994_AIF2_TRI;
2315                 break;
2316         case 3:
2317                 reg = WM8994_POWER_MANAGEMENT_6;
2318                 mask = WM8994_AIF3_TRI;
2319                 break;
2320         default:
2321                 return -EINVAL;
2322         }
2323
2324         if (tristate)
2325                 val = mask;
2326         else
2327                 val = 0;
2328
2329         return snd_soc_update_bits(codec, reg, mask, val);
2330 }
2331
2332 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2333
2334 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2335                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2336
2337 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2338         .set_sysclk     = wm8994_set_dai_sysclk,
2339         .set_fmt        = wm8994_set_dai_fmt,
2340         .hw_params      = wm8994_hw_params,
2341         .digital_mute   = wm8994_aif_mute,
2342         .set_pll        = wm8994_set_fll,
2343         .set_tristate   = wm8994_set_tristate,
2344 };
2345
2346 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2347         .set_sysclk     = wm8994_set_dai_sysclk,
2348         .set_fmt        = wm8994_set_dai_fmt,
2349         .hw_params      = wm8994_hw_params,
2350         .digital_mute   = wm8994_aif_mute,
2351         .set_pll        = wm8994_set_fll,
2352         .set_tristate   = wm8994_set_tristate,
2353 };
2354
2355 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2356         .hw_params      = wm8994_aif3_hw_params,
2357         .set_tristate   = wm8994_set_tristate,
2358 };
2359
2360 static struct snd_soc_dai_driver wm8994_dai[] = {
2361         {
2362                 .name = "wm8994-aif1",
2363                 .id = 1,
2364                 .playback = {
2365                         .stream_name = "AIF1 Playback",
2366                         .channels_min = 1,
2367                         .channels_max = 2,
2368                         .rates = WM8994_RATES,
2369                         .formats = WM8994_FORMATS,
2370                 },
2371                 .capture = {
2372                         .stream_name = "AIF1 Capture",
2373                         .channels_min = 1,
2374                         .channels_max = 2,
2375                         .rates = WM8994_RATES,
2376                         .formats = WM8994_FORMATS,
2377                  },
2378                 .ops = &wm8994_aif1_dai_ops,
2379         },
2380         {
2381                 .name = "wm8994-aif2",
2382                 .id = 2,
2383                 .playback = {
2384                         .stream_name = "AIF2 Playback",
2385                         .channels_min = 1,
2386                         .channels_max = 2,
2387                         .rates = WM8994_RATES,
2388                         .formats = WM8994_FORMATS,
2389                 },
2390                 .capture = {
2391                         .stream_name = "AIF2 Capture",
2392                         .channels_min = 1,
2393                         .channels_max = 2,
2394                         .rates = WM8994_RATES,
2395                         .formats = WM8994_FORMATS,
2396                 },
2397                 .ops = &wm8994_aif2_dai_ops,
2398         },
2399         {
2400                 .name = "wm8994-aif3",
2401                 .id = 3,
2402                 .playback = {
2403                         .stream_name = "AIF3 Playback",
2404                         .channels_min = 1,
2405                         .channels_max = 2,
2406                         .rates = WM8994_RATES,
2407                         .formats = WM8994_FORMATS,
2408                 },
2409                 .capture = {
2410                         .stream_name = "AIF3 Capture",
2411                         .channels_min = 1,
2412                         .channels_max = 2,
2413                         .rates = WM8994_RATES,
2414                         .formats = WM8994_FORMATS,
2415                 },
2416                 .ops = &wm8994_aif3_dai_ops,
2417         }
2418 };
2419
2420 #ifdef CONFIG_PM
2421 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2422 {
2423         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2424         struct wm8994 *control = codec->control_data;
2425         int i, ret;
2426
2427         switch (control->type) {
2428         case WM8994:
2429                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2430                 break;
2431         case WM8958:
2432                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2433                                     WM8958_MICD_ENA, 0);
2434                 break;
2435         }
2436
2437         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2438                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2439                        sizeof(struct wm8994_fll_config));
2440                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2441                 if (ret < 0)
2442                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2443                                  i + 1, ret);
2444         }
2445
2446         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2447
2448         return 0;
2449 }
2450
2451 static int wm8994_resume(struct snd_soc_codec *codec)
2452 {
2453         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2454         struct wm8994 *control = codec->control_data;
2455         int i, ret;
2456         unsigned int val, mask;
2457
2458         if (wm8994->revision < 4) {
2459                 /* force a HW read */
2460                 val = wm8994_reg_read(codec->control_data,
2461                                       WM8994_POWER_MANAGEMENT_5);
2462
2463                 /* modify the cache only */
2464                 codec->cache_only = 1;
2465                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2466                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2467                 val &= mask;
2468                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2469                                     mask, val);
2470                 codec->cache_only = 0;
2471         }
2472
2473         /* Restore the registers */
2474         ret = snd_soc_cache_sync(codec);
2475         if (ret != 0)
2476                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2477
2478         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2479
2480         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2481                 if (!wm8994->fll_suspend[i].out)
2482                         continue;
2483
2484                 ret = _wm8994_set_fll(codec, i + 1,
2485                                      wm8994->fll_suspend[i].src,
2486                                      wm8994->fll_suspend[i].in,
2487                                      wm8994->fll_suspend[i].out);
2488                 if (ret < 0)
2489                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2490                                  i + 1, ret);
2491         }
2492
2493         switch (control->type) {
2494         case WM8994:
2495                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2496                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2497                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2498                 break;
2499         case WM8958:
2500                 if (wm8994->jack_cb)
2501                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2502                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2503                 break;
2504         }
2505
2506         return 0;
2507 }
2508 #else
2509 #define wm8994_suspend NULL
2510 #define wm8994_resume NULL
2511 #endif
2512
2513 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2514 {
2515         struct snd_soc_codec *codec = wm8994->codec;
2516         struct wm8994_pdata *pdata = wm8994->pdata;
2517         struct snd_kcontrol_new controls[] = {
2518                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2519                              wm8994->retune_mobile_enum,
2520                              wm8994_get_retune_mobile_enum,
2521                              wm8994_put_retune_mobile_enum),
2522                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2523                              wm8994->retune_mobile_enum,
2524                              wm8994_get_retune_mobile_enum,
2525                              wm8994_put_retune_mobile_enum),
2526                 SOC_ENUM_EXT("AIF2 EQ Mode",
2527                              wm8994->retune_mobile_enum,
2528                              wm8994_get_retune_mobile_enum,
2529                              wm8994_put_retune_mobile_enum),
2530         };
2531         int ret, i, j;
2532         const char **t;
2533
2534         /* We need an array of texts for the enum API but the number
2535          * of texts is likely to be less than the number of
2536          * configurations due to the sample rate dependency of the
2537          * configurations. */
2538         wm8994->num_retune_mobile_texts = 0;
2539         wm8994->retune_mobile_texts = NULL;
2540         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2541                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2542                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2543                                    wm8994->retune_mobile_texts[j]) == 0)
2544                                 break;
2545                 }
2546
2547                 if (j != wm8994->num_retune_mobile_texts)
2548                         continue;
2549
2550                 /* Expand the array... */
2551                 t = krealloc(wm8994->retune_mobile_texts,
2552                              sizeof(char *) *
2553                              (wm8994->num_retune_mobile_texts + 1),
2554                              GFP_KERNEL);
2555                 if (t == NULL)
2556                         continue;
2557
2558                 /* ...store the new entry... */
2559                 t[wm8994->num_retune_mobile_texts] =
2560                         pdata->retune_mobile_cfgs[i].name;
2561
2562                 /* ...and remember the new version. */
2563                 wm8994->num_retune_mobile_texts++;
2564                 wm8994->retune_mobile_texts = t;
2565         }
2566
2567         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2568                 wm8994->num_retune_mobile_texts);
2569
2570         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2571         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2572
2573         ret = snd_soc_add_controls(wm8994->codec, controls,
2574                                    ARRAY_SIZE(controls));
2575         if (ret != 0)
2576                 dev_err(wm8994->codec->dev,
2577                         "Failed to add ReTune Mobile controls: %d\n", ret);
2578 }
2579
2580 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2581 {
2582         struct snd_soc_codec *codec = wm8994->codec;
2583         struct wm8994_pdata *pdata = wm8994->pdata;
2584         int ret, i;
2585
2586         if (!pdata)
2587                 return;
2588
2589         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2590                                       pdata->lineout2_diff,
2591                                       pdata->lineout1fb,
2592                                       pdata->lineout2fb,
2593                                       pdata->jd_scthr,
2594                                       pdata->jd_thr,
2595                                       pdata->micbias1_lvl,
2596                                       pdata->micbias2_lvl);
2597
2598         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2599
2600         if (pdata->num_drc_cfgs) {
2601                 struct snd_kcontrol_new controls[] = {
2602                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2603                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2604                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2605                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2606                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2607                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2608                 };
2609
2610                 /* We need an array of texts for the enum API */
2611                 wm8994->drc_texts = kmalloc(sizeof(char *)
2612                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2613                 if (!wm8994->drc_texts) {
2614                         dev_err(wm8994->codec->dev,
2615                                 "Failed to allocate %d DRC config texts\n",
2616                                 pdata->num_drc_cfgs);
2617                         return;
2618                 }
2619
2620                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2621                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2622
2623                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2624                 wm8994->drc_enum.texts = wm8994->drc_texts;
2625
2626                 ret = snd_soc_add_controls(wm8994->codec, controls,
2627                                            ARRAY_SIZE(controls));
2628                 if (ret != 0)
2629                         dev_err(wm8994->codec->dev,
2630                                 "Failed to add DRC mode controls: %d\n", ret);
2631
2632                 for (i = 0; i < WM8994_NUM_DRC; i++)
2633                         wm8994_set_drc(codec, i);
2634         }
2635
2636         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2637                 pdata->num_retune_mobile_cfgs);
2638
2639         if (pdata->num_retune_mobile_cfgs)
2640                 wm8994_handle_retune_mobile_pdata(wm8994);
2641         else
2642                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2643                                      ARRAY_SIZE(wm8994_eq_controls));
2644
2645         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2646                 if (pdata->micbias[i]) {
2647                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2648                                 pdata->micbias[i] & 0xffff);
2649                 }
2650         }
2651 }
2652
2653 /**
2654  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2655  *
2656  * @codec:   WM8994 codec
2657  * @jack:    jack to report detection events on
2658  * @micbias: microphone bias to detect on
2659  * @det:     value to report for presence detection
2660  * @shrt:    value to report for short detection
2661  *
2662  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2663  * being used to bring out signals to the processor then only platform
2664  * data configuration is needed for WM8994 and processor GPIOs should
2665  * be configured using snd_soc_jack_add_gpios() instead.
2666  *
2667  * Configuration of detection levels is available via the micbias1_lvl
2668  * and micbias2_lvl platform data members.
2669  */
2670 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2671                       int micbias, int det, int shrt)
2672 {
2673         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2674         struct wm8994_micdet *micdet;
2675         struct wm8994 *control = codec->control_data;
2676         int reg;
2677
2678         if (control->type != WM8994)
2679                 return -EINVAL;
2680
2681         switch (micbias) {
2682         case 1:
2683                 micdet = &wm8994->micdet[0];
2684                 break;
2685         case 2:
2686                 micdet = &wm8994->micdet[1];
2687                 break;
2688         default:
2689                 return -EINVAL;
2690         }
2691
2692         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2693                 micbias, det, shrt);
2694
2695         /* Store the configuration */
2696         micdet->jack = jack;
2697         micdet->det = det;
2698         micdet->shrt = shrt;
2699
2700         /* If either of the jacks is set up then enable detection */
2701         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2702                 reg = WM8994_MICD_ENA;
2703         else
2704                 reg = 0;
2705
2706         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2707
2708         return 0;
2709 }
2710 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2711
2712 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2713 {
2714         struct wm8994_priv *priv = data;
2715         struct snd_soc_codec *codec = priv->codec;
2716         int reg;
2717         int report;
2718
2719 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2720         trace_snd_soc_jack_irq(dev_name(codec->dev));
2721 #endif
2722
2723         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2724         if (reg < 0) {
2725                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2726                         reg);
2727                 return IRQ_HANDLED;
2728         }
2729
2730         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2731
2732         report = 0;
2733         if (reg & WM8994_MIC1_DET_STS)
2734                 report |= priv->micdet[0].det;
2735         if (reg & WM8994_MIC1_SHRT_STS)
2736                 report |= priv->micdet[0].shrt;
2737         snd_soc_jack_report(priv->micdet[0].jack, report,
2738                             priv->micdet[0].det | priv->micdet[0].shrt);
2739
2740         report = 0;
2741         if (reg & WM8994_MIC2_DET_STS)
2742                 report |= priv->micdet[1].det;
2743         if (reg & WM8994_MIC2_SHRT_STS)
2744                 report |= priv->micdet[1].shrt;
2745         snd_soc_jack_report(priv->micdet[1].jack, report,
2746                             priv->micdet[1].det | priv->micdet[1].shrt);
2747
2748         return IRQ_HANDLED;
2749 }
2750
2751 /* Default microphone detection handler for WM8958 - the user can
2752  * override this if they wish.
2753  */
2754 static void wm8958_default_micdet(u16 status, void *data)
2755 {
2756         struct snd_soc_codec *codec = data;
2757         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2758         int report = 0;
2759
2760         /* If nothing present then clear our statuses */
2761         if (!(status & WM8958_MICD_STS))
2762                 goto done;
2763
2764         report = SND_JACK_MICROPHONE;
2765
2766         /* Everything else is buttons; just assign slots */
2767         if (status & 0x1c)
2768                 report |= SND_JACK_BTN_0;
2769
2770 done:
2771         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2772                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2773 }
2774
2775 /**
2776  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2777  *
2778  * @codec:   WM8958 codec
2779  * @jack:    jack to report detection events on
2780  *
2781  * Enable microphone detection functionality for the WM8958.  By
2782  * default simple detection which supports the detection of up to 6
2783  * buttons plus video and microphone functionality is supported.
2784  *
2785  * The WM8958 has an advanced jack detection facility which is able to
2786  * support complex accessory detection, especially when used in
2787  * conjunction with external circuitry.  In order to provide maximum
2788  * flexiblity a callback is provided which allows a completely custom
2789  * detection algorithm.
2790  */
2791 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2792                       wm8958_micdet_cb cb, void *cb_data)
2793 {
2794         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2795         struct wm8994 *control = codec->control_data;
2796
2797         if (control->type != WM8958)
2798                 return -EINVAL;
2799
2800         if (jack) {
2801                 if (!cb) {
2802                         dev_dbg(codec->dev, "Using default micdet callback\n");
2803                         cb = wm8958_default_micdet;
2804                         cb_data = codec;
2805                 }
2806
2807                 wm8994->micdet[0].jack = jack;
2808                 wm8994->jack_cb = cb;
2809                 wm8994->jack_cb_data = cb_data;
2810
2811                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2812                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
2813         } else {
2814                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2815                                     WM8958_MICD_ENA, 0);
2816         }
2817
2818         return 0;
2819 }
2820 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2821
2822 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2823 {
2824         struct wm8994_priv *wm8994 = data;
2825         struct snd_soc_codec *codec = wm8994->codec;
2826         int reg;
2827
2828         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2829         if (reg < 0) {
2830                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2831                         reg);
2832                 return IRQ_NONE;
2833         }
2834
2835         if (!(reg & WM8958_MICD_VALID)) {
2836                 dev_dbg(codec->dev, "Mic detect data not valid\n");
2837                 goto out;
2838         }
2839
2840 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2841         trace_snd_soc_jack_irq(dev_name(codec->dev));
2842 #endif
2843
2844         if (wm8994->jack_cb)
2845                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2846         else
2847                 dev_warn(codec->dev, "Accessory detection with no callback\n");
2848
2849 out:
2850         return IRQ_HANDLED;
2851 }
2852
2853 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2854 {
2855         struct wm8994 *control;
2856         struct wm8994_priv *wm8994;
2857         struct snd_soc_dapm_context *dapm = &codec->dapm;
2858         int ret, i;
2859
2860         codec->control_data = dev_get_drvdata(codec->dev->parent);
2861         control = codec->control_data;
2862
2863         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2864         if (wm8994 == NULL)
2865                 return -ENOMEM;
2866         snd_soc_codec_set_drvdata(codec, wm8994);
2867
2868         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2869         wm8994->codec = codec;
2870
2871         if (wm8994->pdata && wm8994->pdata->micdet_irq)
2872                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2873         else if (wm8994->pdata && wm8994->pdata->irq_base)
2874                 wm8994->micdet_irq = wm8994->pdata->irq_base +
2875                                      WM8994_IRQ_MIC1_DET;
2876
2877         pm_runtime_enable(codec->dev);
2878         pm_runtime_resume(codec->dev);
2879
2880         /* Read our current status back from the chip - we don't want to
2881          * reset as this may interfere with the GPIO or LDO operation. */
2882         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2883                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2884                         continue;
2885
2886                 ret = wm8994_reg_read(codec->control_data, i);
2887                 if (ret <= 0)
2888                         continue;
2889
2890                 ret = snd_soc_cache_write(codec, i, ret);
2891                 if (ret != 0) {
2892                         dev_err(codec->dev,
2893                                 "Failed to initialise cache for 0x%x: %d\n",
2894                                 i, ret);
2895                         goto err;
2896                 }
2897         }
2898
2899         /* Set revision-specific configuration */
2900         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2901         switch (control->type) {
2902         case WM8994:
2903                 switch (wm8994->revision) {
2904                 case 2:
2905                 case 3:
2906                         wm8994->hubs.dcs_codes = -5;
2907                         wm8994->hubs.hp_startup_mode = 1;
2908                         wm8994->hubs.dcs_readback_mode = 1;
2909                         break;
2910                 default:
2911                         wm8994->hubs.dcs_readback_mode = 1;
2912                         break;
2913                 }
2914
2915         case WM8958:
2916                 wm8994->hubs.dcs_readback_mode = 1;
2917                 break;
2918
2919         default:
2920                 break;
2921         }
2922
2923         switch (control->type) {
2924         case WM8994:
2925                 if (wm8994->micdet_irq) {
2926                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2927                                                    wm8994_mic_irq,
2928                                                    IRQF_TRIGGER_RISING,
2929                                                    "Mic1 detect",
2930                                                    wm8994);
2931                         if (ret != 0)
2932                                 dev_warn(codec->dev,
2933                                          "Failed to request Mic1 detect IRQ: %d\n",
2934                                          ret);
2935                 }
2936
2937                 ret = wm8994_request_irq(codec->control_data,
2938                                          WM8994_IRQ_MIC1_SHRT,
2939                                          wm8994_mic_irq, "Mic 1 short",
2940                                          wm8994);
2941                 if (ret != 0)
2942                         dev_warn(codec->dev,
2943                                  "Failed to request Mic1 short IRQ: %d\n",
2944                                  ret);
2945
2946                 ret = wm8994_request_irq(codec->control_data,
2947                                          WM8994_IRQ_MIC2_DET,
2948                                          wm8994_mic_irq, "Mic 2 detect",
2949                                          wm8994);
2950                 if (ret != 0)
2951                         dev_warn(codec->dev,
2952                                  "Failed to request Mic2 detect IRQ: %d\n",
2953                                  ret);
2954
2955                 ret = wm8994_request_irq(codec->control_data,
2956                                          WM8994_IRQ_MIC2_SHRT,
2957                                          wm8994_mic_irq, "Mic 2 short",
2958                                          wm8994);
2959                 if (ret != 0)
2960                         dev_warn(codec->dev,
2961                                  "Failed to request Mic2 short IRQ: %d\n",
2962                                  ret);
2963                 break;
2964
2965         case WM8958:
2966                 if (wm8994->micdet_irq) {
2967                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2968                                                    wm8958_mic_irq,
2969                                                    IRQF_TRIGGER_RISING,
2970                                                    "Mic detect",
2971                                                    wm8994);
2972                         if (ret != 0)
2973                                 dev_warn(codec->dev,
2974                                          "Failed to request Mic detect IRQ: %d\n",
2975                                          ret);
2976                 }
2977         }
2978
2979         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
2980          * configured on init - if a system wants to do this dynamically
2981          * at runtime we can deal with that then.
2982          */
2983         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2984         if (ret < 0) {
2985                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
2986                 goto err_irq;
2987         }
2988         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2989                 wm8994->lrclk_shared[0] = 1;
2990                 wm8994_dai[0].symmetric_rates = 1;
2991         } else {
2992                 wm8994->lrclk_shared[0] = 0;
2993         }
2994
2995         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2996         if (ret < 0) {
2997                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
2998                 goto err_irq;
2999         }
3000         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3001                 wm8994->lrclk_shared[1] = 1;
3002                 wm8994_dai[1].symmetric_rates = 1;
3003         } else {
3004                 wm8994->lrclk_shared[1] = 0;
3005         }
3006
3007         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3008
3009         /* Latch volume updates (right only; we always do left then right). */
3010         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3011                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3012         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3013                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3014         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3015                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3016         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3017                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3018         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3019                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3020         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3021                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3022         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3023                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3024         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3025                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3026         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3027                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3028         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3029                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3030         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3031                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3032         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3033                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3034         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3035                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3036         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3037                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3038         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3039                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3040         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3041                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3042
3043         /* Set the low bit of the 3D stereo depth so TLV matches */
3044         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3045                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3046                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3047         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3048                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3049                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3050         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3051                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3052                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3053
3054         /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3055          * behaviour on idle TDM clock cycles. */
3056         snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3057                             WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3058
3059         wm8994_update_class_w(codec);
3060
3061         wm8994_handle_pdata(wm8994);
3062
3063         wm_hubs_add_analogue_controls(codec);
3064         snd_soc_add_controls(codec, wm8994_snd_controls,
3065                              ARRAY_SIZE(wm8994_snd_controls));
3066         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3067                                   ARRAY_SIZE(wm8994_dapm_widgets));
3068
3069         switch (control->type) {
3070         case WM8994:
3071                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3072                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3073                 if (wm8994->revision < 4) {
3074                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3075                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3076                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3077                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3078                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3079                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3080                 } else {
3081                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3082                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3083                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3084                                                   ARRAY_SIZE(wm8994_adc_widgets));
3085                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3086                                                   ARRAY_SIZE(wm8994_dac_widgets));
3087                 }
3088                 break;
3089         case WM8958:
3090                 snd_soc_add_controls(codec, wm8958_snd_controls,
3091                                      ARRAY_SIZE(wm8958_snd_controls));
3092                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3093                                           ARRAY_SIZE(wm8958_dapm_widgets));
3094                 if (wm8994->revision < 1) {
3095                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3096                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3097                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3098                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3099                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3100                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3101                 } else {
3102                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3103                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3104                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3105                                                   ARRAY_SIZE(wm8994_adc_widgets));
3106                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3107                                                   ARRAY_SIZE(wm8994_dac_widgets));
3108                 }
3109                 break;
3110         }
3111
3112
3113         wm_hubs_add_analogue_routes(codec, 0, 0);
3114         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3115
3116         switch (control->type) {
3117         case WM8994:
3118                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3119                                         ARRAY_SIZE(wm8994_intercon));
3120
3121                 if (wm8994->revision < 4) {
3122                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3123                                                 ARRAY_SIZE(wm8994_revd_intercon));
3124                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3125                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3126                 } else {
3127                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3128                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3129                 }
3130                 break;
3131         case WM8958:
3132                 if (wm8994->revision < 1) {
3133                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3134                                                 ARRAY_SIZE(wm8994_revd_intercon));
3135                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3136                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3137                 } else {
3138                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3139                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3140                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3141                                                 ARRAY_SIZE(wm8958_intercon));
3142                 }
3143
3144                 wm8958_dsp2_init(codec);
3145                 break;
3146         }
3147
3148         return 0;
3149
3150 err_irq:
3151         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3152         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3153         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3154         if (wm8994->micdet_irq)
3155                 free_irq(wm8994->micdet_irq, wm8994);
3156 err:
3157         kfree(wm8994);
3158         return ret;
3159 }
3160
3161 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3162 {
3163         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3164         struct wm8994 *control = codec->control_data;
3165
3166         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3167
3168         pm_runtime_disable(codec->dev);
3169
3170         switch (control->type) {
3171         case WM8994:
3172                 if (wm8994->micdet_irq)
3173                         free_irq(wm8994->micdet_irq, wm8994);
3174                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3175                                 wm8994);
3176                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3177                                 wm8994);
3178                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3179                                 wm8994);
3180                 break;
3181
3182         case WM8958:
3183                 if (wm8994->micdet_irq)
3184                         free_irq(wm8994->micdet_irq, wm8994);
3185                 break;
3186         }
3187         if (wm8994->mbc)
3188                 release_firmware(wm8994->mbc);
3189         if (wm8994->mbc_vss)
3190                 release_firmware(wm8994->mbc_vss);
3191         if (wm8994->enh_eq)
3192                 release_firmware(wm8994->enh_eq);
3193         kfree(wm8994->retune_mobile_texts);
3194         kfree(wm8994->drc_texts);
3195         kfree(wm8994);
3196
3197         return 0;
3198 }
3199
3200 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3201         .probe =        wm8994_codec_probe,
3202         .remove =       wm8994_codec_remove,
3203         .suspend =      wm8994_suspend,
3204         .resume =       wm8994_resume,
3205         .read =         wm8994_read,
3206         .write =        wm8994_write,
3207         .readable_register = wm8994_readable,
3208         .volatile_register = wm8994_volatile,
3209         .set_bias_level = wm8994_set_bias_level,
3210
3211         .reg_cache_size = WM8994_CACHE_SIZE,
3212         .reg_cache_default = wm8994_reg_defaults,
3213         .reg_word_size = 2,
3214         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3215 };
3216
3217 static int __devinit wm8994_probe(struct platform_device *pdev)
3218 {
3219         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3220                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3221 }
3222
3223 static int __devexit wm8994_remove(struct platform_device *pdev)
3224 {
3225         snd_soc_unregister_codec(&pdev->dev);
3226         return 0;
3227 }
3228
3229 static struct platform_driver wm8994_codec_driver = {
3230         .driver = {
3231                    .name = "wm8994-codec",
3232                    .owner = THIS_MODULE,
3233                    },
3234         .probe = wm8994_probe,
3235         .remove = __devexit_p(wm8994_remove),
3236 };
3237
3238 static __init int wm8994_init(void)
3239 {
3240         return platform_driver_register(&wm8994_codec_driver);
3241 }
3242 module_init(wm8994_init);
3243
3244 static __exit void wm8994_exit(void)
3245 {
3246         platform_driver_unregister(&wm8994_codec_driver);
3247 }
3248 module_exit(wm8994_exit);
3249
3250
3251 MODULE_DESCRIPTION("ASoC WM8994 driver");
3252 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3253 MODULE_LICENSE("GPL");
3254 MODULE_ALIAS("platform:wm8994-codec");