sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <linux/io.h>
  35 #include <linux/delay.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/init.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/module.h>
  43 #include <linux/firmware.h>
  44 #include <linux/input.h>
  45 #include <sound/core.h>
  46 #include <sound/info.h>
  47 #include <sound/control.h>
  48 #include <sound/pcm.h>
  49 #include <sound/mpu401.h>
  50 #include <sound/ac97_codec.h>
  51 #include <sound/initval.h>
  52 #include <asm/byteorder.h>
  53
  54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  56 MODULE_LICENSE("GPL");
  57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  58                 "{ESS,ES1988},"
  59                 "{ESS,Allegro PCI},"
  60                 "{ESS,Allegro-1 PCI},"
  61                 "{ESS,Canyon3D-2/LE PCI}}");
  62 /*(DEBLOBBED)*/
  63
  64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  65 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  66 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  67 static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  68 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  69
  70 module_param_array(index, int, NULL, 0444);
  71 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  72 module_param_array(id, charp, NULL, 0444);
  73 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  74 module_param_array(enable, bool, NULL, 0444);
  75 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  76 module_param_array(external_amp, bool, NULL, 0444);
  77 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  78 module_param_array(amp_gpio, int, NULL, 0444);
  79 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  80
  81 #define MAX_PLAYBACKS   2
  82 #define MAX_CAPTURES    1
  83 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  84
  85
  86 /*
  87  * maestro3 registers
  88  */
  89
  90 /* Allegro PCI configuration registers */
  91 #define PCI_LEGACY_AUDIO_CTRL   0x40
  92 #define SOUND_BLASTER_ENABLE    0x00000001
  93 #define FM_SYNTHESIS_ENABLE     0x00000002
  94 #define GAME_PORT_ENABLE        0x00000004
  95 #define MPU401_IO_ENABLE        0x00000008
  96 #define MPU401_IRQ_ENABLE       0x00000010
  97 #define ALIAS_10BIT_IO          0x00000020
  98 #define SB_DMA_MASK             0x000000C0
  99 #define SB_DMA_0                0x00000040
 100 #define SB_DMA_1                0x00000040
 101 #define SB_DMA_R                0x00000080
 102 #define SB_DMA_3                0x000000C0
 103 #define SB_IRQ_MASK             0x00000700
 104 #define SB_IRQ_5                0x00000000
 105 #define SB_IRQ_7                0x00000100
 106 #define SB_IRQ_9                0x00000200
 107 #define SB_IRQ_10               0x00000300
 108 #define MIDI_IRQ_MASK           0x00003800
 109 #define SERIAL_IRQ_ENABLE       0x00004000
 110 #define DISABLE_LEGACY          0x00008000
 111
 112 #define PCI_ALLEGRO_CONFIG      0x50
 113 #define SB_ADDR_240             0x00000004
 114 #define MPU_ADDR_MASK           0x00000018
 115 #define MPU_ADDR_330            0x00000000
 116 #define MPU_ADDR_300            0x00000008
 117 #define MPU_ADDR_320            0x00000010
 118 #define MPU_ADDR_340            0x00000018
 119 #define USE_PCI_TIMING          0x00000040
 120 #define POSTED_WRITE_ENABLE     0x00000080
 121 #define DMA_POLICY_MASK         0x00000700
 122 #define DMA_DDMA                0x00000000
 123 #define DMA_TDMA                0x00000100
 124 #define DMA_PCPCI               0x00000200
 125 #define DMA_WBDMA16             0x00000400
 126 #define DMA_WBDMA4              0x00000500
 127 #define DMA_WBDMA2              0x00000600
 128 #define DMA_WBDMA1              0x00000700
 129 #define DMA_SAFE_GUARD          0x00000800
 130 #define HI_PERF_GP_ENABLE       0x00001000
 131 #define PIC_SNOOP_MODE_0        0x00002000
 132 #define PIC_SNOOP_MODE_1        0x00004000
 133 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 134 #define RING_IN_ENABLE          0x00010000
 135 #define SPDIF_TEST_MODE         0x00020000
 136 #define CLK_MULT_MODE_SELECT_2  0x00040000
 137 #define EEPROM_WRITE_ENABLE     0x00080000
 138 #define CODEC_DIR_IN            0x00100000
 139 #define HV_BUTTON_FROM_GD       0x00200000
 140 #define REDUCED_DEBOUNCE        0x00400000
 141 #define HV_CTRL_ENABLE          0x00800000
 142 #define SPDIF_ENABLE            0x01000000
 143 #define CLK_DIV_SELECT          0x06000000
 144 #define CLK_DIV_BY_48           0x00000000
 145 #define CLK_DIV_BY_49           0x02000000
 146 #define CLK_DIV_BY_50           0x04000000
 147 #define CLK_DIV_RESERVED        0x06000000
 148 #define PM_CTRL_ENABLE          0x08000000
 149 #define CLK_MULT_MODE_SELECT    0x30000000
 150 #define CLK_MULT_MODE_SHIFT     28
 151 #define CLK_MULT_MODE_0         0x00000000
 152 #define CLK_MULT_MODE_1         0x10000000
 153 #define CLK_MULT_MODE_2         0x20000000
 154 #define CLK_MULT_MODE_3         0x30000000
 155 #define INT_CLK_SELECT          0x40000000
 156 #define INT_CLK_MULT_RESET      0x80000000
 157
 158 /* M3 */
 159 #define INT_CLK_SRC_NOT_PCI     0x00100000
 160 #define INT_CLK_MULT_ENABLE     0x80000000
 161
 162 #define PCI_ACPI_CONTROL        0x54
 163 #define PCI_ACPI_D0             0x00000000
 164 #define PCI_ACPI_D1             0xB4F70000
 165 #define PCI_ACPI_D2             0xB4F7B4F7
 166
 167 #define PCI_USER_CONFIG         0x58
 168 #define EXT_PCI_MASTER_ENABLE   0x00000001
 169 #define SPDIF_OUT_SELECT        0x00000002
 170 #define TEST_PIN_DIR_CTRL       0x00000004
 171 #define AC97_CODEC_TEST         0x00000020
 172 #define TRI_STATE_BUFFER        0x00000080
 173 #define IN_CLK_12MHZ_SELECT     0x00000100
 174 #define MULTI_FUNC_DISABLE      0x00000200
 175 #define EXT_MASTER_PAIR_SEL     0x00000400
 176 #define PCI_MASTER_SUPPORT      0x00000800
 177 #define STOP_CLOCK_ENABLE       0x00001000
 178 #define EAPD_DRIVE_ENABLE       0x00002000
 179 #define REQ_TRI_STATE_ENABLE    0x00004000
 180 #define REQ_LOW_ENABLE          0x00008000
 181 #define MIDI_1_ENABLE           0x00010000
 182 #define MIDI_2_ENABLE           0x00020000
 183 #define SB_AUDIO_SYNC           0x00040000
 184 #define HV_CTRL_TEST            0x00100000
 185 #define SOUNDBLASTER_TEST       0x00400000
 186
 187 #define PCI_USER_CONFIG_C       0x5C
 188
 189 #define PCI_DDMA_CTRL           0x60
 190 #define DDMA_ENABLE             0x00000001
 191
 192
 193 /* Allegro registers */
 194 #define HOST_INT_CTRL           0x18
 195 #define SB_INT_ENABLE           0x0001
 196 #define MPU401_INT_ENABLE       0x0002
 197 #define ASSP_INT_ENABLE         0x0010
 198 #define RING_INT_ENABLE         0x0020
 199 #define HV_INT_ENABLE           0x0040
 200 #define CLKRUN_GEN_ENABLE       0x0100
 201 #define HV_CTRL_TO_PME          0x0400
 202 #define SOFTWARE_RESET_ENABLE   0x8000
 203
 204 /*
 205  * should be using the above defines, probably.
 206  */
 207 #define REGB_ENABLE_RESET               0x01
 208 #define REGB_STOP_CLOCK                 0x10
 209
 210 #define HOST_INT_STATUS         0x1A
 211 #define SB_INT_PENDING          0x01
 212 #define MPU401_INT_PENDING      0x02
 213 #define ASSP_INT_PENDING        0x10
 214 #define RING_INT_PENDING        0x20
 215 #define HV_INT_PENDING          0x40
 216
 217 #define HARDWARE_VOL_CTRL       0x1B
 218 #define SHADOW_MIX_REG_VOICE    0x1C
 219 #define HW_VOL_COUNTER_VOICE    0x1D
 220 #define SHADOW_MIX_REG_MASTER   0x1E
 221 #define HW_VOL_COUNTER_MASTER   0x1F
 222
 223 #define CODEC_COMMAND           0x30
 224 #define CODEC_READ_B            0x80
 225
 226 #define CODEC_STATUS            0x30
 227 #define CODEC_BUSY_B            0x01
 228
 229 #define CODEC_DATA              0x32
 230
 231 #define RING_BUS_CTRL_A         0x36
 232 #define RAC_PME_ENABLE          0x0100
 233 #define RAC_SDFS_ENABLE         0x0200
 234 #define LAC_PME_ENABLE          0x0400
 235 #define LAC_SDFS_ENABLE         0x0800
 236 #define SERIAL_AC_LINK_ENABLE   0x1000
 237 #define IO_SRAM_ENABLE          0x2000
 238 #define IIS_INPUT_ENABLE        0x8000
 239
 240 #define RING_BUS_CTRL_B         0x38
 241 #define SECOND_CODEC_ID_MASK    0x0003
 242 #define SPDIF_FUNC_ENABLE       0x0010
 243 #define SECOND_AC_ENABLE        0x0020
 244 #define SB_MODULE_INTF_ENABLE   0x0040
 245 #define SSPE_ENABLE             0x0040
 246 #define M3I_DOCK_ENABLE         0x0080
 247
 248 #define SDO_OUT_DEST_CTRL       0x3A
 249 #define COMMAND_ADDR_OUT        0x0003
 250 #define PCM_LR_OUT_LOCAL        0x0000
 251 #define PCM_LR_OUT_REMOTE       0x0004
 252 #define PCM_LR_OUT_MUTE         0x0008
 253 #define PCM_LR_OUT_BOTH         0x000C
 254 #define LINE1_DAC_OUT_LOCAL     0x0000
 255 #define LINE1_DAC_OUT_REMOTE    0x0010
 256 #define LINE1_DAC_OUT_MUTE      0x0020
 257 #define LINE1_DAC_OUT_BOTH      0x0030
 258 #define PCM_CLS_OUT_LOCAL       0x0000
 259 #define PCM_CLS_OUT_REMOTE      0x0040
 260 #define PCM_CLS_OUT_MUTE        0x0080
 261 #define PCM_CLS_OUT_BOTH        0x00C0
 262 #define PCM_RLF_OUT_LOCAL       0x0000
 263 #define PCM_RLF_OUT_REMOTE      0x0100
 264 #define PCM_RLF_OUT_MUTE        0x0200
 265 #define PCM_RLF_OUT_BOTH        0x0300
 266 #define LINE2_DAC_OUT_LOCAL     0x0000
 267 #define LINE2_DAC_OUT_REMOTE    0x0400
 268 #define LINE2_DAC_OUT_MUTE      0x0800
 269 #define LINE2_DAC_OUT_BOTH      0x0C00
 270 #define HANDSET_OUT_LOCAL       0x0000
 271 #define HANDSET_OUT_REMOTE      0x1000
 272 #define HANDSET_OUT_MUTE        0x2000
 273 #define HANDSET_OUT_BOTH        0x3000
 274 #define IO_CTRL_OUT_LOCAL       0x0000
 275 #define IO_CTRL_OUT_REMOTE      0x4000
 276 #define IO_CTRL_OUT_MUTE        0x8000
 277 #define IO_CTRL_OUT_BOTH        0xC000
 278
 279 #define SDO_IN_DEST_CTRL        0x3C
 280 #define STATUS_ADDR_IN          0x0003
 281 #define PCM_LR_IN_LOCAL         0x0000
 282 #define PCM_LR_IN_REMOTE        0x0004
 283 #define PCM_LR_RESERVED         0x0008
 284 #define PCM_LR_IN_BOTH          0x000C
 285 #define LINE1_ADC_IN_LOCAL      0x0000
 286 #define LINE1_ADC_IN_REMOTE     0x0010
 287 #define LINE1_ADC_IN_MUTE       0x0020
 288 #define MIC_ADC_IN_LOCAL        0x0000
 289 #define MIC_ADC_IN_REMOTE       0x0040
 290 #define MIC_ADC_IN_MUTE         0x0080
 291 #define LINE2_DAC_IN_LOCAL      0x0000
 292 #define LINE2_DAC_IN_REMOTE     0x0400
 293 #define LINE2_DAC_IN_MUTE       0x0800
 294 #define HANDSET_IN_LOCAL        0x0000
 295 #define HANDSET_IN_REMOTE       0x1000
 296 #define HANDSET_IN_MUTE         0x2000
 297 #define IO_STATUS_IN_LOCAL      0x0000
 298 #define IO_STATUS_IN_REMOTE     0x4000
 299
 300 #define SPDIF_IN_CTRL           0x3E
 301 #define SPDIF_IN_ENABLE         0x0001
 302
 303 #define GPIO_DATA               0x60
 304 #define GPIO_DATA_MASK          0x0FFF
 305 #define GPIO_HV_STATUS          0x3000
 306 #define GPIO_PME_STATUS         0x4000
 307
 308 #define GPIO_MASK               0x64
 309 #define GPIO_DIRECTION          0x68
 310 #define GPO_PRIMARY_AC97        0x0001
 311 #define GPI_LINEOUT_SENSE       0x0004
 312 #define GPO_SECONDARY_AC97      0x0008
 313 #define GPI_VOL_DOWN            0x0010
 314 #define GPI_VOL_UP              0x0020
 315 #define GPI_IIS_CLK             0x0040
 316 #define GPI_IIS_LRCLK           0x0080
 317 #define GPI_IIS_DATA            0x0100
 318 #define GPI_DOCKING_STATUS      0x0100
 319 #define GPI_HEADPHONE_SENSE     0x0200
 320 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 321
 322 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 323 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 324
 325 /* M3 */
 326 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 327
 328 #define ASSP_INDEX_PORT         0x80
 329 #define ASSP_MEMORY_PORT        0x82
 330 #define ASSP_DATA_PORT          0x84
 331
 332 #define MPU401_DATA_PORT        0x98
 333 #define MPU401_STATUS_PORT      0x99
 334
 335 #define CLK_MULT_DATA_PORT      0x9C
 336
 337 #define ASSP_CONTROL_A          0xA2
 338 #define ASSP_0_WS_ENABLE        0x01
 339 #define ASSP_CTRL_A_RESERVED1   0x02
 340 #define ASSP_CTRL_A_RESERVED2   0x04
 341 #define ASSP_CLK_49MHZ_SELECT   0x08
 342 #define FAST_PLU_ENABLE         0x10
 343 #define ASSP_CTRL_A_RESERVED3   0x20
 344 #define DSP_CLK_36MHZ_SELECT    0x40
 345
 346 #define ASSP_CONTROL_B          0xA4
 347 #define RESET_ASSP              0x00
 348 #define RUN_ASSP                0x01
 349 #define ENABLE_ASSP_CLOCK       0x00
 350 #define STOP_ASSP_CLOCK         0x10
 351 #define RESET_TOGGLE            0x40
 352
 353 #define ASSP_CONTROL_C          0xA6
 354 #define ASSP_HOST_INT_ENABLE    0x01
 355 #define FM_ADDR_REMAP_DISABLE   0x02
 356 #define HOST_WRITE_PORT_ENABLE  0x08
 357
 358 #define ASSP_HOST_INT_STATUS    0xAC
 359 #define DSP2HOST_REQ_PIORECORD  0x01
 360 #define DSP2HOST_REQ_I2SRATE    0x02
 361 #define DSP2HOST_REQ_TIMER      0x04
 362
 363 /*
 364  * ASSP control regs
 365  */
 366 #define DSP_PORT_TIMER_COUNT    0x06
 367
 368 #define DSP_PORT_MEMORY_INDEX   0x80
 369
 370 #define DSP_PORT_MEMORY_TYPE    0x82
 371 #define MEMTYPE_INTERNAL_CODE   0x0002
 372 #define MEMTYPE_INTERNAL_DATA   0x0003
 373 #define MEMTYPE_MASK            0x0003
 374
 375 #define DSP_PORT_MEMORY_DATA    0x84
 376
 377 #define DSP_PORT_CONTROL_REG_A  0xA2
 378 #define DSP_PORT_CONTROL_REG_B  0xA4
 379 #define DSP_PORT_CONTROL_REG_C  0xA6
 380
 381 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 382 #define REV_A_CODE_MEMORY_END           0x0FFF
 383 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 384 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 385
 386 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 387 #define REV_B_CODE_MEMORY_END           0x0BFF
 388 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 389 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 390
 391 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 392 #define REV_A_DATA_MEMORY_END           0x2FFF
 393 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 394 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 395
 396 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 397 #define REV_B_DATA_MEMORY_END           0x2BFF
 398 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 399 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 400
 401
 402 #define NUM_UNITS_KERNEL_CODE          16
 403 #define NUM_UNITS_KERNEL_DATA           2
 404
 405 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 406 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 407
 408 /*
 409  * Kernel data layout
 410  */
 411
 412 #define DP_SHIFT_COUNT                  7
 413
 414 #define KDATA_BASE_ADDR                 0x1000
 415 #define KDATA_BASE_ADDR2                0x1080
 416
 417 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 418 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 419 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 420 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 421 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 422 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 423 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 424 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 425 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 426
 427 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 428 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 429
 430 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 431 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 432 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 433 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 434 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 435 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 436 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 437 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 438 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 439 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 440
 441 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 442 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 443
 444 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 445 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 446
 447 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 448 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 449
 450 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 451 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 452 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 453
 454 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 455 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 456 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 457 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 458 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 459
 460 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 461 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 462 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 463
 464 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 465 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 466 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 467
 468 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 469 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 470 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 471 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 472 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 473 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 474 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 475 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 476 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 477 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 478
 479 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 480 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 481 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 482
 483 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 484 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 485
 486 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 487 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 488 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 489
 490 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 491 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 492 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 493 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 494 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 495 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 496
 497 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 498 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 499 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 500 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 501 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 502 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 503
 504 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 505 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 506 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 507 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 508 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 509 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 510
 511 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 512 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 513 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 514 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 515
 516 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 517 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 518
 519 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 520 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 521
 522 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 523 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 524 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 525 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 526 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 527
 528 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 529 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 530
 531 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 532 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 533 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 534
 535 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 536 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 537
 538 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 539
 540 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 541 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 542 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 543 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 544 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 545 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 546 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 547 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 548 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 549 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 550 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 551 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 552
 553 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 554 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 555 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 556 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 557
 558 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 559 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 560
 561 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 562 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 563 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 564 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 565
 566 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 567 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 568 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 569 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 570 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 571
 572 /*
 573  * second 'segment' (?) reserved for mixer
 574  * buffers..
 575  */
 576
 577 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 578 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 579 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 580 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 581 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 582 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 583 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 584 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 585 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 586 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 587 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 588 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 589 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 590 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 591 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 592 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 593
 594 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 595 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 596 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 597 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 598 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 599 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 600 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 601 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 602 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 603 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 604 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 605
 606 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 607 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 608 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 609 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 610 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 611 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 612
 613 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 614 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 615 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 616 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 617
 618 /*
 619  * client data area offsets
 620  */
 621 #define CDATA_INSTANCE_READY            0x00
 622
 623 #define CDATA_HOST_SRC_ADDRL            0x01
 624 #define CDATA_HOST_SRC_ADDRH            0x02
 625 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 626 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 627 #define CDATA_HOST_SRC_CURRENTL         0x05
 628 #define CDATA_HOST_SRC_CURRENTH         0x06
 629
 630 #define CDATA_IN_BUF_CONNECT            0x07
 631 #define CDATA_OUT_BUF_CONNECT           0x08
 632
 633 #define CDATA_IN_BUF_BEGIN              0x09
 634 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 635 #define CDATA_IN_BUF_HEAD               0x0B
 636 #define CDATA_IN_BUF_TAIL               0x0C
 637 #define CDATA_OUT_BUF_BEGIN             0x0D
 638 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 639 #define CDATA_OUT_BUF_HEAD              0x0F
 640 #define CDATA_OUT_BUF_TAIL              0x10
 641
 642 #define CDATA_DMA_CONTROL               0x11
 643 #define CDATA_RESERVED                  0x12
 644
 645 #define CDATA_FREQUENCY                 0x13
 646 #define CDATA_LEFT_VOLUME               0x14
 647 #define CDATA_RIGHT_VOLUME              0x15
 648 #define CDATA_LEFT_SUR_VOL              0x16
 649 #define CDATA_RIGHT_SUR_VOL             0x17
 650
 651 #define CDATA_HEADER_LEN                0x18
 652
 653 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 654 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 655 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 656 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 657 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 658 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 659 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 660 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 661
 662 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 663 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 664 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 665 #define MINISRC_BIQUAD_STAGE    2
 666 #define MINISRC_COEF_LOC          0x175
 667
 668 #define DMACONTROL_BLOCK_MASK           0x000F
 669 #define  DMAC_BLOCK0_SELECTOR           0x0000
 670 #define  DMAC_BLOCK1_SELECTOR           0x0001
 671 #define  DMAC_BLOCK2_SELECTOR           0x0002
 672 #define  DMAC_BLOCK3_SELECTOR           0x0003
 673 #define  DMAC_BLOCK4_SELECTOR           0x0004
 674 #define  DMAC_BLOCK5_SELECTOR           0x0005
 675 #define  DMAC_BLOCK6_SELECTOR           0x0006
 676 #define  DMAC_BLOCK7_SELECTOR           0x0007
 677 #define  DMAC_BLOCK8_SELECTOR           0x0008
 678 #define  DMAC_BLOCK9_SELECTOR           0x0009
 679 #define  DMAC_BLOCKA_SELECTOR           0x000A
 680 #define  DMAC_BLOCKB_SELECTOR           0x000B
 681 #define  DMAC_BLOCKC_SELECTOR           0x000C
 682 #define  DMAC_BLOCKD_SELECTOR           0x000D
 683 #define  DMAC_BLOCKE_SELECTOR           0x000E
 684 #define  DMAC_BLOCKF_SELECTOR           0x000F
 685 #define DMACONTROL_PAGE_MASK            0x00F0
 686 #define  DMAC_PAGE0_SELECTOR            0x0030
 687 #define  DMAC_PAGE1_SELECTOR            0x0020
 688 #define  DMAC_PAGE2_SELECTOR            0x0010
 689 #define  DMAC_PAGE3_SELECTOR            0x0000
 690 #define DMACONTROL_AUTOREPEAT           0x1000
 691 #define DMACONTROL_STOPPED              0x2000
 692 #define DMACONTROL_DIRECTION            0x0100
 693
 694 /*
 695  * an arbitrary volume we set the internal
 696  * volume settings to so that the ac97 volume
 697  * range is a little less insane.  0x7fff is
 698  * max.
 699  */
 700 #define ARB_VOLUME ( 0x6800 )
 701
 702 /*
 703  */
 704
 705 struct m3_list {
 706         int curlen;
 707         int mem_addr;
 708         int max;
 709 };
 710
 711 struct m3_dma {
 712
 713         int number;
 714         struct snd_pcm_substream *substream;
 715
 716         struct assp_instance {
 717                 unsigned short code, data;
 718         } inst;
 719
 720         int running;
 721         int opened;
 722
 723         unsigned long buffer_addr;
 724         int dma_size;
 725         int period_size;
 726         unsigned int hwptr;
 727         int count;
 728
 729         int index[3];
 730         struct m3_list *index_list[3];
 731
 732         int in_lists;
 733
 734         struct list_head list;
 735
 736 };
 737
 738 struct snd_m3 {
 739
 740         struct snd_card *card;
 741
 742         unsigned long iobase;
 743
 744         int irq;
 745         unsigned int allegro_flag : 1;
 746
 747         struct snd_ac97 *ac97;
 748
 749         struct snd_pcm *pcm;
 750
 751         struct pci_dev *pci;
 752
 753         int dacs_active;
 754         int timer_users;
 755
 756         struct m3_list  msrc_list;
 757         struct m3_list  mixer_list;
 758         struct m3_list  adc1_list;
 759         struct m3_list  dma_list;
 760
 761         /* for storing reset state..*/
 762         u8 reset_state;
 763
 764         int external_amp;
 765         int amp_gpio;   /* gpio pin #  for external amp, -1 = default */
 766         unsigned int hv_config;         /* hardware-volume config bits */
 767         unsigned irda_workaround :1;    /* avoid to touch 0x10 on GPIO_DIRECTION
 768                                            (e.g. for IrDA on Dell Inspirons) */
 769         unsigned is_omnibook :1;        /* Do HP OmniBook GPIO magic? */
 770
 771         /* midi */
 772         struct snd_rawmidi *rmidi;
 773
 774         /* pcm streams */
 775         int num_substreams;
 776         struct m3_dma *substreams;
 777
 778         spinlock_t reg_lock;
 779
 780 #ifdef CONFIG_SND_MAESTRO3_INPUT
 781         struct input_dev *input_dev;
 782         char phys[64];                  /* physical device path */
 783 #else
 784         struct snd_kcontrol *master_switch;
 785         struct snd_kcontrol *master_volume;
 786 #endif
 787         struct work_struct hwvol_work;
 788
 789         unsigned int in_suspend;
 790
 791 #ifdef CONFIG_PM_SLEEP
 792         u16 *suspend_mem;
 793 #endif
 794
 795         const struct firmware *assp_kernel_image;
 796         const struct firmware *assp_minisrc_image;
 797 };
 798
 799 /*
 800  * pci ids
 801  */
 802 static const struct pci_device_id snd_m3_ids[] = {
 803         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 804          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 805         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 806          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 807         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 808          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 809         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 810          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 811         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 812          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 813         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 814          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 815         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 816          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 817         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 818          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 819         {0,},
 820 };
 821
 822 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 823
 824 static struct snd_pci_quirk m3_amp_quirk_list[] = {
 825         SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
 826         SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
 827         SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
 828         SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
 829         SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
 830         { } /* END */
 831 };
 832
 833 static struct snd_pci_quirk m3_irda_quirk_list[] = {
 834         SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
 835         SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
 836         SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
 837         { } /* END */
 838 };
 839
 840 /* hardware volume quirks */
 841 static struct snd_pci_quirk m3_hv_quirk_list[] = {
 842         /* Allegro chips */
 843         SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 844         SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 845         SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 846         SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 847         SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 848         SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 849         SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 850         SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 851         SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 852         SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 853         SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 854         SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 855         SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 856         SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 857         SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 858         SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 859         SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 860         SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 861         SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 862         SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 863         SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 864         SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 865         SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 866         SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 867         SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 868         SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
 869                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 870         SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
 871                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 872         SND_PCI_QUIRK(0x107B, 0x340A, NULL,
 873                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 874         SND_PCI_QUIRK(0x107B, 0x3450, NULL,
 875                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 876         SND_PCI_QUIRK(0x109F, 0x3134, NULL,
 877                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 878         SND_PCI_QUIRK(0x109F, 0x3161, NULL,
 879                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 880         SND_PCI_QUIRK(0x144D, 0x3280, NULL,
 881                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 882         SND_PCI_QUIRK(0x144D, 0x3281, NULL,
 883                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 884         SND_PCI_QUIRK(0x144D, 0xC002, NULL,
 885                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 886         SND_PCI_QUIRK(0x144D, 0xC003, NULL,
 887                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 888         SND_PCI_QUIRK(0x1509, 0x1740, NULL,
 889                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 890         SND_PCI_QUIRK(0x1610, 0x0010, NULL,
 891                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 892         SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
 893         SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
 894         SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
 895         SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
 896         SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
 897         /* Maestro3 chips */
 898         SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
 899         SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
 900         SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
 901         SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
 902         SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
 903         SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
 904         SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
 905         SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
 906         SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
 907         SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
 908         SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
 909         SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
 910         SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
 911         SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 912         SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 913         SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 914         SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 915         { } /* END */
 916 };
 917
 918 /* HP Omnibook quirks */
 919 static struct snd_pci_quirk m3_omnibook_quirk_list[] = {
 920         SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
 921         SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
 922         { } /* END */
 923 };
 924
 925 /*
 926  * lowlevel functions
 927  */
 928
 929 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
 930 {
 931         outw(value, chip->iobase + reg);
 932 }
 933
 934 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
 935 {
 936         return inw(chip->iobase + reg);
 937 }
 938
 939 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
 940 {
 941         outb(value, chip->iobase + reg);
 942 }
 943
 944 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
 945 {
 946         return inb(chip->iobase + reg);
 947 }
 948
 949 /*
 950  * access 16bit words to the code or data regions of the dsp's memory.
 951  * index addresses 16bit words.
 952  */
 953 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
 954 {
 955         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
 956         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
 957         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
 958 }
 959
 960 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
 961 {
 962         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
 963         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
 964         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
 965 }
 966
 967 static void snd_m3_assp_halt(struct snd_m3 *chip)
 968 {
 969         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
 970         msleep(10);
 971         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 972 }
 973
 974 static void snd_m3_assp_continue(struct snd_m3 *chip)
 975 {
 976         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 977 }
 978
 979
 980 /*
 981  * This makes me sad. the maestro3 has lists
 982  * internally that must be packed.. 0 terminates,
 983  * apparently, or maybe all unused entries have
 984  * to be 0, the lists have static lengths set
 985  * by the binary code images.
 986  */
 987
 988 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
 989 {
 990         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 991                           list->mem_addr + list->curlen,
 992                           val);
 993         return list->curlen++;
 994 }
 995
 996 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
 997 {
 998         u16  val;
 999         int lastindex = list->curlen - 1;
1000
1001         if (index != lastindex) {
1002                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1003                                        list->mem_addr + lastindex);
1004                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1005                                   list->mem_addr + index,
1006                                   val);
1007         }
1008
1009         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1010                           list->mem_addr + lastindex,
1011                           0);
1012
1013         list->curlen--;
1014 }
1015
1016 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1017 {
1018         chip->timer_users++;
1019         if (chip->timer_users != 1)
1020                 return;
1021
1022         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1023                           KDATA_TIMER_COUNT_RELOAD,
1024                           240);
1025
1026         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1027                           KDATA_TIMER_COUNT_CURRENT,
1028                           240);
1029
1030         snd_m3_outw(chip,
1031                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1032                     HOST_INT_CTRL);
1033 }
1034
1035 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1036 {
1037         chip->timer_users--;
1038         if (chip->timer_users > 0)
1039                 return;
1040
1041         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1042                           KDATA_TIMER_COUNT_RELOAD,
1043                           0);
1044
1045         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1046                           KDATA_TIMER_COUNT_CURRENT,
1047                           0);
1048
1049         snd_m3_outw(chip,
1050                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1051                     HOST_INT_CTRL);
1052 }
1053
1054 /*
1055  * start/stop
1056  */
1057
1058 /* spinlock held! */
1059 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1060                             struct snd_pcm_substream *subs)
1061 {
1062         if (! s || ! subs)
1063                 return -EINVAL;
1064
1065         snd_m3_inc_timer_users(chip);
1066         switch (subs->stream) {
1067         case SNDRV_PCM_STREAM_PLAYBACK:
1068                 chip->dacs_active++;
1069                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1070                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1071                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1072                                   KDATA_MIXER_TASK_NUMBER,
1073                                   chip->dacs_active);
1074                 break;
1075         case SNDRV_PCM_STREAM_CAPTURE:
1076                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1077                                   KDATA_ADC1_REQUEST, 1);
1078                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1079                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1080                 break;
1081         }
1082         return 0;
1083 }
1084
1085 /* spinlock held! */
1086 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1087                            struct snd_pcm_substream *subs)
1088 {
1089         if (! s || ! subs)
1090                 return -EINVAL;
1091
1092         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1093                           s->inst.data + CDATA_INSTANCE_READY, 0);
1094         snd_m3_dec_timer_users(chip);
1095         switch (subs->stream) {
1096         case SNDRV_PCM_STREAM_PLAYBACK:
1097                 chip->dacs_active--;
1098                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1099                                   KDATA_MIXER_TASK_NUMBER,
1100                                   chip->dacs_active);
1101                 break;
1102         case SNDRV_PCM_STREAM_CAPTURE:
1103                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1104                                   KDATA_ADC1_REQUEST, 0);
1105                 break;
1106         }
1107         return 0;
1108 }
1109
1110 static int
1111 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1112 {
1113         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1114         struct m3_dma *s = subs->runtime->private_data;
1115         int err = -EINVAL;
1116
1117         if (snd_BUG_ON(!s))
1118                 return -ENXIO;
1119
1120         spin_lock(&chip->reg_lock);
1121         switch (cmd) {
1122         case SNDRV_PCM_TRIGGER_START:
1123         case SNDRV_PCM_TRIGGER_RESUME:
1124                 if (s->running)
1125                         err = -EBUSY;
1126                 else {
1127                         s->running = 1;
1128                         err = snd_m3_pcm_start(chip, s, subs);
1129                 }
1130                 break;
1131         case SNDRV_PCM_TRIGGER_STOP:
1132         case SNDRV_PCM_TRIGGER_SUSPEND:
1133                 if (! s->running)
1134                         err = 0; /* should return error? */
1135                 else {
1136                         s->running = 0;
1137                         err = snd_m3_pcm_stop(chip, s, subs);
1138                 }
1139                 break;
1140         }
1141         spin_unlock(&chip->reg_lock);
1142         return err;
1143 }
1144
1145 /*
1146  * setup
1147  */
1148 static void
1149 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1150 {
1151         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1152         struct snd_pcm_runtime *runtime = subs->runtime;
1153
1154         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1155                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1156                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1157         } else {
1158                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1159                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1160         }
1161         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1162         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1163
1164         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1165         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1166         s->hwptr = 0;
1167         s->count = 0;
1168
1169 #define LO(x) ((x) & 0xffff)
1170 #define HI(x) LO((x) >> 16)
1171
1172         /* host dma buffer pointers */
1173         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1174                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1175                           LO(s->buffer_addr));
1176
1177         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1178                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1179                           HI(s->buffer_addr));
1180
1181         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1182                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1183                           LO(s->buffer_addr + s->dma_size));
1184
1185         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1186                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1187                           HI(s->buffer_addr + s->dma_size));
1188
1189         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1190                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1191                           LO(s->buffer_addr));
1192
1193         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1194                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1195                           HI(s->buffer_addr));
1196 #undef LO
1197 #undef HI
1198
1199         /* dsp buffers */
1200
1201         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1202                           s->inst.data + CDATA_IN_BUF_BEGIN,
1203                           dsp_in_buffer);
1204
1205         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1206                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1207                           dsp_in_buffer + (dsp_in_size / 2));
1208
1209         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1210                           s->inst.data + CDATA_IN_BUF_HEAD,
1211                           dsp_in_buffer);
1212
1213         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1214                           s->inst.data + CDATA_IN_BUF_TAIL,
1215                           dsp_in_buffer);
1216
1217         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1218                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1219                           dsp_out_buffer);
1220
1221         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1222                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1223                           dsp_out_buffer + (dsp_out_size / 2));
1224
1225         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1226                           s->inst.data + CDATA_OUT_BUF_HEAD,
1227                           dsp_out_buffer);
1228
1229         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1230                           s->inst.data + CDATA_OUT_BUF_TAIL,
1231                           dsp_out_buffer);
1232 }
1233
1234 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1235                               struct snd_pcm_runtime *runtime)
1236 {
1237         u32 freq;
1238
1239         /*
1240          * put us in the lists if we're not already there
1241          */
1242         if (! s->in_lists) {
1243                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1244                                               s->inst.data >> DP_SHIFT_COUNT);
1245                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1246                                               s->inst.data >> DP_SHIFT_COUNT);
1247                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1248                                               s->inst.data >> DP_SHIFT_COUNT);
1249                 s->in_lists = 1;
1250         }
1251
1252         /* write to 'mono' word */
1253         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1254                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1255                           runtime->channels == 2 ? 0 : 1);
1256         /* write to '8bit' word */
1257         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1258                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1259                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1260
1261         /* set up dac/adc rate */
1262         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1263         if (freq)
1264                 freq--;
1265
1266         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1267                           s->inst.data + CDATA_FREQUENCY,
1268                           freq);
1269 }
1270
1271
1272 static const struct play_vals {
1273         u16 addr, val;
1274 } pv[] = {
1275         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1276         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1277         {SRC3_DIRECTION_OFFSET, 0} ,
1278         /* +1, +2 are stereo/16 bit */
1279         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1280         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1281         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1282         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1283         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1284         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1285         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1286         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1287         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1288         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1289         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1290         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1291         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1292         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1293         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1294         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1295         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1296 };
1297
1298
1299 /* the mode passed should be already shifted and masked */
1300 static void
1301 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1302                       struct snd_pcm_substream *subs)
1303 {
1304         unsigned int i;
1305
1306         /*
1307          * some per client initializers
1308          */
1309
1310         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1311                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1312                           s->inst.data + 40 + 8);
1313
1314         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1315                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1316                           s->inst.code + MINISRC_COEF_LOC);
1317
1318         /* enable or disable low pass filter? */
1319         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1320                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1321                           subs->runtime->rate > 45000 ? 0xff : 0);
1322
1323         /* tell it which way dma is going? */
1324         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1325                           s->inst.data + CDATA_DMA_CONTROL,
1326                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1327
1328         /*
1329          * set an armload of static initializers
1330          */
1331         for (i = 0; i < ARRAY_SIZE(pv); i++)
1332                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1333                                   s->inst.data + pv[i].addr, pv[i].val);
1334 }
1335
1336 /*
1337  *    Native record driver
1338  */
1339 static const struct rec_vals {
1340         u16 addr, val;
1341 } rv[] = {
1342         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1343         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1344         {SRC3_DIRECTION_OFFSET, 1} ,
1345         /* +1, +2 are stereo/16 bit */
1346         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1347         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1348         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1349         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1350         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1351         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1352         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1353         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1354         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1355         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1356         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1357         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1358         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1359         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1360         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1361         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1362         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1363         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1364         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1365 };
1366
1367 static void
1368 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1369 {
1370         unsigned int i;
1371
1372         /*
1373          * some per client initializers
1374          */
1375
1376         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1377                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1378                           s->inst.data + 40 + 8);
1379
1380         /* tell it which way dma is going? */
1381         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1382                           s->inst.data + CDATA_DMA_CONTROL,
1383                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1384                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1385
1386         /*
1387          * set an armload of static initializers
1388          */
1389         for (i = 0; i < ARRAY_SIZE(rv); i++)
1390                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1391                                   s->inst.data + rv[i].addr, rv[i].val);
1392 }
1393
1394 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1395                                 struct snd_pcm_hw_params *hw_params)
1396 {
1397         struct m3_dma *s = substream->runtime->private_data;
1398         int err;
1399
1400         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1401                 return err;
1402         /* set buffer address */
1403         s->buffer_addr = substream->runtime->dma_addr;
1404         if (s->buffer_addr & 0x3) {
1405                 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1406                 s->buffer_addr = s->buffer_addr & ~0x3;
1407         }
1408         return 0;
1409 }
1410
1411 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1412 {
1413         struct m3_dma *s;
1414
1415         if (substream->runtime->private_data == NULL)
1416                 return 0;
1417         s = substream->runtime->private_data;
1418         snd_pcm_lib_free_pages(substream);
1419         s->buffer_addr = 0;
1420         return 0;
1421 }
1422
1423 static int
1424 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1425 {
1426         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1427         struct snd_pcm_runtime *runtime = subs->runtime;
1428         struct m3_dma *s = runtime->private_data;
1429
1430         if (snd_BUG_ON(!s))
1431                 return -ENXIO;
1432
1433         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1434             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1435                 return -EINVAL;
1436         if (runtime->rate > 48000 ||
1437             runtime->rate < 8000)
1438                 return -EINVAL;
1439
1440         spin_lock_irq(&chip->reg_lock);
1441
1442         snd_m3_pcm_setup1(chip, s, subs);
1443
1444         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1445                 snd_m3_playback_setup(chip, s, subs);
1446         else
1447                 snd_m3_capture_setup(chip, s, subs);
1448
1449         snd_m3_pcm_setup2(chip, s, runtime);
1450
1451         spin_unlock_irq(&chip->reg_lock);
1452
1453         return 0;
1454 }
1455
1456 /*
1457  * get current pointer
1458  */
1459 static unsigned int
1460 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1461 {
1462         u16 hi = 0, lo = 0;
1463         int retry = 10;
1464         u32 addr;
1465
1466         /*
1467          * try and get a valid answer
1468          */
1469         while (retry--) {
1470                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1471                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1472
1473                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1474                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1475
1476                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1477                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1478                         break;
1479         }
1480         addr = lo | ((u32)hi<<16);
1481         return (unsigned int)(addr - s->buffer_addr);
1482 }
1483
1484 static snd_pcm_uframes_t
1485 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1486 {
1487         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1488         unsigned int ptr;
1489         struct m3_dma *s = subs->runtime->private_data;
1490
1491         if (snd_BUG_ON(!s))
1492                 return 0;
1493
1494         spin_lock(&chip->reg_lock);
1495         ptr = snd_m3_get_pointer(chip, s, subs);
1496         spin_unlock(&chip->reg_lock);
1497         return bytes_to_frames(subs->runtime, ptr);
1498 }
1499
1500
1501 /* update pointer */
1502 /* spinlock held! */
1503 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1504 {
1505         struct snd_pcm_substream *subs = s->substream;
1506         unsigned int hwptr;
1507         int diff;
1508
1509         if (! s->running)
1510                 return;
1511
1512         hwptr = snd_m3_get_pointer(chip, s, subs);
1513
1514         /* try to avoid expensive modulo divisions */
1515         if (hwptr >= s->dma_size)
1516                 hwptr %= s->dma_size;
1517
1518         diff = s->dma_size + hwptr - s->hwptr;
1519         if (diff >= s->dma_size)
1520                 diff %= s->dma_size;
1521
1522         s->hwptr = hwptr;
1523         s->count += diff;
1524
1525         if (s->count >= (signed)s->period_size) {
1526
1527                 if (s->count < 2 * (signed)s->period_size)
1528                         s->count -= (signed)s->period_size;
1529                 else
1530                         s->count %= s->period_size;
1531
1532                 spin_unlock(&chip->reg_lock);
1533                 snd_pcm_period_elapsed(subs);
1534                 spin_lock(&chip->reg_lock);
1535         }
1536 }
1537
1538 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1539    (without wrap around) in response to volume button presses and then
1540    generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1541    of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1542 static void snd_m3_update_hw_volume(struct work_struct *work)
1543 {
1544         struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1545         int x, val;
1546
1547         /* Figure out which volume control button was pushed,
1548            based on differences from the default register
1549            values. */
1550         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1551
1552         /* Reset the volume counters to 4. Tests on the allegro integrated
1553            into a Compaq N600C laptop, have revealed that:
1554            1) Writing any value will result in the 2 counters being reset to
1555               4 so writing 0x88 is not strictly necessary
1556            2) Writing to any of the 4 involved registers will reset all 4
1557               of them (and reading them always returns the same value for all
1558               of them)
1559            It could be that a maestro deviates from this, so leave the code
1560            as is. */
1561         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1562         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1563         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1564         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1565
1566         /* Ignore spurious HV interrupts during suspend / resume, this avoids
1567            mistaking them for a mute button press. */
1568         if (chip->in_suspend)
1569                 return;
1570
1571 #ifndef CONFIG_SND_MAESTRO3_INPUT
1572         if (!chip->master_switch || !chip->master_volume)
1573                 return;
1574
1575         val = snd_ac97_read(chip->ac97, AC97_MASTER);
1576         switch (x) {
1577         case 0x88:
1578                 /* The counters have not changed, yet we've received a HV
1579                    interrupt. According to tests run by various people this
1580                    happens when pressing the mute button. */
1581                 val ^= 0x8000;
1582                 break;
1583         case 0xaa:
1584                 /* counters increased by 1 -> volume up */
1585                 if ((val & 0x7f) > 0)
1586                         val--;
1587                 if ((val & 0x7f00) > 0)
1588                         val -= 0x0100;
1589                 break;
1590         case 0x66:
1591                 /* counters decreased by 1 -> volume down */
1592                 if ((val & 0x7f) < 0x1f)
1593                         val++;
1594                 if ((val & 0x7f00) < 0x1f00)
1595                         val += 0x0100;
1596                 break;
1597         }
1598         if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1599                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1600                                &chip->master_switch->id);
1601 #else
1602         if (!chip->input_dev)
1603                 return;
1604
1605         val = 0;
1606         switch (x) {
1607         case 0x88:
1608                 /* The counters have not changed, yet we've received a HV
1609                    interrupt. According to tests run by various people this
1610                    happens when pressing the mute button. */
1611                 val = KEY_MUTE;
1612                 break;
1613         case 0xaa:
1614                 /* counters increased by 1 -> volume up */
1615                 val = KEY_VOLUMEUP;
1616                 break;
1617         case 0x66:
1618                 /* counters decreased by 1 -> volume down */
1619                 val = KEY_VOLUMEDOWN;
1620                 break;
1621         }
1622
1623         if (val) {
1624                 input_report_key(chip->input_dev, val, 1);
1625                 input_sync(chip->input_dev);
1626                 input_report_key(chip->input_dev, val, 0);
1627                 input_sync(chip->input_dev);
1628         }
1629 #endif
1630 }
1631
1632 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1633 {
1634         struct snd_m3 *chip = dev_id;
1635         u8 status;
1636         int i;
1637
1638         status = inb(chip->iobase + HOST_INT_STATUS);
1639
1640         if (status == 0xff)
1641                 return IRQ_NONE;
1642
1643         if (status & HV_INT_PENDING)
1644                 schedule_work(&chip->hwvol_work);
1645
1646         /*
1647          * ack an assp int if its running
1648          * and has an int pending
1649          */
1650         if (status & ASSP_INT_PENDING) {
1651                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1652                 if (!(ctl & STOP_ASSP_CLOCK)) {
1653                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1654                         if (ctl & DSP2HOST_REQ_TIMER) {
1655                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1656                                 /* update adc/dac info if it was a timer int */
1657                                 spin_lock(&chip->reg_lock);
1658                                 for (i = 0; i < chip->num_substreams; i++) {
1659                                         struct m3_dma *s = &chip->substreams[i];
1660                                         if (s->running)
1661                                                 snd_m3_update_ptr(chip, s);
1662                                 }
1663                                 spin_unlock(&chip->reg_lock);
1664                         }
1665                 }
1666         }
1667
1668 #if 0 /* TODO: not supported yet */
1669         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1670                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1671 #endif
1672
1673         /* ack ints */
1674         outb(status, chip->iobase + HOST_INT_STATUS);
1675
1676         return IRQ_HANDLED;
1677 }
1678
1679
1680 /*
1681  */
1682
1683 static struct snd_pcm_hardware snd_m3_playback =
1684 {
1685         .info =                 (SNDRV_PCM_INFO_MMAP |
1686                                  SNDRV_PCM_INFO_INTERLEAVED |
1687                                  SNDRV_PCM_INFO_MMAP_VALID |
1688                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1689                                  /*SNDRV_PCM_INFO_PAUSE |*/
1690                                  SNDRV_PCM_INFO_RESUME),
1691         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1692         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1693         .rate_min =             8000,
1694         .rate_max =             48000,
1695         .channels_min =         1,
1696         .channels_max =         2,
1697         .buffer_bytes_max =     (512*1024),
1698         .period_bytes_min =     64,
1699         .period_bytes_max =     (512*1024),
1700         .periods_min =          1,
1701         .periods_max =          1024,
1702 };
1703
1704 static struct snd_pcm_hardware snd_m3_capture =
1705 {
1706         .info =                 (SNDRV_PCM_INFO_MMAP |
1707                                  SNDRV_PCM_INFO_INTERLEAVED |
1708                                  SNDRV_PCM_INFO_MMAP_VALID |
1709                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1710                                  /*SNDRV_PCM_INFO_PAUSE |*/
1711                                  SNDRV_PCM_INFO_RESUME),
1712         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1713         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1714         .rate_min =             8000,
1715         .rate_max =             48000,
1716         .channels_min =         1,
1717         .channels_max =         2,
1718         .buffer_bytes_max =     (512*1024),
1719         .period_bytes_min =     64,
1720         .period_bytes_max =     (512*1024),
1721         .periods_min =          1,
1722         .periods_max =          1024,
1723 };
1724
1725
1726 /*
1727  */
1728
1729 static int
1730 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1731 {
1732         int i;
1733         struct m3_dma *s;
1734
1735         spin_lock_irq(&chip->reg_lock);
1736         for (i = 0; i < chip->num_substreams; i++) {
1737                 s = &chip->substreams[i];
1738                 if (! s->opened)
1739                         goto __found;
1740         }
1741         spin_unlock_irq(&chip->reg_lock);
1742         return -ENOMEM;
1743 __found:
1744         s->opened = 1;
1745         s->running = 0;
1746         spin_unlock_irq(&chip->reg_lock);
1747
1748         subs->runtime->private_data = s;
1749         s->substream = subs;
1750
1751         /* set list owners */
1752         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1753                 s->index_list[0] = &chip->mixer_list;
1754         } else
1755                 s->index_list[0] = &chip->adc1_list;
1756         s->index_list[1] = &chip->msrc_list;
1757         s->index_list[2] = &chip->dma_list;
1758
1759         return 0;
1760 }
1761
1762 static void
1763 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1764 {
1765         struct m3_dma *s = subs->runtime->private_data;
1766
1767         if (s == NULL)
1768                 return; /* not opened properly */
1769
1770         spin_lock_irq(&chip->reg_lock);
1771         if (s->substream && s->running)
1772                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1773         if (s->in_lists) {
1774                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1775                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1776                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1777                 s->in_lists = 0;
1778         }
1779         s->running = 0;
1780         s->opened = 0;
1781         spin_unlock_irq(&chip->reg_lock);
1782 }
1783
1784 static int
1785 snd_m3_playback_open(struct snd_pcm_substream *subs)
1786 {
1787         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1788         struct snd_pcm_runtime *runtime = subs->runtime;
1789         int err;
1790
1791         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1792                 return err;
1793
1794         runtime->hw = snd_m3_playback;
1795
1796         return 0;
1797 }
1798
1799 static int
1800 snd_m3_playback_close(struct snd_pcm_substream *subs)
1801 {
1802         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1803
1804         snd_m3_substream_close(chip, subs);
1805         return 0;
1806 }
1807
1808 static int
1809 snd_m3_capture_open(struct snd_pcm_substream *subs)
1810 {
1811         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1812         struct snd_pcm_runtime *runtime = subs->runtime;
1813         int err;
1814
1815         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1816                 return err;
1817
1818         runtime->hw = snd_m3_capture;
1819
1820         return 0;
1821 }
1822
1823 static int
1824 snd_m3_capture_close(struct snd_pcm_substream *subs)
1825 {
1826         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1827
1828         snd_m3_substream_close(chip, subs);
1829         return 0;
1830 }
1831
1832 /*
1833  * create pcm instance
1834  */
1835
1836 static const struct snd_pcm_ops snd_m3_playback_ops = {
1837         .open =         snd_m3_playback_open,
1838         .close =        snd_m3_playback_close,
1839         .ioctl =        snd_pcm_lib_ioctl,
1840         .hw_params =    snd_m3_pcm_hw_params,
1841         .hw_free =      snd_m3_pcm_hw_free,
1842         .prepare =      snd_m3_pcm_prepare,
1843         .trigger =      snd_m3_pcm_trigger,
1844         .pointer =      snd_m3_pcm_pointer,
1845 };
1846
1847 static const struct snd_pcm_ops snd_m3_capture_ops = {
1848         .open =         snd_m3_capture_open,
1849         .close =        snd_m3_capture_close,
1850         .ioctl =        snd_pcm_lib_ioctl,
1851         .hw_params =    snd_m3_pcm_hw_params,
1852         .hw_free =      snd_m3_pcm_hw_free,
1853         .prepare =      snd_m3_pcm_prepare,
1854         .trigger =      snd_m3_pcm_trigger,
1855         .pointer =      snd_m3_pcm_pointer,
1856 };
1857
1858 static int
1859 snd_m3_pcm(struct snd_m3 * chip, int device)
1860 {
1861         struct snd_pcm *pcm;
1862         int err;
1863
1864         err = snd_pcm_new(chip->card, chip->card->driver, device,
1865                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1866         if (err < 0)
1867                 return err;
1868
1869         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1870         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1871
1872         pcm->private_data = chip;
1873         pcm->info_flags = 0;
1874         strcpy(pcm->name, chip->card->driver);
1875         chip->pcm = pcm;
1876
1877         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1878                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1879
1880         return 0;
1881 }
1882
1883
1884 /*
1885  * ac97 interface
1886  */
1887
1888 /*
1889  * Wait for the ac97 serial bus to be free.
1890  * return nonzero if the bus is still busy.
1891  */
1892 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1893 {
1894         int i = 10000;
1895
1896         do {
1897                 if (! (snd_m3_inb(chip, 0x30) & 1))
1898                         return 0;
1899                 cpu_relax();
1900         } while (i-- > 0);
1901
1902         dev_err(chip->card->dev, "ac97 serial bus busy\n");
1903         return 1;
1904 }
1905
1906 static unsigned short
1907 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1908 {
1909         struct snd_m3 *chip = ac97->private_data;
1910         unsigned short data = 0xffff;
1911
1912         if (snd_m3_ac97_wait(chip))
1913                 goto fail;
1914         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1915         if (snd_m3_ac97_wait(chip))
1916                 goto fail;
1917         data = snd_m3_inw(chip, CODEC_DATA);
1918 fail:
1919         return data;
1920 }
1921
1922 static void
1923 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1924 {
1925         struct snd_m3 *chip = ac97->private_data;
1926
1927         if (snd_m3_ac97_wait(chip))
1928                 return;
1929         snd_m3_outw(chip, val, CODEC_DATA);
1930         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1931         /*
1932          * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1933          * until the MASTER volume or mute is touched (alsactl restore does not
1934          * work).
1935          */
1936         if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1937                 snd_m3_ac97_wait(chip);
1938                 snd_m3_outw(chip, val, CODEC_DATA);
1939                 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1940         }
1941 }
1942
1943
1944 static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1945 {
1946         int io = chip->iobase;
1947         u16 tmp;
1948
1949         isremote = isremote ? 1 : 0;
1950
1951         tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1952         /* enable dock on Dell Latitude C810 */
1953         if (chip->pci->subsystem_vendor == 0x1028 &&
1954             chip->pci->subsystem_device == 0x00e5)
1955                 tmp |= M3I_DOCK_ENABLE;
1956         outw(tmp | isremote, io + RING_BUS_CTRL_B);
1957         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1958              io + SDO_OUT_DEST_CTRL);
1959         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1960              io + SDO_IN_DEST_CTRL);
1961 }
1962
1963 /*
1964  * hack, returns non zero on err
1965  */
1966 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1967 {
1968         u16 ret;
1969
1970         if (snd_m3_ac97_wait(chip))
1971                 return 1;
1972
1973         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1974
1975         if (snd_m3_ac97_wait(chip))
1976                 return 1;
1977
1978         ret = snd_m3_inw(chip, 0x32);
1979
1980         return (ret == 0) || (ret == 0xffff);
1981 }
1982
1983 static void snd_m3_ac97_reset(struct snd_m3 *chip)
1984 {
1985         u16 dir;
1986         int delay1 = 0, delay2 = 0, i;
1987         int io = chip->iobase;
1988
1989         if (chip->allegro_flag) {
1990                 /*
1991                  * the onboard codec on the allegro seems
1992                  * to want to wait a very long time before
1993                  * coming back to life
1994                  */
1995                 delay1 = 50;
1996                 delay2 = 800;
1997         } else {
1998                 /* maestro3 */
1999                 delay1 = 20;
2000                 delay2 = 500;
2001         }
2002
2003         for (i = 0; i < 5; i++) {
2004                 dir = inw(io + GPIO_DIRECTION);
2005                 if (!chip->irda_workaround)
2006                         dir |= 0x10; /* assuming pci bus master? */
2007
2008                 snd_m3_remote_codec_config(chip, 0);
2009
2010                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2011                 udelay(20);
2012
2013                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2014                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2015                 outw(0, io + GPIO_DATA);
2016                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2017
2018                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2019
2020                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2021                 udelay(5);
2022                 /* ok, bring back the ac-link */
2023                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2024                 outw(~0, io + GPIO_MASK);
2025
2026                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2027
2028                 if (! snd_m3_try_read_vendor(chip))
2029                         break;
2030
2031                 delay1 += 10;
2032                 delay2 += 100;
2033
2034                 dev_dbg(chip->card->dev,
2035                         "retrying codec reset with delays of %d and %d ms\n",
2036                            delay1, delay2);
2037         }
2038
2039 #if 0
2040         /* more gung-ho reset that doesn't
2041          * seem to work anywhere :)
2042          */
2043         tmp = inw(io + RING_BUS_CTRL_A);
2044         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2045         msleep(20);
2046         outw(tmp, io + RING_BUS_CTRL_A);
2047         msleep(50);
2048 #endif
2049 }
2050
2051 static int snd_m3_mixer(struct snd_m3 *chip)
2052 {
2053         struct snd_ac97_bus *pbus;
2054         struct snd_ac97_template ac97;
2055 #ifndef CONFIG_SND_MAESTRO3_INPUT
2056         struct snd_ctl_elem_id elem_id;
2057 #endif
2058         int err;
2059         static struct snd_ac97_bus_ops ops = {
2060                 .write = snd_m3_ac97_write,
2061                 .read = snd_m3_ac97_read,
2062         };
2063
2064         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2065                 return err;
2066
2067         memset(&ac97, 0, sizeof(ac97));
2068         ac97.private_data = chip;
2069         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2070                 return err;
2071
2072         /* seems ac97 PCM needs initialization.. hack hack.. */
2073         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2074         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2075         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2076
2077 #ifndef CONFIG_SND_MAESTRO3_INPUT
2078         memset(&elem_id, 0, sizeof(elem_id));
2079         elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2080         strcpy(elem_id.name, "Master Playback Switch");
2081         chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2082         memset(&elem_id, 0, sizeof(elem_id));
2083         elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2084         strcpy(elem_id.name, "Master Playback Volume");
2085         chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2086 #endif
2087
2088         return 0;
2089 }
2090
2091
2092 /*
2093  * initialize ASSP
2094  */
2095
2096 #define MINISRC_LPF_LEN 10
2097 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2098         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2099         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2100 };
2101
2102 static void snd_m3_assp_init(struct snd_m3 *chip)
2103 {
2104         unsigned int i;
2105         const u16 *data;
2106
2107         /* zero kernel data */
2108         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2109                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2110                                   KDATA_BASE_ADDR + i, 0);
2111
2112         /* zero mixer data? */
2113         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2114                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2115                                   KDATA_BASE_ADDR2 + i, 0);
2116
2117         /* init dma pointer */
2118         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2119                           KDATA_CURRENT_DMA,
2120                           KDATA_DMA_XFER0);
2121
2122         /* write kernel into code memory.. */
2123         data = (const u16 *)chip->assp_kernel_image->data;
2124         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2125                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2126                                   REV_B_CODE_MEMORY_BEGIN + i,
2127                                   le16_to_cpu(data[i]));
2128         }
2129
2130         /*
2131          * We only have this one client and we know that 0x400
2132          * is free in our kernel's mem map, so lets just
2133          * drop it there.  It seems that the minisrc doesn't
2134          * need vectors, so we won't bother with them..
2135          */
2136         data = (const u16 *)chip->assp_minisrc_image->data;
2137         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2138                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2139                                   0x400 + i, le16_to_cpu(data[i]));
2140         }
2141
2142         /*
2143          * write the coefficients for the low pass filter?
2144          */
2145         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2146                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2147                                   0x400 + MINISRC_COEF_LOC + i,
2148                                   minisrc_lpf[i]);
2149         }
2150
2151         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2152                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2153                           0x8000);
2154
2155         /*
2156          * the minisrc is the only thing on
2157          * our task list..
2158          */
2159         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2160                           KDATA_TASK0,
2161                           0x400);
2162
2163         /*
2164          * init the mixer number..
2165          */
2166
2167         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2168                           KDATA_MIXER_TASK_NUMBER,0);
2169
2170         /*
2171          * EXTREME KERNEL MASTER VOLUME
2172          */
2173         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2174                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2175         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2176                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2177
2178         chip->mixer_list.curlen = 0;
2179         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2180         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2181         chip->adc1_list.curlen = 0;
2182         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2183         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2184         chip->dma_list.curlen = 0;
2185         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2186         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2187         chip->msrc_list.curlen = 0;
2188         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2189         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2190 }
2191
2192
2193 static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2194 {
2195         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2196                                MINISRC_IN_BUFFER_SIZE / 2 +
2197                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2198         int address, i;
2199
2200         /*
2201          * the revb memory map has 0x1100 through 0x1c00
2202          * free.
2203          */
2204
2205         /*
2206          * align instance address to 256 bytes so that its
2207          * shifted list address is aligned.
2208          * list address = (mem address >> 1) >> 7;
2209          */
2210         data_bytes = ALIGN(data_bytes, 256);
2211         address = 0x1100 + ((data_bytes/2) * index);
2212
2213         if ((address + (data_bytes/2)) >= 0x1c00) {
2214                 dev_err(chip->card->dev,
2215                         "no memory for %d bytes at ind %d (addr 0x%x)\n",
2216                            data_bytes, index, address);
2217                 return -ENOMEM;
2218         }
2219
2220         s->number = index;
2221         s->inst.code = 0x400;
2222         s->inst.data = address;
2223
2224         for (i = data_bytes / 2; i > 0; address++, i--) {
2225                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2226                                   address, 0);
2227         }
2228
2229         return 0;
2230 }
2231
2232
2233 /*
2234  * this works for the reference board, have to find
2235  * out about others
2236  *
2237  * this needs more magic for 4 speaker, but..
2238  */
2239 static void
2240 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2241 {
2242         int io = chip->iobase;
2243         u16 gpo, polarity;
2244
2245         if (! chip->external_amp)
2246                 return;
2247
2248         polarity = enable ? 0 : 1;
2249         polarity = polarity << chip->amp_gpio;
2250         gpo = 1 << chip->amp_gpio;
2251
2252         outw(~gpo, io + GPIO_MASK);
2253
2254         outw(inw(io + GPIO_DIRECTION) | gpo,
2255              io + GPIO_DIRECTION);
2256
2257         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2258              io + GPIO_DATA);
2259
2260         outw(0xffff, io + GPIO_MASK);
2261 }
2262
2263 static void
2264 snd_m3_hv_init(struct snd_m3 *chip)
2265 {
2266         unsigned long io = chip->iobase;
2267         u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2268
2269         if (!chip->is_omnibook)
2270                 return;
2271
2272         /*
2273          * Volume buttons on some HP OmniBook laptops
2274          * require some GPIO magic to work correctly.
2275          */
2276         outw(0xffff, io + GPIO_MASK);
2277         outw(0x0000, io + GPIO_DATA);
2278
2279         outw(~val, io + GPIO_MASK);
2280         outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2281         outw(val, io + GPIO_MASK);
2282
2283         outw(0xffff, io + GPIO_MASK);
2284 }
2285
2286 static int
2287 snd_m3_chip_init(struct snd_m3 *chip)
2288 {
2289         struct pci_dev *pcidev = chip->pci;
2290         unsigned long io = chip->iobase;
2291         u32 n;
2292         u16 w;
2293         u8 t; /* makes as much sense as 'n', no? */
2294
2295         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2296         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2297                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2298                DISABLE_LEGACY);
2299         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2300
2301         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2302         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2303         n |= chip->hv_config;
2304         /* For some reason we must always use reduced debounce. */
2305         n |= REDUCED_DEBOUNCE;
2306         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2307         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2308
2309         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2310         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2311         n &= ~INT_CLK_SELECT;
2312         if (!chip->allegro_flag) {
2313                 n &= ~INT_CLK_MULT_ENABLE;
2314                 n |= INT_CLK_SRC_NOT_PCI;
2315         }
2316         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2317         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2318
2319         if (chip->allegro_flag) {
2320                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2321                 n |= IN_CLK_12MHZ_SELECT;
2322                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2323         }
2324
2325         t = inb(chip->iobase + ASSP_CONTROL_A);
2326         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2327         t |= ASSP_CLK_49MHZ_SELECT;
2328         t |= ASSP_0_WS_ENABLE;
2329         outb(t, chip->iobase + ASSP_CONTROL_A);
2330
2331         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2332         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2333
2334         outb(0x00, io + HARDWARE_VOL_CTRL);
2335         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2336         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2337         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2338         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2339
2340         return 0;
2341 }
2342
2343 static void
2344 snd_m3_enable_ints(struct snd_m3 *chip)
2345 {
2346         unsigned long io = chip->iobase;
2347         unsigned short val;
2348
2349         /* TODO: MPU401 not supported yet */
2350         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2351         if (chip->hv_config & HV_CTRL_ENABLE)
2352                 val |= HV_INT_ENABLE;
2353         outb(val, chip->iobase + HOST_INT_STATUS);
2354         outw(val, io + HOST_INT_CTRL);
2355         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2356              io + ASSP_CONTROL_C);
2357 }
2358
2359
2360 /*
2361  */
2362
2363 static int snd_m3_free(struct snd_m3 *chip)
2364 {
2365         struct m3_dma *s;
2366         int i;
2367
2368         cancel_work_sync(&chip->hwvol_work);
2369 #ifdef CONFIG_SND_MAESTRO3_INPUT
2370         if (chip->input_dev)
2371                 input_unregister_device(chip->input_dev);
2372 #endif
2373
2374         if (chip->substreams) {
2375                 spin_lock_irq(&chip->reg_lock);
2376                 for (i = 0; i < chip->num_substreams; i++) {
2377                         s = &chip->substreams[i];
2378                         /* check surviving pcms; this should not happen though.. */
2379                         if (s->substream && s->running)
2380                                 snd_m3_pcm_stop(chip, s, s->substream);
2381                 }
2382                 spin_unlock_irq(&chip->reg_lock);
2383                 kfree(chip->substreams);
2384         }
2385         if (chip->iobase) {
2386                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2387         }
2388
2389 #ifdef CONFIG_PM_SLEEP
2390         vfree(chip->suspend_mem);
2391 #endif
2392
2393         if (chip->irq >= 0)
2394                 free_irq(chip->irq, chip);
2395
2396         if (chip->iobase)
2397                 pci_release_regions(chip->pci);
2398
2399         release_firmware(chip->assp_kernel_image);
2400         release_firmware(chip->assp_minisrc_image);
2401
2402         pci_disable_device(chip->pci);
2403         kfree(chip);
2404         return 0;
2405 }
2406
2407
2408 /*
2409  * APM support
2410  */
2411 #ifdef CONFIG_PM_SLEEP
2412 static int m3_suspend(struct device *dev)
2413 {
2414         struct snd_card *card = dev_get_drvdata(dev);
2415         struct snd_m3 *chip = card->private_data;
2416         int i, dsp_index;
2417
2418         if (chip->suspend_mem == NULL)
2419                 return 0;
2420
2421         chip->in_suspend = 1;
2422         cancel_work_sync(&chip->hwvol_work);
2423         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2424         snd_pcm_suspend_all(chip->pcm);
2425         snd_ac97_suspend(chip->ac97);
2426
2427         msleep(10); /* give the assp a chance to idle.. */
2428
2429         snd_m3_assp_halt(chip);
2430
2431         /* save dsp image */
2432         dsp_index = 0;
2433         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2434                 chip->suspend_mem[dsp_index++] =
2435                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2436         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2437                 chip->suspend_mem[dsp_index++] =
2438                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2439         return 0;
2440 }
2441
2442 static int m3_resume(struct device *dev)
2443 {
2444         struct snd_card *card = dev_get_drvdata(dev);
2445         struct snd_m3 *chip = card->private_data;
2446         int i, dsp_index;
2447
2448         if (chip->suspend_mem == NULL)
2449                 return 0;
2450
2451         /* first lets just bring everything back. .*/
2452         snd_m3_outw(chip, 0, 0x54);
2453         snd_m3_outw(chip, 0, 0x56);
2454
2455         snd_m3_chip_init(chip);
2456         snd_m3_assp_halt(chip);
2457         snd_m3_ac97_reset(chip);
2458
2459         /* restore dsp image */
2460         dsp_index = 0;
2461         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2462                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2463                                   chip->suspend_mem[dsp_index++]);
2464         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2465                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2466                                   chip->suspend_mem[dsp_index++]);
2467
2468         /* tell the dma engine to restart itself */
2469         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2470                           KDATA_DMA_ACTIVE, 0);
2471
2472         /* restore ac97 registers */
2473         snd_ac97_resume(chip->ac97);
2474
2475         snd_m3_assp_continue(chip);
2476         snd_m3_enable_ints(chip);
2477         snd_m3_amp_enable(chip, 1);
2478
2479         snd_m3_hv_init(chip);
2480
2481         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2482         chip->in_suspend = 0;
2483         return 0;
2484 }
2485
2486 static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2487 #define M3_PM_OPS       &m3_pm
2488 #else
2489 #define M3_PM_OPS       NULL
2490 #endif /* CONFIG_PM_SLEEP */
2491
2492 #ifdef CONFIG_SND_MAESTRO3_INPUT
2493 static int snd_m3_input_register(struct snd_m3 *chip)
2494 {
2495         struct input_dev *input_dev;
2496         int err;
2497
2498         input_dev = input_allocate_device();
2499         if (!input_dev)
2500                 return -ENOMEM;
2501
2502         snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2503                  pci_name(chip->pci));
2504
2505         input_dev->name = chip->card->driver;
2506         input_dev->phys = chip->phys;
2507         input_dev->id.bustype = BUS_PCI;
2508         input_dev->id.vendor  = chip->pci->vendor;
2509         input_dev->id.product = chip->pci->device;
2510         input_dev->dev.parent = &chip->pci->dev;
2511
2512         __set_bit(EV_KEY, input_dev->evbit);
2513         __set_bit(KEY_MUTE, input_dev->keybit);
2514         __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2515         __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2516
2517         err = input_register_device(input_dev);
2518         if (err) {
2519                 input_free_device(input_dev);
2520                 return err;
2521         }
2522
2523         chip->input_dev = input_dev;
2524         return 0;
2525 }
2526 #endif /* CONFIG_INPUT */
2527
2528 /*
2529  */
2530
2531 static int snd_m3_dev_free(struct snd_device *device)
2532 {
2533         struct snd_m3 *chip = device->device_data;
2534         return snd_m3_free(chip);
2535 }
2536
2537 static int
2538 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2539               int enable_amp,
2540               int amp_gpio,
2541               struct snd_m3 **chip_ret)
2542 {
2543         struct snd_m3 *chip;
2544         int i, err;
2545         const struct snd_pci_quirk *quirk;
2546         static struct snd_device_ops ops = {
2547                 .dev_free =     snd_m3_dev_free,
2548         };
2549
2550         *chip_ret = NULL;
2551
2552         if (pci_enable_device(pci))
2553                 return -EIO;
2554
2555         /* check, if we can restrict PCI DMA transfers to 28 bits */
2556         if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2557             dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2558                 dev_err(card->dev,
2559                         "architecture does not support 28bit PCI busmaster DMA\n");
2560                 pci_disable_device(pci);
2561                 return -ENXIO;
2562         }
2563
2564         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2565         if (chip == NULL) {
2566                 pci_disable_device(pci);
2567                 return -ENOMEM;
2568         }
2569
2570         spin_lock_init(&chip->reg_lock);
2571
2572         switch (pci->device) {
2573         case PCI_DEVICE_ID_ESS_ALLEGRO:
2574         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2575         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2576         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2577                 chip->allegro_flag = 1;
2578                 break;
2579         }
2580
2581         chip->card = card;
2582         chip->pci = pci;
2583         chip->irq = -1;
2584         INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2585
2586         chip->external_amp = enable_amp;
2587         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2588                 chip->amp_gpio = amp_gpio;
2589         else {
2590                 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2591                 if (quirk) {
2592                         dev_info(card->dev, "set amp-gpio for '%s'\n",
2593                                  snd_pci_quirk_name(quirk));
2594                         chip->amp_gpio = quirk->value;
2595                 } else if (chip->allegro_flag)
2596                         chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2597                 else /* presumably this is for all 'maestro3's.. */
2598                         chip->amp_gpio = GPO_EXT_AMP_M3;
2599         }
2600
2601         quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2602         if (quirk) {
2603                 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2604                          snd_pci_quirk_name(quirk));
2605                 chip->irda_workaround = 1;
2606         }
2607         quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2608         if (quirk)
2609                 chip->hv_config = quirk->value;
2610         if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2611                 chip->is_omnibook = 1;
2612
2613         chip->num_substreams = NR_DSPS;
2614         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2615                                    GFP_KERNEL);
2616         if (chip->substreams == NULL) {
2617                 kfree(chip);
2618                 pci_disable_device(pci);
2619                 return -ENOMEM;
2620         }
2621
2622         err = reject_firmware(&chip->assp_kernel_image,
2623                                "/*(DEBLOBBED)*/", &pci->dev);
2624         if (err < 0) {
2625                 snd_m3_free(chip);
2626                 return err;
2627         }
2628
2629         err = reject_firmware(&chip->assp_minisrc_image,
2630                                "/*(DEBLOBBED)*/", &pci->dev);
2631         if (err < 0) {
2632                 snd_m3_free(chip);
2633                 return err;
2634         }
2635
2636         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2637                 snd_m3_free(chip);
2638                 return err;
2639         }
2640         chip->iobase = pci_resource_start(pci, 0);
2641
2642         /* just to be sure */
2643         pci_set_master(pci);
2644
2645         snd_m3_chip_init(chip);
2646         snd_m3_assp_halt(chip);
2647
2648         snd_m3_ac97_reset(chip);
2649
2650         snd_m3_amp_enable(chip, 1);
2651
2652         snd_m3_hv_init(chip);
2653
2654         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2655                         KBUILD_MODNAME, chip)) {
2656                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2657                 snd_m3_free(chip);
2658                 return -ENOMEM;
2659         }
2660         chip->irq = pci->irq;
2661
2662 #ifdef CONFIG_PM_SLEEP
2663         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2664         if (chip->suspend_mem == NULL)
2665                 dev_warn(card->dev, "can't allocate apm buffer\n");
2666 #endif
2667
2668         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2669                 snd_m3_free(chip);
2670                 return err;
2671         }
2672
2673         if ((err = snd_m3_mixer(chip)) < 0)
2674                 return err;
2675
2676         for (i = 0; i < chip->num_substreams; i++) {
2677                 struct m3_dma *s = &chip->substreams[i];
2678                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2679                         return err;
2680         }
2681
2682         if ((err = snd_m3_pcm(chip, 0)) < 0)
2683                 return err;
2684
2685 #ifdef CONFIG_SND_MAESTRO3_INPUT
2686         if (chip->hv_config & HV_CTRL_ENABLE) {
2687                 err = snd_m3_input_register(chip);
2688                 if (err)
2689                         dev_warn(card->dev,
2690                                  "Input device registration failed with error %i",
2691                                  err);
2692         }
2693 #endif
2694
2695         snd_m3_enable_ints(chip);
2696         snd_m3_assp_continue(chip);
2697
2698         *chip_ret = chip;
2699
2700         return 0;
2701 }
2702
2703 /*
2704  */
2705 static int
2706 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2707 {
2708         static int dev;
2709         struct snd_card *card;
2710         struct snd_m3 *chip;
2711         int err;
2712
2713         /* don't pick up modems */
2714         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2715                 return -ENODEV;
2716
2717         if (dev >= SNDRV_CARDS)
2718                 return -ENODEV;
2719         if (!enable[dev]) {
2720                 dev++;
2721                 return -ENOENT;
2722         }
2723
2724         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2725                            0, &card);
2726         if (err < 0)
2727                 return err;
2728
2729         switch (pci->device) {
2730         case PCI_DEVICE_ID_ESS_ALLEGRO:
2731         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2732                 strcpy(card->driver, "Allegro");
2733                 break;
2734         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2735         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2736                 strcpy(card->driver, "Canyon3D-2");
2737                 break;
2738         default:
2739                 strcpy(card->driver, "Maestro3");
2740                 break;
2741         }
2742
2743         if ((err = snd_m3_create(card, pci,
2744                                  external_amp[dev],
2745                                  amp_gpio[dev],
2746                                  &chip)) < 0) {
2747                 snd_card_free(card);
2748                 return err;
2749         }
2750         card->private_data = chip;
2751
2752         sprintf(card->shortname, "ESS %s PCI", card->driver);
2753         sprintf(card->longname, "%s at 0x%lx, irq %d",
2754                 card->shortname, chip->iobase, chip->irq);
2755
2756         if ((err = snd_card_register(card)) < 0) {
2757                 snd_card_free(card);
2758                 return err;
2759         }
2760
2761 #if 0 /* TODO: not supported yet */
2762         /* TODO enable MIDI IRQ and I/O */
2763         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2764                                   chip->iobase + MPU401_DATA_PORT,
2765                                   MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2766                                   -1, &chip->rmidi);
2767         if (err < 0)
2768                 dev_warn(card->dev, "no MIDI support.\n");
2769 #endif
2770
2771         pci_set_drvdata(pci, card);
2772         dev++;
2773         return 0;
2774 }
2775
2776 static void snd_m3_remove(struct pci_dev *pci)
2777 {
2778         snd_card_free(pci_get_drvdata(pci));
2779 }
2780
2781 static struct pci_driver m3_driver = {
2782         .name = KBUILD_MODNAME,
2783         .id_table = snd_m3_ids,
2784         .probe = snd_m3_probe,
2785         .remove = snd_m3_remove,
2786         .driver = {
2787                 .pm = M3_PM_OPS,
2788         },
2789 };
2790
2791 module_pci_driver(m3_driver);