sound/pci/cs4281.c

   1 /*
   2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
   4  *
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <asm/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28 #include <linux/gameport.h>
  29 #include <linux/module.h>
  30 #include <sound/core.h>
  31 #include <sound/control.h>
  32 #include <sound/pcm.h>
  33 #include <sound/rawmidi.h>
  34 #include <sound/ac97_codec.h>
  35 #include <sound/tlv.h>
  36 #include <sound/opl3.h>
  37 #include <sound/initval.h>
  38
  39
  40 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
  42 MODULE_LICENSE("GPL");
  43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
  44
  45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  47 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  48 static bool dual_codec[SNDRV_CARDS];    /* dual codec */
  49
  50 module_param_array(index, int, NULL, 0444);
  51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  52 module_param_array(id, charp, NULL, 0444);
  53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  54 module_param_array(enable, bool, NULL, 0444);
  55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  56 module_param_array(dual_codec, bool, NULL, 0444);
  57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  58
  59 /*
  60  *  Direct registers
  61  */
  62
  63 #define CS4281_BA0_SIZE         0x1000
  64 #define CS4281_BA1_SIZE         0x10000
  65
  66 /*
  67  *  BA0 registers
  68  */
  69 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
  70 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
  71 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
  72 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
  73 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
  74 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
  75 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
  76 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
  77 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
  78 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
  79 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
  80 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
  81 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
  82
  83 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
  84 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
  85 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
  86 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
  87
  88 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
  89                                         /* Use same contants as for BA0_HISR */
  90
  91 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
  92
  93 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
  94 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
  95 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
  96 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
  97
  98 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
  99 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
 100 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
 101 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
 102 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
 103 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
 104
 105 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
 106 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
 107 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
 108 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
 109 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
 110 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
 111 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
 112 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
 113 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
 114 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
 115 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
 116 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
 117 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
 118 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
 119 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
 120 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
 121 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
 122 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
 123 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
 124 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
 125 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
 126 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
 127 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
 128 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
 129
 130 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
 131 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
 132 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
 133 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
 134 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
 135 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
 136 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
 137 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
 138 #define BA0_DMR_MONO            (1<<17) /* Mono */
 139 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
 140 #define BA0_DMR_TYPE_DEMAND     (0<<6)
 141 #define BA0_DMR_TYPE_SINGLE     (1<<6)
 142 #define BA0_DMR_TYPE_BLOCK      (2<<6)
 143 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
 144 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
 145 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
 146 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
 147 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
 148 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
 149
 150 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
 151 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
 152 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
 153
 154 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
 155 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
 156 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
 157 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
 158
 159 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
 160 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
 161 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
 162 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
 163 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
 164 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
 165 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
 166
 167 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
 168 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
 169 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
 170 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
 171
 172 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
 173 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
 174 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
 175 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
 176 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
 177 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
 178 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
 179 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
 180 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
 181
 182 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
 183 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
 184 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
 185 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
 186
 187 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
 188 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
 189 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
 190 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
 191 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
 192 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
 193 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
 194 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
 195
 196 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
 197 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
 198
 199 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
 200 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
 201
 202 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
 203
 204 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
 205 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
 206 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
 207 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
 208 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
 209 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
 210 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
 211 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
 212 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
 213 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
 214
 215 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
 216 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
 217 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
 218 #define BA0_TMS                 0x03f8  /* Test Register */
 219 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
 220
 221 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
 222 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
 223 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
 224 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
 225 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
 226 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
 227 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
 228
 229 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
 230 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
 231
 232 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
 233 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
 234 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
 235 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
 236 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
 237 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
 238 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
 239 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
 240 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
 241 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
 242 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
 243 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
 244 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
 245
 246 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
 247 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
 248 #define BA0_SERC1_AC97          (1<<1)
 249 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
 250
 251 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
 252 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
 253 #define BA0_SERC2_AC97          (1<<1)
 254 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
 255
 256 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
 257
 258 #define BA0_ACCTL               0x0460  /* AC'97 Control */
 259 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
 260 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
 261 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
 262 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
 263 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
 264
 265 #define BA0_ACSTS               0x0464  /* AC'97 Status */
 266 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
 267 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
 268
 269 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
 270 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
 271
 272 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
 273 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
 274
 275 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
 276 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
 277
 278 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
 279 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
 280 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
 281 #define BA0_JSCTL               0x0484  /* Joystick control */
 282 #define BA0_JSC1                0x0488  /* Joystick control */
 283 #define BA0_JSC2                0x048c  /* Joystick control */
 284 #define BA0_JSIO                0x04a0
 285
 286 #define BA0_MIDCR               0x0490  /* MIDI Control */
 287 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
 288 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
 289 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
 290 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
 291 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
 292 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
 293
 294 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
 295
 296 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
 297 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
 298 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
 299 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
 300 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
 301
 302 #define BA0_MIDWP               0x0498  /* MIDI Write */
 303 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
 304
 305 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
 306 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
 307
 308 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
 309 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
 310
 311 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
 312 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
 313 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
 314 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
 315 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
 316 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
 317 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
 318 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
 319 #define BA0_FMDP                0x0734  /* FM Data Port */
 320 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
 321 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
 322
 323 #define BA0_SSPM                0x0740  /* Sound System Power Management */
 324 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
 325 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
 326 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
 327 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
 328 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
 329 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
 330
 331 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
 332 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
 333
 334 #define BA0_SSCR                0x074c  /* Sound System Control Register */
 335 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
 336 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
 337 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
 338 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
 339 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
 340 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
 341 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
 342 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
 343 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
 344
 345 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
 346 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
 347 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
 348 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
 349 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
 350 #define BA0_PASR                0x0768  /* playback sample rate */
 351 #define BA0_CASR                0x076C  /* capture sample rate */
 352
 353 /* Source Slot Numbers - Playback */
 354 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
 355 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
 356 #define SRCSLOT_PHONE_LINE_1_DAC                2
 357 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
 358 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
 359 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
 360 #define SRCSLOT_LFE_PCM_PLAYBACK                6
 361 #define SRCSLOT_PHONE_LINE_2_DAC                7
 362 #define SRCSLOT_HEADSET_DAC                     8
 363 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
 364 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
 365
 366 /* Source Slot Numbers - Capture */
 367 #define SRCSLOT_LEFT_PCM_RECORD                 10
 368 #define SRCSLOT_RIGHT_PCM_RECORD                11
 369 #define SRCSLOT_PHONE_LINE_1_ADC                12
 370 #define SRCSLOT_MIC_ADC                         13
 371 #define SRCSLOT_PHONE_LINE_2_ADC                17
 372 #define SRCSLOT_HEADSET_ADC                     18
 373 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
 374 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
 375 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
 376 #define SRCSLOT_SECONDARY_MIC_ADC               23
 377 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
 378 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
 379
 380 /* Source Slot Numbers - Others */
 381 #define SRCSLOT_POWER_DOWN                      31
 382
 383 /* MIDI modes */
 384 #define CS4281_MODE_OUTPUT              (1<<0)
 385 #define CS4281_MODE_INPUT               (1<<1)
 386
 387 /* joystick bits */
 388 /* Bits for JSPT */
 389 #define JSPT_CAX                                0x00000001
 390 #define JSPT_CAY                                0x00000002
 391 #define JSPT_CBX                                0x00000004
 392 #define JSPT_CBY                                0x00000008
 393 #define JSPT_BA1                                0x00000010
 394 #define JSPT_BA2                                0x00000020
 395 #define JSPT_BB1                                0x00000040
 396 #define JSPT_BB2                                0x00000080
 397
 398 /* Bits for JSCTL */
 399 #define JSCTL_SP_MASK                           0x00000003
 400 #define JSCTL_SP_SLOW                           0x00000000
 401 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
 402 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
 403 #define JSCTL_SP_FAST                           0x00000003
 404 #define JSCTL_ARE                               0x00000004
 405
 406 /* Data register pairs masks */
 407 #define JSC1_Y1V_MASK                           0x0000FFFF
 408 #define JSC1_X1V_MASK                           0xFFFF0000
 409 #define JSC1_Y1V_SHIFT                          0
 410 #define JSC1_X1V_SHIFT                          16
 411 #define JSC2_Y2V_MASK                           0x0000FFFF
 412 #define JSC2_X2V_MASK                           0xFFFF0000
 413 #define JSC2_Y2V_SHIFT                          0
 414 #define JSC2_X2V_SHIFT                          16
 415
 416 /* JS GPIO */
 417 #define JSIO_DAX                                0x00000001
 418 #define JSIO_DAY                                0x00000002
 419 #define JSIO_DBX                                0x00000004
 420 #define JSIO_DBY                                0x00000008
 421 #define JSIO_AXOE                               0x00000010
 422 #define JSIO_AYOE                               0x00000020
 423 #define JSIO_BXOE                               0x00000040
 424 #define JSIO_BYOE                               0x00000080
 425
 426 /*
 427  *
 428  */
 429
 430 struct cs4281_dma {
 431         struct snd_pcm_substream *substream;
 432         unsigned int regDBA;            /* offset to DBA register */
 433         unsigned int regDCA;            /* offset to DCA register */
 434         unsigned int regDBC;            /* offset to DBC register */
 435         unsigned int regDCC;            /* offset to DCC register */
 436         unsigned int regDMR;            /* offset to DMR register */
 437         unsigned int regDCR;            /* offset to DCR register */
 438         unsigned int regHDSR;           /* offset to HDSR register */
 439         unsigned int regFCR;            /* offset to FCR register */
 440         unsigned int regFSIC;           /* offset to FSIC register */
 441         unsigned int valDMR;            /* DMA mode */
 442         unsigned int valDCR;            /* DMA command */
 443         unsigned int valFCR;            /* FIFO control */
 444         unsigned int fifo_offset;       /* FIFO offset within BA1 */
 445         unsigned char left_slot;        /* FIFO left slot */
 446         unsigned char right_slot;       /* FIFO right slot */
 447         int frag;                       /* period number */
 448 };
 449
 450 #define SUSPEND_REGISTERS       20
 451
 452 struct cs4281 {
 453         int irq;
 454
 455         void __iomem *ba0;              /* virtual (accessible) address */
 456         void __iomem *ba1;              /* virtual (accessible) address */
 457         unsigned long ba0_addr;
 458         unsigned long ba1_addr;
 459
 460         int dual_codec;
 461
 462         struct snd_ac97_bus *ac97_bus;
 463         struct snd_ac97 *ac97;
 464         struct snd_ac97 *ac97_secondary;
 465
 466         struct pci_dev *pci;
 467         struct snd_card *card;
 468         struct snd_pcm *pcm;
 469         struct snd_rawmidi *rmidi;
 470         struct snd_rawmidi_substream *midi_input;
 471         struct snd_rawmidi_substream *midi_output;
 472
 473         struct cs4281_dma dma[4];
 474
 475         unsigned char src_left_play_slot;
 476         unsigned char src_right_play_slot;
 477         unsigned char src_left_rec_slot;
 478         unsigned char src_right_rec_slot;
 479
 480         unsigned int spurious_dhtc_irq;
 481         unsigned int spurious_dtc_irq;
 482
 483         spinlock_t reg_lock;
 484         unsigned int midcr;
 485         unsigned int uartm;
 486
 487         struct gameport *gameport;
 488
 489 #ifdef CONFIG_PM_SLEEP
 490         u32 suspend_regs[SUSPEND_REGISTERS];
 491 #endif
 492
 493 };
 494
 495 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
 496
 497 static DEFINE_PCI_DEVICE_TABLE(snd_cs4281_ids) = {
 498         { PCI_VDEVICE(CIRRUS, 0x6005), 0, },    /* CS4281 */
 499         { 0, }
 500 };
 501
 502 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
 503
 504 /*
 505  *  constants
 506  */
 507
 508 #define CS4281_FIFO_SIZE        32
 509
 510 /*
 511  *  common I/O routines
 512  */
 513
 514 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
 515                                       unsigned int val)
 516 {
 517         writel(val, chip->ba0 + offset);
 518 }
 519
 520 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
 521 {
 522         return readl(chip->ba0 + offset);
 523 }
 524
 525 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
 526                                   unsigned short reg, unsigned short val)
 527 {
 528         /*
 529          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 530          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 531          *  3. Write ACCTL = Control Register = 460h for initiating the write
 532          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 533          *  5. if DCV not cleared, break and return error
 534          */
 535         struct cs4281 *chip = ac97->private_data;
 536         int count;
 537
 538         /*
 539          *  Setup the AC97 control registers on the CS461x to send the
 540          *  appropriate command to the AC97 to perform the read.
 541          *  ACCAD = Command Address Register = 46Ch
 542          *  ACCDA = Command Data Register = 470h
 543          *  ACCTL = Control Register = 460h
 544          *  set DCV - will clear when process completed
 545          *  reset CRW - Write command
 546          *  set VFRM - valid frame enabled
 547          *  set ESYN - ASYNC generation enabled
 548          *  set RSTN - ARST# inactive, AC97 codec not reset
 549          */
 550         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 551         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
 552         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
 553                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
 554         for (count = 0; count < 2000; count++) {
 555                 /*
 556                  *  First, we want to wait for a short time.
 557                  */
 558                 udelay(10);
 559                 /*
 560                  *  Now, check to see if the write has completed.
 561                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 562                  */
 563                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
 564                         return;
 565                 }
 566         }
 567         dev_err(chip->card->dev,
 568                 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
 569 }
 570
 571 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
 572                                            unsigned short reg)
 573 {
 574         struct cs4281 *chip = ac97->private_data;
 575         int count;
 576         unsigned short result;
 577         // FIXME: volatile is necessary in the following due to a bug of
 578         // some gcc versions
 579         volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
 580
 581         /*
 582          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 583          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 584          *  3. Write ACCTL = Control Register = 460h for initiating the write
 585          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 586          *  5. if DCV not cleared, break and return error
 587          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 588          */
 589
 590         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 591
 592         /*
 593          *  Setup the AC97 control registers on the CS461x to send the
 594          *  appropriate command to the AC97 to perform the read.
 595          *  ACCAD = Command Address Register = 46Ch
 596          *  ACCDA = Command Data Register = 470h
 597          *  ACCTL = Control Register = 460h
 598          *  set DCV - will clear when process completed
 599          *  set CRW - Read command
 600          *  set VFRM - valid frame enabled
 601          *  set ESYN - ASYNC generation enabled
 602          *  set RSTN - ARST# inactive, AC97 codec not reset
 603          */
 604
 605         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 606         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
 607         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
 608                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
 609                            (ac97_num ? BA0_ACCTL_TC : 0));
 610
 611
 612         /*
 613          *  Wait for the read to occur.
 614          */
 615         for (count = 0; count < 500; count++) {
 616                 /*
 617                  *  First, we want to wait for a short time.
 618                  */
 619                 udelay(10);
 620                 /*
 621                  *  Now, check to see if the read has completed.
 622                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 623                  */
 624                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
 625                         goto __ok1;
 626         }
 627
 628         dev_err(chip->card->dev,
 629                 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 630         result = 0xffff;
 631         goto __end;
 632
 633       __ok1:
 634         /*
 635          *  Wait for the valid status bit to go active.
 636          */
 637         for (count = 0; count < 100; count++) {
 638                 /*
 639                  *  Read the AC97 status register.
 640                  *  ACSTS = Status Register = 464h
 641                  *  VSTS - Valid Status
 642                  */
 643                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
 644                         goto __ok2;
 645                 udelay(10);
 646         }
 647
 648         dev_err(chip->card->dev,
 649                 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
 650         result = 0xffff;
 651         goto __end;
 652
 653       __ok2:
 654         /*
 655          *  Read the data returned from the AC97 register.
 656          *  ACSDA = Status Data Register = 474h
 657          */
 658         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 659
 660       __end:
 661         return result;
 662 }
 663
 664 /*
 665  *  PCM part
 666  */
 667
 668 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
 669 {
 670         struct cs4281_dma *dma = substream->runtime->private_data;
 671         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 672
 673         spin_lock(&chip->reg_lock);
 674         switch (cmd) {
 675         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 676                 dma->valDCR |= BA0_DCR_MSK;
 677                 dma->valFCR |= BA0_FCR_FEN;
 678                 break;
 679         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 680                 dma->valDCR &= ~BA0_DCR_MSK;
 681                 dma->valFCR &= ~BA0_FCR_FEN;
 682                 break;
 683         case SNDRV_PCM_TRIGGER_START:
 684         case SNDRV_PCM_TRIGGER_RESUME:
 685                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
 686                 dma->valDMR |= BA0_DMR_DMA;
 687                 dma->valDCR &= ~BA0_DCR_MSK;
 688                 dma->valFCR |= BA0_FCR_FEN;
 689                 break;
 690         case SNDRV_PCM_TRIGGER_STOP:
 691         case SNDRV_PCM_TRIGGER_SUSPEND:
 692                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
 693                 dma->valDCR |= BA0_DCR_MSK;
 694                 dma->valFCR &= ~BA0_FCR_FEN;
 695                 /* Leave wave playback FIFO enabled for FM */
 696                 if (dma->regFCR != BA0_FCR0)
 697                         dma->valFCR &= ~BA0_FCR_FEN;
 698                 break;
 699         default:
 700                 spin_unlock(&chip->reg_lock);
 701                 return -EINVAL;
 702         }
 703         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
 704         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
 705         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
 706         spin_unlock(&chip->reg_lock);
 707         return 0;
 708 }
 709
 710 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
 711 {
 712         unsigned int val = ~0;
 713
 714         if (real_rate)
 715                 *real_rate = rate;
 716         /* special "hardcoded" rates */
 717         switch (rate) {
 718         case 8000:      return 5;
 719         case 11025:     return 4;
 720         case 16000:     return 3;
 721         case 22050:     return 2;
 722         case 44100:     return 1;
 723         case 48000:     return 0;
 724         default:
 725                 goto __variable;
 726         }
 727       __variable:
 728         val = 1536000 / rate;
 729         if (real_rate)
 730                 *real_rate = 1536000 / val;
 731         return val;
 732 }
 733
 734 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
 735                             struct snd_pcm_runtime *runtime,
 736                             int capture, int src)
 737 {
 738         int rec_mono;
 739
 740         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
 741                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
 742         if (runtime->channels == 1)
 743                 dma->valDMR |= BA0_DMR_MONO;
 744         if (snd_pcm_format_unsigned(runtime->format) > 0)
 745                 dma->valDMR |= BA0_DMR_USIGN;
 746         if (snd_pcm_format_big_endian(runtime->format) > 0)
 747                 dma->valDMR |= BA0_DMR_BEND;
 748         switch (snd_pcm_format_width(runtime->format)) {
 749         case 8: dma->valDMR |= BA0_DMR_SIZE8;
 750                 if (runtime->channels == 1)
 751                         dma->valDMR |= BA0_DMR_SWAPC;
 752                 break;
 753         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
 754         }
 755         dma->frag = 0;  /* for workaround */
 756         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
 757         if (runtime->buffer_size != runtime->period_size)
 758                 dma->valDCR |= BA0_DCR_HTCIE;
 759         /* Initialize DMA */
 760         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
 761         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
 762         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
 763         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
 764                                             (chip->src_right_play_slot << 8) |
 765                                             (chip->src_left_rec_slot << 16) |
 766                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
 767         if (!src)
 768                 goto __skip_src;
 769         if (!capture) {
 770                 if (dma->left_slot == chip->src_left_play_slot) {
 771                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 772                         snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
 773                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
 774                 }
 775         } else {
 776                 if (dma->left_slot == chip->src_left_rec_slot) {
 777                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 778                         snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
 779                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
 780                 }
 781         }
 782       __skip_src:
 783         /* Deactivate wave playback FIFO before changing slot assignments */
 784         if (dma->regFCR == BA0_FCR0)
 785                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
 786         /* Initialize FIFO */
 787         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
 788                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
 789                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
 790                       BA0_FCR_OF(dma->fifo_offset);
 791         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
 792         /* Activate FIFO again for FM playback */
 793         if (dma->regFCR == BA0_FCR0)
 794                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
 795         /* Clear FIFO Status and Interrupt Control Register */
 796         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
 797 }
 798
 799 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
 800                                 struct snd_pcm_hw_params *hw_params)
 801 {
 802         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 803 }
 804
 805 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
 806 {
 807         return snd_pcm_lib_free_pages(substream);
 808 }
 809
 810 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
 811 {
 812         struct snd_pcm_runtime *runtime = substream->runtime;
 813         struct cs4281_dma *dma = runtime->private_data;
 814         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 815
 816         spin_lock_irq(&chip->reg_lock);
 817         snd_cs4281_mode(chip, dma, runtime, 0, 1);
 818         spin_unlock_irq(&chip->reg_lock);
 819         return 0;
 820 }
 821
 822 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
 823 {
 824         struct snd_pcm_runtime *runtime = substream->runtime;
 825         struct cs4281_dma *dma = runtime->private_data;
 826         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 827
 828         spin_lock_irq(&chip->reg_lock);
 829         snd_cs4281_mode(chip, dma, runtime, 1, 1);
 830         spin_unlock_irq(&chip->reg_lock);
 831         return 0;
 832 }
 833
 834 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
 835 {
 836         struct snd_pcm_runtime *runtime = substream->runtime;
 837         struct cs4281_dma *dma = runtime->private_data;
 838         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 839
 840         /*
 841         dev_dbg(chip->card->dev,
 842                 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
 843                 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
 844                jiffies);
 845         */
 846         return runtime->buffer_size -
 847                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
 848 }
 849
 850 static struct snd_pcm_hardware snd_cs4281_playback =
 851 {
 852         .info =                 SNDRV_PCM_INFO_MMAP |
 853                                 SNDRV_PCM_INFO_INTERLEAVED |
 854                                 SNDRV_PCM_INFO_MMAP_VALID |
 855                                 SNDRV_PCM_INFO_PAUSE |
 856                                 SNDRV_PCM_INFO_RESUME,
 857         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 858                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 859                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 860                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 861                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 862         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 863         .rate_min =             4000,
 864         .rate_max =             48000,
 865         .channels_min =         1,
 866         .channels_max =         2,
 867         .buffer_bytes_max =     (512*1024),
 868         .period_bytes_min =     64,
 869         .period_bytes_max =     (512*1024),
 870         .periods_min =          1,
 871         .periods_max =          2,
 872         .fifo_size =            CS4281_FIFO_SIZE,
 873 };
 874
 875 static struct snd_pcm_hardware snd_cs4281_capture =
 876 {
 877         .info =                 SNDRV_PCM_INFO_MMAP |
 878                                 SNDRV_PCM_INFO_INTERLEAVED |
 879                                 SNDRV_PCM_INFO_MMAP_VALID |
 880                                 SNDRV_PCM_INFO_PAUSE |
 881                                 SNDRV_PCM_INFO_RESUME,
 882         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 883                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 884                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 885                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 886                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 887         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 888         .rate_min =             4000,
 889         .rate_max =             48000,
 890         .channels_min =         1,
 891         .channels_max =         2,
 892         .buffer_bytes_max =     (512*1024),
 893         .period_bytes_min =     64,
 894         .period_bytes_max =     (512*1024),
 895         .periods_min =          1,
 896         .periods_max =          2,
 897         .fifo_size =            CS4281_FIFO_SIZE,
 898 };
 899
 900 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
 901 {
 902         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 903         struct snd_pcm_runtime *runtime = substream->runtime;
 904         struct cs4281_dma *dma;
 905
 906         dma = &chip->dma[0];
 907         dma->substream = substream;
 908         dma->left_slot = 0;
 909         dma->right_slot = 1;
 910         runtime->private_data = dma;
 911         runtime->hw = snd_cs4281_playback;
 912         /* should be detected from the AC'97 layer, but it seems
 913            that although CS4297A rev B reports 18-bit ADC resolution,
 914            samples are 20-bit */
 915         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 916         return 0;
 917 }
 918
 919 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
 920 {
 921         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 922         struct snd_pcm_runtime *runtime = substream->runtime;
 923         struct cs4281_dma *dma;
 924
 925         dma = &chip->dma[1];
 926         dma->substream = substream;
 927         dma->left_slot = 10;
 928         dma->right_slot = 11;
 929         runtime->private_data = dma;
 930         runtime->hw = snd_cs4281_capture;
 931         /* should be detected from the AC'97 layer, but it seems
 932            that although CS4297A rev B reports 18-bit ADC resolution,
 933            samples are 20-bit */
 934         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 935         return 0;
 936 }
 937
 938 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
 939 {
 940         struct cs4281_dma *dma = substream->runtime->private_data;
 941
 942         dma->substream = NULL;
 943         return 0;
 944 }
 945
 946 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
 947 {
 948         struct cs4281_dma *dma = substream->runtime->private_data;
 949
 950         dma->substream = NULL;
 951         return 0;
 952 }
 953
 954 static struct snd_pcm_ops snd_cs4281_playback_ops = {
 955         .open =         snd_cs4281_playback_open,
 956         .close =        snd_cs4281_playback_close,
 957         .ioctl =        snd_pcm_lib_ioctl,
 958         .hw_params =    snd_cs4281_hw_params,
 959         .hw_free =      snd_cs4281_hw_free,
 960         .prepare =      snd_cs4281_playback_prepare,
 961         .trigger =      snd_cs4281_trigger,
 962         .pointer =      snd_cs4281_pointer,
 963 };
 964
 965 static struct snd_pcm_ops snd_cs4281_capture_ops = {
 966         .open =         snd_cs4281_capture_open,
 967         .close =        snd_cs4281_capture_close,
 968         .ioctl =        snd_pcm_lib_ioctl,
 969         .hw_params =    snd_cs4281_hw_params,
 970         .hw_free =      snd_cs4281_hw_free,
 971         .prepare =      snd_cs4281_capture_prepare,
 972         .trigger =      snd_cs4281_trigger,
 973         .pointer =      snd_cs4281_pointer,
 974 };
 975
 976 static int snd_cs4281_pcm(struct cs4281 *chip, int device,
 977                           struct snd_pcm **rpcm)
 978 {
 979         struct snd_pcm *pcm;
 980         int err;
 981
 982         if (rpcm)
 983                 *rpcm = NULL;
 984         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
 985         if (err < 0)
 986                 return err;
 987
 988         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
 989         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
 990
 991         pcm->private_data = chip;
 992         pcm->info_flags = 0;
 993         strcpy(pcm->name, "CS4281");
 994         chip->pcm = pcm;
 995
 996         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 997                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
 998
 999         if (rpcm)
1000                 *rpcm = pcm;
1001         return 0;
1002 }
1003
1004 /*
1005  *  Mixer section
1006  */
1007
1008 #define CS_VOL_MASK     0x1f
1009
1010 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
1011                                   struct snd_ctl_elem_info *uinfo)
1012 {
1013         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1014         uinfo->count             = 2;
1015         uinfo->value.integer.min = 0;
1016         uinfo->value.integer.max = CS_VOL_MASK;
1017         return 0;
1018 }
1019
1020 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1021                                  struct snd_ctl_elem_value *ucontrol)
1022 {
1023         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1024         int regL = (kcontrol->private_value >> 16) & 0xffff;
1025         int regR = kcontrol->private_value & 0xffff;
1026         int volL, volR;
1027
1028         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1029         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1030
1031         ucontrol->value.integer.value[0] = volL;
1032         ucontrol->value.integer.value[1] = volR;
1033         return 0;
1034 }
1035
1036 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1037                                  struct snd_ctl_elem_value *ucontrol)
1038 {
1039         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1040         int change = 0;
1041         int regL = (kcontrol->private_value >> 16) & 0xffff;
1042         int regR = kcontrol->private_value & 0xffff;
1043         int volL, volR;
1044
1045         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1046         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1047
1048         if (ucontrol->value.integer.value[0] != volL) {
1049                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1050                 snd_cs4281_pokeBA0(chip, regL, volL);
1051                 change = 1;
1052         }
1053         if (ucontrol->value.integer.value[1] != volR) {
1054                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1055                 snd_cs4281_pokeBA0(chip, regR, volR);
1056                 change = 1;
1057         }
1058         return change;
1059 }
1060
1061 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1062
1063 static struct snd_kcontrol_new snd_cs4281_fm_vol =
1064 {
1065         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1066         .name = "Synth Playback Volume",
1067         .info = snd_cs4281_info_volume,
1068         .get = snd_cs4281_get_volume,
1069         .put = snd_cs4281_put_volume,
1070         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1071         .tlv = { .p = db_scale_dsp },
1072 };
1073
1074 static struct snd_kcontrol_new snd_cs4281_pcm_vol =
1075 {
1076         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1077         .name = "PCM Stream Playback Volume",
1078         .info = snd_cs4281_info_volume,
1079         .get = snd_cs4281_get_volume,
1080         .put = snd_cs4281_put_volume,
1081         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1082         .tlv = { .p = db_scale_dsp },
1083 };
1084
1085 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1086 {
1087         struct cs4281 *chip = bus->private_data;
1088         chip->ac97_bus = NULL;
1089 }
1090
1091 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1092 {
1093         struct cs4281 *chip = ac97->private_data;
1094         if (ac97->num)
1095                 chip->ac97_secondary = NULL;
1096         else
1097                 chip->ac97 = NULL;
1098 }
1099
1100 static int snd_cs4281_mixer(struct cs4281 *chip)
1101 {
1102         struct snd_card *card = chip->card;
1103         struct snd_ac97_template ac97;
1104         int err;
1105         static struct snd_ac97_bus_ops ops = {
1106                 .write = snd_cs4281_ac97_write,
1107                 .read = snd_cs4281_ac97_read,
1108         };
1109
1110         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1111                 return err;
1112         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1113
1114         memset(&ac97, 0, sizeof(ac97));
1115         ac97.private_data = chip;
1116         ac97.private_free = snd_cs4281_mixer_free_ac97;
1117         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1118                 return err;
1119         if (chip->dual_codec) {
1120                 ac97.num = 1;
1121                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1122                         return err;
1123         }
1124         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1125                 return err;
1126         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1127                 return err;
1128         return 0;
1129 }
1130
1131
1132 /*
1133  * proc interface
1134  */
1135
1136 static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1137                                   struct snd_info_buffer *buffer)
1138 {
1139         struct cs4281 *chip = entry->private_data;
1140
1141         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1142         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1143         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1144 }
1145
1146 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1147                                    void *file_private_data,
1148                                    struct file *file, char __user *buf,
1149                                    size_t count, loff_t pos)
1150 {
1151         struct cs4281 *chip = entry->private_data;
1152
1153         if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1154                 return -EFAULT;
1155         return count;
1156 }
1157
1158 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1159                                    void *file_private_data,
1160                                    struct file *file, char __user *buf,
1161                                    size_t count, loff_t pos)
1162 {
1163         struct cs4281 *chip = entry->private_data;
1164
1165         if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1166                 return -EFAULT;
1167         return count;
1168 }
1169
1170 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1171         .read = snd_cs4281_BA0_read,
1172 };
1173
1174 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1175         .read = snd_cs4281_BA1_read,
1176 };
1177
1178 static void snd_cs4281_proc_init(struct cs4281 *chip)
1179 {
1180         struct snd_info_entry *entry;
1181
1182         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1183                 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1184         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1185                 entry->content = SNDRV_INFO_CONTENT_DATA;
1186                 entry->private_data = chip;
1187                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1188                 entry->size = CS4281_BA0_SIZE;
1189         }
1190         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1191                 entry->content = SNDRV_INFO_CONTENT_DATA;
1192                 entry->private_data = chip;
1193                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1194                 entry->size = CS4281_BA1_SIZE;
1195         }
1196 }
1197
1198 /*
1199  * joystick support
1200  */
1201
1202 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1203
1204 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1205 {
1206         struct cs4281 *chip = gameport_get_port_data(gameport);
1207
1208         if (snd_BUG_ON(!chip))
1209                 return;
1210         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1211 }
1212
1213 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1214 {
1215         struct cs4281 *chip = gameport_get_port_data(gameport);
1216
1217         if (snd_BUG_ON(!chip))
1218                 return 0;
1219         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1220 }
1221
1222 #ifdef COOKED_MODE
1223 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1224                                            int *axes, int *buttons)
1225 {
1226         struct cs4281 *chip = gameport_get_port_data(gameport);
1227         unsigned js1, js2, jst;
1228
1229         if (snd_BUG_ON(!chip))
1230                 return 0;
1231
1232         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1233         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1234         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1235
1236         *buttons = (~jst >> 4) & 0x0F;
1237
1238         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1239         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1240         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1241         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1242
1243         for (jst = 0; jst < 4; ++jst)
1244                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1245         return 0;
1246 }
1247 #else
1248 #define snd_cs4281_gameport_cooked_read NULL
1249 #endif
1250
1251 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1252 {
1253         switch (mode) {
1254 #ifdef COOKED_MODE
1255         case GAMEPORT_MODE_COOKED:
1256                 return 0;
1257 #endif
1258         case GAMEPORT_MODE_RAW:
1259                 return 0;
1260         default:
1261                 return -1;
1262         }
1263         return 0;
1264 }
1265
1266 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1267 {
1268         struct gameport *gp;
1269
1270         chip->gameport = gp = gameport_allocate_port();
1271         if (!gp) {
1272                 dev_err(chip->card->dev,
1273                         "cannot allocate memory for gameport\n");
1274                 return -ENOMEM;
1275         }
1276
1277         gameport_set_name(gp, "CS4281 Gameport");
1278         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1279         gameport_set_dev_parent(gp, &chip->pci->dev);
1280         gp->open = snd_cs4281_gameport_open;
1281         gp->read = snd_cs4281_gameport_read;
1282         gp->trigger = snd_cs4281_gameport_trigger;
1283         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1284         gameport_set_port_data(gp, chip);
1285
1286         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1287         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1288
1289         gameport_register_port(gp);
1290
1291         return 0;
1292 }
1293
1294 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1295 {
1296         if (chip->gameport) {
1297                 gameport_unregister_port(chip->gameport);
1298                 chip->gameport = NULL;
1299         }
1300 }
1301 #else
1302 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1303 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1304 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1305
1306 static int snd_cs4281_free(struct cs4281 *chip)
1307 {
1308         snd_cs4281_free_gameport(chip);
1309
1310         if (chip->irq >= 0)
1311                 synchronize_irq(chip->irq);
1312
1313         /* Mask interrupts */
1314         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1315         /* Stop the DLL Clock logic. */
1316         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1317         /* Sound System Power Management - Turn Everything OFF */
1318         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1319         /* PCI interface - D3 state */
1320         pci_set_power_state(chip->pci, PCI_D3hot);
1321
1322         if (chip->irq >= 0)
1323                 free_irq(chip->irq, chip);
1324         if (chip->ba0)
1325                 iounmap(chip->ba0);
1326         if (chip->ba1)
1327                 iounmap(chip->ba1);
1328         pci_release_regions(chip->pci);
1329         pci_disable_device(chip->pci);
1330
1331         kfree(chip);
1332         return 0;
1333 }
1334
1335 static int snd_cs4281_dev_free(struct snd_device *device)
1336 {
1337         struct cs4281 *chip = device->device_data;
1338         return snd_cs4281_free(chip);
1339 }
1340
1341 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1342
1343 static int snd_cs4281_create(struct snd_card *card,
1344                              struct pci_dev *pci,
1345                              struct cs4281 **rchip,
1346                              int dual_codec)
1347 {
1348         struct cs4281 *chip;
1349         unsigned int tmp;
1350         int err;
1351         static struct snd_device_ops ops = {
1352                 .dev_free =     snd_cs4281_dev_free,
1353         };
1354
1355         *rchip = NULL;
1356         if ((err = pci_enable_device(pci)) < 0)
1357                 return err;
1358         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1359         if (chip == NULL) {
1360                 pci_disable_device(pci);
1361                 return -ENOMEM;
1362         }
1363         spin_lock_init(&chip->reg_lock);
1364         chip->card = card;
1365         chip->pci = pci;
1366         chip->irq = -1;
1367         pci_set_master(pci);
1368         if (dual_codec < 0 || dual_codec > 3) {
1369                 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1370                 dual_codec = 0;
1371         }
1372         chip->dual_codec = dual_codec;
1373
1374         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1375                 kfree(chip);
1376                 pci_disable_device(pci);
1377                 return err;
1378         }
1379         chip->ba0_addr = pci_resource_start(pci, 0);
1380         chip->ba1_addr = pci_resource_start(pci, 1);
1381
1382         chip->ba0 = pci_ioremap_bar(pci, 0);
1383         chip->ba1 = pci_ioremap_bar(pci, 1);
1384         if (!chip->ba0 || !chip->ba1) {
1385                 snd_cs4281_free(chip);
1386                 return -ENOMEM;
1387         }
1388
1389         if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1390                         KBUILD_MODNAME, chip)) {
1391                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1392                 snd_cs4281_free(chip);
1393                 return -ENOMEM;
1394         }
1395         chip->irq = pci->irq;
1396
1397         tmp = snd_cs4281_chip_init(chip);
1398         if (tmp) {
1399                 snd_cs4281_free(chip);
1400                 return tmp;
1401         }
1402
1403         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1404                 snd_cs4281_free(chip);
1405                 return err;
1406         }
1407
1408         snd_cs4281_proc_init(chip);
1409
1410         *rchip = chip;
1411         return 0;
1412 }
1413
1414 static int snd_cs4281_chip_init(struct cs4281 *chip)
1415 {
1416         unsigned int tmp;
1417         unsigned long end_time;
1418         int retry_count = 2;
1419
1420         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1421         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1422         if (tmp & BA0_EPPMC_FPDN)
1423                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1424
1425       __retry:
1426         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1427         if (tmp != BA0_CFLR_DEFAULT) {
1428                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1429                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1430                 if (tmp != BA0_CFLR_DEFAULT) {
1431                         dev_err(chip->card->dev,
1432                                 "CFLR setup failed (0x%x)\n", tmp);
1433                         return -EIO;
1434                 }
1435         }
1436
1437         /* Set the 'Configuration Write Protect' register
1438          * to 4281h.  Allows vendor-defined configuration
1439          * space between 0e4h and 0ffh to be written. */
1440         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1441
1442         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1443                 dev_err(chip->card->dev,
1444                         "SERC1 AC'97 check failed (0x%x)\n", tmp);
1445                 return -EIO;
1446         }
1447         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1448                 dev_err(chip->card->dev,
1449                         "SERC2 AC'97 check failed (0x%x)\n", tmp);
1450                 return -EIO;
1451         }
1452
1453         /* Sound System Power Management */
1454         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1455                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1456                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1457
1458         /* Serial Port Power Management */
1459         /* Blast the clock control register to zero so that the
1460          * PLL starts out in a known state, and blast the master serial
1461          * port control register to zero so that the serial ports also
1462          * start out in a known state. */
1463         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1464         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1465
1466         /* Make ESYN go to zero to turn off
1467          * the Sync pulse on the AC97 link. */
1468         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1469         udelay(50);
1470
1471         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1472          *  spec) and then drive it high.  This is done for non AC97 modes since
1473          *  there might be logic external to the CS4281 that uses the ARST# line
1474          *  for a reset. */
1475         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1476         udelay(50);
1477         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1478         msleep(50);
1479
1480         if (chip->dual_codec)
1481                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1482
1483         /*
1484          *  Set the serial port timing configuration.
1485          */
1486         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1487                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1488                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1489
1490         /*
1491          *  Start the DLL Clock logic.
1492          */
1493         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1494         msleep(50);
1495         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1496
1497         /*
1498          * Wait for the DLL ready signal from the clock logic.
1499          */
1500         end_time = jiffies + HZ;
1501         do {
1502                 /*
1503                  *  Read the AC97 status register to see if we've seen a CODEC
1504                  *  signal from the AC97 codec.
1505                  */
1506                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1507                         goto __ok0;
1508                 schedule_timeout_uninterruptible(1);
1509         } while (time_after_eq(end_time, jiffies));
1510
1511         dev_err(chip->card->dev, "DLLRDY not seen\n");
1512         return -EIO;
1513
1514       __ok0:
1515
1516         /*
1517          *  The first thing we do here is to enable sync generation.  As soon
1518          *  as we start receiving bit clock, we'll start producing the SYNC
1519          *  signal.
1520          */
1521         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1522
1523         /*
1524          * Wait for the codec ready signal from the AC97 codec.
1525          */
1526         end_time = jiffies + HZ;
1527         do {
1528                 /*
1529                  *  Read the AC97 status register to see if we've seen a CODEC
1530                  *  signal from the AC97 codec.
1531                  */
1532                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1533                         goto __ok1;
1534                 schedule_timeout_uninterruptible(1);
1535         } while (time_after_eq(end_time, jiffies));
1536
1537         dev_err(chip->card->dev,
1538                 "never read codec ready from AC'97 (0x%x)\n",
1539                 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1540         return -EIO;
1541
1542       __ok1:
1543         if (chip->dual_codec) {
1544                 end_time = jiffies + HZ;
1545                 do {
1546                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1547                                 goto __codec2_ok;
1548                         schedule_timeout_uninterruptible(1);
1549                 } while (time_after_eq(end_time, jiffies));
1550                 dev_info(chip->card->dev,
1551                          "secondary codec doesn't respond. disable it...\n");
1552                 chip->dual_codec = 0;
1553         __codec2_ok: ;
1554         }
1555
1556         /*
1557          *  Assert the valid frame signal so that we can start sending commands
1558          *  to the AC97 codec.
1559          */
1560
1561         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1562
1563         /*
1564          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1565          *  the codec is pumping ADC data across the AC-link.
1566          */
1567
1568         end_time = jiffies + HZ;
1569         do {
1570                 /*
1571                  *  Read the input slot valid register and see if input slots 3
1572                  *  4 are valid yet.
1573                  */
1574                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1575                         goto __ok2;
1576                 schedule_timeout_uninterruptible(1);
1577         } while (time_after_eq(end_time, jiffies));
1578
1579         if (--retry_count > 0)
1580                 goto __retry;
1581         dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1582         return -EIO;
1583
1584       __ok2:
1585
1586         /*
1587          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1588          *  commense the transfer of digital audio data to the AC97 codec.
1589          */
1590         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1591
1592         /*
1593          *  Initialize DMA structures
1594          */
1595         for (tmp = 0; tmp < 4; tmp++) {
1596                 struct cs4281_dma *dma = &chip->dma[tmp];
1597                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1598                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1599                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1600                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1601                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1602                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1603                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1604                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1605                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1606                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1607                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1608                                    BA0_FCR_LS(31) |
1609                                    BA0_FCR_RS(31) |
1610                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1611                                    BA0_FCR_OF(dma->fifo_offset));
1612         }
1613
1614         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1615         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1616         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1617         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1618
1619         /* Activate wave playback FIFO for FM playback */
1620         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1621                               BA0_FCR_RS(1) |
1622                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1623                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1624         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1625         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1626                                             (chip->src_right_play_slot << 8) |
1627                                             (chip->src_left_rec_slot << 16) |
1628                                             (chip->src_right_rec_slot << 24));
1629
1630         /* Initialize digital volume */
1631         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1632         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1633
1634         /* Enable IRQs */
1635         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1636         /* Unmask interrupts */
1637         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1638                                         BA0_HISR_MIDI |
1639                                         BA0_HISR_DMAI |
1640                                         BA0_HISR_DMA(0) |
1641                                         BA0_HISR_DMA(1) |
1642                                         BA0_HISR_DMA(2) |
1643                                         BA0_HISR_DMA(3)));
1644         synchronize_irq(chip->irq);
1645
1646         return 0;
1647 }
1648
1649 /*
1650  *  MIDI section
1651  */
1652
1653 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1654 {
1655         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1656         udelay(100);
1657         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1658 }
1659
1660 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1661 {
1662         struct cs4281 *chip = substream->rmidi->private_data;
1663
1664         spin_lock_irq(&chip->reg_lock);
1665         chip->midcr |= BA0_MIDCR_RXE;
1666         chip->midi_input = substream;
1667         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1668                 snd_cs4281_midi_reset(chip);
1669         } else {
1670                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1671         }
1672         spin_unlock_irq(&chip->reg_lock);
1673         return 0;
1674 }
1675
1676 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1677 {
1678         struct cs4281 *chip = substream->rmidi->private_data;
1679
1680         spin_lock_irq(&chip->reg_lock);
1681         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1682         chip->midi_input = NULL;
1683         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1684                 snd_cs4281_midi_reset(chip);
1685         } else {
1686                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1687         }
1688         chip->uartm &= ~CS4281_MODE_INPUT;
1689         spin_unlock_irq(&chip->reg_lock);
1690         return 0;
1691 }
1692
1693 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1694 {
1695         struct cs4281 *chip = substream->rmidi->private_data;
1696
1697         spin_lock_irq(&chip->reg_lock);
1698         chip->uartm |= CS4281_MODE_OUTPUT;
1699         chip->midcr |= BA0_MIDCR_TXE;
1700         chip->midi_output = substream;
1701         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1702                 snd_cs4281_midi_reset(chip);
1703         } else {
1704                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1705         }
1706         spin_unlock_irq(&chip->reg_lock);
1707         return 0;
1708 }
1709
1710 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1711 {
1712         struct cs4281 *chip = substream->rmidi->private_data;
1713
1714         spin_lock_irq(&chip->reg_lock);
1715         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1716         chip->midi_output = NULL;
1717         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1718                 snd_cs4281_midi_reset(chip);
1719         } else {
1720                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1721         }
1722         chip->uartm &= ~CS4281_MODE_OUTPUT;
1723         spin_unlock_irq(&chip->reg_lock);
1724         return 0;
1725 }
1726
1727 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1728 {
1729         unsigned long flags;
1730         struct cs4281 *chip = substream->rmidi->private_data;
1731
1732         spin_lock_irqsave(&chip->reg_lock, flags);
1733         if (up) {
1734                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1735                         chip->midcr |= BA0_MIDCR_RIE;
1736                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1737                 }
1738         } else {
1739                 if (chip->midcr & BA0_MIDCR_RIE) {
1740                         chip->midcr &= ~BA0_MIDCR_RIE;
1741                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1742                 }
1743         }
1744         spin_unlock_irqrestore(&chip->reg_lock, flags);
1745 }
1746
1747 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1748 {
1749         unsigned long flags;
1750         struct cs4281 *chip = substream->rmidi->private_data;
1751         unsigned char byte;
1752
1753         spin_lock_irqsave(&chip->reg_lock, flags);
1754         if (up) {
1755                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1756                         chip->midcr |= BA0_MIDCR_TIE;
1757                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1758                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1759                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1760                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1761                                         chip->midcr &= ~BA0_MIDCR_TIE;
1762                                 } else {
1763                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1764                                 }
1765                         }
1766                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1767                 }
1768         } else {
1769                 if (chip->midcr & BA0_MIDCR_TIE) {
1770                         chip->midcr &= ~BA0_MIDCR_TIE;
1771                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1772                 }
1773         }
1774         spin_unlock_irqrestore(&chip->reg_lock, flags);
1775 }
1776
1777 static struct snd_rawmidi_ops snd_cs4281_midi_output =
1778 {
1779         .open =         snd_cs4281_midi_output_open,
1780         .close =        snd_cs4281_midi_output_close,
1781         .trigger =      snd_cs4281_midi_output_trigger,
1782 };
1783
1784 static struct snd_rawmidi_ops snd_cs4281_midi_input =
1785 {
1786         .open =         snd_cs4281_midi_input_open,
1787         .close =        snd_cs4281_midi_input_close,
1788         .trigger =      snd_cs4281_midi_input_trigger,
1789 };
1790
1791 static int snd_cs4281_midi(struct cs4281 *chip, int device,
1792                            struct snd_rawmidi **rrawmidi)
1793 {
1794         struct snd_rawmidi *rmidi;
1795         int err;
1796
1797         if (rrawmidi)
1798                 *rrawmidi = NULL;
1799         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1800                 return err;
1801         strcpy(rmidi->name, "CS4281");
1802         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1803         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1804         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1805         rmidi->private_data = chip;
1806         chip->rmidi = rmidi;
1807         if (rrawmidi)
1808                 *rrawmidi = rmidi;
1809         return 0;
1810 }
1811
1812 /*
1813  *  Interrupt handler
1814  */
1815
1816 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1817 {
1818         struct cs4281 *chip = dev_id;
1819         unsigned int status, dma, val;
1820         struct cs4281_dma *cdma;
1821
1822         if (chip == NULL)
1823                 return IRQ_NONE;
1824         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1825         if ((status & 0x7fffffff) == 0) {
1826                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1827                 return IRQ_NONE;
1828         }
1829
1830         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1831                 for (dma = 0; dma < 4; dma++)
1832                         if (status & BA0_HISR_DMA(dma)) {
1833                                 cdma = &chip->dma[dma];
1834                                 spin_lock(&chip->reg_lock);
1835                                 /* ack DMA IRQ */
1836                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1837                                 /* workaround, sometimes CS4281 acknowledges */
1838                                 /* end or middle transfer position twice */
1839                                 cdma->frag++;
1840                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1841                                         cdma->frag--;
1842                                         chip->spurious_dhtc_irq++;
1843                                         spin_unlock(&chip->reg_lock);
1844                                         continue;
1845                                 }
1846                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1847                                         cdma->frag--;
1848                                         chip->spurious_dtc_irq++;
1849                                         spin_unlock(&chip->reg_lock);
1850                                         continue;
1851                                 }
1852                                 spin_unlock(&chip->reg_lock);
1853                                 snd_pcm_period_elapsed(cdma->substream);
1854                         }
1855         }
1856
1857         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1858                 unsigned char c;
1859
1860                 spin_lock(&chip->reg_lock);
1861                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1862                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1863                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1864                                 continue;
1865                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1866                 }
1867                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1868                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1869                                 break;
1870                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1871                                 chip->midcr &= ~BA0_MIDCR_TIE;
1872                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1873                                 break;
1874                         }
1875                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1876                 }
1877                 spin_unlock(&chip->reg_lock);
1878         }
1879
1880         /* EOI to the PCI part... reenables interrupts */
1881         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1882
1883         return IRQ_HANDLED;
1884 }
1885
1886
1887 /*
1888  * OPL3 command
1889  */
1890 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1891                                     unsigned char val)
1892 {
1893         unsigned long flags;
1894         struct cs4281 *chip = opl3->private_data;
1895         void __iomem *port;
1896
1897         if (cmd & OPL3_RIGHT)
1898                 port = chip->ba0 + BA0_B1AP; /* right port */
1899         else
1900                 port = chip->ba0 + BA0_B0AP; /* left port */
1901
1902         spin_lock_irqsave(&opl3->reg_lock, flags);
1903
1904         writel((unsigned int)cmd, port);
1905         udelay(10);
1906
1907         writel((unsigned int)val, port + 4);
1908         udelay(30);
1909
1910         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1911 }
1912
1913 static int snd_cs4281_probe(struct pci_dev *pci,
1914                             const struct pci_device_id *pci_id)
1915 {
1916         static int dev;
1917         struct snd_card *card;
1918         struct cs4281 *chip;
1919         struct snd_opl3 *opl3;
1920         int err;
1921
1922         if (dev >= SNDRV_CARDS)
1923                 return -ENODEV;
1924         if (!enable[dev]) {
1925                 dev++;
1926                 return -ENOENT;
1927         }
1928
1929         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1930                            0, &card);
1931         if (err < 0)
1932                 return err;
1933
1934         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1935                 snd_card_free(card);
1936                 return err;
1937         }
1938         card->private_data = chip;
1939
1940         if ((err = snd_cs4281_mixer(chip)) < 0) {
1941                 snd_card_free(card);
1942                 return err;
1943         }
1944         if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1945                 snd_card_free(card);
1946                 return err;
1947         }
1948         if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1949                 snd_card_free(card);
1950                 return err;
1951         }
1952         if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1953                 snd_card_free(card);
1954                 return err;
1955         }
1956         opl3->private_data = chip;
1957         opl3->command = snd_cs4281_opl3_command;
1958         snd_opl3_init(opl3);
1959         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1960                 snd_card_free(card);
1961                 return err;
1962         }
1963         snd_cs4281_create_gameport(chip);
1964         strcpy(card->driver, "CS4281");
1965         strcpy(card->shortname, "Cirrus Logic CS4281");
1966         sprintf(card->longname, "%s at 0x%lx, irq %d",
1967                 card->shortname,
1968                 chip->ba0_addr,
1969                 chip->irq);
1970
1971         if ((err = snd_card_register(card)) < 0) {
1972                 snd_card_free(card);
1973                 return err;
1974         }
1975
1976         pci_set_drvdata(pci, card);
1977         dev++;
1978         return 0;
1979 }
1980
1981 static void snd_cs4281_remove(struct pci_dev *pci)
1982 {
1983         snd_card_free(pci_get_drvdata(pci));
1984 }
1985
1986 /*
1987  * Power Management
1988  */
1989 #ifdef CONFIG_PM_SLEEP
1990
1991 static int saved_regs[SUSPEND_REGISTERS] = {
1992         BA0_JSCTL,
1993         BA0_GPIOR,
1994         BA0_SSCR,
1995         BA0_MIDCR,
1996         BA0_SRCSA,
1997         BA0_PASR,
1998         BA0_CASR,
1999         BA0_DACSR,
2000         BA0_ADCSR,
2001         BA0_FMLVC,
2002         BA0_FMRVC,
2003         BA0_PPLVC,
2004         BA0_PPRVC,
2005 };
2006
2007 #define CLKCR1_CKRA                             0x00010000L
2008
2009 static int cs4281_suspend(struct device *dev)
2010 {
2011         struct pci_dev *pci = to_pci_dev(dev);
2012         struct snd_card *card = dev_get_drvdata(dev);
2013         struct cs4281 *chip = card->private_data;
2014         u32 ulCLK;
2015         unsigned int i;
2016
2017         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2018         snd_pcm_suspend_all(chip->pcm);
2019
2020         snd_ac97_suspend(chip->ac97);
2021         snd_ac97_suspend(chip->ac97_secondary);
2022
2023         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2024         ulCLK |= CLKCR1_CKRA;
2025         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2026
2027         /* Disable interrupts. */
2028         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2029
2030         /* remember the status registers */
2031         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2032                 if (saved_regs[i])
2033                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2034
2035         /* Turn off the serial ports. */
2036         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2037
2038         /* Power off FM, Joystick, AC link, */
2039         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2040
2041         /* DLL off. */
2042         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2043
2044         /* AC link off. */
2045         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2046
2047         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2048         ulCLK &= ~CLKCR1_CKRA;
2049         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2050
2051         pci_disable_device(pci);
2052         pci_save_state(pci);
2053         pci_set_power_state(pci, PCI_D3hot);
2054         return 0;
2055 }
2056
2057 static int cs4281_resume(struct device *dev)
2058 {
2059         struct pci_dev *pci = to_pci_dev(dev);
2060         struct snd_card *card = dev_get_drvdata(dev);
2061         struct cs4281 *chip = card->private_data;
2062         unsigned int i;
2063         u32 ulCLK;
2064
2065         pci_set_power_state(pci, PCI_D0);
2066         pci_restore_state(pci);
2067         if (pci_enable_device(pci) < 0) {
2068                 dev_err(dev, "pci_enable_device failed, disabling device\n");
2069                 snd_card_disconnect(card);
2070                 return -EIO;
2071         }
2072         pci_set_master(pci);
2073
2074         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2075         ulCLK |= CLKCR1_CKRA;
2076         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2077
2078         snd_cs4281_chip_init(chip);
2079
2080         /* restore the status registers */
2081         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2082                 if (saved_regs[i])
2083                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2084
2085         snd_ac97_resume(chip->ac97);
2086         snd_ac97_resume(chip->ac97_secondary);
2087
2088         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2089         ulCLK &= ~CLKCR1_CKRA;
2090         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2091
2092         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2093         return 0;
2094 }
2095
2096 static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2097 #define CS4281_PM_OPS   &cs4281_pm
2098 #else
2099 #define CS4281_PM_OPS   NULL
2100 #endif /* CONFIG_PM_SLEEP */
2101
2102 static struct pci_driver cs4281_driver = {
2103         .name = KBUILD_MODNAME,
2104         .id_table = snd_cs4281_ids,
2105         .probe = snd_cs4281_probe,
2106         .remove = snd_cs4281_remove,
2107         .driver = {
2108                 .pm = CS4281_PM_OPS,
2109         },
2110 };
2111
2112 module_pci_driver(cs4281_driver);