2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
45 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
46 MLX5_QP_OPTPAR_RRE = 1 << 1,
47 MLX5_QP_OPTPAR_RAE = 1 << 2,
48 MLX5_QP_OPTPAR_RWE = 1 << 3,
49 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
50 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
51 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
52 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
53 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
54 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
55 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
56 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
57 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
58 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
59 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
60 MLX5_QP_OPTPAR_SRQN = 1 << 18,
61 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
62 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
63 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
67 MLX5_QP_STATE_RST = 0,
68 MLX5_QP_STATE_INIT = 1,
69 MLX5_QP_STATE_RTR = 2,
70 MLX5_QP_STATE_RTS = 3,
71 MLX5_QP_STATE_SQER = 4,
72 MLX5_QP_STATE_SQD = 5,
73 MLX5_QP_STATE_ERR = 6,
74 MLX5_QP_STATE_SQ_DRAINING = 7,
75 MLX5_QP_STATE_SUSPENDED = 9,
89 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
90 MLX5_QP_ST_RAW_IPV6 = 0xa,
91 MLX5_QP_ST_SNIFFER = 0xb,
92 MLX5_QP_ST_SYNC_UMR = 0xe,
93 MLX5_QP_ST_PTP_1588 = 0xd,
94 MLX5_QP_ST_REG_UMR = 0xc,
99 MLX5_QP_PM_MIGRATED = 0x3,
100 MLX5_QP_PM_ARMED = 0x0,
101 MLX5_QP_PM_REARM = 0x1
105 MLX5_NON_ZERO_RQ = 0 << 24,
106 MLX5_SRQ_RQ = 1 << 24,
107 MLX5_CRQ_RQ = 2 << 24,
108 MLX5_ZERO_LEN_RQ = 3 << 24
113 MLX5_QP_BIT_SRE = 1 << 15,
114 MLX5_QP_BIT_SWE = 1 << 14,
115 MLX5_QP_BIT_SAE = 1 << 13,
117 MLX5_QP_BIT_RRE = 1 << 15,
118 MLX5_QP_BIT_RWE = 1 << 14,
119 MLX5_QP_BIT_RAE = 1 << 13,
120 MLX5_QP_BIT_RIC = 1 << 4,
124 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
125 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
129 MLX5_SEND_WQE_BB = 64,
133 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
134 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
135 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
136 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
137 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
141 MLX5_FENCE_MODE_NONE = 0 << 5,
142 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
143 MLX5_FENCE_MODE_FENCE = 2 << 5,
144 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
145 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
149 MLX5_QP_LAT_SENSITIVE = 1 << 28,
150 MLX5_QP_BLOCK_MCAST = 1 << 30,
151 MLX5_QP_ENABLE_SIG = 1 << 31,
160 MLX5_FLAGS_INLINE = 1<<7,
161 MLX5_FLAGS_CHECK_FREE = 1<<5,
164 struct mlx5_wqe_fmr_seg {
175 struct mlx5_wqe_ctrl_seg {
176 __be32 opmod_idx_opcode;
184 struct mlx5_wqe_xrc_seg {
189 struct mlx5_wqe_masked_atomic_seg {
192 __be64 swap_add_mask;
215 struct mlx5_wqe_datagram_seg {
219 struct mlx5_wqe_raddr_seg {
225 struct mlx5_wqe_atomic_seg {
230 struct mlx5_wqe_data_seg {
236 struct mlx5_wqe_umr_ctrl_seg {
239 __be16 klm_octowords;
240 __be16 bsf_octowords;
245 struct mlx5_seg_set_psv {
249 __be32 transient_sig;
253 struct mlx5_seg_get_psv {
261 struct mlx5_seg_check_psv {
263 __be16 err_coalescing_op;
267 __be16 xport_err_mask;
275 struct mlx5_rwqe_sig {
281 struct mlx5_wqe_signature_seg {
287 struct mlx5_wqe_inline_seg {
292 struct mlx5_bsf_basic {
304 __be32 raw_data_size;
308 struct mlx5_bsf_ext {
309 __be32 t_init_gen_pro_size;
310 __be32 rsvd_epi_size;
314 struct mlx5_bsf_inl {
317 __be64 w_block_format;
320 __be64 m_block_format;
330 struct mlx5_stride_block_entry {
337 struct mlx5_stride_block_ctrl_seg {
338 __be32 bcount_per_cycle;
345 struct mlx5_core_qp {
346 void (*event) (struct mlx5_core_qp *, int);
349 struct completion free;
350 struct mlx5_rsc_debug *dbg;
354 struct mlx5_qp_path {
366 __be32 tclass_flowlabel;
374 struct mlx5_qp_context {
380 __be32 qp_counter_set_usr_page;
382 __be32 log_pg_sz_remote_qpn;
383 struct mlx5_qp_path pri_path;
384 struct mlx5_qp_path alt_path;
387 __be32 next_send_psn;
390 __be32 last_acked_psn;
393 __be32 rnr_nextrecvpsn;
400 __be16 hw_sq_wqe_counter;
401 __be16 sw_sq_wqe_counter;
402 __be16 hw_rcyclic_byte_counter;
403 __be16 hw_rq_counter;
404 __be16 sw_rcyclic_byte_counter;
405 __be16 sw_rq_counter;
410 __be64 dc_access_key;
414 struct mlx5_create_qp_mbox_in {
415 struct mlx5_inbox_hdr hdr;
418 __be32 opt_param_mask;
420 struct mlx5_qp_context ctx;
425 struct mlx5_create_qp_mbox_out {
426 struct mlx5_outbox_hdr hdr;
431 struct mlx5_destroy_qp_mbox_in {
432 struct mlx5_inbox_hdr hdr;
437 struct mlx5_destroy_qp_mbox_out {
438 struct mlx5_outbox_hdr hdr;
442 struct mlx5_modify_qp_mbox_in {
443 struct mlx5_inbox_hdr hdr;
448 struct mlx5_qp_context ctx;
452 struct mlx5_modify_qp_mbox_out {
453 struct mlx5_outbox_hdr hdr;
457 struct mlx5_query_qp_mbox_in {
458 struct mlx5_inbox_hdr hdr;
463 struct mlx5_query_qp_mbox_out {
464 struct mlx5_outbox_hdr hdr;
468 struct mlx5_qp_context ctx;
473 struct mlx5_conf_sqp_mbox_in {
474 struct mlx5_inbox_hdr hdr;
480 struct mlx5_conf_sqp_mbox_out {
481 struct mlx5_outbox_hdr hdr;
485 struct mlx5_alloc_xrcd_mbox_in {
486 struct mlx5_inbox_hdr hdr;
490 struct mlx5_alloc_xrcd_mbox_out {
491 struct mlx5_outbox_hdr hdr;
496 struct mlx5_dealloc_xrcd_mbox_in {
497 struct mlx5_inbox_hdr hdr;
502 struct mlx5_dealloc_xrcd_mbox_out {
503 struct mlx5_outbox_hdr hdr;
507 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
509 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
512 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
514 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
517 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
518 struct mlx5_core_qp *qp,
519 struct mlx5_create_qp_mbox_in *in,
521 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
522 enum mlx5_qp_state new_state,
523 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
524 struct mlx5_core_qp *qp);
525 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
526 struct mlx5_core_qp *qp);
527 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
528 struct mlx5_query_qp_mbox_out *out, int outlen);
530 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
531 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
532 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
533 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
534 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
535 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
537 static inline const char *mlx5_qp_type_str(int type)
540 case MLX5_QP_ST_RC: return "RC";
541 case MLX5_QP_ST_UC: return "C";
542 case MLX5_QP_ST_UD: return "UD";
543 case MLX5_QP_ST_XRC: return "XRC";
544 case MLX5_QP_ST_MLX: return "MLX";
545 case MLX5_QP_ST_QP0: return "QP0";
546 case MLX5_QP_ST_QP1: return "QP1";
547 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
548 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
549 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
550 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
551 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
552 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
553 default: return "Invalid transport type";
557 static inline const char *mlx5_qp_state_str(int state)
560 case MLX5_QP_STATE_RST:
562 case MLX5_QP_STATE_INIT:
564 case MLX5_QP_STATE_RTR:
566 case MLX5_QP_STATE_RTS:
568 case MLX5_QP_STATE_SQER:
570 case MLX5_QP_STATE_SQD:
572 case MLX5_QP_STATE_ERR:
574 case MLX5_QP_STATE_SQ_DRAINING:
575 return "SQ_DRAINING";
576 case MLX5_QP_STATE_SUSPENDED:
578 default: return "Invalid QP state";
582 #endif /* MLX5_QP_H */