2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_CREATE_XRQ = 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
128 MLX5_CMD_OP_QUERY_XRQ = 0x719,
129 MLX5_CMD_OP_ARM_XRQ = 0x71a,
130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
148 MLX5_CMD_OP_ALLOC_PD = 0x800,
149 MLX5_CMD_OP_DEALLOC_PD = 0x801,
150 MLX5_CMD_OP_ALLOC_UAR = 0x802,
151 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
153 MLX5_CMD_OP_ACCESS_REG = 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
155 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
157 MLX5_CMD_OP_MAD_IFC = 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
160 MLX5_CMD_OP_NOP = 0x80d,
161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
175 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
177 MLX5_CMD_OP_CREATE_LAG = 0x840,
178 MLX5_CMD_OP_MODIFY_LAG = 0x841,
179 MLX5_CMD_OP_QUERY_LAG = 0x842,
180 MLX5_CMD_OP_DESTROY_LAG = 0x843,
181 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
182 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
183 MLX5_CMD_OP_CREATE_TIR = 0x900,
184 MLX5_CMD_OP_MODIFY_TIR = 0x901,
185 MLX5_CMD_OP_DESTROY_TIR = 0x902,
186 MLX5_CMD_OP_QUERY_TIR = 0x903,
187 MLX5_CMD_OP_CREATE_SQ = 0x904,
188 MLX5_CMD_OP_MODIFY_SQ = 0x905,
189 MLX5_CMD_OP_DESTROY_SQ = 0x906,
190 MLX5_CMD_OP_QUERY_SQ = 0x907,
191 MLX5_CMD_OP_CREATE_RQ = 0x908,
192 MLX5_CMD_OP_MODIFY_RQ = 0x909,
193 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
194 MLX5_CMD_OP_QUERY_RQ = 0x90b,
195 MLX5_CMD_OP_CREATE_RMP = 0x90c,
196 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
197 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
198 MLX5_CMD_OP_QUERY_RMP = 0x90f,
199 MLX5_CMD_OP_CREATE_TIS = 0x912,
200 MLX5_CMD_OP_MODIFY_TIS = 0x913,
201 MLX5_CMD_OP_DESTROY_TIS = 0x914,
202 MLX5_CMD_OP_QUERY_TIS = 0x915,
203 MLX5_CMD_OP_CREATE_RQT = 0x916,
204 MLX5_CMD_OP_MODIFY_RQT = 0x917,
205 MLX5_CMD_OP_DESTROY_RQT = 0x918,
206 MLX5_CMD_OP_QUERY_RQT = 0x919,
207 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
208 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
209 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
210 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
211 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
212 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
213 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
215 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
216 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
217 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
218 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
219 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
220 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
221 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
222 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
226 struct mlx5_ifc_flow_table_fields_supported_bits {
229 u8 outer_ether_type[0x1];
230 u8 reserved_at_3[0x1];
231 u8 outer_first_prio[0x1];
232 u8 outer_first_cfi[0x1];
233 u8 outer_first_vid[0x1];
234 u8 reserved_at_7[0x1];
235 u8 outer_second_prio[0x1];
236 u8 outer_second_cfi[0x1];
237 u8 outer_second_vid[0x1];
238 u8 reserved_at_b[0x1];
242 u8 outer_ip_protocol[0x1];
243 u8 outer_ip_ecn[0x1];
244 u8 outer_ip_dscp[0x1];
245 u8 outer_udp_sport[0x1];
246 u8 outer_udp_dport[0x1];
247 u8 outer_tcp_sport[0x1];
248 u8 outer_tcp_dport[0x1];
249 u8 outer_tcp_flags[0x1];
250 u8 outer_gre_protocol[0x1];
251 u8 outer_gre_key[0x1];
252 u8 outer_vxlan_vni[0x1];
253 u8 reserved_at_1a[0x5];
254 u8 source_eswitch_port[0x1];
258 u8 inner_ether_type[0x1];
259 u8 reserved_at_23[0x1];
260 u8 inner_first_prio[0x1];
261 u8 inner_first_cfi[0x1];
262 u8 inner_first_vid[0x1];
263 u8 reserved_at_27[0x1];
264 u8 inner_second_prio[0x1];
265 u8 inner_second_cfi[0x1];
266 u8 inner_second_vid[0x1];
267 u8 reserved_at_2b[0x1];
271 u8 inner_ip_protocol[0x1];
272 u8 inner_ip_ecn[0x1];
273 u8 inner_ip_dscp[0x1];
274 u8 inner_udp_sport[0x1];
275 u8 inner_udp_dport[0x1];
276 u8 inner_tcp_sport[0x1];
277 u8 inner_tcp_dport[0x1];
278 u8 inner_tcp_flags[0x1];
279 u8 reserved_at_37[0x9];
281 u8 reserved_at_40[0x40];
284 struct mlx5_ifc_flow_table_prop_layout_bits {
286 u8 reserved_at_1[0x1];
287 u8 flow_counter[0x1];
288 u8 flow_modify_en[0x1];
290 u8 identified_miss_table_mode[0x1];
291 u8 flow_table_modify[0x1];
294 u8 reserved_at_9[0x17];
296 u8 reserved_at_20[0x2];
297 u8 log_max_ft_size[0x6];
298 u8 reserved_at_28[0x10];
299 u8 max_ft_level[0x8];
301 u8 reserved_at_40[0x20];
303 u8 reserved_at_60[0x18];
304 u8 log_max_ft_num[0x8];
306 u8 reserved_at_80[0x18];
307 u8 log_max_destination[0x8];
309 u8 reserved_at_a0[0x18];
310 u8 log_max_flow[0x8];
312 u8 reserved_at_c0[0x40];
314 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
316 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
319 struct mlx5_ifc_odp_per_transport_service_cap_bits {
324 u8 reserved_at_4[0x1];
326 u8 reserved_at_6[0x1a];
329 struct mlx5_ifc_ipv4_layout_bits {
330 u8 reserved_at_0[0x60];
335 struct mlx5_ifc_ipv6_layout_bits {
339 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
340 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
341 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
342 u8 reserved_at_0[0x80];
345 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
362 u8 reserved_at_91[0x1];
364 u8 reserved_at_93[0x4];
370 u8 reserved_at_c0[0x20];
375 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
377 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
380 struct mlx5_ifc_fte_match_set_misc_bits {
381 u8 reserved_at_0[0x8];
384 u8 reserved_at_20[0x10];
385 u8 source_port[0x10];
387 u8 outer_second_prio[0x3];
388 u8 outer_second_cfi[0x1];
389 u8 outer_second_vid[0xc];
390 u8 inner_second_prio[0x3];
391 u8 inner_second_cfi[0x1];
392 u8 inner_second_vid[0xc];
394 u8 outer_second_vlan_tag[0x1];
395 u8 inner_second_vlan_tag[0x1];
396 u8 reserved_at_62[0xe];
397 u8 gre_protocol[0x10];
403 u8 reserved_at_b8[0x8];
405 u8 reserved_at_c0[0x20];
407 u8 reserved_at_e0[0xc];
408 u8 outer_ipv6_flow_label[0x14];
410 u8 reserved_at_100[0xc];
411 u8 inner_ipv6_flow_label[0x14];
413 u8 reserved_at_120[0xe0];
416 struct mlx5_ifc_cmd_pas_bits {
420 u8 reserved_at_34[0xc];
423 struct mlx5_ifc_uint64_bits {
430 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
431 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
432 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
433 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
434 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
435 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
436 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
437 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
438 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
439 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
442 struct mlx5_ifc_ads_bits {
445 u8 reserved_at_2[0xe];
448 u8 reserved_at_20[0x8];
454 u8 reserved_at_45[0x3];
455 u8 src_addr_index[0x8];
456 u8 reserved_at_50[0x4];
460 u8 reserved_at_60[0x4];
464 u8 rgid_rip[16][0x8];
466 u8 reserved_at_100[0x4];
469 u8 reserved_at_106[0x1];
484 struct mlx5_ifc_flow_table_nic_cap_bits {
485 u8 nic_rx_multi_path_tirs[0x1];
486 u8 nic_rx_multi_path_tirs_fts[0x1];
487 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
488 u8 reserved_at_3[0x1fd];
490 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
492 u8 reserved_at_400[0x200];
494 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
498 u8 reserved_at_a00[0x200];
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
502 u8 reserved_at_e00[0x7200];
505 struct mlx5_ifc_flow_table_eswitch_cap_bits {
506 u8 reserved_at_0[0x200];
508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
510 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
514 u8 reserved_at_800[0x7800];
517 struct mlx5_ifc_e_switch_cap_bits {
518 u8 vport_svlan_strip[0x1];
519 u8 vport_cvlan_strip[0x1];
520 u8 vport_svlan_insert[0x1];
521 u8 vport_cvlan_insert_if_not_exist[0x1];
522 u8 vport_cvlan_insert_overwrite[0x1];
523 u8 reserved_at_5[0x19];
524 u8 nic_vport_node_guid_modify[0x1];
525 u8 nic_vport_port_guid_modify[0x1];
527 u8 vxlan_encap_decap[0x1];
528 u8 nvgre_encap_decap[0x1];
529 u8 reserved_at_22[0x9];
530 u8 log_max_encap_headers[0x5];
532 u8 max_encap_header_size[0xa];
534 u8 reserved_40[0x7c0];
538 struct mlx5_ifc_qos_cap_bits {
539 u8 packet_pacing[0x1];
542 u8 packet_pacing_max_rate[0x20];
543 u8 packet_pacing_min_rate[0x20];
545 u8 packet_pacing_rate_table_size[0x10];
546 u8 reserved_3[0x760];
549 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
553 u8 lro_psh_flag[0x1];
554 u8 lro_time_stamp[0x1];
555 u8 reserved_at_5[0x3];
556 u8 self_lb_en_modifiable[0x1];
557 u8 reserved_at_9[0x2];
559 u8 reserved_at_10[0x2];
560 u8 wqe_inline_mode[0x2];
561 u8 rss_ind_tbl_cap[0x4];
564 u8 reserved_at_1a[0x1];
565 u8 tunnel_lso_const_out_ip_id[0x1];
566 u8 reserved_at_1c[0x2];
567 u8 tunnel_statless_gre[0x1];
568 u8 tunnel_stateless_vxlan[0x1];
570 u8 reserved_at_20[0x20];
572 u8 reserved_at_40[0x10];
573 u8 lro_min_mss_size[0x10];
575 u8 reserved_at_60[0x120];
577 u8 lro_timer_supported_periods[4][0x20];
579 u8 reserved_at_200[0x600];
582 struct mlx5_ifc_roce_cap_bits {
584 u8 reserved_at_1[0x1f];
586 u8 reserved_at_20[0x60];
588 u8 reserved_at_80[0xc];
590 u8 reserved_at_90[0x8];
591 u8 roce_version[0x8];
593 u8 reserved_at_a0[0x10];
594 u8 r_roce_dest_udp_port[0x10];
596 u8 r_roce_max_src_udp_port[0x10];
597 u8 r_roce_min_src_udp_port[0x10];
599 u8 reserved_at_e0[0x10];
600 u8 roce_address_table_size[0x10];
602 u8 reserved_at_100[0x700];
606 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
607 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
608 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
609 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
610 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
611 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
612 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
613 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
614 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
618 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
619 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
620 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
621 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
622 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
623 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
624 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
625 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
626 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
629 struct mlx5_ifc_atomic_caps_bits {
630 u8 reserved_at_0[0x40];
632 u8 atomic_req_8B_endianess_mode[0x2];
633 u8 reserved_at_42[0x4];
634 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
636 u8 reserved_at_47[0x19];
638 u8 reserved_at_60[0x20];
640 u8 reserved_at_80[0x10];
641 u8 atomic_operations[0x10];
643 u8 reserved_at_a0[0x10];
644 u8 atomic_size_qp[0x10];
646 u8 reserved_at_c0[0x10];
647 u8 atomic_size_dc[0x10];
649 u8 reserved_at_e0[0x720];
652 struct mlx5_ifc_odp_cap_bits {
653 u8 reserved_at_0[0x40];
656 u8 reserved_at_41[0x1f];
658 u8 reserved_at_60[0x20];
660 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
662 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
664 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
666 u8 reserved_at_e0[0x720];
669 struct mlx5_ifc_calc_op {
670 u8 reserved_at_0[0x10];
671 u8 reserved_at_10[0x9];
672 u8 op_swap_endianness[0x1];
681 struct mlx5_ifc_vector_calc_cap_bits {
683 u8 reserved_at_1[0x1f];
684 u8 reserved_at_20[0x8];
685 u8 max_vec_count[0x8];
686 u8 reserved_at_30[0xd];
687 u8 max_chunk_size[0x3];
688 struct mlx5_ifc_calc_op calc0;
689 struct mlx5_ifc_calc_op calc1;
690 struct mlx5_ifc_calc_op calc2;
691 struct mlx5_ifc_calc_op calc3;
693 u8 reserved_at_e0[0x720];
697 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
698 MLX5_WQ_TYPE_CYCLIC = 0x1,
699 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
703 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
704 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
708 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
709 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
710 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
711 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
712 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
716 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
717 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
718 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
719 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
720 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
721 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
725 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
726 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
730 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
731 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
732 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
736 MLX5_CAP_PORT_TYPE_IB = 0x0,
737 MLX5_CAP_PORT_TYPE_ETH = 0x1,
740 struct mlx5_ifc_cmd_hca_cap_bits {
741 u8 reserved_at_0[0x80];
743 u8 log_max_srq_sz[0x8];
744 u8 log_max_qp_sz[0x8];
745 u8 reserved_at_90[0xb];
748 u8 reserved_at_a0[0xb];
750 u8 reserved_at_b0[0x10];
752 u8 reserved_at_c0[0x8];
753 u8 log_max_cq_sz[0x8];
754 u8 reserved_at_d0[0xb];
757 u8 log_max_eq_sz[0x8];
758 u8 reserved_at_e8[0x2];
759 u8 log_max_mkey[0x6];
760 u8 reserved_at_f0[0xc];
763 u8 max_indirection[0x8];
764 u8 reserved_at_108[0x1];
765 u8 log_max_mrw_sz[0x7];
766 u8 reserved_at_110[0x2];
767 u8 log_max_bsf_list_size[0x6];
768 u8 reserved_at_118[0x2];
769 u8 log_max_klm_list_size[0x6];
771 u8 reserved_at_120[0xa];
772 u8 log_max_ra_req_dc[0x6];
773 u8 reserved_at_130[0xa];
774 u8 log_max_ra_res_dc[0x6];
776 u8 reserved_at_140[0xa];
777 u8 log_max_ra_req_qp[0x6];
778 u8 reserved_at_150[0xa];
779 u8 log_max_ra_res_qp[0x6];
782 u8 cc_query_allowed[0x1];
783 u8 cc_modify_allowed[0x1];
784 u8 reserved_at_163[0xd];
785 u8 gid_table_size[0x10];
787 u8 out_of_seq_cnt[0x1];
788 u8 vport_counters[0x1];
789 u8 retransmission_q_counters[0x1];
790 u8 reserved_at_183[0x1];
791 u8 modify_rq_counter_set_id[0x1];
792 u8 reserved_at_185[0x1];
794 u8 pkey_table_size[0x10];
796 u8 vport_group_manager[0x1];
797 u8 vhca_group_manager[0x1];
800 u8 reserved_at_1a4[0x1];
802 u8 nic_flow_table[0x1];
803 u8 eswitch_flow_table[0x1];
804 u8 early_vf_enable[0x1];
805 u8 reserved_at_1a9[0x2];
806 u8 local_ca_ack_delay[0x5];
807 u8 reserved_at_1af[0x2];
809 u8 reserved_at_1b2[0x1];
810 u8 disable_link_up[0x1];
815 u8 reserved_at_1c0[0x3];
817 u8 reserved_at_1c8[0x4];
819 u8 reserved_at_1d0[0x1];
821 u8 reserved_at_1d2[0x4];
824 u8 reserved_at_1d8[0x1];
833 u8 stat_rate_support[0x10];
834 u8 reserved_at_1f0[0xc];
837 u8 compact_address_vector[0x1];
839 u8 reserved_at_201[0x2];
840 u8 ipoib_basic_offloads[0x1];
841 u8 reserved_at_205[0xa];
842 u8 drain_sigerr[0x1];
843 u8 cmdif_checksum[0x2];
845 u8 reserved_at_213[0x1];
846 u8 wq_signature[0x1];
847 u8 sctr_data_cqe[0x1];
848 u8 reserved_at_216[0x1];
854 u8 eth_net_offloads[0x1];
857 u8 reserved_at_21f[0x1];
861 u8 cq_moderation[0x1];
862 u8 reserved_at_223[0x3];
866 u8 reserved_at_229[0x1];
867 u8 scqe_break_moderation[0x1];
868 u8 cq_period_start_from_cqe[0x1];
870 u8 reserved_at_22d[0x1];
873 u8 umr_ptr_rlky[0x1];
875 u8 reserved_at_232[0x4];
878 u8 set_deth_sqpn[0x1];
879 u8 reserved_at_239[0x3];
885 u8 reserved_at_240[0xa];
887 u8 reserved_at_250[0x8];
891 u8 reserved_at_261[0x1];
892 u8 pad_tx_eth_packet[0x1];
893 u8 reserved_at_263[0x8];
894 u8 log_bf_reg_size[0x5];
896 u8 reserved_at_270[0xb];
898 u8 num_lag_ports[0x4];
900 u8 reserved_at_280[0x10];
901 u8 max_wqe_sz_sq[0x10];
903 u8 reserved_at_2a0[0x10];
904 u8 max_wqe_sz_rq[0x10];
906 u8 reserved_at_2c0[0x10];
907 u8 max_wqe_sz_sq_dc[0x10];
909 u8 reserved_at_2e0[0x7];
912 u8 reserved_at_300[0x18];
915 u8 reserved_at_320[0x3];
916 u8 log_max_transport_domain[0x5];
917 u8 reserved_at_328[0x3];
919 u8 reserved_at_330[0xb];
920 u8 log_max_xrcd[0x5];
922 u8 reserved_at_340[0x8];
923 u8 log_max_flow_counter_bulk[0x8];
924 u8 max_flow_counter[0x10];
927 u8 reserved_at_360[0x3];
929 u8 reserved_at_368[0x3];
931 u8 reserved_at_370[0x3];
933 u8 reserved_at_378[0x3];
936 u8 basic_cyclic_rcv_wqe[0x1];
937 u8 reserved_at_381[0x2];
939 u8 reserved_at_388[0x3];
941 u8 reserved_at_390[0x3];
942 u8 log_max_rqt_size[0x5];
943 u8 reserved_at_398[0x3];
944 u8 log_max_tis_per_sq[0x5];
946 u8 reserved_at_3a0[0x3];
947 u8 log_max_stride_sz_rq[0x5];
948 u8 reserved_at_3a8[0x3];
949 u8 log_min_stride_sz_rq[0x5];
950 u8 reserved_at_3b0[0x3];
951 u8 log_max_stride_sz_sq[0x5];
952 u8 reserved_at_3b8[0x3];
953 u8 log_min_stride_sz_sq[0x5];
955 u8 reserved_at_3c0[0x1b];
956 u8 log_max_wq_sz[0x5];
958 u8 nic_vport_change_event[0x1];
959 u8 reserved_at_3e1[0xa];
960 u8 log_max_vlan_list[0x5];
961 u8 reserved_at_3f0[0x3];
962 u8 log_max_current_mc_list[0x5];
963 u8 reserved_at_3f8[0x3];
964 u8 log_max_current_uc_list[0x5];
966 u8 reserved_at_400[0x80];
968 u8 reserved_at_480[0x3];
969 u8 log_max_l2_table[0x5];
970 u8 reserved_at_488[0x8];
971 u8 log_uar_page_sz[0x10];
973 u8 reserved_at_4a0[0x20];
974 u8 device_frequency_mhz[0x20];
975 u8 device_frequency_khz[0x20];
977 u8 reserved_at_500[0x80];
979 u8 reserved_at_580[0x3f];
980 u8 cqe_compression[0x1];
982 u8 cqe_compression_timeout[0x10];
983 u8 cqe_compression_max_num[0x10];
985 u8 reserved_at_5e0[0x10];
986 u8 tag_matching[0x1];
987 u8 rndv_offload_rc[0x1];
988 u8 rndv_offload_dc[0x1];
989 u8 log_tag_matching_list_sz[0x5];
990 u8 reserved_at_5e8[0x3];
993 u8 reserved_at_5f0[0x200];
996 enum mlx5_flow_destination_type {
997 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
998 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
999 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1001 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1004 struct mlx5_ifc_dest_format_struct_bits {
1005 u8 destination_type[0x8];
1006 u8 destination_id[0x18];
1008 u8 reserved_at_20[0x20];
1011 struct mlx5_ifc_flow_counter_list_bits {
1013 u8 num_of_counters[0xf];
1014 u8 flow_counter_id[0x10];
1016 u8 reserved_at_20[0x20];
1019 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1020 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1021 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1022 u8 reserved_at_0[0x40];
1025 struct mlx5_ifc_fte_match_param_bits {
1026 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1028 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1030 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1032 u8 reserved_at_600[0xa00];
1036 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1037 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1038 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1039 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1040 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1043 struct mlx5_ifc_rx_hash_field_select_bits {
1044 u8 l3_prot_type[0x1];
1045 u8 l4_prot_type[0x1];
1046 u8 selected_fields[0x1e];
1050 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1051 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1055 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1056 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1059 struct mlx5_ifc_wq_bits {
1061 u8 wq_signature[0x1];
1062 u8 end_padding_mode[0x2];
1064 u8 reserved_at_8[0x18];
1066 u8 hds_skip_first_sge[0x1];
1067 u8 log2_hds_buf_size[0x3];
1068 u8 reserved_at_24[0x7];
1069 u8 page_offset[0x5];
1072 u8 reserved_at_40[0x8];
1075 u8 reserved_at_60[0x8];
1080 u8 hw_counter[0x20];
1082 u8 sw_counter[0x20];
1084 u8 reserved_at_100[0xc];
1085 u8 log_wq_stride[0x4];
1086 u8 reserved_at_110[0x3];
1087 u8 log_wq_pg_sz[0x5];
1088 u8 reserved_at_118[0x3];
1091 u8 reserved_at_120[0x15];
1092 u8 log_wqe_num_of_strides[0x3];
1093 u8 two_byte_shift_en[0x1];
1094 u8 reserved_at_139[0x4];
1095 u8 log_wqe_stride_size[0x3];
1097 u8 reserved_at_140[0x4c0];
1099 struct mlx5_ifc_cmd_pas_bits pas[0];
1102 struct mlx5_ifc_rq_num_bits {
1103 u8 reserved_at_0[0x8];
1107 struct mlx5_ifc_mac_address_layout_bits {
1108 u8 reserved_at_0[0x10];
1109 u8 mac_addr_47_32[0x10];
1111 u8 mac_addr_31_0[0x20];
1114 struct mlx5_ifc_vlan_layout_bits {
1115 u8 reserved_at_0[0x14];
1118 u8 reserved_at_20[0x20];
1121 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1122 u8 reserved_at_0[0xa0];
1124 u8 min_time_between_cnps[0x20];
1126 u8 reserved_at_c0[0x12];
1128 u8 reserved_at_d8[0x5];
1129 u8 cnp_802p_prio[0x3];
1131 u8 reserved_at_e0[0x720];
1134 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1135 u8 reserved_at_0[0x60];
1137 u8 reserved_at_60[0x4];
1138 u8 clamp_tgt_rate[0x1];
1139 u8 reserved_at_65[0x3];
1140 u8 clamp_tgt_rate_after_time_inc[0x1];
1141 u8 reserved_at_69[0x17];
1143 u8 reserved_at_80[0x20];
1145 u8 rpg_time_reset[0x20];
1147 u8 rpg_byte_reset[0x20];
1149 u8 rpg_threshold[0x20];
1151 u8 rpg_max_rate[0x20];
1153 u8 rpg_ai_rate[0x20];
1155 u8 rpg_hai_rate[0x20];
1159 u8 rpg_min_dec_fac[0x20];
1161 u8 rpg_min_rate[0x20];
1163 u8 reserved_at_1c0[0xe0];
1165 u8 rate_to_set_on_first_cnp[0x20];
1169 u8 dce_tcp_rtt[0x20];
1171 u8 rate_reduce_monitor_period[0x20];
1173 u8 reserved_at_320[0x20];
1175 u8 initial_alpha_value[0x20];
1177 u8 reserved_at_360[0x4a0];
1180 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1181 u8 reserved_at_0[0x80];
1183 u8 rppp_max_rps[0x20];
1185 u8 rpg_time_reset[0x20];
1187 u8 rpg_byte_reset[0x20];
1189 u8 rpg_threshold[0x20];
1191 u8 rpg_max_rate[0x20];
1193 u8 rpg_ai_rate[0x20];
1195 u8 rpg_hai_rate[0x20];
1199 u8 rpg_min_dec_fac[0x20];
1201 u8 rpg_min_rate[0x20];
1203 u8 reserved_at_1c0[0x640];
1207 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1208 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1209 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1212 struct mlx5_ifc_resize_field_select_bits {
1213 u8 resize_field_select[0x20];
1217 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1218 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1219 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1220 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1223 struct mlx5_ifc_modify_field_select_bits {
1224 u8 modify_field_select[0x20];
1227 struct mlx5_ifc_field_select_r_roce_np_bits {
1228 u8 field_select_r_roce_np[0x20];
1231 struct mlx5_ifc_field_select_r_roce_rp_bits {
1232 u8 field_select_r_roce_rp[0x20];
1236 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1237 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1238 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1239 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1240 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1241 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1242 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1243 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1244 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1245 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1248 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1249 u8 field_select_8021qaurp[0x20];
1252 struct mlx5_ifc_phys_layer_cntrs_bits {
1253 u8 time_since_last_clear_high[0x20];
1255 u8 time_since_last_clear_low[0x20];
1257 u8 symbol_errors_high[0x20];
1259 u8 symbol_errors_low[0x20];
1261 u8 sync_headers_errors_high[0x20];
1263 u8 sync_headers_errors_low[0x20];
1265 u8 edpl_bip_errors_lane0_high[0x20];
1267 u8 edpl_bip_errors_lane0_low[0x20];
1269 u8 edpl_bip_errors_lane1_high[0x20];
1271 u8 edpl_bip_errors_lane1_low[0x20];
1273 u8 edpl_bip_errors_lane2_high[0x20];
1275 u8 edpl_bip_errors_lane2_low[0x20];
1277 u8 edpl_bip_errors_lane3_high[0x20];
1279 u8 edpl_bip_errors_lane3_low[0x20];
1281 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1283 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1285 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1287 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1289 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1291 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1293 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1295 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1297 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1299 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1301 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1303 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1305 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1307 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1309 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1311 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1313 u8 rs_fec_corrected_blocks_high[0x20];
1315 u8 rs_fec_corrected_blocks_low[0x20];
1317 u8 rs_fec_uncorrectable_blocks_high[0x20];
1319 u8 rs_fec_uncorrectable_blocks_low[0x20];
1321 u8 rs_fec_no_errors_blocks_high[0x20];
1323 u8 rs_fec_no_errors_blocks_low[0x20];
1325 u8 rs_fec_single_error_blocks_high[0x20];
1327 u8 rs_fec_single_error_blocks_low[0x20];
1329 u8 rs_fec_corrected_symbols_total_high[0x20];
1331 u8 rs_fec_corrected_symbols_total_low[0x20];
1333 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1335 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1337 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1339 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1341 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1343 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1345 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1347 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1349 u8 link_down_events[0x20];
1351 u8 successful_recovery_events[0x20];
1353 u8 reserved_at_640[0x180];
1356 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1357 u8 symbol_error_counter[0x10];
1359 u8 link_error_recovery_counter[0x8];
1361 u8 link_downed_counter[0x8];
1363 u8 port_rcv_errors[0x10];
1365 u8 port_rcv_remote_physical_errors[0x10];
1367 u8 port_rcv_switch_relay_errors[0x10];
1369 u8 port_xmit_discards[0x10];
1371 u8 port_xmit_constraint_errors[0x8];
1373 u8 port_rcv_constraint_errors[0x8];
1375 u8 reserved_at_70[0x8];
1377 u8 link_overrun_errors[0x8];
1379 u8 reserved_at_80[0x10];
1381 u8 vl_15_dropped[0x10];
1383 u8 reserved_at_a0[0xa0];
1386 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1387 u8 transmit_queue_high[0x20];
1389 u8 transmit_queue_low[0x20];
1391 u8 reserved_at_40[0x780];
1394 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1395 u8 rx_octets_high[0x20];
1397 u8 rx_octets_low[0x20];
1399 u8 reserved_at_40[0xc0];
1401 u8 rx_frames_high[0x20];
1403 u8 rx_frames_low[0x20];
1405 u8 tx_octets_high[0x20];
1407 u8 tx_octets_low[0x20];
1409 u8 reserved_at_180[0xc0];
1411 u8 tx_frames_high[0x20];
1413 u8 tx_frames_low[0x20];
1415 u8 rx_pause_high[0x20];
1417 u8 rx_pause_low[0x20];
1419 u8 rx_pause_duration_high[0x20];
1421 u8 rx_pause_duration_low[0x20];
1423 u8 tx_pause_high[0x20];
1425 u8 tx_pause_low[0x20];
1427 u8 tx_pause_duration_high[0x20];
1429 u8 tx_pause_duration_low[0x20];
1431 u8 rx_pause_transition_high[0x20];
1433 u8 rx_pause_transition_low[0x20];
1435 u8 reserved_at_3c0[0x400];
1438 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1439 u8 port_transmit_wait_high[0x20];
1441 u8 port_transmit_wait_low[0x20];
1443 u8 reserved_at_40[0x780];
1446 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1447 u8 dot3stats_alignment_errors_high[0x20];
1449 u8 dot3stats_alignment_errors_low[0x20];
1451 u8 dot3stats_fcs_errors_high[0x20];
1453 u8 dot3stats_fcs_errors_low[0x20];
1455 u8 dot3stats_single_collision_frames_high[0x20];
1457 u8 dot3stats_single_collision_frames_low[0x20];
1459 u8 dot3stats_multiple_collision_frames_high[0x20];
1461 u8 dot3stats_multiple_collision_frames_low[0x20];
1463 u8 dot3stats_sqe_test_errors_high[0x20];
1465 u8 dot3stats_sqe_test_errors_low[0x20];
1467 u8 dot3stats_deferred_transmissions_high[0x20];
1469 u8 dot3stats_deferred_transmissions_low[0x20];
1471 u8 dot3stats_late_collisions_high[0x20];
1473 u8 dot3stats_late_collisions_low[0x20];
1475 u8 dot3stats_excessive_collisions_high[0x20];
1477 u8 dot3stats_excessive_collisions_low[0x20];
1479 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1481 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1483 u8 dot3stats_carrier_sense_errors_high[0x20];
1485 u8 dot3stats_carrier_sense_errors_low[0x20];
1487 u8 dot3stats_frame_too_longs_high[0x20];
1489 u8 dot3stats_frame_too_longs_low[0x20];
1491 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1493 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1495 u8 dot3stats_symbol_errors_high[0x20];
1497 u8 dot3stats_symbol_errors_low[0x20];
1499 u8 dot3control_in_unknown_opcodes_high[0x20];
1501 u8 dot3control_in_unknown_opcodes_low[0x20];
1503 u8 dot3in_pause_frames_high[0x20];
1505 u8 dot3in_pause_frames_low[0x20];
1507 u8 dot3out_pause_frames_high[0x20];
1509 u8 dot3out_pause_frames_low[0x20];
1511 u8 reserved_at_400[0x3c0];
1514 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1515 u8 ether_stats_drop_events_high[0x20];
1517 u8 ether_stats_drop_events_low[0x20];
1519 u8 ether_stats_octets_high[0x20];
1521 u8 ether_stats_octets_low[0x20];
1523 u8 ether_stats_pkts_high[0x20];
1525 u8 ether_stats_pkts_low[0x20];
1527 u8 ether_stats_broadcast_pkts_high[0x20];
1529 u8 ether_stats_broadcast_pkts_low[0x20];
1531 u8 ether_stats_multicast_pkts_high[0x20];
1533 u8 ether_stats_multicast_pkts_low[0x20];
1535 u8 ether_stats_crc_align_errors_high[0x20];
1537 u8 ether_stats_crc_align_errors_low[0x20];
1539 u8 ether_stats_undersize_pkts_high[0x20];
1541 u8 ether_stats_undersize_pkts_low[0x20];
1543 u8 ether_stats_oversize_pkts_high[0x20];
1545 u8 ether_stats_oversize_pkts_low[0x20];
1547 u8 ether_stats_fragments_high[0x20];
1549 u8 ether_stats_fragments_low[0x20];
1551 u8 ether_stats_jabbers_high[0x20];
1553 u8 ether_stats_jabbers_low[0x20];
1555 u8 ether_stats_collisions_high[0x20];
1557 u8 ether_stats_collisions_low[0x20];
1559 u8 ether_stats_pkts64octets_high[0x20];
1561 u8 ether_stats_pkts64octets_low[0x20];
1563 u8 ether_stats_pkts65to127octets_high[0x20];
1565 u8 ether_stats_pkts65to127octets_low[0x20];
1567 u8 ether_stats_pkts128to255octets_high[0x20];
1569 u8 ether_stats_pkts128to255octets_low[0x20];
1571 u8 ether_stats_pkts256to511octets_high[0x20];
1573 u8 ether_stats_pkts256to511octets_low[0x20];
1575 u8 ether_stats_pkts512to1023octets_high[0x20];
1577 u8 ether_stats_pkts512to1023octets_low[0x20];
1579 u8 ether_stats_pkts1024to1518octets_high[0x20];
1581 u8 ether_stats_pkts1024to1518octets_low[0x20];
1583 u8 ether_stats_pkts1519to2047octets_high[0x20];
1585 u8 ether_stats_pkts1519to2047octets_low[0x20];
1587 u8 ether_stats_pkts2048to4095octets_high[0x20];
1589 u8 ether_stats_pkts2048to4095octets_low[0x20];
1591 u8 ether_stats_pkts4096to8191octets_high[0x20];
1593 u8 ether_stats_pkts4096to8191octets_low[0x20];
1595 u8 ether_stats_pkts8192to10239octets_high[0x20];
1597 u8 ether_stats_pkts8192to10239octets_low[0x20];
1599 u8 reserved_at_540[0x280];
1602 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1603 u8 if_in_octets_high[0x20];
1605 u8 if_in_octets_low[0x20];
1607 u8 if_in_ucast_pkts_high[0x20];
1609 u8 if_in_ucast_pkts_low[0x20];
1611 u8 if_in_discards_high[0x20];
1613 u8 if_in_discards_low[0x20];
1615 u8 if_in_errors_high[0x20];
1617 u8 if_in_errors_low[0x20];
1619 u8 if_in_unknown_protos_high[0x20];
1621 u8 if_in_unknown_protos_low[0x20];
1623 u8 if_out_octets_high[0x20];
1625 u8 if_out_octets_low[0x20];
1627 u8 if_out_ucast_pkts_high[0x20];
1629 u8 if_out_ucast_pkts_low[0x20];
1631 u8 if_out_discards_high[0x20];
1633 u8 if_out_discards_low[0x20];
1635 u8 if_out_errors_high[0x20];
1637 u8 if_out_errors_low[0x20];
1639 u8 if_in_multicast_pkts_high[0x20];
1641 u8 if_in_multicast_pkts_low[0x20];
1643 u8 if_in_broadcast_pkts_high[0x20];
1645 u8 if_in_broadcast_pkts_low[0x20];
1647 u8 if_out_multicast_pkts_high[0x20];
1649 u8 if_out_multicast_pkts_low[0x20];
1651 u8 if_out_broadcast_pkts_high[0x20];
1653 u8 if_out_broadcast_pkts_low[0x20];
1655 u8 reserved_at_340[0x480];
1658 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1659 u8 a_frames_transmitted_ok_high[0x20];
1661 u8 a_frames_transmitted_ok_low[0x20];
1663 u8 a_frames_received_ok_high[0x20];
1665 u8 a_frames_received_ok_low[0x20];
1667 u8 a_frame_check_sequence_errors_high[0x20];
1669 u8 a_frame_check_sequence_errors_low[0x20];
1671 u8 a_alignment_errors_high[0x20];
1673 u8 a_alignment_errors_low[0x20];
1675 u8 a_octets_transmitted_ok_high[0x20];
1677 u8 a_octets_transmitted_ok_low[0x20];
1679 u8 a_octets_received_ok_high[0x20];
1681 u8 a_octets_received_ok_low[0x20];
1683 u8 a_multicast_frames_xmitted_ok_high[0x20];
1685 u8 a_multicast_frames_xmitted_ok_low[0x20];
1687 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1689 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1691 u8 a_multicast_frames_received_ok_high[0x20];
1693 u8 a_multicast_frames_received_ok_low[0x20];
1695 u8 a_broadcast_frames_received_ok_high[0x20];
1697 u8 a_broadcast_frames_received_ok_low[0x20];
1699 u8 a_in_range_length_errors_high[0x20];
1701 u8 a_in_range_length_errors_low[0x20];
1703 u8 a_out_of_range_length_field_high[0x20];
1705 u8 a_out_of_range_length_field_low[0x20];
1707 u8 a_frame_too_long_errors_high[0x20];
1709 u8 a_frame_too_long_errors_low[0x20];
1711 u8 a_symbol_error_during_carrier_high[0x20];
1713 u8 a_symbol_error_during_carrier_low[0x20];
1715 u8 a_mac_control_frames_transmitted_high[0x20];
1717 u8 a_mac_control_frames_transmitted_low[0x20];
1719 u8 a_mac_control_frames_received_high[0x20];
1721 u8 a_mac_control_frames_received_low[0x20];
1723 u8 a_unsupported_opcodes_received_high[0x20];
1725 u8 a_unsupported_opcodes_received_low[0x20];
1727 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1729 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1731 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1733 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1735 u8 reserved_at_4c0[0x300];
1738 struct mlx5_ifc_cmd_inter_comp_event_bits {
1739 u8 command_completion_vector[0x20];
1741 u8 reserved_at_20[0xc0];
1744 struct mlx5_ifc_stall_vl_event_bits {
1745 u8 reserved_at_0[0x18];
1747 u8 reserved_at_19[0x3];
1750 u8 reserved_at_20[0xa0];
1753 struct mlx5_ifc_db_bf_congestion_event_bits {
1754 u8 event_subtype[0x8];
1755 u8 reserved_at_8[0x8];
1756 u8 congestion_level[0x8];
1757 u8 reserved_at_18[0x8];
1759 u8 reserved_at_20[0xa0];
1762 struct mlx5_ifc_gpio_event_bits {
1763 u8 reserved_at_0[0x60];
1765 u8 gpio_event_hi[0x20];
1767 u8 gpio_event_lo[0x20];
1769 u8 reserved_at_a0[0x40];
1772 struct mlx5_ifc_port_state_change_event_bits {
1773 u8 reserved_at_0[0x40];
1776 u8 reserved_at_44[0x1c];
1778 u8 reserved_at_60[0x80];
1781 struct mlx5_ifc_dropped_packet_logged_bits {
1782 u8 reserved_at_0[0xe0];
1786 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1787 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1790 struct mlx5_ifc_cq_error_bits {
1791 u8 reserved_at_0[0x8];
1794 u8 reserved_at_20[0x20];
1796 u8 reserved_at_40[0x18];
1799 u8 reserved_at_60[0x80];
1802 struct mlx5_ifc_rdma_page_fault_event_bits {
1803 u8 bytes_committed[0x20];
1807 u8 reserved_at_40[0x10];
1808 u8 packet_len[0x10];
1810 u8 rdma_op_len[0x20];
1814 u8 reserved_at_c0[0x5];
1821 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1822 u8 bytes_committed[0x20];
1824 u8 reserved_at_20[0x10];
1827 u8 reserved_at_40[0x10];
1830 u8 reserved_at_60[0x60];
1832 u8 reserved_at_c0[0x5];
1839 struct mlx5_ifc_qp_events_bits {
1840 u8 reserved_at_0[0xa0];
1843 u8 reserved_at_a8[0x18];
1845 u8 reserved_at_c0[0x8];
1846 u8 qpn_rqn_sqn[0x18];
1849 struct mlx5_ifc_dct_events_bits {
1850 u8 reserved_at_0[0xc0];
1852 u8 reserved_at_c0[0x8];
1853 u8 dct_number[0x18];
1856 struct mlx5_ifc_comp_event_bits {
1857 u8 reserved_at_0[0xc0];
1859 u8 reserved_at_c0[0x8];
1864 MLX5_QPC_STATE_RST = 0x0,
1865 MLX5_QPC_STATE_INIT = 0x1,
1866 MLX5_QPC_STATE_RTR = 0x2,
1867 MLX5_QPC_STATE_RTS = 0x3,
1868 MLX5_QPC_STATE_SQER = 0x4,
1869 MLX5_QPC_STATE_ERR = 0x6,
1870 MLX5_QPC_STATE_SQD = 0x7,
1871 MLX5_QPC_STATE_SUSPENDED = 0x9,
1875 MLX5_QPC_ST_RC = 0x0,
1876 MLX5_QPC_ST_UC = 0x1,
1877 MLX5_QPC_ST_UD = 0x2,
1878 MLX5_QPC_ST_XRC = 0x3,
1879 MLX5_QPC_ST_DCI = 0x5,
1880 MLX5_QPC_ST_QP0 = 0x7,
1881 MLX5_QPC_ST_QP1 = 0x8,
1882 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1883 MLX5_QPC_ST_REG_UMR = 0xc,
1887 MLX5_QPC_PM_STATE_ARMED = 0x0,
1888 MLX5_QPC_PM_STATE_REARM = 0x1,
1889 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1890 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1894 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1895 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1899 MLX5_QPC_MTU_256_BYTES = 0x1,
1900 MLX5_QPC_MTU_512_BYTES = 0x2,
1901 MLX5_QPC_MTU_1K_BYTES = 0x3,
1902 MLX5_QPC_MTU_2K_BYTES = 0x4,
1903 MLX5_QPC_MTU_4K_BYTES = 0x5,
1904 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1908 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1909 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1910 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1911 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1912 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1913 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1914 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1915 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1919 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1920 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1921 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1925 MLX5_QPC_CS_RES_DISABLE = 0x0,
1926 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1927 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1930 struct mlx5_ifc_qpc_bits {
1932 u8 lag_tx_port_affinity[0x4];
1934 u8 reserved_at_10[0x3];
1936 u8 reserved_at_15[0x7];
1937 u8 end_padding_mode[0x2];
1938 u8 reserved_at_1e[0x2];
1940 u8 wq_signature[0x1];
1941 u8 block_lb_mc[0x1];
1942 u8 atomic_like_write_en[0x1];
1943 u8 latency_sensitive[0x1];
1944 u8 reserved_at_24[0x1];
1945 u8 drain_sigerr[0x1];
1946 u8 reserved_at_26[0x2];
1950 u8 log_msg_max[0x5];
1951 u8 reserved_at_48[0x1];
1952 u8 log_rq_size[0x4];
1953 u8 log_rq_stride[0x3];
1955 u8 log_sq_size[0x4];
1956 u8 reserved_at_55[0x6];
1958 u8 ulp_stateless_offload_mode[0x4];
1960 u8 counter_set_id[0x8];
1963 u8 reserved_at_80[0x8];
1964 u8 user_index[0x18];
1966 u8 reserved_at_a0[0x3];
1967 u8 log_page_size[0x5];
1968 u8 remote_qpn[0x18];
1970 struct mlx5_ifc_ads_bits primary_address_path;
1972 struct mlx5_ifc_ads_bits secondary_address_path;
1974 u8 log_ack_req_freq[0x4];
1975 u8 reserved_at_384[0x4];
1976 u8 log_sra_max[0x3];
1977 u8 reserved_at_38b[0x2];
1978 u8 retry_count[0x3];
1980 u8 reserved_at_393[0x1];
1982 u8 cur_rnr_retry[0x3];
1983 u8 cur_retry_count[0x3];
1984 u8 reserved_at_39b[0x5];
1986 u8 reserved_at_3a0[0x20];
1988 u8 reserved_at_3c0[0x8];
1989 u8 next_send_psn[0x18];
1991 u8 reserved_at_3e0[0x8];
1994 u8 reserved_at_400[0x8];
1997 u8 reserved_at_420[0x20];
1999 u8 reserved_at_440[0x8];
2000 u8 last_acked_psn[0x18];
2002 u8 reserved_at_460[0x8];
2005 u8 reserved_at_480[0x8];
2006 u8 log_rra_max[0x3];
2007 u8 reserved_at_48b[0x1];
2008 u8 atomic_mode[0x4];
2012 u8 reserved_at_493[0x1];
2013 u8 page_offset[0x6];
2014 u8 reserved_at_49a[0x3];
2015 u8 cd_slave_receive[0x1];
2016 u8 cd_slave_send[0x1];
2019 u8 reserved_at_4a0[0x3];
2020 u8 min_rnr_nak[0x5];
2021 u8 next_rcv_psn[0x18];
2023 u8 reserved_at_4c0[0x8];
2026 u8 reserved_at_4e0[0x8];
2033 u8 reserved_at_560[0x5];
2035 u8 srqn_rmpn_xrqn[0x18];
2037 u8 reserved_at_580[0x8];
2040 u8 hw_sq_wqebb_counter[0x10];
2041 u8 sw_sq_wqebb_counter[0x10];
2043 u8 hw_rq_counter[0x20];
2045 u8 sw_rq_counter[0x20];
2047 u8 reserved_at_600[0x20];
2049 u8 reserved_at_620[0xf];
2054 u8 dc_access_key[0x40];
2056 u8 reserved_at_680[0xc0];
2059 struct mlx5_ifc_roce_addr_layout_bits {
2060 u8 source_l3_address[16][0x8];
2062 u8 reserved_at_80[0x3];
2065 u8 source_mac_47_32[0x10];
2067 u8 source_mac_31_0[0x20];
2069 u8 reserved_at_c0[0x14];
2070 u8 roce_l3_type[0x4];
2071 u8 roce_version[0x8];
2073 u8 reserved_at_e0[0x20];
2076 union mlx5_ifc_hca_cap_union_bits {
2077 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2078 struct mlx5_ifc_odp_cap_bits odp_cap;
2079 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2080 struct mlx5_ifc_roce_cap_bits roce_cap;
2081 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2082 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2083 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2084 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2085 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2086 struct mlx5_ifc_qos_cap_bits qos_cap;
2087 u8 reserved_at_0[0x8000];
2091 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2092 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2093 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2094 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2095 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2096 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2099 struct mlx5_ifc_flow_context_bits {
2100 u8 reserved_at_0[0x20];
2104 u8 reserved_at_40[0x8];
2107 u8 reserved_at_60[0x10];
2110 u8 reserved_at_80[0x8];
2111 u8 destination_list_size[0x18];
2113 u8 reserved_at_a0[0x8];
2114 u8 flow_counter_list_size[0x18];
2118 u8 reserved_at_e0[0x120];
2120 struct mlx5_ifc_fte_match_param_bits match_value;
2122 u8 reserved_at_1200[0x600];
2124 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2128 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2129 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2132 struct mlx5_ifc_xrc_srqc_bits {
2134 u8 log_xrc_srq_size[0x4];
2135 u8 reserved_at_8[0x18];
2137 u8 wq_signature[0x1];
2139 u8 reserved_at_22[0x1];
2141 u8 basic_cyclic_rcv_wqe[0x1];
2142 u8 log_rq_stride[0x3];
2145 u8 page_offset[0x6];
2146 u8 reserved_at_46[0x2];
2149 u8 reserved_at_60[0x20];
2151 u8 user_index_equal_xrc_srqn[0x1];
2152 u8 reserved_at_81[0x1];
2153 u8 log_page_size[0x6];
2154 u8 user_index[0x18];
2156 u8 reserved_at_a0[0x20];
2158 u8 reserved_at_c0[0x8];
2164 u8 reserved_at_100[0x40];
2166 u8 db_record_addr_h[0x20];
2168 u8 db_record_addr_l[0x1e];
2169 u8 reserved_at_17e[0x2];
2171 u8 reserved_at_180[0x80];
2174 struct mlx5_ifc_traffic_counter_bits {
2180 struct mlx5_ifc_tisc_bits {
2181 u8 strict_lag_tx_port_affinity[0x1];
2182 u8 reserved_at_1[0x3];
2183 u8 lag_tx_port_affinity[0x04];
2185 u8 reserved_at_8[0x4];
2187 u8 reserved_at_10[0x10];
2189 u8 reserved_at_20[0x100];
2191 u8 reserved_at_120[0x8];
2192 u8 transport_domain[0x18];
2194 u8 reserved_at_140[0x3c0];
2198 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2199 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2203 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2204 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2208 MLX5_RX_HASH_FN_NONE = 0x0,
2209 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2210 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2214 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2215 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2218 struct mlx5_ifc_tirc_bits {
2219 u8 reserved_at_0[0x20];
2222 u8 reserved_at_24[0x1c];
2224 u8 reserved_at_40[0x40];
2226 u8 reserved_at_80[0x4];
2227 u8 lro_timeout_period_usecs[0x10];
2228 u8 lro_enable_mask[0x4];
2229 u8 lro_max_ip_payload_size[0x8];
2231 u8 reserved_at_a0[0x40];
2233 u8 reserved_at_e0[0x8];
2234 u8 inline_rqn[0x18];
2236 u8 rx_hash_symmetric[0x1];
2237 u8 reserved_at_101[0x1];
2238 u8 tunneled_offload_en[0x1];
2239 u8 reserved_at_103[0x5];
2240 u8 indirect_table[0x18];
2243 u8 reserved_at_124[0x2];
2244 u8 self_lb_block[0x2];
2245 u8 transport_domain[0x18];
2247 u8 rx_hash_toeplitz_key[10][0x20];
2249 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2251 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2253 u8 reserved_at_2c0[0x4c0];
2257 MLX5_SRQC_STATE_GOOD = 0x0,
2258 MLX5_SRQC_STATE_ERROR = 0x1,
2261 struct mlx5_ifc_srqc_bits {
2263 u8 log_srq_size[0x4];
2264 u8 reserved_at_8[0x18];
2266 u8 wq_signature[0x1];
2268 u8 reserved_at_22[0x1];
2270 u8 reserved_at_24[0x1];
2271 u8 log_rq_stride[0x3];
2274 u8 page_offset[0x6];
2275 u8 reserved_at_46[0x2];
2278 u8 reserved_at_60[0x20];
2280 u8 reserved_at_80[0x2];
2281 u8 log_page_size[0x6];
2282 u8 reserved_at_88[0x18];
2284 u8 reserved_at_a0[0x20];
2286 u8 reserved_at_c0[0x8];
2292 u8 reserved_at_100[0x40];
2296 u8 reserved_at_180[0x80];
2300 MLX5_SQC_STATE_RST = 0x0,
2301 MLX5_SQC_STATE_RDY = 0x1,
2302 MLX5_SQC_STATE_ERR = 0x3,
2305 struct mlx5_ifc_sqc_bits {
2309 u8 flush_in_error_en[0x1];
2310 u8 reserved_at_4[0x1];
2311 u8 min_wqe_inline_mode[0x3];
2314 u8 reserved_at_d[0x13];
2316 u8 reserved_at_20[0x8];
2317 u8 user_index[0x18];
2319 u8 reserved_at_40[0x8];
2322 u8 reserved_at_60[0x90];
2324 u8 packet_pacing_rate_limit_index[0x10];
2325 u8 tis_lst_sz[0x10];
2326 u8 reserved_at_110[0x10];
2328 u8 reserved_at_120[0x40];
2330 u8 reserved_at_160[0x8];
2333 struct mlx5_ifc_wq_bits wq;
2336 struct mlx5_ifc_rqtc_bits {
2337 u8 reserved_at_0[0xa0];
2339 u8 reserved_at_a0[0x10];
2340 u8 rqt_max_size[0x10];
2342 u8 reserved_at_c0[0x10];
2343 u8 rqt_actual_size[0x10];
2345 u8 reserved_at_e0[0x6a0];
2347 struct mlx5_ifc_rq_num_bits rq_num[0];
2351 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2352 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2356 MLX5_RQC_STATE_RST = 0x0,
2357 MLX5_RQC_STATE_RDY = 0x1,
2358 MLX5_RQC_STATE_ERR = 0x3,
2361 struct mlx5_ifc_rqc_bits {
2363 u8 reserved_at_1[0x1];
2364 u8 scatter_fcs[0x1];
2366 u8 mem_rq_type[0x4];
2368 u8 reserved_at_c[0x1];
2369 u8 flush_in_error_en[0x1];
2370 u8 reserved_at_e[0x12];
2372 u8 reserved_at_20[0x8];
2373 u8 user_index[0x18];
2375 u8 reserved_at_40[0x8];
2378 u8 counter_set_id[0x8];
2379 u8 reserved_at_68[0x18];
2381 u8 reserved_at_80[0x8];
2384 u8 reserved_at_a0[0xe0];
2386 struct mlx5_ifc_wq_bits wq;
2390 MLX5_RMPC_STATE_RDY = 0x1,
2391 MLX5_RMPC_STATE_ERR = 0x3,
2394 struct mlx5_ifc_rmpc_bits {
2395 u8 reserved_at_0[0x8];
2397 u8 reserved_at_c[0x14];
2399 u8 basic_cyclic_rcv_wqe[0x1];
2400 u8 reserved_at_21[0x1f];
2402 u8 reserved_at_40[0x140];
2404 struct mlx5_ifc_wq_bits wq;
2407 struct mlx5_ifc_nic_vport_context_bits {
2408 u8 reserved_at_0[0x5];
2409 u8 min_wqe_inline_mode[0x3];
2410 u8 reserved_at_8[0x17];
2413 u8 arm_change_event[0x1];
2414 u8 reserved_at_21[0x1a];
2415 u8 event_on_mtu[0x1];
2416 u8 event_on_promisc_change[0x1];
2417 u8 event_on_vlan_change[0x1];
2418 u8 event_on_mc_address_change[0x1];
2419 u8 event_on_uc_address_change[0x1];
2421 u8 reserved_at_40[0xf0];
2425 u8 system_image_guid[0x40];
2429 u8 reserved_at_200[0x140];
2430 u8 qkey_violation_counter[0x10];
2431 u8 reserved_at_350[0x430];
2435 u8 promisc_all[0x1];
2436 u8 reserved_at_783[0x2];
2437 u8 allowed_list_type[0x3];
2438 u8 reserved_at_788[0xc];
2439 u8 allowed_list_size[0xc];
2441 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2443 u8 reserved_at_7e0[0x20];
2445 u8 current_uc_mac_address[0][0x40];
2449 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2450 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2451 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2454 struct mlx5_ifc_mkc_bits {
2455 u8 reserved_at_0[0x1];
2457 u8 reserved_at_2[0xd];
2458 u8 small_fence_on_rdma_read_response[0x1];
2465 u8 access_mode[0x2];
2466 u8 reserved_at_18[0x8];
2471 u8 reserved_at_40[0x20];
2476 u8 reserved_at_63[0x2];
2477 u8 expected_sigerr_count[0x1];
2478 u8 reserved_at_66[0x1];
2482 u8 start_addr[0x40];
2486 u8 bsf_octword_size[0x20];
2488 u8 reserved_at_120[0x80];
2490 u8 translations_octword_size[0x20];
2492 u8 reserved_at_1c0[0x1b];
2493 u8 log_page_size[0x5];
2495 u8 reserved_at_1e0[0x20];
2498 struct mlx5_ifc_pkey_bits {
2499 u8 reserved_at_0[0x10];
2503 struct mlx5_ifc_array128_auto_bits {
2504 u8 array128_auto[16][0x8];
2507 struct mlx5_ifc_hca_vport_context_bits {
2508 u8 field_select[0x20];
2510 u8 reserved_at_20[0xe0];
2512 u8 sm_virt_aware[0x1];
2515 u8 grh_required[0x1];
2516 u8 reserved_at_104[0xc];
2517 u8 port_physical_state[0x4];
2518 u8 vport_state_policy[0x4];
2520 u8 vport_state[0x4];
2522 u8 reserved_at_120[0x20];
2524 u8 system_image_guid[0x40];
2532 u8 cap_mask1_field_select[0x20];
2536 u8 cap_mask2_field_select[0x20];
2538 u8 reserved_at_280[0x80];
2541 u8 reserved_at_310[0x4];
2542 u8 init_type_reply[0x4];
2544 u8 subnet_timeout[0x5];
2548 u8 reserved_at_334[0xc];
2550 u8 qkey_violation_counter[0x10];
2551 u8 pkey_violation_counter[0x10];
2553 u8 reserved_at_360[0xca0];
2556 struct mlx5_ifc_esw_vport_context_bits {
2557 u8 reserved_at_0[0x3];
2558 u8 vport_svlan_strip[0x1];
2559 u8 vport_cvlan_strip[0x1];
2560 u8 vport_svlan_insert[0x1];
2561 u8 vport_cvlan_insert[0x2];
2562 u8 reserved_at_8[0x18];
2564 u8 reserved_at_20[0x20];
2573 u8 reserved_at_60[0x7a0];
2577 MLX5_EQC_STATUS_OK = 0x0,
2578 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2582 MLX5_EQC_ST_ARMED = 0x9,
2583 MLX5_EQC_ST_FIRED = 0xa,
2586 struct mlx5_ifc_eqc_bits {
2588 u8 reserved_at_4[0x9];
2591 u8 reserved_at_f[0x5];
2593 u8 reserved_at_18[0x8];
2595 u8 reserved_at_20[0x20];
2597 u8 reserved_at_40[0x14];
2598 u8 page_offset[0x6];
2599 u8 reserved_at_5a[0x6];
2601 u8 reserved_at_60[0x3];
2602 u8 log_eq_size[0x5];
2605 u8 reserved_at_80[0x20];
2607 u8 reserved_at_a0[0x18];
2610 u8 reserved_at_c0[0x3];
2611 u8 log_page_size[0x5];
2612 u8 reserved_at_c8[0x18];
2614 u8 reserved_at_e0[0x60];
2616 u8 reserved_at_140[0x8];
2617 u8 consumer_counter[0x18];
2619 u8 reserved_at_160[0x8];
2620 u8 producer_counter[0x18];
2622 u8 reserved_at_180[0x80];
2626 MLX5_DCTC_STATE_ACTIVE = 0x0,
2627 MLX5_DCTC_STATE_DRAINING = 0x1,
2628 MLX5_DCTC_STATE_DRAINED = 0x2,
2632 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2633 MLX5_DCTC_CS_RES_NA = 0x1,
2634 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2638 MLX5_DCTC_MTU_256_BYTES = 0x1,
2639 MLX5_DCTC_MTU_512_BYTES = 0x2,
2640 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2641 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2642 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2645 struct mlx5_ifc_dctc_bits {
2646 u8 reserved_at_0[0x4];
2648 u8 reserved_at_8[0x18];
2650 u8 reserved_at_20[0x8];
2651 u8 user_index[0x18];
2653 u8 reserved_at_40[0x8];
2656 u8 counter_set_id[0x8];
2657 u8 atomic_mode[0x4];
2661 u8 atomic_like_write_en[0x1];
2662 u8 latency_sensitive[0x1];
2665 u8 reserved_at_73[0xd];
2667 u8 reserved_at_80[0x8];
2669 u8 reserved_at_90[0x3];
2670 u8 min_rnr_nak[0x5];
2671 u8 reserved_at_98[0x8];
2673 u8 reserved_at_a0[0x8];
2676 u8 reserved_at_c0[0x8];
2680 u8 reserved_at_e8[0x4];
2681 u8 flow_label[0x14];
2683 u8 dc_access_key[0x40];
2685 u8 reserved_at_140[0x5];
2688 u8 pkey_index[0x10];
2690 u8 reserved_at_160[0x8];
2691 u8 my_addr_index[0x8];
2692 u8 reserved_at_170[0x8];
2695 u8 dc_access_key_violation_count[0x20];
2697 u8 reserved_at_1a0[0x14];
2703 u8 reserved_at_1c0[0x40];
2707 MLX5_CQC_STATUS_OK = 0x0,
2708 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2709 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2713 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2714 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2718 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2719 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2720 MLX5_CQC_ST_FIRED = 0xa,
2724 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2725 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2726 MLX5_CQ_PERIOD_NUM_MODES
2729 struct mlx5_ifc_cqc_bits {
2731 u8 reserved_at_4[0x4];
2734 u8 reserved_at_c[0x1];
2735 u8 scqe_break_moderation_en[0x1];
2737 u8 cq_period_mode[0x2];
2738 u8 cqe_comp_en[0x1];
2739 u8 mini_cqe_res_format[0x2];
2741 u8 reserved_at_18[0x8];
2743 u8 reserved_at_20[0x20];
2745 u8 reserved_at_40[0x14];
2746 u8 page_offset[0x6];
2747 u8 reserved_at_5a[0x6];
2749 u8 reserved_at_60[0x3];
2750 u8 log_cq_size[0x5];
2753 u8 reserved_at_80[0x4];
2755 u8 cq_max_count[0x10];
2757 u8 reserved_at_a0[0x18];
2760 u8 reserved_at_c0[0x3];
2761 u8 log_page_size[0x5];
2762 u8 reserved_at_c8[0x18];
2764 u8 reserved_at_e0[0x20];
2766 u8 reserved_at_100[0x8];
2767 u8 last_notified_index[0x18];
2769 u8 reserved_at_120[0x8];
2770 u8 last_solicit_index[0x18];
2772 u8 reserved_at_140[0x8];
2773 u8 consumer_counter[0x18];
2775 u8 reserved_at_160[0x8];
2776 u8 producer_counter[0x18];
2778 u8 reserved_at_180[0x40];
2783 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2784 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2785 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2786 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2787 u8 reserved_at_0[0x800];
2790 struct mlx5_ifc_query_adapter_param_block_bits {
2791 u8 reserved_at_0[0xc0];
2793 u8 reserved_at_c0[0x8];
2794 u8 ieee_vendor_id[0x18];
2796 u8 reserved_at_e0[0x10];
2797 u8 vsd_vendor_id[0x10];
2801 u8 vsd_contd_psid[16][0x8];
2805 MLX5_XRQC_STATE_GOOD = 0x0,
2806 MLX5_XRQC_STATE_ERROR = 0x1,
2810 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2811 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2815 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2818 struct mlx5_ifc_tag_matching_topology_context_bits {
2819 u8 log_matching_list_sz[0x4];
2820 u8 reserved_at_4[0xc];
2821 u8 append_next_index[0x10];
2823 u8 sw_phase_cnt[0x10];
2824 u8 hw_phase_cnt[0x10];
2826 u8 reserved_at_40[0x40];
2829 struct mlx5_ifc_xrqc_bits {
2832 u8 reserved_at_5[0xf];
2834 u8 reserved_at_18[0x4];
2837 u8 reserved_at_20[0x8];
2838 u8 user_index[0x18];
2840 u8 reserved_at_40[0x8];
2843 u8 reserved_at_60[0xa0];
2845 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2847 u8 reserved_at_180[0x200];
2849 struct mlx5_ifc_wq_bits wq;
2852 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2853 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2854 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2855 u8 reserved_at_0[0x20];
2858 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2859 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2860 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2861 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2862 u8 reserved_at_0[0x20];
2865 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2866 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2867 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2868 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2869 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2870 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2871 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2872 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2873 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2874 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2875 u8 reserved_at_0[0x7c0];
2878 union mlx5_ifc_event_auto_bits {
2879 struct mlx5_ifc_comp_event_bits comp_event;
2880 struct mlx5_ifc_dct_events_bits dct_events;
2881 struct mlx5_ifc_qp_events_bits qp_events;
2882 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2883 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2884 struct mlx5_ifc_cq_error_bits cq_error;
2885 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2886 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2887 struct mlx5_ifc_gpio_event_bits gpio_event;
2888 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2889 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2890 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2891 u8 reserved_at_0[0xe0];
2894 struct mlx5_ifc_health_buffer_bits {
2895 u8 reserved_at_0[0x100];
2897 u8 assert_existptr[0x20];
2899 u8 assert_callra[0x20];
2901 u8 reserved_at_140[0x40];
2903 u8 fw_version[0x20];
2907 u8 reserved_at_1c0[0x20];
2909 u8 irisc_index[0x8];
2914 struct mlx5_ifc_register_loopback_control_bits {
2916 u8 reserved_at_1[0x7];
2918 u8 reserved_at_10[0x10];
2920 u8 reserved_at_20[0x60];
2923 struct mlx5_ifc_teardown_hca_out_bits {
2925 u8 reserved_at_8[0x18];
2929 u8 reserved_at_40[0x40];
2933 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2934 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2937 struct mlx5_ifc_teardown_hca_in_bits {
2939 u8 reserved_at_10[0x10];
2941 u8 reserved_at_20[0x10];
2944 u8 reserved_at_40[0x10];
2947 u8 reserved_at_60[0x20];
2950 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2952 u8 reserved_at_8[0x18];
2956 u8 reserved_at_40[0x40];
2959 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2961 u8 reserved_at_10[0x10];
2963 u8 reserved_at_20[0x10];
2966 u8 reserved_at_40[0x8];
2969 u8 reserved_at_60[0x20];
2971 u8 opt_param_mask[0x20];
2973 u8 reserved_at_a0[0x20];
2975 struct mlx5_ifc_qpc_bits qpc;
2977 u8 reserved_at_800[0x80];
2980 struct mlx5_ifc_sqd2rts_qp_out_bits {
2982 u8 reserved_at_8[0x18];
2986 u8 reserved_at_40[0x40];
2989 struct mlx5_ifc_sqd2rts_qp_in_bits {
2991 u8 reserved_at_10[0x10];
2993 u8 reserved_at_20[0x10];
2996 u8 reserved_at_40[0x8];
2999 u8 reserved_at_60[0x20];
3001 u8 opt_param_mask[0x20];
3003 u8 reserved_at_a0[0x20];
3005 struct mlx5_ifc_qpc_bits qpc;
3007 u8 reserved_at_800[0x80];
3010 struct mlx5_ifc_set_roce_address_out_bits {
3012 u8 reserved_at_8[0x18];
3016 u8 reserved_at_40[0x40];
3019 struct mlx5_ifc_set_roce_address_in_bits {
3021 u8 reserved_at_10[0x10];
3023 u8 reserved_at_20[0x10];
3026 u8 roce_address_index[0x10];
3027 u8 reserved_at_50[0x10];
3029 u8 reserved_at_60[0x20];
3031 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3034 struct mlx5_ifc_set_mad_demux_out_bits {
3036 u8 reserved_at_8[0x18];
3040 u8 reserved_at_40[0x40];
3044 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3045 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3048 struct mlx5_ifc_set_mad_demux_in_bits {
3050 u8 reserved_at_10[0x10];
3052 u8 reserved_at_20[0x10];
3055 u8 reserved_at_40[0x20];
3057 u8 reserved_at_60[0x6];
3059 u8 reserved_at_68[0x18];
3062 struct mlx5_ifc_set_l2_table_entry_out_bits {
3064 u8 reserved_at_8[0x18];
3068 u8 reserved_at_40[0x40];
3071 struct mlx5_ifc_set_l2_table_entry_in_bits {
3073 u8 reserved_at_10[0x10];
3075 u8 reserved_at_20[0x10];
3078 u8 reserved_at_40[0x60];
3080 u8 reserved_at_a0[0x8];
3081 u8 table_index[0x18];
3083 u8 reserved_at_c0[0x20];
3085 u8 reserved_at_e0[0x13];
3089 struct mlx5_ifc_mac_address_layout_bits mac_address;
3091 u8 reserved_at_140[0xc0];
3094 struct mlx5_ifc_set_issi_out_bits {
3096 u8 reserved_at_8[0x18];
3100 u8 reserved_at_40[0x40];
3103 struct mlx5_ifc_set_issi_in_bits {
3105 u8 reserved_at_10[0x10];
3107 u8 reserved_at_20[0x10];
3110 u8 reserved_at_40[0x10];
3111 u8 current_issi[0x10];
3113 u8 reserved_at_60[0x20];
3116 struct mlx5_ifc_set_hca_cap_out_bits {
3118 u8 reserved_at_8[0x18];
3122 u8 reserved_at_40[0x40];
3125 struct mlx5_ifc_set_hca_cap_in_bits {
3127 u8 reserved_at_10[0x10];
3129 u8 reserved_at_20[0x10];
3132 u8 reserved_at_40[0x40];
3134 union mlx5_ifc_hca_cap_union_bits capability;
3138 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3139 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3140 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3141 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3144 struct mlx5_ifc_set_fte_out_bits {
3146 u8 reserved_at_8[0x18];
3150 u8 reserved_at_40[0x40];
3153 struct mlx5_ifc_set_fte_in_bits {
3155 u8 reserved_at_10[0x10];
3157 u8 reserved_at_20[0x10];
3160 u8 other_vport[0x1];
3161 u8 reserved_at_41[0xf];
3162 u8 vport_number[0x10];
3164 u8 reserved_at_60[0x20];
3167 u8 reserved_at_88[0x18];
3169 u8 reserved_at_a0[0x8];
3172 u8 reserved_at_c0[0x18];
3173 u8 modify_enable_mask[0x8];
3175 u8 reserved_at_e0[0x20];
3177 u8 flow_index[0x20];
3179 u8 reserved_at_120[0xe0];
3181 struct mlx5_ifc_flow_context_bits flow_context;
3184 struct mlx5_ifc_rts2rts_qp_out_bits {
3186 u8 reserved_at_8[0x18];
3190 u8 reserved_at_40[0x40];
3193 struct mlx5_ifc_rts2rts_qp_in_bits {
3195 u8 reserved_at_10[0x10];
3197 u8 reserved_at_20[0x10];
3200 u8 reserved_at_40[0x8];
3203 u8 reserved_at_60[0x20];
3205 u8 opt_param_mask[0x20];
3207 u8 reserved_at_a0[0x20];
3209 struct mlx5_ifc_qpc_bits qpc;
3211 u8 reserved_at_800[0x80];
3214 struct mlx5_ifc_rtr2rts_qp_out_bits {
3216 u8 reserved_at_8[0x18];
3220 u8 reserved_at_40[0x40];
3223 struct mlx5_ifc_rtr2rts_qp_in_bits {
3225 u8 reserved_at_10[0x10];
3227 u8 reserved_at_20[0x10];
3230 u8 reserved_at_40[0x8];
3233 u8 reserved_at_60[0x20];
3235 u8 opt_param_mask[0x20];
3237 u8 reserved_at_a0[0x20];
3239 struct mlx5_ifc_qpc_bits qpc;
3241 u8 reserved_at_800[0x80];
3244 struct mlx5_ifc_rst2init_qp_out_bits {
3246 u8 reserved_at_8[0x18];
3250 u8 reserved_at_40[0x40];
3253 struct mlx5_ifc_rst2init_qp_in_bits {
3255 u8 reserved_at_10[0x10];
3257 u8 reserved_at_20[0x10];
3260 u8 reserved_at_40[0x8];
3263 u8 reserved_at_60[0x20];
3265 u8 opt_param_mask[0x20];
3267 u8 reserved_at_a0[0x20];
3269 struct mlx5_ifc_qpc_bits qpc;
3271 u8 reserved_at_800[0x80];
3274 struct mlx5_ifc_query_xrq_out_bits {
3276 u8 reserved_at_8[0x18];
3280 u8 reserved_at_40[0x40];
3282 struct mlx5_ifc_xrqc_bits xrq_context;
3285 struct mlx5_ifc_query_xrq_in_bits {
3287 u8 reserved_at_10[0x10];
3289 u8 reserved_at_20[0x10];
3292 u8 reserved_at_40[0x8];
3295 u8 reserved_at_60[0x20];
3298 struct mlx5_ifc_query_xrc_srq_out_bits {
3300 u8 reserved_at_8[0x18];
3304 u8 reserved_at_40[0x40];
3306 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3308 u8 reserved_at_280[0x600];
3313 struct mlx5_ifc_query_xrc_srq_in_bits {
3315 u8 reserved_at_10[0x10];
3317 u8 reserved_at_20[0x10];
3320 u8 reserved_at_40[0x8];
3323 u8 reserved_at_60[0x20];
3327 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3328 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3331 struct mlx5_ifc_query_vport_state_out_bits {
3333 u8 reserved_at_8[0x18];
3337 u8 reserved_at_40[0x20];
3339 u8 reserved_at_60[0x18];
3340 u8 admin_state[0x4];
3345 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3346 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3349 struct mlx5_ifc_query_vport_state_in_bits {
3351 u8 reserved_at_10[0x10];
3353 u8 reserved_at_20[0x10];
3356 u8 other_vport[0x1];
3357 u8 reserved_at_41[0xf];
3358 u8 vport_number[0x10];
3360 u8 reserved_at_60[0x20];
3363 struct mlx5_ifc_query_vport_counter_out_bits {
3365 u8 reserved_at_8[0x18];
3369 u8 reserved_at_40[0x40];
3371 struct mlx5_ifc_traffic_counter_bits received_errors;
3373 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3375 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3377 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3379 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3381 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3383 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3385 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3387 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3389 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3391 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3393 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3395 u8 reserved_at_680[0xa00];
3399 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3402 struct mlx5_ifc_query_vport_counter_in_bits {
3404 u8 reserved_at_10[0x10];
3406 u8 reserved_at_20[0x10];
3409 u8 other_vport[0x1];
3410 u8 reserved_at_41[0xb];
3412 u8 vport_number[0x10];
3414 u8 reserved_at_60[0x60];
3417 u8 reserved_at_c1[0x1f];
3419 u8 reserved_at_e0[0x20];
3422 struct mlx5_ifc_query_tis_out_bits {
3424 u8 reserved_at_8[0x18];
3428 u8 reserved_at_40[0x40];
3430 struct mlx5_ifc_tisc_bits tis_context;
3433 struct mlx5_ifc_query_tis_in_bits {
3435 u8 reserved_at_10[0x10];
3437 u8 reserved_at_20[0x10];
3440 u8 reserved_at_40[0x8];
3443 u8 reserved_at_60[0x20];
3446 struct mlx5_ifc_query_tir_out_bits {
3448 u8 reserved_at_8[0x18];
3452 u8 reserved_at_40[0xc0];
3454 struct mlx5_ifc_tirc_bits tir_context;
3457 struct mlx5_ifc_query_tir_in_bits {
3459 u8 reserved_at_10[0x10];
3461 u8 reserved_at_20[0x10];
3464 u8 reserved_at_40[0x8];
3467 u8 reserved_at_60[0x20];
3470 struct mlx5_ifc_query_srq_out_bits {
3472 u8 reserved_at_8[0x18];
3476 u8 reserved_at_40[0x40];
3478 struct mlx5_ifc_srqc_bits srq_context_entry;
3480 u8 reserved_at_280[0x600];
3485 struct mlx5_ifc_query_srq_in_bits {
3487 u8 reserved_at_10[0x10];
3489 u8 reserved_at_20[0x10];
3492 u8 reserved_at_40[0x8];
3495 u8 reserved_at_60[0x20];
3498 struct mlx5_ifc_query_sq_out_bits {
3500 u8 reserved_at_8[0x18];
3504 u8 reserved_at_40[0xc0];
3506 struct mlx5_ifc_sqc_bits sq_context;
3509 struct mlx5_ifc_query_sq_in_bits {
3511 u8 reserved_at_10[0x10];
3513 u8 reserved_at_20[0x10];
3516 u8 reserved_at_40[0x8];
3519 u8 reserved_at_60[0x20];
3522 struct mlx5_ifc_query_special_contexts_out_bits {
3524 u8 reserved_at_8[0x18];
3528 u8 dump_fill_mkey[0x20];
3533 struct mlx5_ifc_query_special_contexts_in_bits {
3535 u8 reserved_at_10[0x10];
3537 u8 reserved_at_20[0x10];
3540 u8 reserved_at_40[0x40];
3543 struct mlx5_ifc_query_rqt_out_bits {
3545 u8 reserved_at_8[0x18];
3549 u8 reserved_at_40[0xc0];
3551 struct mlx5_ifc_rqtc_bits rqt_context;
3554 struct mlx5_ifc_query_rqt_in_bits {
3556 u8 reserved_at_10[0x10];
3558 u8 reserved_at_20[0x10];
3561 u8 reserved_at_40[0x8];
3564 u8 reserved_at_60[0x20];
3567 struct mlx5_ifc_query_rq_out_bits {
3569 u8 reserved_at_8[0x18];
3573 u8 reserved_at_40[0xc0];
3575 struct mlx5_ifc_rqc_bits rq_context;
3578 struct mlx5_ifc_query_rq_in_bits {
3580 u8 reserved_at_10[0x10];
3582 u8 reserved_at_20[0x10];
3585 u8 reserved_at_40[0x8];
3588 u8 reserved_at_60[0x20];
3591 struct mlx5_ifc_query_roce_address_out_bits {
3593 u8 reserved_at_8[0x18];
3597 u8 reserved_at_40[0x40];
3599 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3602 struct mlx5_ifc_query_roce_address_in_bits {
3604 u8 reserved_at_10[0x10];
3606 u8 reserved_at_20[0x10];
3609 u8 roce_address_index[0x10];
3610 u8 reserved_at_50[0x10];
3612 u8 reserved_at_60[0x20];
3615 struct mlx5_ifc_query_rmp_out_bits {
3617 u8 reserved_at_8[0x18];
3621 u8 reserved_at_40[0xc0];
3623 struct mlx5_ifc_rmpc_bits rmp_context;
3626 struct mlx5_ifc_query_rmp_in_bits {
3628 u8 reserved_at_10[0x10];
3630 u8 reserved_at_20[0x10];
3633 u8 reserved_at_40[0x8];
3636 u8 reserved_at_60[0x20];
3639 struct mlx5_ifc_query_qp_out_bits {
3641 u8 reserved_at_8[0x18];
3645 u8 reserved_at_40[0x40];
3647 u8 opt_param_mask[0x20];
3649 u8 reserved_at_a0[0x20];
3651 struct mlx5_ifc_qpc_bits qpc;
3653 u8 reserved_at_800[0x80];
3658 struct mlx5_ifc_query_qp_in_bits {
3660 u8 reserved_at_10[0x10];
3662 u8 reserved_at_20[0x10];
3665 u8 reserved_at_40[0x8];
3668 u8 reserved_at_60[0x20];
3671 struct mlx5_ifc_query_q_counter_out_bits {
3673 u8 reserved_at_8[0x18];
3677 u8 reserved_at_40[0x40];
3679 u8 rx_write_requests[0x20];
3681 u8 reserved_at_a0[0x20];
3683 u8 rx_read_requests[0x20];
3685 u8 reserved_at_e0[0x20];
3687 u8 rx_atomic_requests[0x20];
3689 u8 reserved_at_120[0x20];
3691 u8 rx_dct_connect[0x20];
3693 u8 reserved_at_160[0x20];
3695 u8 out_of_buffer[0x20];
3697 u8 reserved_at_1a0[0x20];
3699 u8 out_of_sequence[0x20];
3701 u8 reserved_at_1e0[0x20];
3703 u8 duplicate_request[0x20];
3705 u8 reserved_at_220[0x20];
3707 u8 rnr_nak_retry_err[0x20];
3709 u8 reserved_at_260[0x20];
3711 u8 packet_seq_err[0x20];
3713 u8 reserved_at_2a0[0x20];
3715 u8 implied_nak_seq_err[0x20];
3717 u8 reserved_at_2e0[0x20];
3719 u8 local_ack_timeout_err[0x20];
3721 u8 reserved_at_320[0x4e0];
3724 struct mlx5_ifc_query_q_counter_in_bits {
3726 u8 reserved_at_10[0x10];
3728 u8 reserved_at_20[0x10];
3731 u8 reserved_at_40[0x80];
3734 u8 reserved_at_c1[0x1f];
3736 u8 reserved_at_e0[0x18];
3737 u8 counter_set_id[0x8];
3740 struct mlx5_ifc_query_pages_out_bits {
3742 u8 reserved_at_8[0x18];
3746 u8 reserved_at_40[0x10];
3747 u8 function_id[0x10];
3753 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3754 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3755 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3758 struct mlx5_ifc_query_pages_in_bits {
3760 u8 reserved_at_10[0x10];
3762 u8 reserved_at_20[0x10];
3765 u8 reserved_at_40[0x10];
3766 u8 function_id[0x10];
3768 u8 reserved_at_60[0x20];
3771 struct mlx5_ifc_query_nic_vport_context_out_bits {
3773 u8 reserved_at_8[0x18];
3777 u8 reserved_at_40[0x40];
3779 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3782 struct mlx5_ifc_query_nic_vport_context_in_bits {
3784 u8 reserved_at_10[0x10];
3786 u8 reserved_at_20[0x10];
3789 u8 other_vport[0x1];
3790 u8 reserved_at_41[0xf];
3791 u8 vport_number[0x10];
3793 u8 reserved_at_60[0x5];
3794 u8 allowed_list_type[0x3];
3795 u8 reserved_at_68[0x18];
3798 struct mlx5_ifc_query_mkey_out_bits {
3800 u8 reserved_at_8[0x18];
3804 u8 reserved_at_40[0x40];
3806 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3808 u8 reserved_at_280[0x600];
3810 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3812 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3815 struct mlx5_ifc_query_mkey_in_bits {
3817 u8 reserved_at_10[0x10];
3819 u8 reserved_at_20[0x10];
3822 u8 reserved_at_40[0x8];
3823 u8 mkey_index[0x18];
3826 u8 reserved_at_61[0x1f];
3829 struct mlx5_ifc_query_mad_demux_out_bits {
3831 u8 reserved_at_8[0x18];
3835 u8 reserved_at_40[0x40];
3837 u8 mad_dumux_parameters_block[0x20];
3840 struct mlx5_ifc_query_mad_demux_in_bits {
3842 u8 reserved_at_10[0x10];
3844 u8 reserved_at_20[0x10];
3847 u8 reserved_at_40[0x40];
3850 struct mlx5_ifc_query_l2_table_entry_out_bits {
3852 u8 reserved_at_8[0x18];
3856 u8 reserved_at_40[0xa0];
3858 u8 reserved_at_e0[0x13];
3862 struct mlx5_ifc_mac_address_layout_bits mac_address;
3864 u8 reserved_at_140[0xc0];
3867 struct mlx5_ifc_query_l2_table_entry_in_bits {
3869 u8 reserved_at_10[0x10];
3871 u8 reserved_at_20[0x10];
3874 u8 reserved_at_40[0x60];
3876 u8 reserved_at_a0[0x8];
3877 u8 table_index[0x18];
3879 u8 reserved_at_c0[0x140];
3882 struct mlx5_ifc_query_issi_out_bits {
3884 u8 reserved_at_8[0x18];
3888 u8 reserved_at_40[0x10];
3889 u8 current_issi[0x10];
3891 u8 reserved_at_60[0xa0];
3893 u8 reserved_at_100[76][0x8];
3894 u8 supported_issi_dw0[0x20];
3897 struct mlx5_ifc_query_issi_in_bits {
3899 u8 reserved_at_10[0x10];
3901 u8 reserved_at_20[0x10];
3904 u8 reserved_at_40[0x40];
3907 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3909 u8 reserved_at_8[0x18];
3913 u8 reserved_at_40[0x40];
3915 struct mlx5_ifc_pkey_bits pkey[0];
3918 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3920 u8 reserved_at_10[0x10];
3922 u8 reserved_at_20[0x10];
3925 u8 other_vport[0x1];
3926 u8 reserved_at_41[0xb];
3928 u8 vport_number[0x10];
3930 u8 reserved_at_60[0x10];
3931 u8 pkey_index[0x10];
3935 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3936 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3937 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3940 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3942 u8 reserved_at_8[0x18];
3946 u8 reserved_at_40[0x20];
3949 u8 reserved_at_70[0x10];
3951 struct mlx5_ifc_array128_auto_bits gid[0];
3954 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3956 u8 reserved_at_10[0x10];
3958 u8 reserved_at_20[0x10];
3961 u8 other_vport[0x1];
3962 u8 reserved_at_41[0xb];
3964 u8 vport_number[0x10];
3966 u8 reserved_at_60[0x10];
3970 struct mlx5_ifc_query_hca_vport_context_out_bits {
3972 u8 reserved_at_8[0x18];
3976 u8 reserved_at_40[0x40];
3978 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3981 struct mlx5_ifc_query_hca_vport_context_in_bits {
3983 u8 reserved_at_10[0x10];
3985 u8 reserved_at_20[0x10];
3988 u8 other_vport[0x1];
3989 u8 reserved_at_41[0xb];
3991 u8 vport_number[0x10];
3993 u8 reserved_at_60[0x20];
3996 struct mlx5_ifc_query_hca_cap_out_bits {
3998 u8 reserved_at_8[0x18];
4002 u8 reserved_at_40[0x40];
4004 union mlx5_ifc_hca_cap_union_bits capability;
4007 struct mlx5_ifc_query_hca_cap_in_bits {
4009 u8 reserved_at_10[0x10];
4011 u8 reserved_at_20[0x10];
4014 u8 reserved_at_40[0x40];
4017 struct mlx5_ifc_query_flow_table_out_bits {
4019 u8 reserved_at_8[0x18];
4023 u8 reserved_at_40[0x80];
4025 u8 reserved_at_c0[0x8];
4027 u8 reserved_at_d0[0x8];
4030 u8 reserved_at_e0[0x120];
4033 struct mlx5_ifc_query_flow_table_in_bits {
4035 u8 reserved_at_10[0x10];
4037 u8 reserved_at_20[0x10];
4040 u8 reserved_at_40[0x40];
4043 u8 reserved_at_88[0x18];
4045 u8 reserved_at_a0[0x8];
4048 u8 reserved_at_c0[0x140];
4051 struct mlx5_ifc_query_fte_out_bits {
4053 u8 reserved_at_8[0x18];
4057 u8 reserved_at_40[0x1c0];
4059 struct mlx5_ifc_flow_context_bits flow_context;
4062 struct mlx5_ifc_query_fte_in_bits {
4064 u8 reserved_at_10[0x10];
4066 u8 reserved_at_20[0x10];
4069 u8 reserved_at_40[0x40];
4072 u8 reserved_at_88[0x18];
4074 u8 reserved_at_a0[0x8];
4077 u8 reserved_at_c0[0x40];
4079 u8 flow_index[0x20];
4081 u8 reserved_at_120[0xe0];
4085 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4086 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4087 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4090 struct mlx5_ifc_query_flow_group_out_bits {
4092 u8 reserved_at_8[0x18];
4096 u8 reserved_at_40[0xa0];
4098 u8 start_flow_index[0x20];
4100 u8 reserved_at_100[0x20];
4102 u8 end_flow_index[0x20];
4104 u8 reserved_at_140[0xa0];
4106 u8 reserved_at_1e0[0x18];
4107 u8 match_criteria_enable[0x8];
4109 struct mlx5_ifc_fte_match_param_bits match_criteria;
4111 u8 reserved_at_1200[0xe00];
4114 struct mlx5_ifc_query_flow_group_in_bits {
4116 u8 reserved_at_10[0x10];
4118 u8 reserved_at_20[0x10];
4121 u8 reserved_at_40[0x40];
4124 u8 reserved_at_88[0x18];
4126 u8 reserved_at_a0[0x8];
4131 u8 reserved_at_e0[0x120];
4134 struct mlx5_ifc_query_flow_counter_out_bits {
4136 u8 reserved_at_8[0x18];
4140 u8 reserved_at_40[0x40];
4142 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4145 struct mlx5_ifc_query_flow_counter_in_bits {
4147 u8 reserved_at_10[0x10];
4149 u8 reserved_at_20[0x10];
4152 u8 reserved_at_40[0x80];
4155 u8 reserved_at_c1[0xf];
4156 u8 num_of_counters[0x10];
4158 u8 reserved_at_e0[0x10];
4159 u8 flow_counter_id[0x10];
4162 struct mlx5_ifc_query_esw_vport_context_out_bits {
4164 u8 reserved_at_8[0x18];
4168 u8 reserved_at_40[0x40];
4170 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4173 struct mlx5_ifc_query_esw_vport_context_in_bits {
4175 u8 reserved_at_10[0x10];
4177 u8 reserved_at_20[0x10];
4180 u8 other_vport[0x1];
4181 u8 reserved_at_41[0xf];
4182 u8 vport_number[0x10];
4184 u8 reserved_at_60[0x20];
4187 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4189 u8 reserved_at_8[0x18];
4193 u8 reserved_at_40[0x40];
4196 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4197 u8 reserved_at_0[0x1c];
4198 u8 vport_cvlan_insert[0x1];
4199 u8 vport_svlan_insert[0x1];
4200 u8 vport_cvlan_strip[0x1];
4201 u8 vport_svlan_strip[0x1];
4204 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4206 u8 reserved_at_10[0x10];
4208 u8 reserved_at_20[0x10];
4211 u8 other_vport[0x1];
4212 u8 reserved_at_41[0xf];
4213 u8 vport_number[0x10];
4215 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4217 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4220 struct mlx5_ifc_query_eq_out_bits {
4222 u8 reserved_at_8[0x18];
4226 u8 reserved_at_40[0x40];
4228 struct mlx5_ifc_eqc_bits eq_context_entry;
4230 u8 reserved_at_280[0x40];
4232 u8 event_bitmask[0x40];
4234 u8 reserved_at_300[0x580];
4239 struct mlx5_ifc_query_eq_in_bits {
4241 u8 reserved_at_10[0x10];
4243 u8 reserved_at_20[0x10];
4246 u8 reserved_at_40[0x18];
4249 u8 reserved_at_60[0x20];
4252 struct mlx5_ifc_encap_header_in_bits {
4253 u8 reserved_at_0[0x5];
4254 u8 header_type[0x3];
4255 u8 reserved_at_8[0xe];
4256 u8 encap_header_size[0xa];
4258 u8 reserved_at_20[0x10];
4259 u8 encap_header[2][0x8];
4261 u8 more_encap_header[0][0x8];
4264 struct mlx5_ifc_query_encap_header_out_bits {
4266 u8 reserved_at_8[0x18];
4270 u8 reserved_at_40[0xa0];
4272 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4275 struct mlx5_ifc_query_encap_header_in_bits {
4277 u8 reserved_at_10[0x10];
4279 u8 reserved_at_20[0x10];
4284 u8 reserved_at_60[0xa0];
4287 struct mlx5_ifc_alloc_encap_header_out_bits {
4289 u8 reserved_at_8[0x18];
4295 u8 reserved_at_60[0x20];
4298 struct mlx5_ifc_alloc_encap_header_in_bits {
4300 u8 reserved_at_10[0x10];
4302 u8 reserved_at_20[0x10];
4305 u8 reserved_at_40[0xa0];
4307 struct mlx5_ifc_encap_header_in_bits encap_header;
4310 struct mlx5_ifc_dealloc_encap_header_out_bits {
4312 u8 reserved_at_8[0x18];
4316 u8 reserved_at_40[0x40];
4319 struct mlx5_ifc_dealloc_encap_header_in_bits {
4321 u8 reserved_at_10[0x10];
4323 u8 reserved_20[0x10];
4328 u8 reserved_60[0x20];
4331 struct mlx5_ifc_query_dct_out_bits {
4333 u8 reserved_at_8[0x18];
4337 u8 reserved_at_40[0x40];
4339 struct mlx5_ifc_dctc_bits dct_context_entry;
4341 u8 reserved_at_280[0x180];
4344 struct mlx5_ifc_query_dct_in_bits {
4346 u8 reserved_at_10[0x10];
4348 u8 reserved_at_20[0x10];
4351 u8 reserved_at_40[0x8];
4354 u8 reserved_at_60[0x20];
4357 struct mlx5_ifc_query_cq_out_bits {
4359 u8 reserved_at_8[0x18];
4363 u8 reserved_at_40[0x40];
4365 struct mlx5_ifc_cqc_bits cq_context;
4367 u8 reserved_at_280[0x600];
4372 struct mlx5_ifc_query_cq_in_bits {
4374 u8 reserved_at_10[0x10];
4376 u8 reserved_at_20[0x10];
4379 u8 reserved_at_40[0x8];
4382 u8 reserved_at_60[0x20];
4385 struct mlx5_ifc_query_cong_status_out_bits {
4387 u8 reserved_at_8[0x18];
4391 u8 reserved_at_40[0x20];
4395 u8 reserved_at_62[0x1e];
4398 struct mlx5_ifc_query_cong_status_in_bits {
4400 u8 reserved_at_10[0x10];
4402 u8 reserved_at_20[0x10];
4405 u8 reserved_at_40[0x18];
4407 u8 cong_protocol[0x4];
4409 u8 reserved_at_60[0x20];
4412 struct mlx5_ifc_query_cong_statistics_out_bits {
4414 u8 reserved_at_8[0x18];
4418 u8 reserved_at_40[0x40];
4424 u8 cnp_ignored_high[0x20];
4426 u8 cnp_ignored_low[0x20];
4428 u8 cnp_handled_high[0x20];
4430 u8 cnp_handled_low[0x20];
4432 u8 reserved_at_140[0x100];
4434 u8 time_stamp_high[0x20];
4436 u8 time_stamp_low[0x20];
4438 u8 accumulators_period[0x20];
4440 u8 ecn_marked_roce_packets_high[0x20];
4442 u8 ecn_marked_roce_packets_low[0x20];
4444 u8 cnps_sent_high[0x20];
4446 u8 cnps_sent_low[0x20];
4448 u8 reserved_at_320[0x560];
4451 struct mlx5_ifc_query_cong_statistics_in_bits {
4453 u8 reserved_at_10[0x10];
4455 u8 reserved_at_20[0x10];
4459 u8 reserved_at_41[0x1f];
4461 u8 reserved_at_60[0x20];
4464 struct mlx5_ifc_query_cong_params_out_bits {
4466 u8 reserved_at_8[0x18];
4470 u8 reserved_at_40[0x40];
4472 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4475 struct mlx5_ifc_query_cong_params_in_bits {
4477 u8 reserved_at_10[0x10];
4479 u8 reserved_at_20[0x10];
4482 u8 reserved_at_40[0x1c];
4483 u8 cong_protocol[0x4];
4485 u8 reserved_at_60[0x20];
4488 struct mlx5_ifc_query_adapter_out_bits {
4490 u8 reserved_at_8[0x18];
4494 u8 reserved_at_40[0x40];
4496 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4499 struct mlx5_ifc_query_adapter_in_bits {
4501 u8 reserved_at_10[0x10];
4503 u8 reserved_at_20[0x10];
4506 u8 reserved_at_40[0x40];
4509 struct mlx5_ifc_qp_2rst_out_bits {
4511 u8 reserved_at_8[0x18];
4515 u8 reserved_at_40[0x40];
4518 struct mlx5_ifc_qp_2rst_in_bits {
4520 u8 reserved_at_10[0x10];
4522 u8 reserved_at_20[0x10];
4525 u8 reserved_at_40[0x8];
4528 u8 reserved_at_60[0x20];
4531 struct mlx5_ifc_qp_2err_out_bits {
4533 u8 reserved_at_8[0x18];
4537 u8 reserved_at_40[0x40];
4540 struct mlx5_ifc_qp_2err_in_bits {
4542 u8 reserved_at_10[0x10];
4544 u8 reserved_at_20[0x10];
4547 u8 reserved_at_40[0x8];
4550 u8 reserved_at_60[0x20];
4553 struct mlx5_ifc_page_fault_resume_out_bits {
4555 u8 reserved_at_8[0x18];
4559 u8 reserved_at_40[0x40];
4562 struct mlx5_ifc_page_fault_resume_in_bits {
4564 u8 reserved_at_10[0x10];
4566 u8 reserved_at_20[0x10];
4570 u8 reserved_at_41[0x4];
4576 u8 reserved_at_60[0x20];
4579 struct mlx5_ifc_nop_out_bits {
4581 u8 reserved_at_8[0x18];
4585 u8 reserved_at_40[0x40];
4588 struct mlx5_ifc_nop_in_bits {
4590 u8 reserved_at_10[0x10];
4592 u8 reserved_at_20[0x10];
4595 u8 reserved_at_40[0x40];
4598 struct mlx5_ifc_modify_vport_state_out_bits {
4600 u8 reserved_at_8[0x18];
4604 u8 reserved_at_40[0x40];
4607 struct mlx5_ifc_modify_vport_state_in_bits {
4609 u8 reserved_at_10[0x10];
4611 u8 reserved_at_20[0x10];
4614 u8 other_vport[0x1];
4615 u8 reserved_at_41[0xf];
4616 u8 vport_number[0x10];
4618 u8 reserved_at_60[0x18];
4619 u8 admin_state[0x4];
4620 u8 reserved_at_7c[0x4];
4623 struct mlx5_ifc_modify_tis_out_bits {
4625 u8 reserved_at_8[0x18];
4629 u8 reserved_at_40[0x40];
4632 struct mlx5_ifc_modify_tis_bitmask_bits {
4633 u8 reserved_at_0[0x20];
4635 u8 reserved_at_20[0x1d];
4636 u8 lag_tx_port_affinity[0x1];
4637 u8 strict_lag_tx_port_affinity[0x1];
4641 struct mlx5_ifc_modify_tis_in_bits {
4643 u8 reserved_at_10[0x10];
4645 u8 reserved_at_20[0x10];
4648 u8 reserved_at_40[0x8];
4651 u8 reserved_at_60[0x20];
4653 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4655 u8 reserved_at_c0[0x40];
4657 struct mlx5_ifc_tisc_bits ctx;
4660 struct mlx5_ifc_modify_tir_bitmask_bits {
4661 u8 reserved_at_0[0x20];
4663 u8 reserved_at_20[0x1b];
4665 u8 reserved_at_3c[0x1];
4667 u8 reserved_at_3e[0x1];
4671 struct mlx5_ifc_modify_tir_out_bits {
4673 u8 reserved_at_8[0x18];
4677 u8 reserved_at_40[0x40];
4680 struct mlx5_ifc_modify_tir_in_bits {
4682 u8 reserved_at_10[0x10];
4684 u8 reserved_at_20[0x10];
4687 u8 reserved_at_40[0x8];
4690 u8 reserved_at_60[0x20];
4692 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4694 u8 reserved_at_c0[0x40];
4696 struct mlx5_ifc_tirc_bits ctx;
4699 struct mlx5_ifc_modify_sq_out_bits {
4701 u8 reserved_at_8[0x18];
4705 u8 reserved_at_40[0x40];
4708 struct mlx5_ifc_modify_sq_in_bits {
4710 u8 reserved_at_10[0x10];
4712 u8 reserved_at_20[0x10];
4716 u8 reserved_at_44[0x4];
4719 u8 reserved_at_60[0x20];
4721 u8 modify_bitmask[0x40];
4723 u8 reserved_at_c0[0x40];
4725 struct mlx5_ifc_sqc_bits ctx;
4728 struct mlx5_ifc_modify_rqt_out_bits {
4730 u8 reserved_at_8[0x18];
4734 u8 reserved_at_40[0x40];
4737 struct mlx5_ifc_rqt_bitmask_bits {
4738 u8 reserved_at_0[0x20];
4740 u8 reserved_at_20[0x1f];
4744 struct mlx5_ifc_modify_rqt_in_bits {
4746 u8 reserved_at_10[0x10];
4748 u8 reserved_at_20[0x10];
4751 u8 reserved_at_40[0x8];
4754 u8 reserved_at_60[0x20];
4756 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4758 u8 reserved_at_c0[0x40];
4760 struct mlx5_ifc_rqtc_bits ctx;
4763 struct mlx5_ifc_modify_rq_out_bits {
4765 u8 reserved_at_8[0x18];
4769 u8 reserved_at_40[0x40];
4773 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4774 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4777 struct mlx5_ifc_modify_rq_in_bits {
4779 u8 reserved_at_10[0x10];
4781 u8 reserved_at_20[0x10];
4785 u8 reserved_at_44[0x4];
4788 u8 reserved_at_60[0x20];
4790 u8 modify_bitmask[0x40];
4792 u8 reserved_at_c0[0x40];
4794 struct mlx5_ifc_rqc_bits ctx;
4797 struct mlx5_ifc_modify_rmp_out_bits {
4799 u8 reserved_at_8[0x18];
4803 u8 reserved_at_40[0x40];
4806 struct mlx5_ifc_rmp_bitmask_bits {
4807 u8 reserved_at_0[0x20];
4809 u8 reserved_at_20[0x1f];
4813 struct mlx5_ifc_modify_rmp_in_bits {
4815 u8 reserved_at_10[0x10];
4817 u8 reserved_at_20[0x10];
4821 u8 reserved_at_44[0x4];
4824 u8 reserved_at_60[0x20];
4826 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4828 u8 reserved_at_c0[0x40];
4830 struct mlx5_ifc_rmpc_bits ctx;
4833 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4835 u8 reserved_at_8[0x18];
4839 u8 reserved_at_40[0x40];
4842 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4843 u8 reserved_at_0[0x16];
4848 u8 change_event[0x1];
4850 u8 permanent_address[0x1];
4851 u8 addresses_list[0x1];
4853 u8 reserved_at_1f[0x1];
4856 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4858 u8 reserved_at_10[0x10];
4860 u8 reserved_at_20[0x10];
4863 u8 other_vport[0x1];
4864 u8 reserved_at_41[0xf];
4865 u8 vport_number[0x10];
4867 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4869 u8 reserved_at_80[0x780];
4871 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4874 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4876 u8 reserved_at_8[0x18];
4880 u8 reserved_at_40[0x40];
4883 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4885 u8 reserved_at_10[0x10];
4887 u8 reserved_at_20[0x10];
4890 u8 other_vport[0x1];
4891 u8 reserved_at_41[0xb];
4893 u8 vport_number[0x10];
4895 u8 reserved_at_60[0x20];
4897 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4900 struct mlx5_ifc_modify_cq_out_bits {
4902 u8 reserved_at_8[0x18];
4906 u8 reserved_at_40[0x40];
4910 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4911 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4914 struct mlx5_ifc_modify_cq_in_bits {
4916 u8 reserved_at_10[0x10];
4918 u8 reserved_at_20[0x10];
4921 u8 reserved_at_40[0x8];
4924 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4926 struct mlx5_ifc_cqc_bits cq_context;
4928 u8 reserved_at_280[0x600];
4933 struct mlx5_ifc_modify_cong_status_out_bits {
4935 u8 reserved_at_8[0x18];
4939 u8 reserved_at_40[0x40];
4942 struct mlx5_ifc_modify_cong_status_in_bits {
4944 u8 reserved_at_10[0x10];
4946 u8 reserved_at_20[0x10];
4949 u8 reserved_at_40[0x18];
4951 u8 cong_protocol[0x4];
4955 u8 reserved_at_62[0x1e];
4958 struct mlx5_ifc_modify_cong_params_out_bits {
4960 u8 reserved_at_8[0x18];
4964 u8 reserved_at_40[0x40];
4967 struct mlx5_ifc_modify_cong_params_in_bits {
4969 u8 reserved_at_10[0x10];
4971 u8 reserved_at_20[0x10];
4974 u8 reserved_at_40[0x1c];
4975 u8 cong_protocol[0x4];
4977 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4979 u8 reserved_at_80[0x80];
4981 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4984 struct mlx5_ifc_manage_pages_out_bits {
4986 u8 reserved_at_8[0x18];
4990 u8 output_num_entries[0x20];
4992 u8 reserved_at_60[0x20];
4998 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4999 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5000 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5003 struct mlx5_ifc_manage_pages_in_bits {
5005 u8 reserved_at_10[0x10];
5007 u8 reserved_at_20[0x10];
5010 u8 reserved_at_40[0x10];
5011 u8 function_id[0x10];
5013 u8 input_num_entries[0x20];
5018 struct mlx5_ifc_mad_ifc_out_bits {
5020 u8 reserved_at_8[0x18];
5024 u8 reserved_at_40[0x40];
5026 u8 response_mad_packet[256][0x8];
5029 struct mlx5_ifc_mad_ifc_in_bits {
5031 u8 reserved_at_10[0x10];
5033 u8 reserved_at_20[0x10];
5036 u8 remote_lid[0x10];
5037 u8 reserved_at_50[0x8];
5040 u8 reserved_at_60[0x20];
5045 struct mlx5_ifc_init_hca_out_bits {
5047 u8 reserved_at_8[0x18];
5051 u8 reserved_at_40[0x40];
5054 struct mlx5_ifc_init_hca_in_bits {
5056 u8 reserved_at_10[0x10];
5058 u8 reserved_at_20[0x10];
5061 u8 reserved_at_40[0x40];
5064 struct mlx5_ifc_init2rtr_qp_out_bits {
5066 u8 reserved_at_8[0x18];
5070 u8 reserved_at_40[0x40];
5073 struct mlx5_ifc_init2rtr_qp_in_bits {
5075 u8 reserved_at_10[0x10];
5077 u8 reserved_at_20[0x10];
5080 u8 reserved_at_40[0x8];
5083 u8 reserved_at_60[0x20];
5085 u8 opt_param_mask[0x20];
5087 u8 reserved_at_a0[0x20];
5089 struct mlx5_ifc_qpc_bits qpc;
5091 u8 reserved_at_800[0x80];
5094 struct mlx5_ifc_init2init_qp_out_bits {
5096 u8 reserved_at_8[0x18];
5100 u8 reserved_at_40[0x40];
5103 struct mlx5_ifc_init2init_qp_in_bits {
5105 u8 reserved_at_10[0x10];
5107 u8 reserved_at_20[0x10];
5110 u8 reserved_at_40[0x8];
5113 u8 reserved_at_60[0x20];
5115 u8 opt_param_mask[0x20];
5117 u8 reserved_at_a0[0x20];
5119 struct mlx5_ifc_qpc_bits qpc;
5121 u8 reserved_at_800[0x80];
5124 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5126 u8 reserved_at_8[0x18];
5130 u8 reserved_at_40[0x40];
5132 u8 packet_headers_log[128][0x8];
5134 u8 packet_syndrome[64][0x8];
5137 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5139 u8 reserved_at_10[0x10];
5141 u8 reserved_at_20[0x10];
5144 u8 reserved_at_40[0x40];
5147 struct mlx5_ifc_gen_eqe_in_bits {
5149 u8 reserved_at_10[0x10];
5151 u8 reserved_at_20[0x10];
5154 u8 reserved_at_40[0x18];
5157 u8 reserved_at_60[0x20];
5162 struct mlx5_ifc_gen_eq_out_bits {
5164 u8 reserved_at_8[0x18];
5168 u8 reserved_at_40[0x40];
5171 struct mlx5_ifc_enable_hca_out_bits {
5173 u8 reserved_at_8[0x18];
5177 u8 reserved_at_40[0x20];
5180 struct mlx5_ifc_enable_hca_in_bits {
5182 u8 reserved_at_10[0x10];
5184 u8 reserved_at_20[0x10];
5187 u8 reserved_at_40[0x10];
5188 u8 function_id[0x10];
5190 u8 reserved_at_60[0x20];
5193 struct mlx5_ifc_drain_dct_out_bits {
5195 u8 reserved_at_8[0x18];
5199 u8 reserved_at_40[0x40];
5202 struct mlx5_ifc_drain_dct_in_bits {
5204 u8 reserved_at_10[0x10];
5206 u8 reserved_at_20[0x10];
5209 u8 reserved_at_40[0x8];
5212 u8 reserved_at_60[0x20];
5215 struct mlx5_ifc_disable_hca_out_bits {
5217 u8 reserved_at_8[0x18];
5221 u8 reserved_at_40[0x20];
5224 struct mlx5_ifc_disable_hca_in_bits {
5226 u8 reserved_at_10[0x10];
5228 u8 reserved_at_20[0x10];
5231 u8 reserved_at_40[0x10];
5232 u8 function_id[0x10];
5234 u8 reserved_at_60[0x20];
5237 struct mlx5_ifc_detach_from_mcg_out_bits {
5239 u8 reserved_at_8[0x18];
5243 u8 reserved_at_40[0x40];
5246 struct mlx5_ifc_detach_from_mcg_in_bits {
5248 u8 reserved_at_10[0x10];
5250 u8 reserved_at_20[0x10];
5253 u8 reserved_at_40[0x8];
5256 u8 reserved_at_60[0x20];
5258 u8 multicast_gid[16][0x8];
5261 struct mlx5_ifc_destroy_xrq_out_bits {
5263 u8 reserved_at_8[0x18];
5267 u8 reserved_at_40[0x40];
5270 struct mlx5_ifc_destroy_xrq_in_bits {
5272 u8 reserved_at_10[0x10];
5274 u8 reserved_at_20[0x10];
5277 u8 reserved_at_40[0x8];
5280 u8 reserved_at_60[0x20];
5283 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5285 u8 reserved_at_8[0x18];
5289 u8 reserved_at_40[0x40];
5292 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5294 u8 reserved_at_10[0x10];
5296 u8 reserved_at_20[0x10];
5299 u8 reserved_at_40[0x8];
5302 u8 reserved_at_60[0x20];
5305 struct mlx5_ifc_destroy_tis_out_bits {
5307 u8 reserved_at_8[0x18];
5311 u8 reserved_at_40[0x40];
5314 struct mlx5_ifc_destroy_tis_in_bits {
5316 u8 reserved_at_10[0x10];
5318 u8 reserved_at_20[0x10];
5321 u8 reserved_at_40[0x8];
5324 u8 reserved_at_60[0x20];
5327 struct mlx5_ifc_destroy_tir_out_bits {
5329 u8 reserved_at_8[0x18];
5333 u8 reserved_at_40[0x40];
5336 struct mlx5_ifc_destroy_tir_in_bits {
5338 u8 reserved_at_10[0x10];
5340 u8 reserved_at_20[0x10];
5343 u8 reserved_at_40[0x8];
5346 u8 reserved_at_60[0x20];
5349 struct mlx5_ifc_destroy_srq_out_bits {
5351 u8 reserved_at_8[0x18];
5355 u8 reserved_at_40[0x40];
5358 struct mlx5_ifc_destroy_srq_in_bits {
5360 u8 reserved_at_10[0x10];
5362 u8 reserved_at_20[0x10];
5365 u8 reserved_at_40[0x8];
5368 u8 reserved_at_60[0x20];
5371 struct mlx5_ifc_destroy_sq_out_bits {
5373 u8 reserved_at_8[0x18];
5377 u8 reserved_at_40[0x40];
5380 struct mlx5_ifc_destroy_sq_in_bits {
5382 u8 reserved_at_10[0x10];
5384 u8 reserved_at_20[0x10];
5387 u8 reserved_at_40[0x8];
5390 u8 reserved_at_60[0x20];
5393 struct mlx5_ifc_destroy_rqt_out_bits {
5395 u8 reserved_at_8[0x18];
5399 u8 reserved_at_40[0x40];
5402 struct mlx5_ifc_destroy_rqt_in_bits {
5404 u8 reserved_at_10[0x10];
5406 u8 reserved_at_20[0x10];
5409 u8 reserved_at_40[0x8];
5412 u8 reserved_at_60[0x20];
5415 struct mlx5_ifc_destroy_rq_out_bits {
5417 u8 reserved_at_8[0x18];
5421 u8 reserved_at_40[0x40];
5424 struct mlx5_ifc_destroy_rq_in_bits {
5426 u8 reserved_at_10[0x10];
5428 u8 reserved_at_20[0x10];
5431 u8 reserved_at_40[0x8];
5434 u8 reserved_at_60[0x20];
5437 struct mlx5_ifc_destroy_rmp_out_bits {
5439 u8 reserved_at_8[0x18];
5443 u8 reserved_at_40[0x40];
5446 struct mlx5_ifc_destroy_rmp_in_bits {
5448 u8 reserved_at_10[0x10];
5450 u8 reserved_at_20[0x10];
5453 u8 reserved_at_40[0x8];
5456 u8 reserved_at_60[0x20];
5459 struct mlx5_ifc_destroy_qp_out_bits {
5461 u8 reserved_at_8[0x18];
5465 u8 reserved_at_40[0x40];
5468 struct mlx5_ifc_destroy_qp_in_bits {
5470 u8 reserved_at_10[0x10];
5472 u8 reserved_at_20[0x10];
5475 u8 reserved_at_40[0x8];
5478 u8 reserved_at_60[0x20];
5481 struct mlx5_ifc_destroy_psv_out_bits {
5483 u8 reserved_at_8[0x18];
5487 u8 reserved_at_40[0x40];
5490 struct mlx5_ifc_destroy_psv_in_bits {
5492 u8 reserved_at_10[0x10];
5494 u8 reserved_at_20[0x10];
5497 u8 reserved_at_40[0x8];
5500 u8 reserved_at_60[0x20];
5503 struct mlx5_ifc_destroy_mkey_out_bits {
5505 u8 reserved_at_8[0x18];
5509 u8 reserved_at_40[0x40];
5512 struct mlx5_ifc_destroy_mkey_in_bits {
5514 u8 reserved_at_10[0x10];
5516 u8 reserved_at_20[0x10];
5519 u8 reserved_at_40[0x8];
5520 u8 mkey_index[0x18];
5522 u8 reserved_at_60[0x20];
5525 struct mlx5_ifc_destroy_flow_table_out_bits {
5527 u8 reserved_at_8[0x18];
5531 u8 reserved_at_40[0x40];
5534 struct mlx5_ifc_destroy_flow_table_in_bits {
5536 u8 reserved_at_10[0x10];
5538 u8 reserved_at_20[0x10];
5541 u8 other_vport[0x1];
5542 u8 reserved_at_41[0xf];
5543 u8 vport_number[0x10];
5545 u8 reserved_at_60[0x20];
5548 u8 reserved_at_88[0x18];
5550 u8 reserved_at_a0[0x8];
5553 u8 reserved_at_c0[0x140];
5556 struct mlx5_ifc_destroy_flow_group_out_bits {
5558 u8 reserved_at_8[0x18];
5562 u8 reserved_at_40[0x40];
5565 struct mlx5_ifc_destroy_flow_group_in_bits {
5567 u8 reserved_at_10[0x10];
5569 u8 reserved_at_20[0x10];
5572 u8 other_vport[0x1];
5573 u8 reserved_at_41[0xf];
5574 u8 vport_number[0x10];
5576 u8 reserved_at_60[0x20];
5579 u8 reserved_at_88[0x18];
5581 u8 reserved_at_a0[0x8];
5586 u8 reserved_at_e0[0x120];
5589 struct mlx5_ifc_destroy_eq_out_bits {
5591 u8 reserved_at_8[0x18];
5595 u8 reserved_at_40[0x40];
5598 struct mlx5_ifc_destroy_eq_in_bits {
5600 u8 reserved_at_10[0x10];
5602 u8 reserved_at_20[0x10];
5605 u8 reserved_at_40[0x18];
5608 u8 reserved_at_60[0x20];
5611 struct mlx5_ifc_destroy_dct_out_bits {
5613 u8 reserved_at_8[0x18];
5617 u8 reserved_at_40[0x40];
5620 struct mlx5_ifc_destroy_dct_in_bits {
5622 u8 reserved_at_10[0x10];
5624 u8 reserved_at_20[0x10];
5627 u8 reserved_at_40[0x8];
5630 u8 reserved_at_60[0x20];
5633 struct mlx5_ifc_destroy_cq_out_bits {
5635 u8 reserved_at_8[0x18];
5639 u8 reserved_at_40[0x40];
5642 struct mlx5_ifc_destroy_cq_in_bits {
5644 u8 reserved_at_10[0x10];
5646 u8 reserved_at_20[0x10];
5649 u8 reserved_at_40[0x8];
5652 u8 reserved_at_60[0x20];
5655 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5657 u8 reserved_at_8[0x18];
5661 u8 reserved_at_40[0x40];
5664 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5666 u8 reserved_at_10[0x10];
5668 u8 reserved_at_20[0x10];
5671 u8 reserved_at_40[0x20];
5673 u8 reserved_at_60[0x10];
5674 u8 vxlan_udp_port[0x10];
5677 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5679 u8 reserved_at_8[0x18];
5683 u8 reserved_at_40[0x40];
5686 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5688 u8 reserved_at_10[0x10];
5690 u8 reserved_at_20[0x10];
5693 u8 reserved_at_40[0x60];
5695 u8 reserved_at_a0[0x8];
5696 u8 table_index[0x18];
5698 u8 reserved_at_c0[0x140];
5701 struct mlx5_ifc_delete_fte_out_bits {
5703 u8 reserved_at_8[0x18];
5707 u8 reserved_at_40[0x40];
5710 struct mlx5_ifc_delete_fte_in_bits {
5712 u8 reserved_at_10[0x10];
5714 u8 reserved_at_20[0x10];
5717 u8 other_vport[0x1];
5718 u8 reserved_at_41[0xf];
5719 u8 vport_number[0x10];
5721 u8 reserved_at_60[0x20];
5724 u8 reserved_at_88[0x18];
5726 u8 reserved_at_a0[0x8];
5729 u8 reserved_at_c0[0x40];
5731 u8 flow_index[0x20];
5733 u8 reserved_at_120[0xe0];
5736 struct mlx5_ifc_dealloc_xrcd_out_bits {
5738 u8 reserved_at_8[0x18];
5742 u8 reserved_at_40[0x40];
5745 struct mlx5_ifc_dealloc_xrcd_in_bits {
5747 u8 reserved_at_10[0x10];
5749 u8 reserved_at_20[0x10];
5752 u8 reserved_at_40[0x8];
5755 u8 reserved_at_60[0x20];
5758 struct mlx5_ifc_dealloc_uar_out_bits {
5760 u8 reserved_at_8[0x18];
5764 u8 reserved_at_40[0x40];
5767 struct mlx5_ifc_dealloc_uar_in_bits {
5769 u8 reserved_at_10[0x10];
5771 u8 reserved_at_20[0x10];
5774 u8 reserved_at_40[0x8];
5777 u8 reserved_at_60[0x20];
5780 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5782 u8 reserved_at_8[0x18];
5786 u8 reserved_at_40[0x40];
5789 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5791 u8 reserved_at_10[0x10];
5793 u8 reserved_at_20[0x10];
5796 u8 reserved_at_40[0x8];
5797 u8 transport_domain[0x18];
5799 u8 reserved_at_60[0x20];
5802 struct mlx5_ifc_dealloc_q_counter_out_bits {
5804 u8 reserved_at_8[0x18];
5808 u8 reserved_at_40[0x40];
5811 struct mlx5_ifc_dealloc_q_counter_in_bits {
5813 u8 reserved_at_10[0x10];
5815 u8 reserved_at_20[0x10];
5818 u8 reserved_at_40[0x18];
5819 u8 counter_set_id[0x8];
5821 u8 reserved_at_60[0x20];
5824 struct mlx5_ifc_dealloc_pd_out_bits {
5826 u8 reserved_at_8[0x18];
5830 u8 reserved_at_40[0x40];
5833 struct mlx5_ifc_dealloc_pd_in_bits {
5835 u8 reserved_at_10[0x10];
5837 u8 reserved_at_20[0x10];
5840 u8 reserved_at_40[0x8];
5843 u8 reserved_at_60[0x20];
5846 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5848 u8 reserved_at_8[0x18];
5852 u8 reserved_at_40[0x40];
5855 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5857 u8 reserved_at_10[0x10];
5859 u8 reserved_at_20[0x10];
5862 u8 reserved_at_40[0x10];
5863 u8 flow_counter_id[0x10];
5865 u8 reserved_at_60[0x20];
5868 struct mlx5_ifc_create_xrq_out_bits {
5870 u8 reserved_at_8[0x18];
5874 u8 reserved_at_40[0x8];
5877 u8 reserved_at_60[0x20];
5880 struct mlx5_ifc_create_xrq_in_bits {
5882 u8 reserved_at_10[0x10];
5884 u8 reserved_at_20[0x10];
5887 u8 reserved_at_40[0x40];
5889 struct mlx5_ifc_xrqc_bits xrq_context;
5892 struct mlx5_ifc_create_xrc_srq_out_bits {
5894 u8 reserved_at_8[0x18];
5898 u8 reserved_at_40[0x8];
5901 u8 reserved_at_60[0x20];
5904 struct mlx5_ifc_create_xrc_srq_in_bits {
5906 u8 reserved_at_10[0x10];
5908 u8 reserved_at_20[0x10];
5911 u8 reserved_at_40[0x40];
5913 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5915 u8 reserved_at_280[0x600];
5920 struct mlx5_ifc_create_tis_out_bits {
5922 u8 reserved_at_8[0x18];
5926 u8 reserved_at_40[0x8];
5929 u8 reserved_at_60[0x20];
5932 struct mlx5_ifc_create_tis_in_bits {
5934 u8 reserved_at_10[0x10];
5936 u8 reserved_at_20[0x10];
5939 u8 reserved_at_40[0xc0];
5941 struct mlx5_ifc_tisc_bits ctx;
5944 struct mlx5_ifc_create_tir_out_bits {
5946 u8 reserved_at_8[0x18];
5950 u8 reserved_at_40[0x8];
5953 u8 reserved_at_60[0x20];
5956 struct mlx5_ifc_create_tir_in_bits {
5958 u8 reserved_at_10[0x10];
5960 u8 reserved_at_20[0x10];
5963 u8 reserved_at_40[0xc0];
5965 struct mlx5_ifc_tirc_bits ctx;
5968 struct mlx5_ifc_create_srq_out_bits {
5970 u8 reserved_at_8[0x18];
5974 u8 reserved_at_40[0x8];
5977 u8 reserved_at_60[0x20];
5980 struct mlx5_ifc_create_srq_in_bits {
5982 u8 reserved_at_10[0x10];
5984 u8 reserved_at_20[0x10];
5987 u8 reserved_at_40[0x40];
5989 struct mlx5_ifc_srqc_bits srq_context_entry;
5991 u8 reserved_at_280[0x600];
5996 struct mlx5_ifc_create_sq_out_bits {
5998 u8 reserved_at_8[0x18];
6002 u8 reserved_at_40[0x8];
6005 u8 reserved_at_60[0x20];
6008 struct mlx5_ifc_create_sq_in_bits {
6010 u8 reserved_at_10[0x10];
6012 u8 reserved_at_20[0x10];
6015 u8 reserved_at_40[0xc0];
6017 struct mlx5_ifc_sqc_bits ctx;
6020 struct mlx5_ifc_create_rqt_out_bits {
6022 u8 reserved_at_8[0x18];
6026 u8 reserved_at_40[0x8];
6029 u8 reserved_at_60[0x20];
6032 struct mlx5_ifc_create_rqt_in_bits {
6034 u8 reserved_at_10[0x10];
6036 u8 reserved_at_20[0x10];
6039 u8 reserved_at_40[0xc0];
6041 struct mlx5_ifc_rqtc_bits rqt_context;
6044 struct mlx5_ifc_create_rq_out_bits {
6046 u8 reserved_at_8[0x18];
6050 u8 reserved_at_40[0x8];
6053 u8 reserved_at_60[0x20];
6056 struct mlx5_ifc_create_rq_in_bits {
6058 u8 reserved_at_10[0x10];
6060 u8 reserved_at_20[0x10];
6063 u8 reserved_at_40[0xc0];
6065 struct mlx5_ifc_rqc_bits ctx;
6068 struct mlx5_ifc_create_rmp_out_bits {
6070 u8 reserved_at_8[0x18];
6074 u8 reserved_at_40[0x8];
6077 u8 reserved_at_60[0x20];
6080 struct mlx5_ifc_create_rmp_in_bits {
6082 u8 reserved_at_10[0x10];
6084 u8 reserved_at_20[0x10];
6087 u8 reserved_at_40[0xc0];
6089 struct mlx5_ifc_rmpc_bits ctx;
6092 struct mlx5_ifc_create_qp_out_bits {
6094 u8 reserved_at_8[0x18];
6098 u8 reserved_at_40[0x8];
6101 u8 reserved_at_60[0x20];
6104 struct mlx5_ifc_create_qp_in_bits {
6106 u8 reserved_at_10[0x10];
6108 u8 reserved_at_20[0x10];
6111 u8 reserved_at_40[0x40];
6113 u8 opt_param_mask[0x20];
6115 u8 reserved_at_a0[0x20];
6117 struct mlx5_ifc_qpc_bits qpc;
6119 u8 reserved_at_800[0x80];
6124 struct mlx5_ifc_create_psv_out_bits {
6126 u8 reserved_at_8[0x18];
6130 u8 reserved_at_40[0x40];
6132 u8 reserved_at_80[0x8];
6133 u8 psv0_index[0x18];
6135 u8 reserved_at_a0[0x8];
6136 u8 psv1_index[0x18];
6138 u8 reserved_at_c0[0x8];
6139 u8 psv2_index[0x18];
6141 u8 reserved_at_e0[0x8];
6142 u8 psv3_index[0x18];
6145 struct mlx5_ifc_create_psv_in_bits {
6147 u8 reserved_at_10[0x10];
6149 u8 reserved_at_20[0x10];
6153 u8 reserved_at_44[0x4];
6156 u8 reserved_at_60[0x20];
6159 struct mlx5_ifc_create_mkey_out_bits {
6161 u8 reserved_at_8[0x18];
6165 u8 reserved_at_40[0x8];
6166 u8 mkey_index[0x18];
6168 u8 reserved_at_60[0x20];
6171 struct mlx5_ifc_create_mkey_in_bits {
6173 u8 reserved_at_10[0x10];
6175 u8 reserved_at_20[0x10];
6178 u8 reserved_at_40[0x20];
6181 u8 reserved_at_61[0x1f];
6183 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6185 u8 reserved_at_280[0x80];
6187 u8 translations_octword_actual_size[0x20];
6189 u8 reserved_at_320[0x560];
6191 u8 klm_pas_mtt[0][0x20];
6194 struct mlx5_ifc_create_flow_table_out_bits {
6196 u8 reserved_at_8[0x18];
6200 u8 reserved_at_40[0x8];
6203 u8 reserved_at_60[0x20];
6206 struct mlx5_ifc_create_flow_table_in_bits {
6208 u8 reserved_at_10[0x10];
6210 u8 reserved_at_20[0x10];
6213 u8 other_vport[0x1];
6214 u8 reserved_at_41[0xf];
6215 u8 vport_number[0x10];
6217 u8 reserved_at_60[0x20];
6220 u8 reserved_at_88[0x18];
6222 u8 reserved_at_a0[0x20];
6226 u8 reserved_at_c2[0x2];
6227 u8 table_miss_mode[0x4];
6229 u8 reserved_at_d0[0x8];
6232 u8 reserved_at_e0[0x8];
6233 u8 table_miss_id[0x18];
6235 u8 reserved_at_100[0x8];
6236 u8 lag_master_next_table_id[0x18];
6238 u8 reserved_at_120[0x80];
6241 struct mlx5_ifc_create_flow_group_out_bits {
6243 u8 reserved_at_8[0x18];
6247 u8 reserved_at_40[0x8];
6250 u8 reserved_at_60[0x20];
6254 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6255 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6256 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6259 struct mlx5_ifc_create_flow_group_in_bits {
6261 u8 reserved_at_10[0x10];
6263 u8 reserved_at_20[0x10];
6266 u8 other_vport[0x1];
6267 u8 reserved_at_41[0xf];
6268 u8 vport_number[0x10];
6270 u8 reserved_at_60[0x20];
6273 u8 reserved_at_88[0x18];
6275 u8 reserved_at_a0[0x8];
6278 u8 reserved_at_c0[0x20];
6280 u8 start_flow_index[0x20];
6282 u8 reserved_at_100[0x20];
6284 u8 end_flow_index[0x20];
6286 u8 reserved_at_140[0xa0];
6288 u8 reserved_at_1e0[0x18];
6289 u8 match_criteria_enable[0x8];
6291 struct mlx5_ifc_fte_match_param_bits match_criteria;
6293 u8 reserved_at_1200[0xe00];
6296 struct mlx5_ifc_create_eq_out_bits {
6298 u8 reserved_at_8[0x18];
6302 u8 reserved_at_40[0x18];
6305 u8 reserved_at_60[0x20];
6308 struct mlx5_ifc_create_eq_in_bits {
6310 u8 reserved_at_10[0x10];
6312 u8 reserved_at_20[0x10];
6315 u8 reserved_at_40[0x40];
6317 struct mlx5_ifc_eqc_bits eq_context_entry;
6319 u8 reserved_at_280[0x40];
6321 u8 event_bitmask[0x40];
6323 u8 reserved_at_300[0x580];
6328 struct mlx5_ifc_create_dct_out_bits {
6330 u8 reserved_at_8[0x18];
6334 u8 reserved_at_40[0x8];
6337 u8 reserved_at_60[0x20];
6340 struct mlx5_ifc_create_dct_in_bits {
6342 u8 reserved_at_10[0x10];
6344 u8 reserved_at_20[0x10];
6347 u8 reserved_at_40[0x40];
6349 struct mlx5_ifc_dctc_bits dct_context_entry;
6351 u8 reserved_at_280[0x180];
6354 struct mlx5_ifc_create_cq_out_bits {
6356 u8 reserved_at_8[0x18];
6360 u8 reserved_at_40[0x8];
6363 u8 reserved_at_60[0x20];
6366 struct mlx5_ifc_create_cq_in_bits {
6368 u8 reserved_at_10[0x10];
6370 u8 reserved_at_20[0x10];
6373 u8 reserved_at_40[0x40];
6375 struct mlx5_ifc_cqc_bits cq_context;
6377 u8 reserved_at_280[0x600];
6382 struct mlx5_ifc_config_int_moderation_out_bits {
6384 u8 reserved_at_8[0x18];
6388 u8 reserved_at_40[0x4];
6390 u8 int_vector[0x10];
6392 u8 reserved_at_60[0x20];
6396 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6397 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6400 struct mlx5_ifc_config_int_moderation_in_bits {
6402 u8 reserved_at_10[0x10];
6404 u8 reserved_at_20[0x10];
6407 u8 reserved_at_40[0x4];
6409 u8 int_vector[0x10];
6411 u8 reserved_at_60[0x20];
6414 struct mlx5_ifc_attach_to_mcg_out_bits {
6416 u8 reserved_at_8[0x18];
6420 u8 reserved_at_40[0x40];
6423 struct mlx5_ifc_attach_to_mcg_in_bits {
6425 u8 reserved_at_10[0x10];
6427 u8 reserved_at_20[0x10];
6430 u8 reserved_at_40[0x8];
6433 u8 reserved_at_60[0x20];
6435 u8 multicast_gid[16][0x8];
6438 struct mlx5_ifc_arm_xrq_out_bits {
6440 u8 reserved_at_8[0x18];
6444 u8 reserved_at_40[0x40];
6447 struct mlx5_ifc_arm_xrq_in_bits {
6449 u8 reserved_at_10[0x10];
6451 u8 reserved_at_20[0x10];
6454 u8 reserved_at_40[0x8];
6457 u8 reserved_at_60[0x10];
6461 struct mlx5_ifc_arm_xrc_srq_out_bits {
6463 u8 reserved_at_8[0x18];
6467 u8 reserved_at_40[0x40];
6471 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6474 struct mlx5_ifc_arm_xrc_srq_in_bits {
6476 u8 reserved_at_10[0x10];
6478 u8 reserved_at_20[0x10];
6481 u8 reserved_at_40[0x8];
6484 u8 reserved_at_60[0x10];
6488 struct mlx5_ifc_arm_rq_out_bits {
6490 u8 reserved_at_8[0x18];
6494 u8 reserved_at_40[0x40];
6498 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6499 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6502 struct mlx5_ifc_arm_rq_in_bits {
6504 u8 reserved_at_10[0x10];
6506 u8 reserved_at_20[0x10];
6509 u8 reserved_at_40[0x8];
6510 u8 srq_number[0x18];
6512 u8 reserved_at_60[0x10];
6516 struct mlx5_ifc_arm_dct_out_bits {
6518 u8 reserved_at_8[0x18];
6522 u8 reserved_at_40[0x40];
6525 struct mlx5_ifc_arm_dct_in_bits {
6527 u8 reserved_at_10[0x10];
6529 u8 reserved_at_20[0x10];
6532 u8 reserved_at_40[0x8];
6533 u8 dct_number[0x18];
6535 u8 reserved_at_60[0x20];
6538 struct mlx5_ifc_alloc_xrcd_out_bits {
6540 u8 reserved_at_8[0x18];
6544 u8 reserved_at_40[0x8];
6547 u8 reserved_at_60[0x20];
6550 struct mlx5_ifc_alloc_xrcd_in_bits {
6552 u8 reserved_at_10[0x10];
6554 u8 reserved_at_20[0x10];
6557 u8 reserved_at_40[0x40];
6560 struct mlx5_ifc_alloc_uar_out_bits {
6562 u8 reserved_at_8[0x18];
6566 u8 reserved_at_40[0x8];
6569 u8 reserved_at_60[0x20];
6572 struct mlx5_ifc_alloc_uar_in_bits {
6574 u8 reserved_at_10[0x10];
6576 u8 reserved_at_20[0x10];
6579 u8 reserved_at_40[0x40];
6582 struct mlx5_ifc_alloc_transport_domain_out_bits {
6584 u8 reserved_at_8[0x18];
6588 u8 reserved_at_40[0x8];
6589 u8 transport_domain[0x18];
6591 u8 reserved_at_60[0x20];
6594 struct mlx5_ifc_alloc_transport_domain_in_bits {
6596 u8 reserved_at_10[0x10];
6598 u8 reserved_at_20[0x10];
6601 u8 reserved_at_40[0x40];
6604 struct mlx5_ifc_alloc_q_counter_out_bits {
6606 u8 reserved_at_8[0x18];
6610 u8 reserved_at_40[0x18];
6611 u8 counter_set_id[0x8];
6613 u8 reserved_at_60[0x20];
6616 struct mlx5_ifc_alloc_q_counter_in_bits {
6618 u8 reserved_at_10[0x10];
6620 u8 reserved_at_20[0x10];
6623 u8 reserved_at_40[0x40];
6626 struct mlx5_ifc_alloc_pd_out_bits {
6628 u8 reserved_at_8[0x18];
6632 u8 reserved_at_40[0x8];
6635 u8 reserved_at_60[0x20];
6638 struct mlx5_ifc_alloc_pd_in_bits {
6640 u8 reserved_at_10[0x10];
6642 u8 reserved_at_20[0x10];
6645 u8 reserved_at_40[0x40];
6648 struct mlx5_ifc_alloc_flow_counter_out_bits {
6650 u8 reserved_at_8[0x18];
6654 u8 reserved_at_40[0x10];
6655 u8 flow_counter_id[0x10];
6657 u8 reserved_at_60[0x20];
6660 struct mlx5_ifc_alloc_flow_counter_in_bits {
6662 u8 reserved_at_10[0x10];
6664 u8 reserved_at_20[0x10];
6667 u8 reserved_at_40[0x40];
6670 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6672 u8 reserved_at_8[0x18];
6676 u8 reserved_at_40[0x40];
6679 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6681 u8 reserved_at_10[0x10];
6683 u8 reserved_at_20[0x10];
6686 u8 reserved_at_40[0x20];
6688 u8 reserved_at_60[0x10];
6689 u8 vxlan_udp_port[0x10];
6692 struct mlx5_ifc_set_rate_limit_out_bits {
6694 u8 reserved_at_8[0x18];
6698 u8 reserved_at_40[0x40];
6701 struct mlx5_ifc_set_rate_limit_in_bits {
6703 u8 reserved_at_10[0x10];
6705 u8 reserved_at_20[0x10];
6708 u8 reserved_at_40[0x10];
6709 u8 rate_limit_index[0x10];
6711 u8 reserved_at_60[0x20];
6713 u8 rate_limit[0x20];
6716 struct mlx5_ifc_access_register_out_bits {
6718 u8 reserved_at_8[0x18];
6722 u8 reserved_at_40[0x40];
6724 u8 register_data[0][0x20];
6728 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6729 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6732 struct mlx5_ifc_access_register_in_bits {
6734 u8 reserved_at_10[0x10];
6736 u8 reserved_at_20[0x10];
6739 u8 reserved_at_40[0x10];
6740 u8 register_id[0x10];
6744 u8 register_data[0][0x20];
6747 struct mlx5_ifc_sltp_reg_bits {
6752 u8 reserved_at_12[0x2];
6754 u8 reserved_at_18[0x8];
6756 u8 reserved_at_20[0x20];
6758 u8 reserved_at_40[0x7];
6764 u8 reserved_at_60[0xc];
6765 u8 ob_preemp_mode[0x4];
6769 u8 reserved_at_80[0x20];
6772 struct mlx5_ifc_slrg_reg_bits {
6777 u8 reserved_at_12[0x2];
6779 u8 reserved_at_18[0x8];
6781 u8 time_to_link_up[0x10];
6782 u8 reserved_at_30[0xc];
6783 u8 grade_lane_speed[0x4];
6785 u8 grade_version[0x8];
6788 u8 reserved_at_60[0x4];
6789 u8 height_grade_type[0x4];
6790 u8 height_grade[0x18];
6795 u8 reserved_at_a0[0x10];
6796 u8 height_sigma[0x10];
6798 u8 reserved_at_c0[0x20];
6800 u8 reserved_at_e0[0x4];
6801 u8 phase_grade_type[0x4];
6802 u8 phase_grade[0x18];
6804 u8 reserved_at_100[0x8];
6805 u8 phase_eo_pos[0x8];
6806 u8 reserved_at_110[0x8];
6807 u8 phase_eo_neg[0x8];
6809 u8 ffe_set_tested[0x10];
6810 u8 test_errors_per_lane[0x10];
6813 struct mlx5_ifc_pvlc_reg_bits {
6814 u8 reserved_at_0[0x8];
6816 u8 reserved_at_10[0x10];
6818 u8 reserved_at_20[0x1c];
6821 u8 reserved_at_40[0x1c];
6824 u8 reserved_at_60[0x1c];
6825 u8 vl_operational[0x4];
6828 struct mlx5_ifc_pude_reg_bits {
6831 u8 reserved_at_10[0x4];
6832 u8 admin_status[0x4];
6833 u8 reserved_at_18[0x4];
6834 u8 oper_status[0x4];
6836 u8 reserved_at_20[0x60];
6839 struct mlx5_ifc_ptys_reg_bits {
6840 u8 reserved_at_0[0x1];
6841 u8 an_disable_admin[0x1];
6842 u8 an_disable_cap[0x1];
6843 u8 reserved_at_3[0x5];
6845 u8 reserved_at_10[0xd];
6849 u8 reserved_at_24[0x3c];
6851 u8 eth_proto_capability[0x20];
6853 u8 ib_link_width_capability[0x10];
6854 u8 ib_proto_capability[0x10];
6856 u8 reserved_at_a0[0x20];
6858 u8 eth_proto_admin[0x20];
6860 u8 ib_link_width_admin[0x10];
6861 u8 ib_proto_admin[0x10];
6863 u8 reserved_at_100[0x20];
6865 u8 eth_proto_oper[0x20];
6867 u8 ib_link_width_oper[0x10];
6868 u8 ib_proto_oper[0x10];
6870 u8 reserved_at_160[0x20];
6872 u8 eth_proto_lp_advertise[0x20];
6874 u8 reserved_at_1a0[0x60];
6877 struct mlx5_ifc_mlcr_reg_bits {
6878 u8 reserved_at_0[0x8];
6880 u8 reserved_at_10[0x20];
6882 u8 beacon_duration[0x10];
6883 u8 reserved_at_40[0x10];
6885 u8 beacon_remain[0x10];
6888 struct mlx5_ifc_ptas_reg_bits {
6889 u8 reserved_at_0[0x20];
6891 u8 algorithm_options[0x10];
6892 u8 reserved_at_30[0x4];
6893 u8 repetitions_mode[0x4];
6894 u8 num_of_repetitions[0x8];
6896 u8 grade_version[0x8];
6897 u8 height_grade_type[0x4];
6898 u8 phase_grade_type[0x4];
6899 u8 height_grade_weight[0x8];
6900 u8 phase_grade_weight[0x8];
6902 u8 gisim_measure_bits[0x10];
6903 u8 adaptive_tap_measure_bits[0x10];
6905 u8 ber_bath_high_error_threshold[0x10];
6906 u8 ber_bath_mid_error_threshold[0x10];
6908 u8 ber_bath_low_error_threshold[0x10];
6909 u8 one_ratio_high_threshold[0x10];
6911 u8 one_ratio_high_mid_threshold[0x10];
6912 u8 one_ratio_low_mid_threshold[0x10];
6914 u8 one_ratio_low_threshold[0x10];
6915 u8 ndeo_error_threshold[0x10];
6917 u8 mixer_offset_step_size[0x10];
6918 u8 reserved_at_110[0x8];
6919 u8 mix90_phase_for_voltage_bath[0x8];
6921 u8 mixer_offset_start[0x10];
6922 u8 mixer_offset_end[0x10];
6924 u8 reserved_at_140[0x15];
6925 u8 ber_test_time[0xb];
6928 struct mlx5_ifc_pspa_reg_bits {
6932 u8 reserved_at_18[0x8];
6934 u8 reserved_at_20[0x20];
6937 struct mlx5_ifc_pqdr_reg_bits {
6938 u8 reserved_at_0[0x8];
6940 u8 reserved_at_10[0x5];
6942 u8 reserved_at_18[0x6];
6945 u8 reserved_at_20[0x20];
6947 u8 reserved_at_40[0x10];
6948 u8 min_threshold[0x10];
6950 u8 reserved_at_60[0x10];
6951 u8 max_threshold[0x10];
6953 u8 reserved_at_80[0x10];
6954 u8 mark_probability_denominator[0x10];
6956 u8 reserved_at_a0[0x60];
6959 struct mlx5_ifc_ppsc_reg_bits {
6960 u8 reserved_at_0[0x8];
6962 u8 reserved_at_10[0x10];
6964 u8 reserved_at_20[0x60];
6966 u8 reserved_at_80[0x1c];
6969 u8 reserved_at_a0[0x1c];
6970 u8 wrps_status[0x4];
6972 u8 reserved_at_c0[0x8];
6973 u8 up_threshold[0x8];
6974 u8 reserved_at_d0[0x8];
6975 u8 down_threshold[0x8];
6977 u8 reserved_at_e0[0x20];
6979 u8 reserved_at_100[0x1c];
6982 u8 reserved_at_120[0x1c];
6983 u8 srps_status[0x4];
6985 u8 reserved_at_140[0x40];
6988 struct mlx5_ifc_pplr_reg_bits {
6989 u8 reserved_at_0[0x8];
6991 u8 reserved_at_10[0x10];
6993 u8 reserved_at_20[0x8];
6995 u8 reserved_at_30[0x8];
6999 struct mlx5_ifc_pplm_reg_bits {
7000 u8 reserved_at_0[0x8];
7002 u8 reserved_at_10[0x10];
7004 u8 reserved_at_20[0x20];
7006 u8 port_profile_mode[0x8];
7007 u8 static_port_profile[0x8];
7008 u8 active_port_profile[0x8];
7009 u8 reserved_at_58[0x8];
7011 u8 retransmission_active[0x8];
7012 u8 fec_mode_active[0x18];
7014 u8 reserved_at_80[0x20];
7017 struct mlx5_ifc_ppcnt_reg_bits {
7021 u8 reserved_at_12[0x8];
7025 u8 reserved_at_21[0x1c];
7028 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7031 struct mlx5_ifc_ppad_reg_bits {
7032 u8 reserved_at_0[0x3];
7034 u8 reserved_at_4[0x4];
7040 u8 reserved_at_40[0x40];
7043 struct mlx5_ifc_pmtu_reg_bits {
7044 u8 reserved_at_0[0x8];
7046 u8 reserved_at_10[0x10];
7049 u8 reserved_at_30[0x10];
7052 u8 reserved_at_50[0x10];
7055 u8 reserved_at_70[0x10];
7058 struct mlx5_ifc_pmpr_reg_bits {
7059 u8 reserved_at_0[0x8];
7061 u8 reserved_at_10[0x10];
7063 u8 reserved_at_20[0x18];
7064 u8 attenuation_5g[0x8];
7066 u8 reserved_at_40[0x18];
7067 u8 attenuation_7g[0x8];
7069 u8 reserved_at_60[0x18];
7070 u8 attenuation_12g[0x8];
7073 struct mlx5_ifc_pmpe_reg_bits {
7074 u8 reserved_at_0[0x8];
7076 u8 reserved_at_10[0xc];
7077 u8 module_status[0x4];
7079 u8 reserved_at_20[0x60];
7082 struct mlx5_ifc_pmpc_reg_bits {
7083 u8 module_state_updated[32][0x8];
7086 struct mlx5_ifc_pmlpn_reg_bits {
7087 u8 reserved_at_0[0x4];
7088 u8 mlpn_status[0x4];
7090 u8 reserved_at_10[0x10];
7093 u8 reserved_at_21[0x1f];
7096 struct mlx5_ifc_pmlp_reg_bits {
7098 u8 reserved_at_1[0x7];
7100 u8 reserved_at_10[0x8];
7103 u8 lane0_module_mapping[0x20];
7105 u8 lane1_module_mapping[0x20];
7107 u8 lane2_module_mapping[0x20];
7109 u8 lane3_module_mapping[0x20];
7111 u8 reserved_at_a0[0x160];
7114 struct mlx5_ifc_pmaos_reg_bits {
7115 u8 reserved_at_0[0x8];
7117 u8 reserved_at_10[0x4];
7118 u8 admin_status[0x4];
7119 u8 reserved_at_18[0x4];
7120 u8 oper_status[0x4];
7124 u8 reserved_at_22[0x1c];
7127 u8 reserved_at_40[0x40];
7130 struct mlx5_ifc_plpc_reg_bits {
7131 u8 reserved_at_0[0x4];
7133 u8 reserved_at_10[0x4];
7135 u8 reserved_at_18[0x8];
7137 u8 reserved_at_20[0x10];
7138 u8 lane_speed[0x10];
7140 u8 reserved_at_40[0x17];
7142 u8 fec_mode_policy[0x8];
7144 u8 retransmission_capability[0x8];
7145 u8 fec_mode_capability[0x18];
7147 u8 retransmission_support_admin[0x8];
7148 u8 fec_mode_support_admin[0x18];
7150 u8 retransmission_request_admin[0x8];
7151 u8 fec_mode_request_admin[0x18];
7153 u8 reserved_at_c0[0x80];
7156 struct mlx5_ifc_plib_reg_bits {
7157 u8 reserved_at_0[0x8];
7159 u8 reserved_at_10[0x8];
7162 u8 reserved_at_20[0x60];
7165 struct mlx5_ifc_plbf_reg_bits {
7166 u8 reserved_at_0[0x8];
7168 u8 reserved_at_10[0xd];
7171 u8 reserved_at_20[0x20];
7174 struct mlx5_ifc_pipg_reg_bits {
7175 u8 reserved_at_0[0x8];
7177 u8 reserved_at_10[0x10];
7180 u8 reserved_at_21[0x19];
7182 u8 reserved_at_3e[0x2];
7185 struct mlx5_ifc_pifr_reg_bits {
7186 u8 reserved_at_0[0x8];
7188 u8 reserved_at_10[0x10];
7190 u8 reserved_at_20[0xe0];
7192 u8 port_filter[8][0x20];
7194 u8 port_filter_update_en[8][0x20];
7197 struct mlx5_ifc_pfcc_reg_bits {
7198 u8 reserved_at_0[0x8];
7200 u8 reserved_at_10[0x10];
7203 u8 reserved_at_24[0x4];
7204 u8 prio_mask_tx[0x8];
7205 u8 reserved_at_30[0x8];
7206 u8 prio_mask_rx[0x8];
7210 u8 reserved_at_42[0x6];
7212 u8 reserved_at_50[0x10];
7216 u8 reserved_at_62[0x6];
7218 u8 reserved_at_70[0x10];
7220 u8 reserved_at_80[0x80];
7223 struct mlx5_ifc_pelc_reg_bits {
7225 u8 reserved_at_4[0x4];
7227 u8 reserved_at_10[0x10];
7230 u8 op_capability[0x8];
7236 u8 capability[0x40];
7242 u8 reserved_at_140[0x80];
7245 struct mlx5_ifc_peir_reg_bits {
7246 u8 reserved_at_0[0x8];
7248 u8 reserved_at_10[0x10];
7250 u8 reserved_at_20[0xc];
7251 u8 error_count[0x4];
7252 u8 reserved_at_30[0x10];
7254 u8 reserved_at_40[0xc];
7256 u8 reserved_at_50[0x8];
7260 struct mlx5_ifc_pcap_reg_bits {
7261 u8 reserved_at_0[0x8];
7263 u8 reserved_at_10[0x10];
7265 u8 port_capability_mask[4][0x20];
7268 struct mlx5_ifc_paos_reg_bits {
7271 u8 reserved_at_10[0x4];
7272 u8 admin_status[0x4];
7273 u8 reserved_at_18[0x4];
7274 u8 oper_status[0x4];
7278 u8 reserved_at_22[0x1c];
7281 u8 reserved_at_40[0x40];
7284 struct mlx5_ifc_pamp_reg_bits {
7285 u8 reserved_at_0[0x8];
7286 u8 opamp_group[0x8];
7287 u8 reserved_at_10[0xc];
7288 u8 opamp_group_type[0x4];
7290 u8 start_index[0x10];
7291 u8 reserved_at_30[0x4];
7292 u8 num_of_indices[0xc];
7294 u8 index_data[18][0x10];
7297 struct mlx5_ifc_pcmr_reg_bits {
7298 u8 reserved_at_0[0x8];
7300 u8 reserved_at_10[0x2e];
7302 u8 reserved_at_3f[0x1f];
7304 u8 reserved_at_5f[0x1];
7307 struct mlx5_ifc_lane_2_module_mapping_bits {
7308 u8 reserved_at_0[0x6];
7310 u8 reserved_at_8[0x6];
7312 u8 reserved_at_10[0x8];
7316 struct mlx5_ifc_bufferx_reg_bits {
7317 u8 reserved_at_0[0x6];
7320 u8 reserved_at_8[0xc];
7323 u8 xoff_threshold[0x10];
7324 u8 xon_threshold[0x10];
7327 struct mlx5_ifc_set_node_in_bits {
7328 u8 node_description[64][0x8];
7331 struct mlx5_ifc_register_power_settings_bits {
7332 u8 reserved_at_0[0x18];
7333 u8 power_settings_level[0x8];
7335 u8 reserved_at_20[0x60];
7338 struct mlx5_ifc_register_host_endianness_bits {
7340 u8 reserved_at_1[0x1f];
7342 u8 reserved_at_20[0x60];
7345 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7346 u8 reserved_at_0[0x20];
7350 u8 addressh_63_32[0x20];
7352 u8 addressl_31_0[0x20];
7355 struct mlx5_ifc_ud_adrs_vector_bits {
7359 u8 reserved_at_41[0x7];
7360 u8 destination_qp_dct[0x18];
7362 u8 static_rate[0x4];
7363 u8 sl_eth_prio[0x4];
7366 u8 rlid_udp_sport[0x10];
7368 u8 reserved_at_80[0x20];
7370 u8 rmac_47_16[0x20];
7376 u8 reserved_at_e0[0x1];
7378 u8 reserved_at_e2[0x2];
7379 u8 src_addr_index[0x8];
7380 u8 flow_label[0x14];
7382 u8 rgid_rip[16][0x8];
7385 struct mlx5_ifc_pages_req_event_bits {
7386 u8 reserved_at_0[0x10];
7387 u8 function_id[0x10];
7391 u8 reserved_at_40[0xa0];
7394 struct mlx5_ifc_eqe_bits {
7395 u8 reserved_at_0[0x8];
7397 u8 reserved_at_10[0x8];
7398 u8 event_sub_type[0x8];
7400 u8 reserved_at_20[0xe0];
7402 union mlx5_ifc_event_auto_bits event_data;
7404 u8 reserved_at_1e0[0x10];
7406 u8 reserved_at_1f8[0x7];
7411 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7414 struct mlx5_ifc_cmd_queue_entry_bits {
7416 u8 reserved_at_8[0x18];
7418 u8 input_length[0x20];
7420 u8 input_mailbox_pointer_63_32[0x20];
7422 u8 input_mailbox_pointer_31_9[0x17];
7423 u8 reserved_at_77[0x9];
7425 u8 command_input_inline_data[16][0x8];
7427 u8 command_output_inline_data[16][0x8];
7429 u8 output_mailbox_pointer_63_32[0x20];
7431 u8 output_mailbox_pointer_31_9[0x17];
7432 u8 reserved_at_1b7[0x9];
7434 u8 output_length[0x20];
7438 u8 reserved_at_1f0[0x8];
7443 struct mlx5_ifc_cmd_out_bits {
7445 u8 reserved_at_8[0x18];
7449 u8 command_output[0x20];
7452 struct mlx5_ifc_cmd_in_bits {
7454 u8 reserved_at_10[0x10];
7456 u8 reserved_at_20[0x10];
7459 u8 command[0][0x20];
7462 struct mlx5_ifc_cmd_if_box_bits {
7463 u8 mailbox_data[512][0x8];
7465 u8 reserved_at_1000[0x180];
7467 u8 next_pointer_63_32[0x20];
7469 u8 next_pointer_31_10[0x16];
7470 u8 reserved_at_11b6[0xa];
7472 u8 block_number[0x20];
7474 u8 reserved_at_11e0[0x8];
7476 u8 ctrl_signature[0x8];
7480 struct mlx5_ifc_mtt_bits {
7481 u8 ptag_63_32[0x20];
7484 u8 reserved_at_38[0x6];
7489 struct mlx5_ifc_query_wol_rol_out_bits {
7491 u8 reserved_at_8[0x18];
7495 u8 reserved_at_40[0x10];
7499 u8 reserved_at_60[0x20];
7502 struct mlx5_ifc_query_wol_rol_in_bits {
7504 u8 reserved_at_10[0x10];
7506 u8 reserved_at_20[0x10];
7509 u8 reserved_at_40[0x40];
7512 struct mlx5_ifc_set_wol_rol_out_bits {
7514 u8 reserved_at_8[0x18];
7518 u8 reserved_at_40[0x40];
7521 struct mlx5_ifc_set_wol_rol_in_bits {
7523 u8 reserved_at_10[0x10];
7525 u8 reserved_at_20[0x10];
7528 u8 rol_mode_valid[0x1];
7529 u8 wol_mode_valid[0x1];
7530 u8 reserved_at_42[0xe];
7534 u8 reserved_at_60[0x20];
7538 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7539 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7540 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7544 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7545 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7546 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7550 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7551 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7552 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7553 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7554 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7555 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7556 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7557 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7558 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7559 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7560 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7563 struct mlx5_ifc_initial_seg_bits {
7564 u8 fw_rev_minor[0x10];
7565 u8 fw_rev_major[0x10];
7567 u8 cmd_interface_rev[0x10];
7568 u8 fw_rev_subminor[0x10];
7570 u8 reserved_at_40[0x40];
7572 u8 cmdq_phy_addr_63_32[0x20];
7574 u8 cmdq_phy_addr_31_12[0x14];
7575 u8 reserved_at_b4[0x2];
7576 u8 nic_interface[0x2];
7577 u8 log_cmdq_size[0x4];
7578 u8 log_cmdq_stride[0x4];
7580 u8 command_doorbell_vector[0x20];
7582 u8 reserved_at_e0[0xf00];
7584 u8 initializing[0x1];
7585 u8 reserved_at_fe1[0x4];
7586 u8 nic_interface_supported[0x3];
7587 u8 reserved_at_fe8[0x18];
7589 struct mlx5_ifc_health_buffer_bits health_buffer;
7591 u8 no_dram_nic_offset[0x20];
7593 u8 reserved_at_1220[0x6e40];
7595 u8 reserved_at_8060[0x1f];
7598 u8 health_syndrome[0x8];
7599 u8 health_counter[0x18];
7601 u8 reserved_at_80a0[0x17fc0];
7604 union mlx5_ifc_ports_control_registers_document_bits {
7605 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7606 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7607 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7608 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7609 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7610 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7611 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7612 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7613 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7614 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7615 struct mlx5_ifc_paos_reg_bits paos_reg;
7616 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7617 struct mlx5_ifc_peir_reg_bits peir_reg;
7618 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7619 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7620 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7621 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7622 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7623 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7624 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7625 struct mlx5_ifc_plib_reg_bits plib_reg;
7626 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7627 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7628 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7629 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7630 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7631 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7632 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7633 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7634 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7635 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7636 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7637 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7638 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7639 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7640 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7641 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7642 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7643 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7644 struct mlx5_ifc_pude_reg_bits pude_reg;
7645 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7646 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7647 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7648 u8 reserved_at_0[0x60e0];
7651 union mlx5_ifc_debug_enhancements_document_bits {
7652 struct mlx5_ifc_health_buffer_bits health_buffer;
7653 u8 reserved_at_0[0x200];
7656 union mlx5_ifc_uplink_pci_interface_document_bits {
7657 struct mlx5_ifc_initial_seg_bits initial_seg;
7658 u8 reserved_at_0[0x20060];
7661 struct mlx5_ifc_set_flow_table_root_out_bits {
7663 u8 reserved_at_8[0x18];
7667 u8 reserved_at_40[0x40];
7670 struct mlx5_ifc_set_flow_table_root_in_bits {
7672 u8 reserved_at_10[0x10];
7674 u8 reserved_at_20[0x10];
7677 u8 other_vport[0x1];
7678 u8 reserved_at_41[0xf];
7679 u8 vport_number[0x10];
7681 u8 reserved_at_60[0x20];
7684 u8 reserved_at_88[0x18];
7686 u8 reserved_at_a0[0x8];
7689 u8 reserved_at_c0[0x140];
7693 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7694 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7697 struct mlx5_ifc_modify_flow_table_out_bits {
7699 u8 reserved_at_8[0x18];
7703 u8 reserved_at_40[0x40];
7706 struct mlx5_ifc_modify_flow_table_in_bits {
7708 u8 reserved_at_10[0x10];
7710 u8 reserved_at_20[0x10];
7713 u8 other_vport[0x1];
7714 u8 reserved_at_41[0xf];
7715 u8 vport_number[0x10];
7717 u8 reserved_at_60[0x10];
7718 u8 modify_field_select[0x10];
7721 u8 reserved_at_88[0x18];
7723 u8 reserved_at_a0[0x8];
7726 u8 reserved_at_c0[0x4];
7727 u8 table_miss_mode[0x4];
7728 u8 reserved_at_c8[0x18];
7730 u8 reserved_at_e0[0x8];
7731 u8 table_miss_id[0x18];
7733 u8 reserved_at_100[0x8];
7734 u8 lag_master_next_table_id[0x18];
7736 u8 reserved_at_120[0x80];
7739 struct mlx5_ifc_ets_tcn_config_reg_bits {
7743 u8 reserved_at_3[0x9];
7745 u8 reserved_at_10[0x9];
7746 u8 bw_allocation[0x7];
7748 u8 reserved_at_20[0xc];
7749 u8 max_bw_units[0x4];
7750 u8 reserved_at_30[0x8];
7751 u8 max_bw_value[0x8];
7754 struct mlx5_ifc_ets_global_config_reg_bits {
7755 u8 reserved_at_0[0x2];
7757 u8 reserved_at_3[0x1d];
7759 u8 reserved_at_20[0xc];
7760 u8 max_bw_units[0x4];
7761 u8 reserved_at_30[0x8];
7762 u8 max_bw_value[0x8];
7765 struct mlx5_ifc_qetc_reg_bits {
7766 u8 reserved_at_0[0x8];
7767 u8 port_number[0x8];
7768 u8 reserved_at_10[0x30];
7770 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7771 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7774 struct mlx5_ifc_qtct_reg_bits {
7775 u8 reserved_at_0[0x8];
7776 u8 port_number[0x8];
7777 u8 reserved_at_10[0xd];
7780 u8 reserved_at_20[0x1d];
7784 struct mlx5_ifc_mcia_reg_bits {
7786 u8 reserved_at_1[0x7];
7788 u8 reserved_at_10[0x8];
7791 u8 i2c_device_address[0x8];
7792 u8 page_number[0x8];
7793 u8 device_address[0x10];
7795 u8 reserved_at_40[0x10];
7798 u8 reserved_at_60[0x20];
7814 struct mlx5_ifc_dcbx_param_bits {
7815 u8 dcbx_cee_cap[0x1];
7816 u8 dcbx_ieee_cap[0x1];
7817 u8 dcbx_standby_cap[0x1];
7818 u8 reserved_at_0[0x5];
7819 u8 port_number[0x8];
7820 u8 reserved_at_10[0xa];
7821 u8 max_application_table_size[6];
7822 u8 reserved_at_20[0x15];
7823 u8 version_oper[0x3];
7824 u8 reserved_at_38[5];
7825 u8 version_admin[0x3];
7826 u8 willing_admin[0x1];
7827 u8 reserved_at_41[0x3];
7828 u8 pfc_cap_oper[0x4];
7829 u8 reserved_at_48[0x4];
7830 u8 pfc_cap_admin[0x4];
7831 u8 reserved_at_50[0x4];
7832 u8 num_of_tc_oper[0x4];
7833 u8 reserved_at_58[0x4];
7834 u8 num_of_tc_admin[0x4];
7835 u8 remote_willing[0x1];
7836 u8 reserved_at_61[3];
7837 u8 remote_pfc_cap[4];
7838 u8 reserved_at_68[0x14];
7839 u8 remote_num_of_tc[0x4];
7840 u8 reserved_at_80[0x18];
7842 u8 reserved_at_a0[0x160];
7845 struct mlx5_ifc_lagc_bits {
7846 u8 reserved_at_0[0x1d];
7849 u8 reserved_at_20[0x14];
7850 u8 tx_remap_affinity_2[0x4];
7851 u8 reserved_at_38[0x4];
7852 u8 tx_remap_affinity_1[0x4];
7855 struct mlx5_ifc_create_lag_out_bits {
7857 u8 reserved_at_8[0x18];
7861 u8 reserved_at_40[0x40];
7864 struct mlx5_ifc_create_lag_in_bits {
7866 u8 reserved_at_10[0x10];
7868 u8 reserved_at_20[0x10];
7871 struct mlx5_ifc_lagc_bits ctx;
7874 struct mlx5_ifc_modify_lag_out_bits {
7876 u8 reserved_at_8[0x18];
7880 u8 reserved_at_40[0x40];
7883 struct mlx5_ifc_modify_lag_in_bits {
7885 u8 reserved_at_10[0x10];
7887 u8 reserved_at_20[0x10];
7890 u8 reserved_at_40[0x20];
7891 u8 field_select[0x20];
7893 struct mlx5_ifc_lagc_bits ctx;
7896 struct mlx5_ifc_query_lag_out_bits {
7898 u8 reserved_at_8[0x18];
7902 u8 reserved_at_40[0x40];
7904 struct mlx5_ifc_lagc_bits ctx;
7907 struct mlx5_ifc_query_lag_in_bits {
7909 u8 reserved_at_10[0x10];
7911 u8 reserved_at_20[0x10];
7914 u8 reserved_at_40[0x40];
7917 struct mlx5_ifc_destroy_lag_out_bits {
7919 u8 reserved_at_8[0x18];
7923 u8 reserved_at_40[0x40];
7926 struct mlx5_ifc_destroy_lag_in_bits {
7928 u8 reserved_at_10[0x10];
7930 u8 reserved_at_20[0x10];
7933 u8 reserved_at_40[0x40];
7936 struct mlx5_ifc_create_vport_lag_out_bits {
7938 u8 reserved_at_8[0x18];
7942 u8 reserved_at_40[0x40];
7945 struct mlx5_ifc_create_vport_lag_in_bits {
7947 u8 reserved_at_10[0x10];
7949 u8 reserved_at_20[0x10];
7952 u8 reserved_at_40[0x40];
7955 struct mlx5_ifc_destroy_vport_lag_out_bits {
7957 u8 reserved_at_8[0x18];
7961 u8 reserved_at_40[0x40];
7964 struct mlx5_ifc_destroy_vport_lag_in_bits {
7966 u8 reserved_at_10[0x10];
7968 u8 reserved_at_20[0x10];
7971 u8 reserved_at_40[0x40];
7974 #endif /* MLX5_IFC_H */