include/linux/irqchip/arm-gic.h

   1 /*
   2  *  include/linux/irqchip/arm-gic.h
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __LINUX_IRQCHIP_ARM_GIC_H
  11 #define __LINUX_IRQCHIP_ARM_GIC_H
  12
  13 #define GIC_CPU_CTRL                    0x00
  14 #define GIC_CPU_PRIMASK                 0x04
  15 #define GIC_CPU_BINPOINT                0x08
  16 #define GIC_CPU_INTACK                  0x0c
  17 #define GIC_CPU_EOI                     0x10
  18 #define GIC_CPU_RUNNINGPRI              0x14
  19 #define GIC_CPU_HIGHPRI                 0x18
  20 #define GIC_CPU_ALIAS_BINPOINT          0x1c
  21 #define GIC_CPU_ACTIVEPRIO              0xd0
  22 #define GIC_CPU_IDENT                   0xfc
  23
  24 #define GICC_IAR_INT_ID_MASK            0x3ff
  25
  26 #define GIC_DIST_CTRL                   0x000
  27 #define GIC_DIST_CTR                    0x004
  28 #define GIC_DIST_IGROUP                 0x080
  29 #define GIC_DIST_ENABLE_SET             0x100
  30 #define GIC_DIST_ENABLE_CLEAR           0x180
  31 #define GIC_DIST_PENDING_SET            0x200
  32 #define GIC_DIST_PENDING_CLEAR          0x280
  33 #define GIC_DIST_ACTIVE_SET             0x300
  34 #define GIC_DIST_ACTIVE_CLEAR           0x380
  35 #define GIC_DIST_PRI                    0x400
  36 #define GIC_DIST_TARGET                 0x800
  37 #define GIC_DIST_CONFIG                 0xc00
  38 #define GIC_DIST_SOFTINT                0xf00
  39 #define GIC_DIST_SGI_PENDING_CLEAR      0xf10
  40 #define GIC_DIST_SGI_PENDING_SET        0xf20
  41
  42 #define GICH_HCR                        0x0
  43 #define GICH_VTR                        0x4
  44 #define GICH_VMCR                       0x8
  45 #define GICH_MISR                       0x10
  46 #define GICH_EISR0                      0x20
  47 #define GICH_EISR1                      0x24
  48 #define GICH_ELRSR0                     0x30
  49 #define GICH_ELRSR1                     0x34
  50 #define GICH_APR                        0xf0
  51 #define GICH_LR0                        0x100
  52
  53 #define GICH_HCR_EN                     (1 << 0)
  54 #define GICH_HCR_UIE                    (1 << 1)
  55
  56 #define GICH_LR_VIRTUALID               (0x3ff << 0)
  57 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
  58 #define GICH_LR_PHYSID_CPUID            (7 << GICH_LR_PHYSID_CPUID_SHIFT)
  59 #define GICH_LR_STATE                   (3 << 28)
  60 #define GICH_LR_PENDING_BIT             (1 << 28)
  61 #define GICH_LR_ACTIVE_BIT              (1 << 29)
  62 #define GICH_LR_EOI                     (1 << 19)
  63
  64 #define GICH_VMCR_CTRL_SHIFT            0
  65 #define GICH_VMCR_CTRL_MASK             (0x21f << GICH_VMCR_CTRL_SHIFT)
  66 #define GICH_VMCR_PRIMASK_SHIFT         27
  67 #define GICH_VMCR_PRIMASK_MASK          (0x1f << GICH_VMCR_PRIMASK_SHIFT)
  68 #define GICH_VMCR_BINPOINT_SHIFT        21
  69 #define GICH_VMCR_BINPOINT_MASK         (0x7 << GICH_VMCR_BINPOINT_SHIFT)
  70 #define GICH_VMCR_ALIAS_BINPOINT_SHIFT  18
  71 #define GICH_VMCR_ALIAS_BINPOINT_MASK   (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
  72
  73 #define GICH_MISR_EOI                   (1 << 0)
  74 #define GICH_MISR_U                     (1 << 1)
  75
  76 #ifndef __ASSEMBLY__
  77
  78 struct device_node;
  79
  80 extern struct irq_chip gic_arch_extn;
  81
  82 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
  83                     u32 offset, struct device_node *);
  84 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
  85 void gic_cpu_if_down(void);
  86
  87 static inline void gic_init(unsigned int nr, int start,
  88                             void __iomem *dist , void __iomem *cpu)
  89 {
  90         gic_init_bases(nr, start, dist, cpu, 0, NULL);
  91 }
  92
  93 void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
  94 int gic_get_cpu_id(unsigned int cpu);
  95 void gic_migrate_target(unsigned int new_cpu_id);
  96 unsigned long gic_get_sgir_physaddr(void);
  97
  98 extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
  99 static inline void __init register_routable_domain_ops
 100                                         (const struct irq_domain_ops *ops)
 101 {
 102         gic_routable_irq_domain_ops = ops;
 103 }
 104 #endif /* __ASSEMBLY */
 105 #endif