1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
9 #include <linux/device.h>
10 #include <linux/perf_event.h>
11 #include <linux/sched.h>
13 /* Peripheral id registers (0xFD0-0xFEC) */
14 #define CORESIGHT_PERIPHIDR4 0xfd0
15 #define CORESIGHT_PERIPHIDR5 0xfd4
16 #define CORESIGHT_PERIPHIDR6 0xfd8
17 #define CORESIGHT_PERIPHIDR7 0xfdC
18 #define CORESIGHT_PERIPHIDR0 0xfe0
19 #define CORESIGHT_PERIPHIDR1 0xfe4
20 #define CORESIGHT_PERIPHIDR2 0xfe8
21 #define CORESIGHT_PERIPHIDR3 0xfeC
22 /* Component id registers (0xFF0-0xFFC) */
23 #define CORESIGHT_COMPIDR0 0xff0
24 #define CORESIGHT_COMPIDR1 0xff4
25 #define CORESIGHT_COMPIDR2 0xff8
26 #define CORESIGHT_COMPIDR3 0xffC
28 #define ETM_ARCH_V3_3 0x23
29 #define ETM_ARCH_V3_5 0x25
30 #define PFT_ARCH_V1_0 0x30
31 #define PFT_ARCH_V1_1 0x31
33 #define CORESIGHT_UNLOCK 0xc5acce55
35 extern struct bus_type coresight_bustype;
37 enum coresight_dev_type {
38 CORESIGHT_DEV_TYPE_NONE,
39 CORESIGHT_DEV_TYPE_SINK,
40 CORESIGHT_DEV_TYPE_LINK,
41 CORESIGHT_DEV_TYPE_LINKSINK,
42 CORESIGHT_DEV_TYPE_SOURCE,
43 CORESIGHT_DEV_TYPE_HELPER,
44 CORESIGHT_DEV_TYPE_ECT,
47 enum coresight_dev_subtype_sink {
48 CORESIGHT_DEV_SUBTYPE_SINK_NONE,
49 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
50 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
53 enum coresight_dev_subtype_link {
54 CORESIGHT_DEV_SUBTYPE_LINK_NONE,
55 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
56 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
57 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
60 enum coresight_dev_subtype_source {
61 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
62 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
63 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
64 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
67 enum coresight_dev_subtype_helper {
68 CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
69 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
72 /* Embedded Cross Trigger (ECT) sub-types */
73 enum coresight_dev_subtype_ect {
74 CORESIGHT_DEV_SUBTYPE_ECT_NONE,
75 CORESIGHT_DEV_SUBTYPE_ECT_CTI,
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
81 * by @coresight_dev_subtype_sink.
82 * @link_subtype: type of link this component is, as defined
83 * by @coresight_dev_subtype_link.
84 * @source_subtype: type of source this component is, as defined
85 * by @coresight_dev_subtype_source.
86 * @helper_subtype: type of helper this component is, as defined
87 * by @coresight_dev_subtype_helper.
88 * @ect_subtype: type of cross trigger this component is, as
89 * defined by @coresight_dev_subtype_ect
91 union coresight_dev_subtype {
92 /* We have some devices which acts as LINK and SINK */
94 enum coresight_dev_subtype_sink sink_subtype;
95 enum coresight_dev_subtype_link link_subtype;
97 enum coresight_dev_subtype_source source_subtype;
98 enum coresight_dev_subtype_helper helper_subtype;
99 enum coresight_dev_subtype_ect ect_subtype;
103 * struct coresight_platform_data - data harvested from the firmware
106 * @nr_inport: Number of elements for the input connections.
107 * @nr_outport: Number of elements for the output connections.
108 * @conns: Sparse array of nr_outport connections from this component.
110 struct coresight_platform_data {
113 struct coresight_connection *conns;
117 * struct coresight_desc - description of a component required from drivers
118 * @type: as defined by @coresight_dev_type.
119 * @subtype: as defined by @coresight_dev_subtype.
120 * @ops: generic operations for this component, as defined
122 * @pdata: platform data collected from DT.
123 * @dev: The device entity associated to this component.
124 * @groups: operations specific to this component. These will end up
125 * in the component's sysfs sub-directory.
126 * @name: name for the coresight device, also shown under sysfs.
128 struct coresight_desc {
129 enum coresight_dev_type type;
130 union coresight_dev_subtype subtype;
131 const struct coresight_ops *ops;
132 struct coresight_platform_data *pdata;
134 const struct attribute_group **groups;
139 * struct coresight_connection - representation of a single connection
140 * @outport: a connection's output port number.
141 * @child_port: remote component's port number @output is connected to.
142 * @chid_fwnode: remote component's fwnode handle.
143 * @child_dev: a @coresight_device representation of the component
144 connected to @outport.
146 struct coresight_connection {
149 struct fwnode_handle *child_fwnode;
150 struct coresight_device *child_dev;
154 * struct coresight_device - representation of a device as used by the framework
155 * @pdata: Platform data with device connections associated to this device.
156 * @type: as defined by @coresight_dev_type.
157 * @subtype: as defined by @coresight_dev_subtype.
158 * @ops: generic operations for this component, as defined
160 * @dev: The device entity associated to this component.
161 * @refcnt: keep track of what is in use.
162 * @orphan: true if the component has connections that haven't been linked.
163 * @enable: 'true' if component is currently part of an active path.
164 * @activated: 'true' only if a _sink_ has been activated. A sink can be
165 * activated but not yet enabled. Enabling for a _sink_
166 * appens when a source has been selected for that it.
167 * @ea: Device attribute for sink representation under PMU directory.
168 * @ect_dev: Associated cross trigger device. Not part of the trace data
169 * path or connections.
171 struct coresight_device {
172 struct coresight_platform_data *pdata;
173 enum coresight_dev_type type;
174 union coresight_dev_subtype subtype;
175 const struct coresight_ops *ops;
179 bool enable; /* true only if configured as part of a path */
180 /* sink specific fields */
181 bool activated; /* true only if a sink is part of a path */
182 struct dev_ext_attribute *ea;
183 /* cross trigger handling */
184 struct coresight_device *ect_dev;
188 * coresight_dev_list - Mapping for devices to "name" index for device
191 * @nr_idx: Number of entries already allocated.
192 * @pfx: Prefix pattern for device name.
193 * @fwnode_list: Array of fwnode_handles associated with each allocated
194 * index, upto nr_idx entries.
196 struct coresight_dev_list {
199 struct fwnode_handle **fwnode_list;
202 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
203 static struct coresight_dev_list (var) = { \
206 .fwnode_list = NULL, \
209 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
211 #define source_ops(csdev) csdev->ops->source_ops
212 #define sink_ops(csdev) csdev->ops->sink_ops
213 #define link_ops(csdev) csdev->ops->link_ops
214 #define helper_ops(csdev) csdev->ops->helper_ops
215 #define ect_ops(csdev) csdev->ops->ect_ops
218 * struct coresight_ops_sink - basic operations for a sink
219 * Operations available for sinks
220 * @enable: enables the sink.
221 * @disable: disables the sink.
222 * @alloc_buffer: initialises perf's ring buffer for trace collection.
223 * @free_buffer: release memory allocated in @get_config.
224 * @update_buffer: update buffer pointers after a trace session.
226 struct coresight_ops_sink {
227 int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
228 int (*disable)(struct coresight_device *csdev);
229 void *(*alloc_buffer)(struct coresight_device *csdev,
230 struct perf_event *event, void **pages,
231 int nr_pages, bool overwrite);
232 void (*free_buffer)(void *config);
233 unsigned long (*update_buffer)(struct coresight_device *csdev,
234 struct perf_output_handle *handle,
239 * struct coresight_ops_link - basic operations for a link
240 * Operations available for links.
241 * @enable: enables flow between iport and oport.
242 * @disable: disables flow between iport and oport.
244 struct coresight_ops_link {
245 int (*enable)(struct coresight_device *csdev, int iport, int oport);
246 void (*disable)(struct coresight_device *csdev, int iport, int oport);
250 * struct coresight_ops_source - basic operations for a source
251 * Operations available for sources.
252 * @cpu_id: returns the value of the CPU number this component
254 * @trace_id: returns the value of the component's trace ID as known
256 * @enable: enables tracing for a source.
257 * @disable: disables tracing for a source.
259 struct coresight_ops_source {
260 int (*cpu_id)(struct coresight_device *csdev);
261 int (*trace_id)(struct coresight_device *csdev);
262 int (*enable)(struct coresight_device *csdev,
263 struct perf_event *event, u32 mode);
264 void (*disable)(struct coresight_device *csdev,
265 struct perf_event *event);
269 * struct coresight_ops_helper - Operations for a helper device.
271 * All operations could pass in a device specific data, which could
272 * help the helper device to determine what to do.
274 * @enable : Enable the device
275 * @disable : Disable the device
277 struct coresight_ops_helper {
278 int (*enable)(struct coresight_device *csdev, void *data);
279 int (*disable)(struct coresight_device *csdev, void *data);
283 * struct coresight_ops_ect - Ops for an embedded cross trigger device
285 * @enable : Enable the device
286 * @disable : Disable the device
288 struct coresight_ops_ect {
289 int (*enable)(struct coresight_device *csdev);
290 int (*disable)(struct coresight_device *csdev);
293 struct coresight_ops {
294 const struct coresight_ops_sink *sink_ops;
295 const struct coresight_ops_link *link_ops;
296 const struct coresight_ops_source *source_ops;
297 const struct coresight_ops_helper *helper_ops;
298 const struct coresight_ops_ect *ect_ops;
301 #ifdef CONFIG_CORESIGHT
302 extern struct coresight_device *
303 coresight_register(struct coresight_desc *desc);
304 extern void coresight_unregister(struct coresight_device *csdev);
305 extern int coresight_enable(struct coresight_device *csdev);
306 extern void coresight_disable(struct coresight_device *csdev);
307 extern int coresight_timeout(void __iomem *addr, u32 offset,
308 int position, int value);
310 extern int coresight_claim_device(void __iomem *base);
311 extern int coresight_claim_device_unlocked(void __iomem *base);
313 extern void coresight_disclaim_device(void __iomem *base);
314 extern void coresight_disclaim_device_unlocked(void __iomem *base);
315 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
318 extern bool coresight_loses_context_with_cpu(struct device *dev);
320 static inline struct coresight_device *
321 coresight_register(struct coresight_desc *desc) { return NULL; }
322 static inline void coresight_unregister(struct coresight_device *csdev) {}
324 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
325 static inline void coresight_disable(struct coresight_device *csdev) {}
326 static inline int coresight_timeout(void __iomem *addr, u32 offset,
327 int position, int value) { return 1; }
328 static inline int coresight_claim_device_unlocked(void __iomem *base)
333 static inline int coresight_claim_device(void __iomem *base)
338 static inline void coresight_disclaim_device(void __iomem *base) {}
339 static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
341 static inline bool coresight_loses_context_with_cpu(struct device *dev)
347 extern int coresight_get_cpu(struct device *dev);
349 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);