Linux-libre 4.14.132-gnu
[librecmc/linux-libre.git] / include / dt-bindings / clock / qcom,gcc-mdm9615.h
1 /*
2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3  * Copyright (c) BayLibre, SAS.
4  * Author : Neil Armstrong <narmstrong@baylibre.com>
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H
17 #define _DT_BINDINGS_CLK_MDM_GCC_9615_H
18
19 #define AFAB_CLK_SRC                            0
20 #define AFAB_CORE_CLK                           1
21 #define SFAB_MSS_Q6_SW_A_CLK                    2
22 #define SFAB_MSS_Q6_FW_A_CLK                    3
23 #define QDSS_STM_CLK                            4
24 #define SCSS_A_CLK                              5
25 #define SCSS_H_CLK                              6
26 #define SCSS_XO_SRC_CLK                         7
27 #define AFAB_EBI1_CH0_A_CLK                     8
28 #define AFAB_EBI1_CH1_A_CLK                     9
29 #define AFAB_AXI_S0_FCLK                        10
30 #define AFAB_AXI_S1_FCLK                        11
31 #define AFAB_AXI_S2_FCLK                        12
32 #define AFAB_AXI_S3_FCLK                        13
33 #define AFAB_AXI_S4_FCLK                        14
34 #define SFAB_CORE_CLK                           15
35 #define SFAB_AXI_S0_FCLK                        16
36 #define SFAB_AXI_S1_FCLK                        17
37 #define SFAB_AXI_S2_FCLK                        18
38 #define SFAB_AXI_S3_FCLK                        19
39 #define SFAB_AXI_S4_FCLK                        20
40 #define SFAB_AHB_S0_FCLK                        21
41 #define SFAB_AHB_S1_FCLK                        22
42 #define SFAB_AHB_S2_FCLK                        23
43 #define SFAB_AHB_S3_FCLK                        24
44 #define SFAB_AHB_S4_FCLK                        25
45 #define SFAB_AHB_S5_FCLK                        26
46 #define SFAB_AHB_S6_FCLK                        27
47 #define SFAB_AHB_S7_FCLK                        28
48 #define QDSS_AT_CLK_SRC                         29
49 #define QDSS_AT_CLK                             30
50 #define QDSS_TRACECLKIN_CLK_SRC                 31
51 #define QDSS_TRACECLKIN_CLK                     32
52 #define QDSS_TSCTR_CLK_SRC                      33
53 #define QDSS_TSCTR_CLK                          34
54 #define SFAB_ADM0_M0_A_CLK                      35
55 #define SFAB_ADM0_M1_A_CLK                      36
56 #define SFAB_ADM0_M2_H_CLK                      37
57 #define ADM0_CLK                                38
58 #define ADM0_PBUS_CLK                           39
59 #define MSS_XPU_CLK                             40
60 #define IMEM0_A_CLK                             41
61 #define QDSS_H_CLK                              42
62 #define PCIE_A_CLK                              43
63 #define PCIE_AUX_CLK                            44
64 #define PCIE_PHY_REF_CLK                        45
65 #define PCIE_H_CLK                              46
66 #define SFAB_CLK_SRC                            47
67 #define MAHB0_CLK                               48
68 #define Q6SW_CLK_SRC                            49
69 #define Q6SW_CLK                                50
70 #define Q6FW_CLK_SRC                            51
71 #define Q6FW_CLK                                52
72 #define SFAB_MSS_M_A_CLK                        53
73 #define SFAB_USB3_M_A_CLK                       54
74 #define SFAB_LPASS_Q6_A_CLK                     55
75 #define SFAB_AFAB_M_A_CLK                       56
76 #define AFAB_SFAB_M0_A_CLK                      57
77 #define AFAB_SFAB_M1_A_CLK                      58
78 #define SFAB_SATA_S_H_CLK                       59
79 #define DFAB_CLK_SRC                            60
80 #define DFAB_CLK                                61
81 #define SFAB_DFAB_M_A_CLK                       62
82 #define DFAB_SFAB_M_A_CLK                       63
83 #define DFAB_SWAY0_H_CLK                        64
84 #define DFAB_SWAY1_H_CLK                        65
85 #define DFAB_ARB0_H_CLK                         66
86 #define DFAB_ARB1_H_CLK                         67
87 #define PPSS_H_CLK                              68
88 #define PPSS_PROC_CLK                           69
89 #define PPSS_TIMER0_CLK                         70
90 #define PPSS_TIMER1_CLK                         71
91 #define PMEM_A_CLK                              72
92 #define DMA_BAM_H_CLK                           73
93 #define SIC_H_CLK                               74
94 #define SPS_TIC_H_CLK                           75
95 #define SLIMBUS_H_CLK                           76
96 #define SLIMBUS_XO_SRC_CLK                      77
97 #define CFPB_2X_CLK_SRC                         78
98 #define CFPB_CLK                                79
99 #define CFPB0_H_CLK                             80
100 #define CFPB1_H_CLK                             81
101 #define CFPB2_H_CLK                             82
102 #define SFAB_CFPB_M_H_CLK                       83
103 #define CFPB_MASTER_H_CLK                       84
104 #define SFAB_CFPB_S_H_CLK                       85
105 #define CFPB_SPLITTER_H_CLK                     86
106 #define TSIF_H_CLK                              87
107 #define TSIF_INACTIVITY_TIMERS_CLK              88
108 #define TSIF_REF_SRC                            89
109 #define TSIF_REF_CLK                            90
110 #define CE1_H_CLK                               91
111 #define CE1_CORE_CLK                            92
112 #define CE1_SLEEP_CLK                           93
113 #define CE2_H_CLK                               94
114 #define CE2_CORE_CLK                            95
115 #define SFPB_H_CLK_SRC                          97
116 #define SFPB_H_CLK                              98
117 #define SFAB_SFPB_M_H_CLK                       99
118 #define SFAB_SFPB_S_H_CLK                       100
119 #define RPM_PROC_CLK                            101
120 #define RPM_BUS_H_CLK                           102
121 #define RPM_SLEEP_CLK                           103
122 #define RPM_TIMER_CLK                           104
123 #define RPM_MSG_RAM_H_CLK                       105
124 #define PMIC_ARB0_H_CLK                         106
125 #define PMIC_ARB1_H_CLK                         107
126 #define PMIC_SSBI2_SRC                          108
127 #define PMIC_SSBI2_CLK                          109
128 #define SDC1_H_CLK                              110
129 #define SDC2_H_CLK                              111
130 #define SDC3_H_CLK                              112
131 #define SDC4_H_CLK                              113
132 #define SDC5_H_CLK                              114
133 #define SDC1_SRC                                115
134 #define SDC2_SRC                                116
135 #define SDC3_SRC                                117
136 #define SDC4_SRC                                118
137 #define SDC5_SRC                                119
138 #define SDC1_CLK                                120
139 #define SDC2_CLK                                121
140 #define SDC3_CLK                                122
141 #define SDC4_CLK                                123
142 #define SDC5_CLK                                124
143 #define DFAB_A2_H_CLK                           125
144 #define USB_HS1_H_CLK                           126
145 #define USB_HS1_XCVR_SRC                        127
146 #define USB_HS1_XCVR_CLK                        128
147 #define USB_HSIC_H_CLK                          129
148 #define USB_HSIC_XCVR_FS_SRC                    130
149 #define USB_HSIC_XCVR_FS_CLK                    131
150 #define USB_HSIC_SYSTEM_CLK_SRC                 132
151 #define USB_HSIC_SYSTEM_CLK                     133
152 #define CFPB0_C0_H_CLK                          134
153 #define CFPB0_C1_H_CLK                          135
154 #define CFPB0_D0_H_CLK                          136
155 #define CFPB0_D1_H_CLK                          137
156 #define USB_FS1_H_CLK                           138
157 #define USB_FS1_XCVR_FS_SRC                     139
158 #define USB_FS1_XCVR_FS_CLK                     140
159 #define USB_FS1_SYSTEM_CLK                      141
160 #define USB_FS2_H_CLK                           142
161 #define USB_FS2_XCVR_FS_SRC                     143
162 #define USB_FS2_XCVR_FS_CLK                     144
163 #define USB_FS2_SYSTEM_CLK                      145
164 #define GSBI_COMMON_SIM_SRC                     146
165 #define GSBI1_H_CLK                             147
166 #define GSBI2_H_CLK                             148
167 #define GSBI3_H_CLK                             149
168 #define GSBI4_H_CLK                             150
169 #define GSBI5_H_CLK                             151
170 #define GSBI6_H_CLK                             152
171 #define GSBI7_H_CLK                             153
172 #define GSBI8_H_CLK                             154
173 #define GSBI9_H_CLK                             155
174 #define GSBI10_H_CLK                            156
175 #define GSBI11_H_CLK                            157
176 #define GSBI12_H_CLK                            158
177 #define GSBI1_UART_SRC                          159
178 #define GSBI1_UART_CLK                          160
179 #define GSBI2_UART_SRC                          161
180 #define GSBI2_UART_CLK                          162
181 #define GSBI3_UART_SRC                          163
182 #define GSBI3_UART_CLK                          164
183 #define GSBI4_UART_SRC                          165
184 #define GSBI4_UART_CLK                          166
185 #define GSBI5_UART_SRC                          167
186 #define GSBI5_UART_CLK                          168
187 #define GSBI6_UART_SRC                          169
188 #define GSBI6_UART_CLK                          170
189 #define GSBI7_UART_SRC                          171
190 #define GSBI7_UART_CLK                          172
191 #define GSBI8_UART_SRC                          173
192 #define GSBI8_UART_CLK                          174
193 #define GSBI9_UART_SRC                          175
194 #define GSBI9_UART_CLK                          176
195 #define GSBI10_UART_SRC                         177
196 #define GSBI10_UART_CLK                         178
197 #define GSBI11_UART_SRC                         179
198 #define GSBI11_UART_CLK                         180
199 #define GSBI12_UART_SRC                         181
200 #define GSBI12_UART_CLK                         182
201 #define GSBI1_QUP_SRC                           183
202 #define GSBI1_QUP_CLK                           184
203 #define GSBI2_QUP_SRC                           185
204 #define GSBI2_QUP_CLK                           186
205 #define GSBI3_QUP_SRC                           187
206 #define GSBI3_QUP_CLK                           188
207 #define GSBI4_QUP_SRC                           189
208 #define GSBI4_QUP_CLK                           190
209 #define GSBI5_QUP_SRC                           191
210 #define GSBI5_QUP_CLK                           192
211 #define GSBI6_QUP_SRC                           193
212 #define GSBI6_QUP_CLK                           194
213 #define GSBI7_QUP_SRC                           195
214 #define GSBI7_QUP_CLK                           196
215 #define GSBI8_QUP_SRC                           197
216 #define GSBI8_QUP_CLK                           198
217 #define GSBI9_QUP_SRC                           199
218 #define GSBI9_QUP_CLK                           200
219 #define GSBI10_QUP_SRC                          201
220 #define GSBI10_QUP_CLK                          202
221 #define GSBI11_QUP_SRC                          203
222 #define GSBI11_QUP_CLK                          204
223 #define GSBI12_QUP_SRC                          205
224 #define GSBI12_QUP_CLK                          206
225 #define GSBI1_SIM_CLK                           207
226 #define GSBI2_SIM_CLK                           208
227 #define GSBI3_SIM_CLK                           209
228 #define GSBI4_SIM_CLK                           210
229 #define GSBI5_SIM_CLK                           211
230 #define GSBI6_SIM_CLK                           212
231 #define GSBI7_SIM_CLK                           213
232 #define GSBI8_SIM_CLK                           214
233 #define GSBI9_SIM_CLK                           215
234 #define GSBI10_SIM_CLK                          216
235 #define GSBI11_SIM_CLK                          217
236 #define GSBI12_SIM_CLK                          218
237 #define USB_HSIC_HSIC_CLK_SRC                   219
238 #define USB_HSIC_HSIC_CLK                       220
239 #define USB_HSIC_HSIO_CAL_CLK                   221
240 #define SPDM_CFG_H_CLK                          222
241 #define SPDM_MSTR_H_CLK                         223
242 #define SPDM_FF_CLK_SRC                         224
243 #define SPDM_FF_CLK                             225
244 #define SEC_CTRL_CLK                            226
245 #define SEC_CTRL_ACC_CLK_SRC                    227
246 #define SEC_CTRL_ACC_CLK                        228
247 #define TLMM_H_CLK                              229
248 #define TLMM_CLK                                230
249 #define SFAB_MSS_S_H_CLK                        231
250 #define MSS_SLP_CLK                             232
251 #define MSS_Q6SW_JTAG_CLK                       233
252 #define MSS_Q6FW_JTAG_CLK                       234
253 #define MSS_S_H_CLK                             235
254 #define MSS_CXO_SRC_CLK                         236
255 #define SATA_H_CLK                              237
256 #define SATA_CLK_SRC                            238
257 #define SATA_RXOOB_CLK                          239
258 #define SATA_PMALIVE_CLK                        240
259 #define SATA_PHY_REF_CLK                        241
260 #define TSSC_CLK_SRC                            242
261 #define TSSC_CLK                                243
262 #define PDM_SRC                                 244
263 #define PDM_CLK                                 245
264 #define GP0_SRC                                 246
265 #define GP0_CLK                                 247
266 #define GP1_SRC                                 248
267 #define GP1_CLK                                 249
268 #define GP2_SRC                                 250
269 #define GP2_CLK                                 251
270 #define MPM_CLK                                 252
271 #define EBI1_CLK_SRC                            253
272 #define EBI1_CH0_CLK                            254
273 #define EBI1_CH1_CLK                            255
274 #define EBI1_2X_CLK                             256
275 #define EBI1_CH0_DQ_CLK                         257
276 #define EBI1_CH1_DQ_CLK                         258
277 #define EBI1_CH0_CA_CLK                         259
278 #define EBI1_CH1_CA_CLK                         260
279 #define EBI1_XO_CLK                             261
280 #define SFAB_SMPSS_S_H_CLK                      262
281 #define PRNG_SRC                                263
282 #define PRNG_CLK                                264
283 #define PXO_SRC                                 265
284 #define LPASS_CXO_CLK                           266
285 #define LPASS_PXO_CLK                           267
286 #define SPDM_CY_PORT0_CLK                       268
287 #define SPDM_CY_PORT1_CLK                       269
288 #define SPDM_CY_PORT2_CLK                       270
289 #define SPDM_CY_PORT3_CLK                       271
290 #define SPDM_CY_PORT4_CLK                       272
291 #define SPDM_CY_PORT5_CLK                       273
292 #define SPDM_CY_PORT6_CLK                       274
293 #define SPDM_CY_PORT7_CLK                       275
294 #define PLL0                                    276
295 #define PLL0_VOTE                               277
296 #define PLL3                                    278
297 #define PLL3_VOTE                               279
298 #define PLL4_VOTE                               280
299 #define PLL5                                    281
300 #define PLL5_VOTE                               282
301 #define PLL6                                    283
302 #define PLL6_VOTE                               284
303 #define PLL7_VOTE                               285
304 #define PLL8                                    286
305 #define PLL8_VOTE                               287
306 #define PLL9                                    288
307 #define PLL10                                   289
308 #define PLL11                                   290
309 #define PLL12                                   291
310 #define PLL13                                   292
311 #define PLL14                                   293
312 #define PLL14_VOTE                              294
313 #define USB_HS3_H_CLK                           295
314 #define USB_HS3_XCVR_SRC                        296
315 #define USB_HS3_XCVR_CLK                        297
316 #define USB_HS4_H_CLK                           298
317 #define USB_HS4_XCVR_SRC                        299
318 #define USB_HS4_XCVR_CLK                        300
319 #define SATA_PHY_CFG_CLK                        301
320 #define SATA_A_CLK                              302
321 #define CE3_SRC                                 303
322 #define CE3_CORE_CLK                            304
323 #define CE3_H_CLK                               305
324 #define USB_HS1_SYSTEM_CLK_SRC                  306
325 #define USB_HS1_SYSTEM_CLK                      307
326 #define EBI2_CLK                                308
327 #define EBI2_AON_CLK                            309
328
329 #endif