drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #include <linux/interrupt.h>
  27
  28 #ifdef pr_fmt
  29 #undef pr_fmt
  30 #endif
  31
  32 #ifdef DSS_SUBSYS_NAME
  33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  34 #else
  35 #define pr_fmt(fmt) fmt
  36 #endif
  37
  38 #define DSSDBG(format, ...) \
  39         pr_debug(format, ## __VA_ARGS__)
  40
  41 #ifdef DSS_SUBSYS_NAME
  42 #define DSSERR(format, ...) \
  43         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  44         ## __VA_ARGS__)
  45 #else
  46 #define DSSERR(format, ...) \
  47         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  48 #endif
  49
  50 #ifdef DSS_SUBSYS_NAME
  51 #define DSSINFO(format, ...) \
  52         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  53         ## __VA_ARGS__)
  54 #else
  55 #define DSSINFO(format, ...) \
  56         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  57 #endif
  58
  59 #ifdef DSS_SUBSYS_NAME
  60 #define DSSWARN(format, ...) \
  61         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  62         ## __VA_ARGS__)
  63 #else
  64 #define DSSWARN(format, ...) \
  65         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  66 #endif
  67
  68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  69    number. For example 7:0 */
  70 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  73 #define FLD_MOD(orig, val, start, end) \
  74         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  75
  76 enum dss_io_pad_mode {
  77         DSS_IO_PAD_MODE_RESET,
  78         DSS_IO_PAD_MODE_RFBI,
  79         DSS_IO_PAD_MODE_BYPASS,
  80 };
  81
  82 enum dss_hdmi_venc_clk_source_select {
  83         DSS_VENC_TV_CLK = 0,
  84         DSS_HDMI_M_PCLK = 1,
  85 };
  86
  87 enum dss_dsi_content_type {
  88         DSS_DSI_CONTENT_DCS,
  89         DSS_DSI_CONTENT_GENERIC,
  90 };
  91
  92 enum dss_writeback_channel {
  93         DSS_WB_LCD1_MGR =       0,
  94         DSS_WB_LCD2_MGR =       1,
  95         DSS_WB_TV_MGR =         2,
  96         DSS_WB_OVL0 =           3,
  97         DSS_WB_OVL1 =           4,
  98         DSS_WB_OVL2 =           5,
  99         DSS_WB_OVL3 =           6,
 100         DSS_WB_LCD3_MGR =       7,
 101 };
 102
 103 struct dss_clock_info {
 104         /* rates that we get with dividers below */
 105         unsigned long fck;
 106
 107         /* dividers */
 108         u16 fck_div;
 109 };
 110
 111 struct dispc_clock_info {
 112         /* rates that we get with dividers below */
 113         unsigned long lck;
 114         unsigned long pck;
 115
 116         /* dividers */
 117         u16 lck_div;
 118         u16 pck_div;
 119 };
 120
 121 struct dsi_clock_info {
 122         /* rates that we get with dividers below */
 123         unsigned long fint;
 124         unsigned long clkin4ddr;
 125         unsigned long clkin;
 126         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 127                                                  * OMAP4: PLLx_CLK1 */
 128         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 129                                                  * OMAP4: PLLx_CLK2 */
 130         unsigned long lp_clk;
 131
 132         /* dividers */
 133         u16 regn;
 134         u16 regm;
 135         u16 regm_dispc; /* OMAP3: REGM3
 136                          * OMAP4: REGM4 */
 137         u16 regm_dsi;   /* OMAP3: REGM4
 138                          * OMAP4: REGM5 */
 139         u16 lp_clk_div;
 140 };
 141
 142 struct reg_field {
 143         u16 reg;
 144         u8 high;
 145         u8 low;
 146 };
 147
 148 struct dss_lcd_mgr_config {
 149         enum dss_io_pad_mode io_pad_mode;
 150
 151         bool stallmode;
 152         bool fifohandcheck;
 153
 154         struct dispc_clock_info clock_info;
 155
 156         int video_port_width;
 157
 158         int lcden_sig_polarity;
 159 };
 160
 161 struct seq_file;
 162 struct platform_device;
 163
 164 /* core */
 165 struct platform_device *dss_get_core_pdev(void);
 166 struct bus_type *dss_get_bus(void);
 167 struct regulator *dss_get_vdds_dsi(void);
 168 struct regulator *dss_get_vdds_sdi(void);
 169 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 170 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 171 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 172 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 173
 174 struct omap_dss_device *dss_alloc_and_init_device(struct device *parent);
 175 int dss_add_device(struct omap_dss_device *dssdev);
 176 void dss_unregister_device(struct omap_dss_device *dssdev);
 177 void dss_unregister_child_devices(struct device *parent);
 178 void dss_put_device(struct omap_dss_device *dssdev);
 179 void dss_copy_device_pdata(struct omap_dss_device *dst,
 180                 const struct omap_dss_device *src);
 181
 182 /* output */
 183 void dss_register_output(struct omap_dss_output *out);
 184 void dss_unregister_output(struct omap_dss_output *out);
 185
 186 /* display */
 187 int dss_suspend_all_devices(void);
 188 int dss_resume_all_devices(void);
 189 void dss_disable_all_devices(void);
 190
 191 int display_init_sysfs(struct platform_device *pdev,
 192                 struct omap_dss_device *dssdev);
 193 void display_uninit_sysfs(struct platform_device *pdev,
 194                 struct omap_dss_device *dssdev);
 195
 196 /* manager */
 197 int dss_init_overlay_managers(struct platform_device *pdev);
 198 void dss_uninit_overlay_managers(struct platform_device *pdev);
 199 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
 200                 const struct omap_overlay_manager_info *info);
 201 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
 202                 const struct omap_video_timings *timings);
 203 int dss_mgr_check(struct omap_overlay_manager *mgr,
 204                 struct omap_overlay_manager_info *info,
 205                 const struct omap_video_timings *mgr_timings,
 206                 const struct dss_lcd_mgr_config *config,
 207                 struct omap_overlay_info **overlay_infos);
 208
 209 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 210 {
 211         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 212                         id == OMAP_DSS_CHANNEL_LCD3)
 213                 return true;
 214         else
 215                 return false;
 216 }
 217
 218 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
 219                 struct platform_device *pdev);
 220 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
 221
 222 /* overlay */
 223 void dss_init_overlays(struct platform_device *pdev);
 224 void dss_uninit_overlays(struct platform_device *pdev);
 225 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 226 int dss_ovl_simple_check(struct omap_overlay *ovl,
 227                 const struct omap_overlay_info *info);
 228 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
 229                 const struct omap_video_timings *mgr_timings);
 230 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
 231                 enum omap_color_mode mode);
 232 int dss_overlay_kobj_init(struct omap_overlay *ovl,
 233                 struct platform_device *pdev);
 234 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
 235
 236 /* DSS */
 237 int dss_init_platform_driver(void) __init;
 238 void dss_uninit_platform_driver(void);
 239
 240 unsigned long dss_get_dispc_clk_rate(void);
 241 int dss_dpi_select_source(enum omap_channel channel);
 242 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 243 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 244 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 245 void dss_dump_clocks(struct seq_file *s);
 246
 247 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 248 void dss_debug_dump_clocks(struct seq_file *s);
 249 #endif
 250
 251 int dss_get_ctx_loss_count(void);
 252
 253 void dss_sdi_init(int datapairs);
 254 int dss_sdi_enable(void);
 255 void dss_sdi_disable(void);
 256
 257 void dss_select_dsi_clk_source(int dsi_module,
 258                 enum omap_dss_clk_source clk_src);
 259 void dss_select_lcd_clk_source(enum omap_channel channel,
 260                 enum omap_dss_clk_source clk_src);
 261 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 262 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 263 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 264
 265 void dss_set_venc_output(enum omap_dss_venc_type type);
 266 void dss_set_dac_pwrdn_bgz(bool enable);
 267
 268 unsigned long dss_get_dpll4_rate(void);
 269 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 270 int dss_set_clock_div(struct dss_clock_info *cinfo);
 271
 272 typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data);
 273 bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data);
 274
 275 /* SDI */
 276 int sdi_init_platform_driver(void) __init;
 277 void sdi_uninit_platform_driver(void) __exit;
 278
 279 /* DSI */
 280
 281 typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
 282                 unsigned long pll, void *data);
 283 typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
 284                 void *data);
 285
 286 #ifdef CONFIG_OMAP2_DSS_DSI
 287
 288 struct dentry;
 289 struct file_operations;
 290
 291 int dsi_init_platform_driver(void) __init;
 292 void dsi_uninit_platform_driver(void) __exit;
 293
 294 int dsi_runtime_get(struct platform_device *dsidev);
 295 void dsi_runtime_put(struct platform_device *dsidev);
 296
 297 void dsi_dump_clocks(struct seq_file *s);
 298
 299 void dsi_irq_handler(void);
 300 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 301
 302 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
 303
 304 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
 305                 unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
 306 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
 307                 unsigned long pll_min, unsigned long pll_max,
 308                 dsi_pll_calc_func func, void *data);
 309
 310 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 311 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 312                 struct dsi_clock_info *cinfo);
 313 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 314                 bool enable_hsdiv);
 315 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 316 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 317 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 318 struct platform_device *dsi_get_dsidev_from_id(int module);
 319 #else
 320 static inline int dsi_runtime_get(struct platform_device *dsidev)
 321 {
 322         return 0;
 323 }
 324 static inline void dsi_runtime_put(struct platform_device *dsidev)
 325 {
 326 }
 327 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 328 {
 329         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 330         return 0;
 331 }
 332 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 333 {
 334         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 335         return 0;
 336 }
 337 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 338                 struct dsi_clock_info *cinfo)
 339 {
 340         WARN("%s: DSI not compiled in\n", __func__);
 341         return -ENODEV;
 342 }
 343 static inline int dsi_pll_init(struct platform_device *dsidev,
 344                 bool enable_hsclk, bool enable_hsdiv)
 345 {
 346         WARN("%s: DSI not compiled in\n", __func__);
 347         return -ENODEV;
 348 }
 349 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 350                 bool disconnect_lanes)
 351 {
 352 }
 353 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 354 {
 355 }
 356 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 357 {
 358 }
 359 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 360 {
 361         return NULL;
 362 }
 363
 364 static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
 365 {
 366         return 0;
 367 }
 368
 369 static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
 370                 unsigned long pll, unsigned long out_min,
 371                 dsi_hsdiv_calc_func func, void *data)
 372 {
 373         return false;
 374 }
 375
 376 static inline bool dsi_pll_calc(struct platform_device *dsidev,
 377                 unsigned long clkin,
 378                 unsigned long pll_min, unsigned long pll_max,
 379                 dsi_pll_calc_func func, void *data)
 380 {
 381         return false;
 382 }
 383
 384 #endif
 385
 386 /* DPI */
 387 int dpi_init_platform_driver(void) __init;
 388 void dpi_uninit_platform_driver(void) __exit;
 389
 390 /* DISPC */
 391 int dispc_init_platform_driver(void) __init;
 392 void dispc_uninit_platform_driver(void) __exit;
 393 void dispc_dump_clocks(struct seq_file *s);
 394
 395 void dispc_enable_sidle(void);
 396 void dispc_disable_sidle(void);
 397
 398 void dispc_lcd_enable_signal(bool enable);
 399 void dispc_pck_free_enable(bool enable);
 400 void dispc_enable_fifomerge(bool enable);
 401 void dispc_enable_gamma_table(bool enable);
 402 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 403
 404 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
 405                 unsigned long pck, void *data);
 406 bool dispc_div_calc(unsigned long dispc,
 407                 unsigned long pck_min, unsigned long pck_max,
 408                 dispc_div_calc_func func, void *data);
 409
 410 bool dispc_mgr_timings_ok(enum omap_channel channel,
 411                 const struct omap_video_timings *timings);
 412 unsigned long dispc_fclk_rate(void);
 413 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 414                 struct dispc_clock_info *cinfo);
 415
 416
 417 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 418 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 419                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 420                 bool manual_update);
 421
 422 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 423 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 424 unsigned long dispc_core_clk_rate(void);
 425 void dispc_mgr_set_clock_div(enum omap_channel channel,
 426                 const struct dispc_clock_info *cinfo);
 427 int dispc_mgr_get_clock_div(enum omap_channel channel,
 428                 struct dispc_clock_info *cinfo);
 429
 430 u32 dispc_wb_get_framedone_irq(void);
 431 bool dispc_wb_go_busy(void);
 432 void dispc_wb_go(void);
 433 void dispc_wb_enable(bool enable);
 434 bool dispc_wb_is_enabled(void);
 435 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 436 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 437                 bool mem_to_mem, const struct omap_video_timings *timings);
 438
 439 /* VENC */
 440 #ifdef CONFIG_OMAP2_DSS_VENC
 441 int venc_init_platform_driver(void) __init;
 442 void venc_uninit_platform_driver(void) __exit;
 443 unsigned long venc_get_pixel_clock(void);
 444 #else
 445 static inline unsigned long venc_get_pixel_clock(void)
 446 {
 447         WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
 448         return 0;
 449 }
 450 #endif
 451 int omapdss_venc_display_enable(struct omap_dss_device *dssdev);
 452 void omapdss_venc_display_disable(struct omap_dss_device *dssdev);
 453 void omapdss_venc_set_timings(struct omap_dss_device *dssdev,
 454                 struct omap_video_timings *timings);
 455 int omapdss_venc_check_timings(struct omap_dss_device *dssdev,
 456                 struct omap_video_timings *timings);
 457 u32 omapdss_venc_get_wss(struct omap_dss_device *dssdev);
 458 int omapdss_venc_set_wss(struct omap_dss_device *dssdev, u32 wss);
 459 void omapdss_venc_set_type(struct omap_dss_device *dssdev,
 460                 enum omap_dss_venc_type type);
 461 void omapdss_venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
 462                 bool invert_polarity);
 463 int venc_panel_init(void);
 464 void venc_panel_exit(void);
 465
 466 /* HDMI */
 467 #ifdef CONFIG_OMAP4_DSS_HDMI
 468 int hdmi_init_platform_driver(void) __init;
 469 void hdmi_uninit_platform_driver(void) __exit;
 470 unsigned long hdmi_get_pixel_clock(void);
 471 #else
 472 static inline unsigned long hdmi_get_pixel_clock(void)
 473 {
 474         WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
 475         return 0;
 476 }
 477 #endif
 478 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 479 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 480 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev);
 481 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev);
 482 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
 483                 struct omap_video_timings *timings);
 484 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 485                                         struct omap_video_timings *timings);
 486 int omapdss_hdmi_read_edid(u8 *buf, int len);
 487 bool omapdss_hdmi_detect(void);
 488 int hdmi_panel_init(void);
 489 void hdmi_panel_exit(void);
 490 #ifdef CONFIG_OMAP4_DSS_HDMI_AUDIO
 491 int hdmi_audio_enable(void);
 492 void hdmi_audio_disable(void);
 493 int hdmi_audio_start(void);
 494 void hdmi_audio_stop(void);
 495 bool hdmi_mode_has_audio(void);
 496 int hdmi_audio_config(struct omap_dss_audio *audio);
 497 #endif
 498
 499 /* RFBI */
 500 int rfbi_init_platform_driver(void) __init;
 501 void rfbi_uninit_platform_driver(void) __exit;
 502
 503
 504 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 505 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 506 {
 507         int b;
 508         for (b = 0; b < 32; ++b) {
 509                 if (irqstatus & (1 << b))
 510                         irq_arr[b]++;
 511         }
 512 }
 513 #endif
 514
 515 #endif