2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
42 #include <linux/component.h>
44 #include <video/omapfb_dss.h>
47 #include "dss_features.h"
51 #define DISPC_SZ_REGS SZ_4K
53 enum omap_burst_size {
59 #define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
62 #define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
65 struct dispc_features {
76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
84 unsigned long (*calc_core_clk) (unsigned long pclk,
85 u16 width, u16 height, u16 out_width, u16 out_height,
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
98 bool set_max_preload:1;
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
106 bool has_writeback:1;
109 #define DISPC_MAX_NR_FIFOS 5
112 struct platform_device *pdev;
116 irq_handler_t user_handler;
119 unsigned long core_clk_rate;
120 unsigned long tv_pclk_rate;
122 u32 fifo_size[DISPC_MAX_NR_FIFOS];
123 /* maps which plane is using a fifo. fifo-id -> plane-id */
124 int fifo_assignment[DISPC_MAX_NR_FIFOS];
127 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
129 const struct dispc_features *feat;
133 struct regmap *syscon_pol;
134 u32 syscon_pol_offset;
136 /* DISPC_CONTROL & DISPC_CONFIG lock*/
137 spinlock_t control_lock;
140 enum omap_color_component {
141 /* used for all color formats for OMAP3 and earlier
142 * and for RGB and Y color component on OMAP4
144 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
145 /* used for UV component for
146 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
147 * color formats on OMAP4
149 DISPC_COLOR_COMPONENT_UV = 1 << 1,
152 enum mgr_reg_fields {
153 DISPC_MGR_FLD_ENABLE,
154 DISPC_MGR_FLD_STNTFT,
156 DISPC_MGR_FLD_TFTDATALINES,
157 DISPC_MGR_FLD_STALLMODE,
158 DISPC_MGR_FLD_TCKENABLE,
159 DISPC_MGR_FLD_TCKSELECTION,
161 DISPC_MGR_FLD_FIFOHANDCHECK,
162 /* used to maintain a count of the above fields */
166 struct dispc_reg_field {
172 static const struct {
177 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
179 [OMAP_DSS_CHANNEL_LCD] = {
181 .vsync_irq = DISPC_IRQ_VSYNC,
182 .framedone_irq = DISPC_IRQ_FRAMEDONE,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
186 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
189 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
192 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
196 [OMAP_DSS_CHANNEL_DIGIT] = {
198 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
199 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
203 [DISPC_MGR_FLD_STNTFT] = { },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { },
206 [DISPC_MGR_FLD_STALLMODE] = { },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
209 [DISPC_MGR_FLD_CPR] = { },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
213 [OMAP_DSS_CHANNEL_LCD2] = {
215 .vsync_irq = DISPC_IRQ_VSYNC2,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
230 [OMAP_DSS_CHANNEL_LCD3] = {
232 .vsync_irq = DISPC_IRQ_VSYNC3,
233 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
234 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
236 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
237 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
238 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
239 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
240 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
241 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
242 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
243 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
244 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
249 struct color_conv_coef {
250 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
254 static unsigned long dispc_fclk_rate(void);
255 static unsigned long dispc_core_clk_rate(void);
256 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
257 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
259 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
260 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
262 static inline void dispc_write_reg(const u16 idx, u32 val)
264 __raw_writel(val, dispc.base + idx);
267 static inline u32 dispc_read_reg(const u16 idx)
269 return __raw_readl(dispc.base + idx);
272 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
274 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 return REG_GET(rfld.reg, rfld.high, rfld.low);
278 static void mgr_fld_write(enum omap_channel channel,
279 enum mgr_reg_fields regfld, int val) {
280 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
281 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
285 spin_lock_irqsave(&dispc.control_lock, flags);
287 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
290 spin_unlock_irqrestore(&dispc.control_lock, flags);
294 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
296 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
298 static void dispc_save_context(void)
302 DSSDBG("dispc_save_context\n");
308 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
309 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
311 if (dss_has_feature(FEAT_MGR_LCD2)) {
315 if (dss_has_feature(FEAT_MGR_LCD3)) {
320 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
321 SR(DEFAULT_COLOR(i));
324 if (i == OMAP_DSS_CHANNEL_DIGIT)
335 if (dss_has_feature(FEAT_CPR)) {
342 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
347 SR(OVL_ATTRIBUTES(i));
348 SR(OVL_FIFO_THRESHOLD(i));
350 SR(OVL_PIXEL_INC(i));
351 if (dss_has_feature(FEAT_PRELOAD))
353 if (i == OMAP_DSS_GFX) {
354 SR(OVL_WINDOW_SKIP(i));
359 SR(OVL_PICTURE_SIZE(i));
363 for (j = 0; j < 8; j++)
364 SR(OVL_FIR_COEF_H(i, j));
366 for (j = 0; j < 8; j++)
367 SR(OVL_FIR_COEF_HV(i, j));
369 for (j = 0; j < 5; j++)
370 SR(OVL_CONV_COEF(i, j));
372 if (dss_has_feature(FEAT_FIR_COEF_V)) {
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_V(i, j));
377 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
384 for (j = 0; j < 8; j++)
385 SR(OVL_FIR_COEF_H2(i, j));
387 for (j = 0; j < 8; j++)
388 SR(OVL_FIR_COEF_HV2(i, j));
390 for (j = 0; j < 8; j++)
391 SR(OVL_FIR_COEF_V2(i, j));
393 if (dss_has_feature(FEAT_ATTR2))
394 SR(OVL_ATTRIBUTES2(i));
397 if (dss_has_feature(FEAT_CORE_CLK_DIV))
400 dispc.ctx_valid = true;
402 DSSDBG("context saved\n");
405 static void dispc_restore_context(void)
409 DSSDBG("dispc_restore_context\n");
411 if (!dispc.ctx_valid)
418 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
419 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
421 if (dss_has_feature(FEAT_MGR_LCD2))
423 if (dss_has_feature(FEAT_MGR_LCD3))
426 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
427 RR(DEFAULT_COLOR(i));
430 if (i == OMAP_DSS_CHANNEL_DIGIT)
441 if (dss_has_feature(FEAT_CPR)) {
448 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
453 RR(OVL_ATTRIBUTES(i));
454 RR(OVL_FIFO_THRESHOLD(i));
456 RR(OVL_PIXEL_INC(i));
457 if (dss_has_feature(FEAT_PRELOAD))
459 if (i == OMAP_DSS_GFX) {
460 RR(OVL_WINDOW_SKIP(i));
465 RR(OVL_PICTURE_SIZE(i));
469 for (j = 0; j < 8; j++)
470 RR(OVL_FIR_COEF_H(i, j));
472 for (j = 0; j < 8; j++)
473 RR(OVL_FIR_COEF_HV(i, j));
475 for (j = 0; j < 5; j++)
476 RR(OVL_CONV_COEF(i, j));
478 if (dss_has_feature(FEAT_FIR_COEF_V)) {
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_V(i, j));
483 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_H2(i, j));
493 for (j = 0; j < 8; j++)
494 RR(OVL_FIR_COEF_HV2(i, j));
496 for (j = 0; j < 8; j++)
497 RR(OVL_FIR_COEF_V2(i, j));
499 if (dss_has_feature(FEAT_ATTR2))
500 RR(OVL_ATTRIBUTES2(i));
503 if (dss_has_feature(FEAT_CORE_CLK_DIV))
506 /* enable last, because LCD & DIGIT enable are here */
508 if (dss_has_feature(FEAT_MGR_LCD2))
510 if (dss_has_feature(FEAT_MGR_LCD3))
512 /* clear spurious SYNC_LOST_DIGIT interrupts */
513 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
516 * enable last so IRQs won't trigger before
517 * the context is fully restored
521 DSSDBG("context restored\n");
527 int dispc_runtime_get(void)
531 DSSDBG("dispc_runtime_get\n");
533 r = pm_runtime_get_sync(&dispc.pdev->dev);
535 return r < 0 ? r : 0;
537 EXPORT_SYMBOL(dispc_runtime_get);
539 void dispc_runtime_put(void)
543 DSSDBG("dispc_runtime_put\n");
545 r = pm_runtime_put_sync(&dispc.pdev->dev);
546 WARN_ON(r < 0 && r != -ENOSYS);
548 EXPORT_SYMBOL(dispc_runtime_put);
550 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
552 return mgr_desc[channel].vsync_irq;
554 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
556 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
558 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
561 return mgr_desc[channel].framedone_irq;
563 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
565 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
567 return mgr_desc[channel].sync_lost_irq;
569 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
571 u32 dispc_wb_get_framedone_irq(void)
573 return DISPC_IRQ_FRAMEDONEWB;
576 bool dispc_mgr_go_busy(enum omap_channel channel)
578 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
580 EXPORT_SYMBOL(dispc_mgr_go_busy);
582 void dispc_mgr_go(enum omap_channel channel)
584 WARN_ON(!dispc_mgr_is_enabled(channel));
585 WARN_ON(dispc_mgr_go_busy(channel));
587 DSSDBG("GO %s\n", mgr_desc[channel].name);
589 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
591 EXPORT_SYMBOL(dispc_mgr_go);
593 bool dispc_wb_go_busy(void)
595 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
598 void dispc_wb_go(void)
600 enum omap_plane plane = OMAP_DSS_WB;
603 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
608 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
610 DSSERR("GO bit not down for WB\n");
614 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
617 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
619 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
622 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
624 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
627 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
629 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
632 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
634 BUG_ON(plane == OMAP_DSS_GFX);
636 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
639 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
642 BUG_ON(plane == OMAP_DSS_GFX);
644 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
647 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
649 BUG_ON(plane == OMAP_DSS_GFX);
651 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
654 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
655 int fir_vinc, int five_taps,
656 enum omap_color_component color_comp)
658 const struct dispc_coef *h_coef, *v_coef;
661 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
662 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
664 for (i = 0; i < 8; i++) {
667 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
668 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
669 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
670 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
671 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
672 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
673 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
674 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
676 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
677 dispc_ovl_write_firh_reg(plane, i, h);
678 dispc_ovl_write_firhv_reg(plane, i, hv);
680 dispc_ovl_write_firh2_reg(plane, i, h);
681 dispc_ovl_write_firhv2_reg(plane, i, hv);
687 for (i = 0; i < 8; i++) {
689 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
690 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
691 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
692 dispc_ovl_write_firv_reg(plane, i, v);
694 dispc_ovl_write_firv2_reg(plane, i, v);
700 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
701 const struct color_conv_coef *ct)
703 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
705 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
707 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
709 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
716 static void dispc_setup_color_conv_coef(void)
719 int num_ovl = dss_feat_get_num_ovls();
720 const struct color_conv_coef ctbl_bt601_5_ovl = {
722 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
724 const struct color_conv_coef ctbl_bt601_5_wb = {
726 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
729 for (i = 1; i < num_ovl; i++)
730 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
732 if (dispc.feat->has_writeback)
733 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
736 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
738 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
741 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
743 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
746 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
748 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
751 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
753 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
756 static void dispc_ovl_set_pos(enum omap_plane plane,
757 enum omap_overlay_caps caps, int x, int y)
761 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
764 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
766 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
769 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
772 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
774 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
775 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
777 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
780 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
785 BUG_ON(plane == OMAP_DSS_GFX);
787 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
789 if (plane == OMAP_DSS_WB)
790 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
792 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
795 static void dispc_ovl_set_zorder(enum omap_plane plane,
796 enum omap_overlay_caps caps, u8 zorder)
798 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
804 static void dispc_ovl_enable_zorder_planes(void)
808 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
811 for (i = 0; i < dss_feat_get_num_ovls(); i++)
812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
815 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
816 enum omap_overlay_caps caps, bool enable)
818 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
824 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
825 enum omap_overlay_caps caps, u8 global_alpha)
827 static const unsigned shifts[] = { 0, 8, 16, 24, };
830 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
833 shift = shifts[plane];
834 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
837 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
839 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
842 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
844 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
847 static void dispc_ovl_set_color_mode(enum omap_plane plane,
848 enum omap_color_mode color_mode)
851 if (plane != OMAP_DSS_GFX) {
852 switch (color_mode) {
853 case OMAP_DSS_COLOR_NV12:
855 case OMAP_DSS_COLOR_RGBX16:
857 case OMAP_DSS_COLOR_RGBA16:
859 case OMAP_DSS_COLOR_RGB12U:
861 case OMAP_DSS_COLOR_ARGB16:
863 case OMAP_DSS_COLOR_RGB16:
865 case OMAP_DSS_COLOR_ARGB16_1555:
867 case OMAP_DSS_COLOR_RGB24U:
869 case OMAP_DSS_COLOR_RGB24P:
871 case OMAP_DSS_COLOR_YUV2:
873 case OMAP_DSS_COLOR_UYVY:
875 case OMAP_DSS_COLOR_ARGB32:
877 case OMAP_DSS_COLOR_RGBA32:
879 case OMAP_DSS_COLOR_RGBX32:
881 case OMAP_DSS_COLOR_XRGB16_1555:
887 switch (color_mode) {
888 case OMAP_DSS_COLOR_CLUT1:
890 case OMAP_DSS_COLOR_CLUT2:
892 case OMAP_DSS_COLOR_CLUT4:
894 case OMAP_DSS_COLOR_CLUT8:
896 case OMAP_DSS_COLOR_RGB12U:
898 case OMAP_DSS_COLOR_ARGB16:
900 case OMAP_DSS_COLOR_RGB16:
902 case OMAP_DSS_COLOR_ARGB16_1555:
904 case OMAP_DSS_COLOR_RGB24U:
906 case OMAP_DSS_COLOR_RGB24P:
908 case OMAP_DSS_COLOR_RGBX16:
910 case OMAP_DSS_COLOR_RGBA16:
912 case OMAP_DSS_COLOR_ARGB32:
914 case OMAP_DSS_COLOR_RGBA32:
916 case OMAP_DSS_COLOR_RGBX32:
918 case OMAP_DSS_COLOR_XRGB16_1555:
925 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
928 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
929 enum omap_dss_rotation_type rotation_type)
931 if (dss_has_feature(FEAT_BURST_2D) == 0)
934 if (rotation_type == OMAP_DSS_ROT_TILER)
935 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
937 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
940 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
944 int chan = 0, chan2 = 0;
950 case OMAP_DSS_VIDEO1:
951 case OMAP_DSS_VIDEO2:
952 case OMAP_DSS_VIDEO3:
960 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
961 if (dss_has_feature(FEAT_MGR_LCD2)) {
963 case OMAP_DSS_CHANNEL_LCD:
967 case OMAP_DSS_CHANNEL_DIGIT:
971 case OMAP_DSS_CHANNEL_LCD2:
975 case OMAP_DSS_CHANNEL_LCD3:
976 if (dss_has_feature(FEAT_MGR_LCD3)) {
984 case OMAP_DSS_CHANNEL_WB:
993 val = FLD_MOD(val, chan, shift, shift);
994 val = FLD_MOD(val, chan2, 31, 30);
996 val = FLD_MOD(val, channel, shift, shift);
998 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1000 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1002 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1011 case OMAP_DSS_VIDEO1:
1012 case OMAP_DSS_VIDEO2:
1013 case OMAP_DSS_VIDEO3:
1021 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1023 if (FLD_GET(val, shift, shift) == 1)
1024 return OMAP_DSS_CHANNEL_DIGIT;
1026 if (!dss_has_feature(FEAT_MGR_LCD2))
1027 return OMAP_DSS_CHANNEL_LCD;
1029 switch (FLD_GET(val, 31, 30)) {
1032 return OMAP_DSS_CHANNEL_LCD;
1034 return OMAP_DSS_CHANNEL_LCD2;
1036 return OMAP_DSS_CHANNEL_LCD3;
1038 return OMAP_DSS_CHANNEL_WB;
1042 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1044 enum omap_plane plane = OMAP_DSS_WB;
1046 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1049 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1050 enum omap_burst_size burst_size)
1052 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1055 shift = shifts[plane];
1056 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1059 static void dispc_configure_burst_sizes(void)
1062 const int burst_size = BURST_SIZE_X8;
1064 /* Configure burst size always to maximum size */
1065 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1066 dispc_ovl_set_burst_size(i, burst_size);
1067 if (dispc.feat->has_writeback)
1068 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1071 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1073 unsigned unit = dss_feat_get_burst_size_unit();
1074 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1078 void dispc_enable_gamma_table(bool enable)
1081 * This is partially implemented to support only disabling of
1085 DSSWARN("Gamma table enabling for TV not yet supported");
1089 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1092 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1094 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1097 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1100 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1101 const struct omap_dss_cpr_coefs *coefs)
1103 u32 coef_r, coef_g, coef_b;
1105 if (!dss_mgr_is_lcd(channel))
1108 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1109 FLD_VAL(coefs->rb, 9, 0);
1110 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1111 FLD_VAL(coefs->gb, 9, 0);
1112 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1113 FLD_VAL(coefs->bb, 9, 0);
1115 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1116 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1117 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1120 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1124 BUG_ON(plane == OMAP_DSS_GFX);
1126 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1127 val = FLD_MOD(val, enable, 9, 9);
1128 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1131 static void dispc_ovl_enable_replication(enum omap_plane plane,
1132 enum omap_overlay_caps caps, bool enable)
1134 static const unsigned shifts[] = { 5, 10, 10, 10 };
1137 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1140 shift = shifts[plane];
1141 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1144 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1149 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1150 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1152 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1155 static void dispc_init_fifos(void)
1163 unit = dss_feat_get_buffer_size_unit();
1165 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1167 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1168 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1170 dispc.fifo_size[fifo] = size;
1173 * By default fifos are mapped directly to overlays, fifo 0 to
1174 * ovl 0, fifo 1 to ovl 1, etc.
1176 dispc.fifo_assignment[fifo] = fifo;
1180 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1181 * causes problems with certain use cases, like using the tiler in 2D
1182 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1183 * giving GFX plane a larger fifo. WB but should work fine with a
1186 if (dispc.feat->gfx_fifo_workaround) {
1189 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1191 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1192 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1193 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1194 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1196 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1198 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1199 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1203 * Setup default fifo thresholds.
1205 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1207 const bool use_fifomerge = false;
1208 const bool manual_update = false;
1210 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1211 use_fifomerge, manual_update);
1213 dispc_ovl_set_fifo_threshold(i, low, high);
1216 if (dispc.feat->has_writeback) {
1218 const bool use_fifomerge = false;
1219 const bool manual_update = false;
1221 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1222 use_fifomerge, manual_update);
1224 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1228 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1233 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1234 if (dispc.fifo_assignment[fifo] == plane)
1235 size += dispc.fifo_size[fifo];
1241 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1243 u8 hi_start, hi_end, lo_start, lo_end;
1246 unit = dss_feat_get_buffer_size_unit();
1248 WARN_ON(low % unit != 0);
1249 WARN_ON(high % unit != 0);
1254 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1255 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1257 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1259 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1260 lo_start, lo_end) * unit,
1261 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1262 hi_start, hi_end) * unit,
1263 low * unit, high * unit);
1265 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1266 FLD_VAL(high, hi_start, hi_end) |
1267 FLD_VAL(low, lo_start, lo_end));
1270 * configure the preload to the pipeline's high threhold, if HT it's too
1271 * large for the preload field, set the threshold to the maximum value
1272 * that can be held by the preload register
1274 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1275 plane != OMAP_DSS_WB)
1276 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1279 void dispc_enable_fifomerge(bool enable)
1281 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1286 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1287 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1290 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1291 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1295 * All sizes are in bytes. Both the buffer and burst are made of
1296 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1299 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1300 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1303 burst_size = dispc_ovl_get_burst_size(plane);
1304 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1306 if (use_fifomerge) {
1307 total_fifo_size = 0;
1308 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1309 total_fifo_size += dispc_ovl_get_fifo_size(i);
1311 total_fifo_size = ovl_fifo_size;
1315 * We use the same low threshold for both fifomerge and non-fifomerge
1316 * cases, but for fifomerge we calculate the high threshold using the
1317 * combined fifo size
1320 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1321 *fifo_low = ovl_fifo_size - burst_size * 2;
1322 *fifo_high = total_fifo_size - burst_size;
1323 } else if (plane == OMAP_DSS_WB) {
1325 * Most optimal configuration for writeback is to push out data
1326 * to the interconnect the moment writeback pushes enough pixels
1327 * in the FIFO to form a burst
1330 *fifo_high = burst_size;
1332 *fifo_low = ovl_fifo_size - burst_size;
1333 *fifo_high = total_fifo_size - buf_unit;
1337 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1341 if (plane == OMAP_DSS_GFX)
1346 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1349 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1352 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1353 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1356 static void dispc_init_mflag(void)
1361 * HACK: NV12 color format and MFLAG seem to have problems working
1362 * together: using two displays, and having an NV12 overlay on one of
1363 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1364 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1365 * remove the errors, but there doesn't seem to be a clear logic on
1366 * which values work and which not.
1368 * As a work-around, set force MFLAG to always on.
1370 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1371 (1 << 0) | /* MFLAG_CTRL = force always on */
1372 (0 << 2)); /* MFLAG_START = disable */
1374 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1375 u32 size = dispc_ovl_get_fifo_size(i);
1376 u32 unit = dss_feat_get_buffer_size_unit();
1379 dispc_ovl_set_mflag(i, true);
1382 * Simulation team suggests below thesholds:
1383 * HT = fifosize * 5 / 8;
1384 * LT = fifosize * 4 / 8;
1387 low = size * 4 / 8 / unit;
1388 high = size * 5 / 8 / unit;
1390 dispc_ovl_set_mflag_threshold(i, low, high);
1393 if (dispc.feat->has_writeback) {
1394 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1395 u32 unit = dss_feat_get_buffer_size_unit();
1398 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1401 * Simulation team suggests below thesholds:
1402 * HT = fifosize * 5 / 8;
1403 * LT = fifosize * 4 / 8;
1406 low = size * 4 / 8 / unit;
1407 high = size * 5 / 8 / unit;
1409 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1413 static void dispc_ovl_set_fir(enum omap_plane plane,
1415 enum omap_color_component color_comp)
1419 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1420 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1422 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1423 &hinc_start, &hinc_end);
1424 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1425 &vinc_start, &vinc_end);
1426 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1427 FLD_VAL(hinc, hinc_start, hinc_end);
1429 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1431 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1432 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1436 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1439 u8 hor_start, hor_end, vert_start, vert_end;
1441 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1442 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1444 val = FLD_VAL(vaccu, vert_start, vert_end) |
1445 FLD_VAL(haccu, hor_start, hor_end);
1447 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1450 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1453 u8 hor_start, hor_end, vert_start, vert_end;
1455 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1456 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1458 val = FLD_VAL(vaccu, vert_start, vert_end) |
1459 FLD_VAL(haccu, hor_start, hor_end);
1461 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1464 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1469 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1470 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1473 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1478 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1479 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1482 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1483 u16 orig_width, u16 orig_height,
1484 u16 out_width, u16 out_height,
1485 bool five_taps, u8 rotation,
1486 enum omap_color_component color_comp)
1488 int fir_hinc, fir_vinc;
1490 fir_hinc = 1024 * orig_width / out_width;
1491 fir_vinc = 1024 * orig_height / out_height;
1493 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1495 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1498 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1499 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1500 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1502 int h_accu2_0, h_accu2_1;
1503 int v_accu2_0, v_accu2_1;
1504 int chroma_hinc, chroma_vinc;
1514 const struct accu *accu_table;
1515 const struct accu *accu_val;
1517 static const struct accu accu_nv12[4] = {
1518 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1519 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1520 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1521 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1524 static const struct accu accu_nv12_ilace[4] = {
1525 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1526 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1527 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1528 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1531 static const struct accu accu_yuv[4] = {
1532 { 0, 1, 0, 1, 0, 1, 0, 1 },
1533 { 0, 1, 0, 1, 0, 1, 0, 1 },
1534 { -1, 1, 0, 1, 0, 1, 0, 1 },
1535 { 0, 1, 0, 1, -1, 1, 0, 1 },
1539 case OMAP_DSS_ROT_0:
1542 case OMAP_DSS_ROT_90:
1545 case OMAP_DSS_ROT_180:
1548 case OMAP_DSS_ROT_270:
1556 switch (color_mode) {
1557 case OMAP_DSS_COLOR_NV12:
1559 accu_table = accu_nv12_ilace;
1561 accu_table = accu_nv12;
1563 case OMAP_DSS_COLOR_YUV2:
1564 case OMAP_DSS_COLOR_UYVY:
1565 accu_table = accu_yuv;
1572 accu_val = &accu_table[idx];
1574 chroma_hinc = 1024 * orig_width / out_width;
1575 chroma_vinc = 1024 * orig_height / out_height;
1577 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1578 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1579 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1580 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1582 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1583 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1586 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1587 u16 orig_width, u16 orig_height,
1588 u16 out_width, u16 out_height,
1589 bool ilace, bool five_taps,
1590 bool fieldmode, enum omap_color_mode color_mode,
1597 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1598 out_width, out_height, five_taps,
1599 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1600 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1602 /* RESIZEENABLE and VERTICALTAPS */
1603 l &= ~((0x3 << 5) | (0x1 << 21));
1604 l |= (orig_width != out_width) ? (1 << 5) : 0;
1605 l |= (orig_height != out_height) ? (1 << 6) : 0;
1606 l |= five_taps ? (1 << 21) : 0;
1608 /* VRESIZECONF and HRESIZECONF */
1609 if (dss_has_feature(FEAT_RESIZECONF)) {
1611 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1612 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1615 /* LINEBUFFERSPLIT */
1616 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1618 l |= five_taps ? (1 << 22) : 0;
1621 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1624 * field 0 = even field = bottom field
1625 * field 1 = odd field = top field
1627 if (ilace && !fieldmode) {
1629 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1630 if (accu0 >= 1024/2) {
1636 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1637 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1640 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1641 u16 orig_width, u16 orig_height,
1642 u16 out_width, u16 out_height,
1643 bool ilace, bool five_taps,
1644 bool fieldmode, enum omap_color_mode color_mode,
1647 int scale_x = out_width != orig_width;
1648 int scale_y = out_height != orig_height;
1649 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1651 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1653 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1654 color_mode != OMAP_DSS_COLOR_UYVY &&
1655 color_mode != OMAP_DSS_COLOR_NV12)) {
1656 /* reset chroma resampling for RGB formats */
1657 if (plane != OMAP_DSS_WB)
1658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1662 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1663 out_height, ilace, color_mode, rotation);
1665 switch (color_mode) {
1666 case OMAP_DSS_COLOR_NV12:
1667 if (chroma_upscale) {
1668 /* UV is subsampled by 2 horizontally and vertically */
1672 /* UV is downsampled by 2 horizontally and vertically */
1678 case OMAP_DSS_COLOR_YUV2:
1679 case OMAP_DSS_COLOR_UYVY:
1680 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1681 if (rotation == OMAP_DSS_ROT_0 ||
1682 rotation == OMAP_DSS_ROT_180) {
1684 /* UV is subsampled by 2 horizontally */
1687 /* UV is downsampled by 2 horizontally */
1691 /* must use FIR for YUV422 if rotated */
1692 if (rotation != OMAP_DSS_ROT_0)
1693 scale_x = scale_y = true;
1701 if (out_width != orig_width)
1703 if (out_height != orig_height)
1706 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1707 out_width, out_height, five_taps,
1708 rotation, DISPC_COLOR_COMPONENT_UV);
1710 if (plane != OMAP_DSS_WB)
1711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1712 (scale_x || scale_y) ? 1 : 0, 8, 8);
1715 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1717 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1720 static void dispc_ovl_set_scaling(enum omap_plane plane,
1721 u16 orig_width, u16 orig_height,
1722 u16 out_width, u16 out_height,
1723 bool ilace, bool five_taps,
1724 bool fieldmode, enum omap_color_mode color_mode,
1727 BUG_ON(plane == OMAP_DSS_GFX);
1729 dispc_ovl_set_scaling_common(plane,
1730 orig_width, orig_height,
1731 out_width, out_height,
1733 fieldmode, color_mode,
1736 dispc_ovl_set_scaling_uv(plane,
1737 orig_width, orig_height,
1738 out_width, out_height,
1740 fieldmode, color_mode,
1744 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1745 enum omap_dss_rotation_type rotation_type,
1746 bool mirroring, enum omap_color_mode color_mode)
1748 bool row_repeat = false;
1751 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1752 color_mode == OMAP_DSS_COLOR_UYVY) {
1756 case OMAP_DSS_ROT_0:
1759 case OMAP_DSS_ROT_90:
1762 case OMAP_DSS_ROT_180:
1765 case OMAP_DSS_ROT_270:
1771 case OMAP_DSS_ROT_0:
1774 case OMAP_DSS_ROT_90:
1777 case OMAP_DSS_ROT_180:
1780 case OMAP_DSS_ROT_270:
1786 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1793 * OMAP4/5 Errata i631:
1794 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1795 * rows beyond the framebuffer, which may cause OCP error.
1797 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1798 rotation_type != OMAP_DSS_ROT_TILER)
1801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1802 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1803 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1804 row_repeat ? 1 : 0, 18, 18);
1806 if (color_mode == OMAP_DSS_COLOR_NV12) {
1807 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1808 (rotation == OMAP_DSS_ROT_0 ||
1809 rotation == OMAP_DSS_ROT_180);
1811 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1816 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1818 switch (color_mode) {
1819 case OMAP_DSS_COLOR_CLUT1:
1821 case OMAP_DSS_COLOR_CLUT2:
1823 case OMAP_DSS_COLOR_CLUT4:
1825 case OMAP_DSS_COLOR_CLUT8:
1826 case OMAP_DSS_COLOR_NV12:
1828 case OMAP_DSS_COLOR_RGB12U:
1829 case OMAP_DSS_COLOR_RGB16:
1830 case OMAP_DSS_COLOR_ARGB16:
1831 case OMAP_DSS_COLOR_YUV2:
1832 case OMAP_DSS_COLOR_UYVY:
1833 case OMAP_DSS_COLOR_RGBA16:
1834 case OMAP_DSS_COLOR_RGBX16:
1835 case OMAP_DSS_COLOR_ARGB16_1555:
1836 case OMAP_DSS_COLOR_XRGB16_1555:
1838 case OMAP_DSS_COLOR_RGB24P:
1840 case OMAP_DSS_COLOR_RGB24U:
1841 case OMAP_DSS_COLOR_ARGB32:
1842 case OMAP_DSS_COLOR_RGBA32:
1843 case OMAP_DSS_COLOR_RGBX32:
1851 static s32 pixinc(int pixels, u8 ps)
1855 else if (pixels > 1)
1856 return 1 + (pixels - 1) * ps;
1857 else if (pixels < 0)
1858 return 1 - (-pixels + 1) * ps;
1864 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1866 u16 width, u16 height,
1867 enum omap_color_mode color_mode, bool fieldmode,
1868 unsigned int field_offset,
1869 unsigned *offset0, unsigned *offset1,
1870 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1874 /* FIXME CLUT formats */
1875 switch (color_mode) {
1876 case OMAP_DSS_COLOR_CLUT1:
1877 case OMAP_DSS_COLOR_CLUT2:
1878 case OMAP_DSS_COLOR_CLUT4:
1879 case OMAP_DSS_COLOR_CLUT8:
1882 case OMAP_DSS_COLOR_YUV2:
1883 case OMAP_DSS_COLOR_UYVY:
1887 ps = color_mode_to_bpp(color_mode) / 8;
1891 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1895 * field 0 = even field = bottom field
1896 * field 1 = odd field = top field
1898 switch (rotation + mirror * 4) {
1899 case OMAP_DSS_ROT_0:
1900 case OMAP_DSS_ROT_180:
1902 * If the pixel format is YUV or UYVY divide the width
1903 * of the image by 2 for 0 and 180 degree rotation.
1905 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1906 color_mode == OMAP_DSS_COLOR_UYVY)
1909 case OMAP_DSS_ROT_90:
1910 case OMAP_DSS_ROT_270:
1913 *offset0 = field_offset * screen_width * ps;
1917 *row_inc = pixinc(1 +
1918 (y_predecim * screen_width - x_predecim * width) +
1919 (fieldmode ? screen_width : 0), ps);
1920 *pix_inc = pixinc(x_predecim, ps);
1923 case OMAP_DSS_ROT_0 + 4:
1924 case OMAP_DSS_ROT_180 + 4:
1925 /* If the pixel format is YUV or UYVY divide the width
1926 * of the image by 2 for 0 degree and 180 degree
1928 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1929 color_mode == OMAP_DSS_COLOR_UYVY)
1932 case OMAP_DSS_ROT_90 + 4:
1933 case OMAP_DSS_ROT_270 + 4:
1936 *offset0 = field_offset * screen_width * ps;
1939 *row_inc = pixinc(1 -
1940 (y_predecim * screen_width + x_predecim * width) -
1941 (fieldmode ? screen_width : 0), ps);
1942 *pix_inc = pixinc(x_predecim, ps);
1951 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1953 u16 width, u16 height,
1954 enum omap_color_mode color_mode, bool fieldmode,
1955 unsigned int field_offset,
1956 unsigned *offset0, unsigned *offset1,
1957 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1962 /* FIXME CLUT formats */
1963 switch (color_mode) {
1964 case OMAP_DSS_COLOR_CLUT1:
1965 case OMAP_DSS_COLOR_CLUT2:
1966 case OMAP_DSS_COLOR_CLUT4:
1967 case OMAP_DSS_COLOR_CLUT8:
1971 ps = color_mode_to_bpp(color_mode) / 8;
1975 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1978 /* width & height are overlay sizes, convert to fb sizes */
1980 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1989 * field 0 = even field = bottom field
1990 * field 1 = odd field = top field
1992 switch (rotation + mirror * 4) {
1993 case OMAP_DSS_ROT_0:
1996 *offset0 = *offset1 + field_offset * screen_width * ps;
1998 *offset0 = *offset1;
1999 *row_inc = pixinc(1 +
2000 (y_predecim * screen_width - fbw * x_predecim) +
2001 (fieldmode ? screen_width : 0), ps);
2002 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2003 color_mode == OMAP_DSS_COLOR_UYVY)
2004 *pix_inc = pixinc(x_predecim, 2 * ps);
2006 *pix_inc = pixinc(x_predecim, ps);
2008 case OMAP_DSS_ROT_90:
2009 *offset1 = screen_width * (fbh - 1) * ps;
2011 *offset0 = *offset1 + field_offset * ps;
2013 *offset0 = *offset1;
2014 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2015 y_predecim + (fieldmode ? 1 : 0), ps);
2016 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2018 case OMAP_DSS_ROT_180:
2019 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2021 *offset0 = *offset1 - field_offset * screen_width * ps;
2023 *offset0 = *offset1;
2024 *row_inc = pixinc(-1 -
2025 (y_predecim * screen_width - fbw * x_predecim) -
2026 (fieldmode ? screen_width : 0), ps);
2027 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2028 color_mode == OMAP_DSS_COLOR_UYVY)
2029 *pix_inc = pixinc(-x_predecim, 2 * ps);
2031 *pix_inc = pixinc(-x_predecim, ps);
2033 case OMAP_DSS_ROT_270:
2034 *offset1 = (fbw - 1) * ps;
2036 *offset0 = *offset1 - field_offset * ps;
2038 *offset0 = *offset1;
2039 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2040 y_predecim - (fieldmode ? 1 : 0), ps);
2041 *pix_inc = pixinc(x_predecim * screen_width, ps);
2045 case OMAP_DSS_ROT_0 + 4:
2046 *offset1 = (fbw - 1) * ps;
2048 *offset0 = *offset1 + field_offset * screen_width * ps;
2050 *offset0 = *offset1;
2051 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2052 (fieldmode ? screen_width : 0),
2054 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2055 color_mode == OMAP_DSS_COLOR_UYVY)
2056 *pix_inc = pixinc(-x_predecim, 2 * ps);
2058 *pix_inc = pixinc(-x_predecim, ps);
2061 case OMAP_DSS_ROT_90 + 4:
2064 *offset0 = *offset1 + field_offset * ps;
2066 *offset0 = *offset1;
2067 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2068 y_predecim + (fieldmode ? 1 : 0),
2070 *pix_inc = pixinc(x_predecim * screen_width, ps);
2073 case OMAP_DSS_ROT_180 + 4:
2074 *offset1 = screen_width * (fbh - 1) * ps;
2076 *offset0 = *offset1 - field_offset * screen_width * ps;
2078 *offset0 = *offset1;
2079 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2080 (fieldmode ? screen_width : 0),
2082 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2083 color_mode == OMAP_DSS_COLOR_UYVY)
2084 *pix_inc = pixinc(x_predecim, 2 * ps);
2086 *pix_inc = pixinc(x_predecim, ps);
2089 case OMAP_DSS_ROT_270 + 4:
2090 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2092 *offset0 = *offset1 - field_offset * ps;
2094 *offset0 = *offset1;
2095 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2096 y_predecim - (fieldmode ? 1 : 0),
2098 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2107 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2108 enum omap_color_mode color_mode, bool fieldmode,
2109 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2110 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2114 switch (color_mode) {
2115 case OMAP_DSS_COLOR_CLUT1:
2116 case OMAP_DSS_COLOR_CLUT2:
2117 case OMAP_DSS_COLOR_CLUT4:
2118 case OMAP_DSS_COLOR_CLUT8:
2122 ps = color_mode_to_bpp(color_mode) / 8;
2126 DSSDBG("scrw %d, width %d\n", screen_width, width);
2129 * field 0 = even field = bottom field
2130 * field 1 = odd field = top field
2134 *offset0 = *offset1 + field_offset * screen_width * ps;
2136 *offset0 = *offset1;
2137 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2138 (fieldmode ? screen_width : 0), ps);
2139 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2140 color_mode == OMAP_DSS_COLOR_UYVY)
2141 *pix_inc = pixinc(x_predecim, 2 * ps);
2143 *pix_inc = pixinc(x_predecim, ps);
2147 * This function is used to avoid synclosts in OMAP3, because of some
2148 * undocumented horizontal position and timing related limitations.
2150 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2151 const struct omap_video_timings *t, u16 pos_x,
2152 u16 width, u16 height, u16 out_width, u16 out_height,
2155 const int ds = DIV_ROUND_UP(height, out_height);
2156 unsigned long nonactive;
2157 static const u8 limits[3] = { 8, 10, 20 };
2161 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2164 if (out_height < height)
2166 if (out_width < width)
2168 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2169 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2170 if (blank <= limits[i])
2173 /* FIXME add checks for 3-tap filter once the limitations are known */
2178 * Pixel data should be prepared before visible display point starts.
2179 * So, atleast DS-2 lines must have already been fetched by DISPC
2180 * during nonactive - pos_x period.
2182 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2183 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2184 val, max(0, ds - 2) * width);
2185 if (val < max(0, ds - 2) * width)
2189 * All lines need to be refilled during the nonactive period of which
2190 * only one line can be loaded during the active period. So, atleast
2191 * DS - 1 lines should be loaded during nonactive period.
2193 val = div_u64((u64)nonactive * lclk, pclk);
2194 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2195 val, max(0, ds - 1) * width);
2196 if (val < max(0, ds - 1) * width)
2202 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2203 const struct omap_video_timings *mgr_timings, u16 width,
2204 u16 height, u16 out_width, u16 out_height,
2205 enum omap_color_mode color_mode)
2210 if (height <= out_height && width <= out_width)
2211 return (unsigned long) pclk;
2213 if (height > out_height) {
2214 unsigned int ppl = mgr_timings->x_res;
2216 tmp = (u64)pclk * height * out_width;
2217 do_div(tmp, 2 * out_height * ppl);
2220 if (height > 2 * out_height) {
2221 if (ppl == out_width)
2224 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2225 do_div(tmp, 2 * out_height * (ppl - out_width));
2226 core_clk = max_t(u32, core_clk, tmp);
2230 if (width > out_width) {
2231 tmp = (u64)pclk * width;
2232 do_div(tmp, out_width);
2233 core_clk = max_t(u32, core_clk, tmp);
2235 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2242 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2243 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2245 if (height > out_height && width > out_width)
2251 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2252 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2254 unsigned int hf, vf;
2257 * FIXME how to determine the 'A' factor
2258 * for the no downscaling case ?
2261 if (width > 3 * out_width)
2263 else if (width > 2 * out_width)
2265 else if (width > out_width)
2269 if (height > out_height)
2274 return pclk * vf * hf;
2277 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2278 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2281 * If the overlay/writeback is in mem to mem mode, there are no
2282 * downscaling limitations with respect to pixel clock, return 1 as
2283 * required core clock to represent that we have sufficient enough
2284 * core clock to do maximum downscaling
2289 if (width > out_width)
2290 return DIV_ROUND_UP(pclk, out_width) * width;
2295 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2296 const struct omap_video_timings *mgr_timings,
2297 u16 width, u16 height, u16 out_width, u16 out_height,
2298 enum omap_color_mode color_mode, bool *five_taps,
2299 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2300 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2303 u16 in_width, in_height;
2304 int min_factor = min(*decim_x, *decim_y);
2305 const int maxsinglelinewidth =
2306 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2311 in_height = height / *decim_y;
2312 in_width = width / *decim_x;
2313 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2314 in_height, out_width, out_height, mem_to_mem);
2315 error = (in_width > maxsinglelinewidth || !*core_clk ||
2316 *core_clk > dispc_core_clk_rate());
2318 if (*decim_x == *decim_y) {
2319 *decim_x = min_factor;
2322 swap(*decim_x, *decim_y);
2323 if (*decim_x < *decim_y)
2327 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2330 DSSERR("failed to find scaling settings\n");
2334 if (in_width > maxsinglelinewidth) {
2335 DSSERR("Cannot scale max input width exceeded");
2341 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2342 const struct omap_video_timings *mgr_timings,
2343 u16 width, u16 height, u16 out_width, u16 out_height,
2344 enum omap_color_mode color_mode, bool *five_taps,
2345 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2346 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2349 u16 in_width, in_height;
2350 const int maxsinglelinewidth =
2351 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2354 in_height = height / *decim_y;
2355 in_width = width / *decim_x;
2356 *five_taps = in_height > out_height;
2358 if (in_width > maxsinglelinewidth)
2359 if (in_height > out_height &&
2360 in_height < out_height * 2)
2364 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2365 in_width, in_height, out_width,
2366 out_height, color_mode);
2368 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2369 in_height, out_width, out_height,
2372 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2373 pos_x, in_width, in_height, out_width,
2374 out_height, *five_taps);
2375 if (error && *five_taps) {
2380 error = (error || in_width > maxsinglelinewidth * 2 ||
2381 (in_width > maxsinglelinewidth && *five_taps) ||
2382 !*core_clk || *core_clk > dispc_core_clk_rate());
2385 /* verify that we're inside the limits of scaler */
2386 if (in_width / 4 > out_width)
2390 if (in_height / 4 > out_height)
2393 if (in_height / 2 > out_height)
2400 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2403 DSSERR("failed to find scaling settings\n");
2407 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2408 in_height, out_width, out_height, *five_taps)) {
2409 DSSERR("horizontal timing too tight\n");
2413 if (in_width > (maxsinglelinewidth * 2)) {
2414 DSSERR("Cannot setup scaling");
2415 DSSERR("width exceeds maximum width possible");
2419 if (in_width > maxsinglelinewidth && *five_taps) {
2420 DSSERR("cannot setup scaling with five taps");
2426 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2427 const struct omap_video_timings *mgr_timings,
2428 u16 width, u16 height, u16 out_width, u16 out_height,
2429 enum omap_color_mode color_mode, bool *five_taps,
2430 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2431 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2433 u16 in_width, in_width_max;
2434 int decim_x_min = *decim_x;
2435 u16 in_height = height / *decim_y;
2436 const int maxsinglelinewidth =
2437 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2438 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2441 in_width_max = out_width * maxdownscale;
2443 in_width_max = dispc_core_clk_rate() /
2444 DIV_ROUND_UP(pclk, out_width);
2447 *decim_x = DIV_ROUND_UP(width, in_width_max);
2449 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2450 if (*decim_x > *x_predecim)
2454 in_width = width / *decim_x;
2455 } while (*decim_x <= *x_predecim &&
2456 in_width > maxsinglelinewidth && ++*decim_x);
2458 if (in_width > maxsinglelinewidth) {
2459 DSSERR("Cannot scale width exceeds max line width");
2463 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2464 out_width, out_height, mem_to_mem);
2468 #define DIV_FRAC(dividend, divisor) \
2469 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2471 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2472 enum omap_overlay_caps caps,
2473 const struct omap_video_timings *mgr_timings,
2474 u16 width, u16 height, u16 out_width, u16 out_height,
2475 enum omap_color_mode color_mode, bool *five_taps,
2476 int *x_predecim, int *y_predecim, u16 pos_x,
2477 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2479 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2480 const int max_decim_limit = 16;
2481 unsigned long core_clk = 0;
2482 int decim_x, decim_y, ret;
2484 if (width == out_width && height == out_height)
2487 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2488 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2492 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2496 *x_predecim = *y_predecim = 1;
2498 *x_predecim = max_decim_limit;
2499 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2500 dss_has_feature(FEAT_BURST_2D)) ?
2501 2 : max_decim_limit;
2504 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2505 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2506 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2507 color_mode == OMAP_DSS_COLOR_CLUT8) {
2514 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2515 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2517 if (decim_x > *x_predecim || out_width > width * 8)
2520 if (decim_y > *y_predecim || out_height > height * 8)
2523 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2524 out_width, out_height, color_mode, five_taps,
2525 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2530 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2532 out_width, out_height,
2533 out_width / width, DIV_FRAC(out_width, width),
2534 out_height / height, DIV_FRAC(out_height, height),
2537 width / decim_x, height / decim_y,
2538 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2539 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2542 core_clk, dispc_core_clk_rate());
2544 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2545 DSSERR("failed to set up scaling, "
2546 "required core clk rate = %lu Hz, "
2547 "current core clk rate = %lu Hz\n",
2548 core_clk, dispc_core_clk_rate());
2552 *x_predecim = decim_x;
2553 *y_predecim = decim_y;
2557 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2558 const struct omap_overlay_info *oi,
2559 const struct omap_video_timings *timings,
2560 int *x_predecim, int *y_predecim)
2562 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2563 bool five_taps = true;
2564 bool fieldmode = false;
2565 u16 in_height = oi->height;
2566 u16 in_width = oi->width;
2567 bool ilace = timings->interlace;
2568 u16 out_width, out_height;
2569 int pos_x = oi->pos_x;
2570 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2571 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2573 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2574 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2576 if (ilace && oi->height == out_height)
2584 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2585 in_height, out_height);
2588 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2591 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2592 in_height, out_width, out_height, oi->color_mode,
2593 &five_taps, x_predecim, y_predecim, pos_x,
2594 oi->rotation_type, false);
2596 EXPORT_SYMBOL(dispc_ovl_check);
2598 static int dispc_ovl_setup_common(enum omap_plane plane,
2599 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2600 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2601 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2602 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2603 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2604 bool replication, const struct omap_video_timings *mgr_timings,
2607 bool five_taps = true;
2608 bool fieldmode = false;
2610 unsigned offset0, offset1;
2613 u16 frame_width, frame_height;
2614 unsigned int field_offset = 0;
2615 u16 in_height = height;
2616 u16 in_width = width;
2617 int x_predecim = 1, y_predecim = 1;
2618 bool ilace = mgr_timings->interlace;
2619 unsigned long pclk = dispc_plane_pclk_rate(plane);
2620 unsigned long lclk = dispc_plane_lclk_rate(plane);
2622 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2625 switch (color_mode) {
2626 case OMAP_DSS_COLOR_YUV2:
2627 case OMAP_DSS_COLOR_UYVY:
2628 case OMAP_DSS_COLOR_NV12:
2630 DSSERR("input width %d is not even for YUV format\n",
2640 out_width = out_width == 0 ? width : out_width;
2641 out_height = out_height == 0 ? height : out_height;
2643 if (ilace && height == out_height)
2652 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2653 "out_height %d\n", in_height, pos_y,
2657 if (!dss_feat_color_mode_supported(plane, color_mode))
2660 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2661 in_height, out_width, out_height, color_mode,
2662 &five_taps, &x_predecim, &y_predecim, pos_x,
2663 rotation_type, mem_to_mem);
2667 in_width = in_width / x_predecim;
2668 in_height = in_height / y_predecim;
2670 if (x_predecim > 1 || y_predecim > 1)
2671 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2672 x_predecim, y_predecim, in_width, in_height);
2674 switch (color_mode) {
2675 case OMAP_DSS_COLOR_YUV2:
2676 case OMAP_DSS_COLOR_UYVY:
2677 case OMAP_DSS_COLOR_NV12:
2679 DSSDBG("predecimated input width is not even for YUV format\n");
2680 DSSDBG("adjusting input width %d -> %d\n",
2681 in_width, in_width & ~1);
2691 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2692 color_mode == OMAP_DSS_COLOR_UYVY ||
2693 color_mode == OMAP_DSS_COLOR_NV12)
2696 if (ilace && !fieldmode) {
2698 * when downscaling the bottom field may have to start several
2699 * source lines below the top field. Unfortunately ACCUI
2700 * registers will only hold the fractional part of the offset
2701 * so the integer part must be added to the base address of the
2704 if (!in_height || in_height == out_height)
2707 field_offset = in_height / out_height / 2;
2710 /* Fields are independent but interleaved in memory. */
2719 if (plane == OMAP_DSS_WB) {
2720 frame_width = out_width;
2721 frame_height = out_height;
2723 frame_width = in_width;
2724 frame_height = height;
2727 if (rotation_type == OMAP_DSS_ROT_TILER)
2728 calc_tiler_rotation_offset(screen_width, frame_width,
2729 color_mode, fieldmode, field_offset,
2730 &offset0, &offset1, &row_inc, &pix_inc,
2731 x_predecim, y_predecim);
2732 else if (rotation_type == OMAP_DSS_ROT_DMA)
2733 calc_dma_rotation_offset(rotation, mirror, screen_width,
2734 frame_width, frame_height,
2735 color_mode, fieldmode, field_offset,
2736 &offset0, &offset1, &row_inc, &pix_inc,
2737 x_predecim, y_predecim);
2739 calc_vrfb_rotation_offset(rotation, mirror,
2740 screen_width, frame_width, frame_height,
2741 color_mode, fieldmode, field_offset,
2742 &offset0, &offset1, &row_inc, &pix_inc,
2743 x_predecim, y_predecim);
2745 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2746 offset0, offset1, row_inc, pix_inc);
2748 dispc_ovl_set_color_mode(plane, color_mode);
2750 dispc_ovl_configure_burst_type(plane, rotation_type);
2752 dispc_ovl_set_ba0(plane, paddr + offset0);
2753 dispc_ovl_set_ba1(plane, paddr + offset1);
2755 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2756 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2757 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2760 if (dispc.feat->last_pixel_inc_missing)
2761 row_inc += pix_inc - 1;
2763 dispc_ovl_set_row_inc(plane, row_inc);
2764 dispc_ovl_set_pix_inc(plane, pix_inc);
2766 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2767 in_height, out_width, out_height);
2769 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2771 dispc_ovl_set_input_size(plane, in_width, in_height);
2773 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2774 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2775 out_height, ilace, five_taps, fieldmode,
2776 color_mode, rotation);
2777 dispc_ovl_set_output_size(plane, out_width, out_height);
2778 dispc_ovl_set_vid_color_conv(plane, cconv);
2781 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2784 dispc_ovl_set_zorder(plane, caps, zorder);
2785 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2786 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2788 dispc_ovl_enable_replication(plane, caps, replication);
2793 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2794 bool replication, const struct omap_video_timings *mgr_timings,
2798 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2799 enum omap_channel channel;
2801 channel = dispc_ovl_get_channel_out(plane);
2803 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2804 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2805 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2806 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2807 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2809 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2810 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2811 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2812 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2813 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2817 EXPORT_SYMBOL(dispc_ovl_setup);
2819 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2820 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2824 enum omap_plane plane = OMAP_DSS_WB;
2825 const int pos_x = 0, pos_y = 0;
2826 const u8 zorder = 0, global_alpha = 0;
2827 const bool replication = false;
2829 int in_width = mgr_timings->x_res;
2830 int in_height = mgr_timings->y_res;
2831 enum omap_overlay_caps caps =
2832 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2834 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2835 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2836 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2839 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2840 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2841 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2842 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2843 replication, mgr_timings, mem_to_mem);
2845 switch (wi->color_mode) {
2846 case OMAP_DSS_COLOR_RGB16:
2847 case OMAP_DSS_COLOR_RGB24P:
2848 case OMAP_DSS_COLOR_ARGB16:
2849 case OMAP_DSS_COLOR_RGBA16:
2850 case OMAP_DSS_COLOR_RGB12U:
2851 case OMAP_DSS_COLOR_ARGB16_1555:
2852 case OMAP_DSS_COLOR_XRGB16_1555:
2853 case OMAP_DSS_COLOR_RGBX16:
2861 /* setup extra DISPC_WB_ATTRIBUTES */
2862 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2863 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2864 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2866 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2868 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2869 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2877 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2878 mgr_timings->vbp, 255);
2881 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2887 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2889 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2891 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2895 EXPORT_SYMBOL(dispc_ovl_enable);
2897 bool dispc_ovl_enabled(enum omap_plane plane)
2899 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2901 EXPORT_SYMBOL(dispc_ovl_enabled);
2903 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2905 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2906 /* flush posted write */
2907 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2909 EXPORT_SYMBOL(dispc_mgr_enable);
2911 bool dispc_mgr_is_enabled(enum omap_channel channel)
2913 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2915 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2917 void dispc_wb_enable(bool enable)
2919 dispc_ovl_enable(OMAP_DSS_WB, enable);
2922 bool dispc_wb_is_enabled(void)
2924 return dispc_ovl_enabled(OMAP_DSS_WB);
2927 static void dispc_lcd_enable_signal_polarity(bool act_high)
2929 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2932 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2935 void dispc_lcd_enable_signal(bool enable)
2937 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2940 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2943 void dispc_pck_free_enable(bool enable)
2945 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2948 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2951 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2953 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2957 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2959 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2962 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2964 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2968 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2970 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2973 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2974 enum omap_dss_trans_key_type type,
2977 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2979 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2982 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2984 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2987 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2990 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2993 if (ch == OMAP_DSS_CHANNEL_LCD)
2994 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2995 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2996 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2999 void dispc_mgr_setup(enum omap_channel channel,
3000 const struct omap_overlay_manager_info *info)
3002 dispc_mgr_set_default_color(channel, info->default_color);
3003 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3004 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3005 dispc_mgr_enable_alpha_fixed_zorder(channel,
3006 info->partial_alpha_enabled);
3007 if (dss_has_feature(FEAT_CPR)) {
3008 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3009 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3012 EXPORT_SYMBOL(dispc_mgr_setup);
3014 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3018 switch (data_lines) {
3036 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3039 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3045 case DSS_IO_PAD_MODE_RESET:
3049 case DSS_IO_PAD_MODE_RFBI:
3053 case DSS_IO_PAD_MODE_BYPASS:
3062 l = dispc_read_reg(DISPC_CONTROL);
3063 l = FLD_MOD(l, gpout0, 15, 15);
3064 l = FLD_MOD(l, gpout1, 16, 16);
3065 dispc_write_reg(DISPC_CONTROL, l);
3068 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3070 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3073 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3074 const struct dss_lcd_mgr_config *config)
3076 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3078 dispc_mgr_enable_stallmode(channel, config->stallmode);
3079 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3081 dispc_mgr_set_clock_div(channel, &config->clock_info);
3083 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3085 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3087 dispc_mgr_set_lcd_type_tft(channel);
3089 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3091 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3093 return width <= dispc.feat->mgr_width_max &&
3094 height <= dispc.feat->mgr_height_max;
3097 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3098 int vsw, int vfp, int vbp)
3100 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3101 hfp < 1 || hfp > dispc.feat->hp_max ||
3102 hbp < 1 || hbp > dispc.feat->hp_max ||
3103 vsw < 1 || vsw > dispc.feat->sw_max ||
3104 vfp < 0 || vfp > dispc.feat->vp_max ||
3105 vbp < 0 || vbp > dispc.feat->vp_max)
3110 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3113 if (dss_mgr_is_lcd(channel))
3114 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3116 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3119 bool dispc_mgr_timings_ok(enum omap_channel channel,
3120 const struct omap_video_timings *timings)
3122 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3125 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3128 if (dss_mgr_is_lcd(channel)) {
3129 /* TODO: OMAP4+ supports interlace for LCD outputs */
3130 if (timings->interlace)
3133 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3134 timings->hbp, timings->vsw, timings->vfp,
3142 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3143 int hfp, int hbp, int vsw, int vfp, int vbp,
3144 enum omap_dss_signal_level vsync_level,
3145 enum omap_dss_signal_level hsync_level,
3146 enum omap_dss_signal_edge data_pclk_edge,
3147 enum omap_dss_signal_level de_level,
3148 enum omap_dss_signal_edge sync_pclk_edge)
3151 u32 timing_h, timing_v, l;
3152 bool onoff, rf, ipc, vs, hs, de;
3154 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3155 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3156 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3157 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3158 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3159 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3161 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3162 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3164 switch (vsync_level) {
3165 case OMAPDSS_SIG_ACTIVE_LOW:
3168 case OMAPDSS_SIG_ACTIVE_HIGH:
3175 switch (hsync_level) {
3176 case OMAPDSS_SIG_ACTIVE_LOW:
3179 case OMAPDSS_SIG_ACTIVE_HIGH:
3187 case OMAPDSS_SIG_ACTIVE_LOW:
3190 case OMAPDSS_SIG_ACTIVE_HIGH:
3197 switch (data_pclk_edge) {
3198 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3201 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3208 /* always use the 'rf' setting */
3211 switch (sync_pclk_edge) {
3212 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3215 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3222 l = FLD_VAL(onoff, 17, 17) |
3223 FLD_VAL(rf, 16, 16) |
3224 FLD_VAL(de, 15, 15) |
3225 FLD_VAL(ipc, 14, 14) |
3226 FLD_VAL(hs, 13, 13) |
3227 FLD_VAL(vs, 12, 12);
3229 /* always set ALIGN bit when available */
3230 if (dispc.feat->supports_sync_align)
3233 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3235 if (dispc.syscon_pol) {
3236 const int shifts[] = {
3237 [OMAP_DSS_CHANNEL_LCD] = 0,
3238 [OMAP_DSS_CHANNEL_LCD2] = 1,
3239 [OMAP_DSS_CHANNEL_LCD3] = 2,
3244 mask = (1 << 0) | (1 << 3) | (1 << 6);
3245 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3247 mask <<= 16 + shifts[channel];
3248 val <<= 16 + shifts[channel];
3250 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3255 /* change name to mode? */
3256 void dispc_mgr_set_timings(enum omap_channel channel,
3257 const struct omap_video_timings *timings)
3259 unsigned xtot, ytot;
3260 unsigned long ht, vt;
3261 struct omap_video_timings t = *timings;
3263 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3265 if (!dispc_mgr_timings_ok(channel, &t)) {
3270 if (dss_mgr_is_lcd(channel)) {
3271 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3272 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3273 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3275 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3276 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3278 ht = timings->pixelclock / xtot;
3279 vt = timings->pixelclock / xtot / ytot;
3281 DSSDBG("pck %u\n", timings->pixelclock);
3282 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3283 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3284 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3285 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3286 t.de_level, t.sync_pclk_edge);
3288 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3294 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3296 EXPORT_SYMBOL(dispc_mgr_set_timings);
3298 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3301 BUG_ON(lck_div < 1);
3302 BUG_ON(pck_div < 1);
3304 dispc_write_reg(DISPC_DIVISORo(channel),
3305 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3307 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3308 channel == OMAP_DSS_CHANNEL_LCD)
3309 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3312 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3316 l = dispc_read_reg(DISPC_DIVISORo(channel));
3317 *lck_div = FLD_GET(l, 23, 16);
3318 *pck_div = FLD_GET(l, 7, 0);
3321 static unsigned long dispc_fclk_rate(void)
3323 struct dss_pll *pll;
3324 unsigned long r = 0;
3326 switch (dss_get_dispc_clk_source()) {
3327 case OMAP_DSS_CLK_SRC_FCK:
3328 r = dss_get_dispc_clk_rate();
3330 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3331 pll = dss_pll_find("dsi0");
3333 pll = dss_pll_find("video0");
3335 r = pll->cinfo.clkout[0];
3337 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3338 pll = dss_pll_find("dsi1");
3340 pll = dss_pll_find("video1");
3342 r = pll->cinfo.clkout[0];
3352 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3354 struct dss_pll *pll;
3359 if (dss_mgr_is_lcd(channel)) {
3360 l = dispc_read_reg(DISPC_DIVISORo(channel));
3362 lcd = FLD_GET(l, 23, 16);
3364 switch (dss_get_lcd_clk_source(channel)) {
3365 case OMAP_DSS_CLK_SRC_FCK:
3366 r = dss_get_dispc_clk_rate();
3368 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3369 pll = dss_pll_find("dsi0");
3371 pll = dss_pll_find("video0");
3373 r = pll->cinfo.clkout[0];
3375 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3376 pll = dss_pll_find("dsi1");
3378 pll = dss_pll_find("video1");
3380 r = pll->cinfo.clkout[0];
3389 return dispc_fclk_rate();
3393 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3397 if (dss_mgr_is_lcd(channel)) {
3401 l = dispc_read_reg(DISPC_DIVISORo(channel));
3403 pcd = FLD_GET(l, 7, 0);
3405 r = dispc_mgr_lclk_rate(channel);
3409 return dispc.tv_pclk_rate;
3413 void dispc_set_tv_pclk(unsigned long pclk)
3415 dispc.tv_pclk_rate = pclk;
3418 static unsigned long dispc_core_clk_rate(void)
3420 return dispc.core_clk_rate;
3423 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3425 enum omap_channel channel;
3427 if (plane == OMAP_DSS_WB)
3430 channel = dispc_ovl_get_channel_out(plane);
3432 return dispc_mgr_pclk_rate(channel);
3435 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3437 enum omap_channel channel;
3439 if (plane == OMAP_DSS_WB)
3442 channel = dispc_ovl_get_channel_out(plane);
3444 return dispc_mgr_lclk_rate(channel);
3447 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3450 enum omap_dss_clk_source lcd_clk_src;
3452 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3454 lcd_clk_src = dss_get_lcd_clk_source(channel);
3456 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3457 dss_get_generic_clk_source_name(lcd_clk_src),
3458 dss_feat_get_clk_source_name(lcd_clk_src));
3460 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3462 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3463 dispc_mgr_lclk_rate(channel), lcd);
3464 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3465 dispc_mgr_pclk_rate(channel), pcd);
3468 void dispc_dump_clocks(struct seq_file *s)
3472 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3474 if (dispc_runtime_get())
3477 seq_printf(s, "- DISPC -\n");
3479 seq_printf(s, "dispc fclk source = %s (%s)\n",
3480 dss_get_generic_clk_source_name(dispc_clk_src),
3481 dss_feat_get_clk_source_name(dispc_clk_src));
3483 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3485 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3486 seq_printf(s, "- DISPC-CORE-CLK -\n");
3487 l = dispc_read_reg(DISPC_DIVISOR);
3488 lcd = FLD_GET(l, 23, 16);
3490 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3491 (dispc_fclk_rate()/lcd), lcd);
3494 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3496 if (dss_has_feature(FEAT_MGR_LCD2))
3497 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3498 if (dss_has_feature(FEAT_MGR_LCD3))
3499 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3501 dispc_runtime_put();
3504 static void dispc_dump_regs(struct seq_file *s)
3507 const char *mgr_names[] = {
3508 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3509 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3510 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3511 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3513 const char *ovl_names[] = {
3514 [OMAP_DSS_GFX] = "GFX",
3515 [OMAP_DSS_VIDEO1] = "VID1",
3516 [OMAP_DSS_VIDEO2] = "VID2",
3517 [OMAP_DSS_VIDEO3] = "VID3",
3518 [OMAP_DSS_WB] = "WB",
3520 const char **p_names;
3522 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3524 if (dispc_runtime_get())
3527 /* DISPC common registers */
3528 DUMPREG(DISPC_REVISION);
3529 DUMPREG(DISPC_SYSCONFIG);
3530 DUMPREG(DISPC_SYSSTATUS);
3531 DUMPREG(DISPC_IRQSTATUS);
3532 DUMPREG(DISPC_IRQENABLE);
3533 DUMPREG(DISPC_CONTROL);
3534 DUMPREG(DISPC_CONFIG);
3535 DUMPREG(DISPC_CAPABLE);
3536 DUMPREG(DISPC_LINE_STATUS);
3537 DUMPREG(DISPC_LINE_NUMBER);
3538 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3539 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3540 DUMPREG(DISPC_GLOBAL_ALPHA);
3541 if (dss_has_feature(FEAT_MGR_LCD2)) {
3542 DUMPREG(DISPC_CONTROL2);
3543 DUMPREG(DISPC_CONFIG2);
3545 if (dss_has_feature(FEAT_MGR_LCD3)) {
3546 DUMPREG(DISPC_CONTROL3);
3547 DUMPREG(DISPC_CONFIG3);
3549 if (dss_has_feature(FEAT_MFLAG))
3550 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3554 #define DISPC_REG(i, name) name(i)
3555 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3556 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3557 dispc_read_reg(DISPC_REG(i, r)))
3559 p_names = mgr_names;
3561 /* DISPC channel specific registers */
3562 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3563 DUMPREG(i, DISPC_DEFAULT_COLOR);
3564 DUMPREG(i, DISPC_TRANS_COLOR);
3565 DUMPREG(i, DISPC_SIZE_MGR);
3567 if (i == OMAP_DSS_CHANNEL_DIGIT)
3570 DUMPREG(i, DISPC_TIMING_H);
3571 DUMPREG(i, DISPC_TIMING_V);
3572 DUMPREG(i, DISPC_POL_FREQ);
3573 DUMPREG(i, DISPC_DIVISORo);
3575 DUMPREG(i, DISPC_DATA_CYCLE1);
3576 DUMPREG(i, DISPC_DATA_CYCLE2);
3577 DUMPREG(i, DISPC_DATA_CYCLE3);
3579 if (dss_has_feature(FEAT_CPR)) {
3580 DUMPREG(i, DISPC_CPR_COEF_R);
3581 DUMPREG(i, DISPC_CPR_COEF_G);
3582 DUMPREG(i, DISPC_CPR_COEF_B);
3586 p_names = ovl_names;
3588 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3589 DUMPREG(i, DISPC_OVL_BA0);
3590 DUMPREG(i, DISPC_OVL_BA1);
3591 DUMPREG(i, DISPC_OVL_POSITION);
3592 DUMPREG(i, DISPC_OVL_SIZE);
3593 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3594 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3595 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3596 DUMPREG(i, DISPC_OVL_ROW_INC);
3597 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3599 if (dss_has_feature(FEAT_PRELOAD))
3600 DUMPREG(i, DISPC_OVL_PRELOAD);
3601 if (dss_has_feature(FEAT_MFLAG))
3602 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3604 if (i == OMAP_DSS_GFX) {
3605 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3606 DUMPREG(i, DISPC_OVL_TABLE_BA);
3610 DUMPREG(i, DISPC_OVL_FIR);
3611 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3612 DUMPREG(i, DISPC_OVL_ACCU0);
3613 DUMPREG(i, DISPC_OVL_ACCU1);
3614 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3615 DUMPREG(i, DISPC_OVL_BA0_UV);
3616 DUMPREG(i, DISPC_OVL_BA1_UV);
3617 DUMPREG(i, DISPC_OVL_FIR2);
3618 DUMPREG(i, DISPC_OVL_ACCU2_0);
3619 DUMPREG(i, DISPC_OVL_ACCU2_1);
3621 if (dss_has_feature(FEAT_ATTR2))
3622 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3625 if (dispc.feat->has_writeback) {
3627 DUMPREG(i, DISPC_OVL_BA0);
3628 DUMPREG(i, DISPC_OVL_BA1);
3629 DUMPREG(i, DISPC_OVL_SIZE);
3630 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3631 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3632 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3633 DUMPREG(i, DISPC_OVL_ROW_INC);
3634 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3636 if (dss_has_feature(FEAT_MFLAG))
3637 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3639 DUMPREG(i, DISPC_OVL_FIR);
3640 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3641 DUMPREG(i, DISPC_OVL_ACCU0);
3642 DUMPREG(i, DISPC_OVL_ACCU1);
3643 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3644 DUMPREG(i, DISPC_OVL_BA0_UV);
3645 DUMPREG(i, DISPC_OVL_BA1_UV);
3646 DUMPREG(i, DISPC_OVL_FIR2);
3647 DUMPREG(i, DISPC_OVL_ACCU2_0);
3648 DUMPREG(i, DISPC_OVL_ACCU2_1);
3650 if (dss_has_feature(FEAT_ATTR2))
3651 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3657 #define DISPC_REG(plane, name, i) name(plane, i)
3658 #define DUMPREG(plane, name, i) \
3659 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3660 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3661 dispc_read_reg(DISPC_REG(plane, name, i)))
3663 /* Video pipeline coefficient registers */
3665 /* start from OMAP_DSS_VIDEO1 */
3666 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3667 for (j = 0; j < 8; j++)
3668 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3670 for (j = 0; j < 8; j++)
3671 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3673 for (j = 0; j < 5; j++)
3674 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3676 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3677 for (j = 0; j < 8; j++)
3678 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3681 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3682 for (j = 0; j < 8; j++)
3683 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3685 for (j = 0; j < 8; j++)
3686 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3688 for (j = 0; j < 8; j++)
3689 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3693 dispc_runtime_put();
3699 /* calculate clock rates using dividers in cinfo */
3700 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3701 struct dispc_clock_info *cinfo)
3703 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3705 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3708 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3709 cinfo->pck = cinfo->lck / cinfo->pck_div;
3714 bool dispc_div_calc(unsigned long dispc,
3715 unsigned long pck_min, unsigned long pck_max,
3716 dispc_div_calc_func func, void *data)
3718 int lckd, lckd_start, lckd_stop;
3719 int pckd, pckd_start, pckd_stop;
3720 unsigned long pck, lck;
3721 unsigned long lck_max;
3722 unsigned long pckd_hw_min, pckd_hw_max;
3723 unsigned min_fck_per_pck;
3726 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3727 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3729 min_fck_per_pck = 0;
3732 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3733 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3735 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3737 pck_min = pck_min ? pck_min : 1;
3738 pck_max = pck_max ? pck_max : ULONG_MAX;
3740 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3741 lckd_stop = min(dispc / pck_min, 255ul);
3743 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3746 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3747 pckd_stop = min(lck / pck_min, pckd_hw_max);
3749 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3753 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3754 * clock, which means we're configuring DISPC fclk here
3755 * also. Thus we need to use the calculated lck. For
3756 * OMAP4+ the DISPC fclk is a separate clock.
3758 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3759 fck = dispc_core_clk_rate();
3763 if (fck < pck * min_fck_per_pck)
3766 if (func(lckd, pckd, lck, pck, data))
3774 void dispc_mgr_set_clock_div(enum omap_channel channel,
3775 const struct dispc_clock_info *cinfo)
3777 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3778 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3780 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3783 int dispc_mgr_get_clock_div(enum omap_channel channel,
3784 struct dispc_clock_info *cinfo)
3788 fck = dispc_fclk_rate();
3790 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3791 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3793 cinfo->lck = fck / cinfo->lck_div;
3794 cinfo->pck = cinfo->lck / cinfo->pck_div;
3799 u32 dispc_read_irqstatus(void)
3801 return dispc_read_reg(DISPC_IRQSTATUS);
3803 EXPORT_SYMBOL(dispc_read_irqstatus);
3805 void dispc_clear_irqstatus(u32 mask)
3807 dispc_write_reg(DISPC_IRQSTATUS, mask);
3809 EXPORT_SYMBOL(dispc_clear_irqstatus);
3811 u32 dispc_read_irqenable(void)
3813 return dispc_read_reg(DISPC_IRQENABLE);
3815 EXPORT_SYMBOL(dispc_read_irqenable);
3817 void dispc_write_irqenable(u32 mask)
3819 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3821 /* clear the irqstatus for newly enabled irqs */
3822 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3824 dispc_write_reg(DISPC_IRQENABLE, mask);
3826 EXPORT_SYMBOL(dispc_write_irqenable);
3828 void dispc_enable_sidle(void)
3830 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3833 void dispc_disable_sidle(void)
3835 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3838 static void _omap_dispc_initial_config(void)
3842 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3843 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3844 l = dispc_read_reg(DISPC_DIVISOR);
3845 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3846 l = FLD_MOD(l, 1, 0, 0);
3847 l = FLD_MOD(l, 1, 23, 16);
3848 dispc_write_reg(DISPC_DIVISOR, l);
3850 dispc.core_clk_rate = dispc_fclk_rate();
3854 if (dss_has_feature(FEAT_FUNCGATED))
3855 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3857 dispc_setup_color_conv_coef();
3859 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3863 dispc_configure_burst_sizes();
3865 dispc_ovl_enable_zorder_planes();
3867 if (dispc.feat->mstandby_workaround)
3868 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3870 if (dss_has_feature(FEAT_MFLAG))
3874 static const struct dispc_features omap24xx_dispc_feats = {
3881 .mgr_width_start = 10,
3882 .mgr_height_start = 26,
3883 .mgr_width_max = 2048,
3884 .mgr_height_max = 2048,
3885 .max_lcd_pclk = 66500000,
3886 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3887 .calc_core_clk = calc_core_clk_24xx,
3889 .no_framedone_tv = true,
3890 .set_max_preload = false,
3891 .last_pixel_inc_missing = true,
3894 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3901 .mgr_width_start = 10,
3902 .mgr_height_start = 26,
3903 .mgr_width_max = 2048,
3904 .mgr_height_max = 2048,
3905 .max_lcd_pclk = 173000000,
3906 .max_tv_pclk = 59000000,
3907 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3908 .calc_core_clk = calc_core_clk_34xx,
3910 .no_framedone_tv = true,
3911 .set_max_preload = false,
3912 .last_pixel_inc_missing = true,
3915 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3922 .mgr_width_start = 10,
3923 .mgr_height_start = 26,
3924 .mgr_width_max = 2048,
3925 .mgr_height_max = 2048,
3926 .max_lcd_pclk = 173000000,
3927 .max_tv_pclk = 59000000,
3928 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3929 .calc_core_clk = calc_core_clk_34xx,
3931 .no_framedone_tv = true,
3932 .set_max_preload = false,
3933 .last_pixel_inc_missing = true,
3936 static const struct dispc_features omap44xx_dispc_feats = {
3943 .mgr_width_start = 10,
3944 .mgr_height_start = 26,
3945 .mgr_width_max = 2048,
3946 .mgr_height_max = 2048,
3947 .max_lcd_pclk = 170000000,
3948 .max_tv_pclk = 185625000,
3949 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3950 .calc_core_clk = calc_core_clk_44xx,
3952 .gfx_fifo_workaround = true,
3953 .set_max_preload = true,
3954 .supports_sync_align = true,
3955 .has_writeback = true,
3958 static const struct dispc_features omap54xx_dispc_feats = {
3965 .mgr_width_start = 11,
3966 .mgr_height_start = 27,
3967 .mgr_width_max = 4096,
3968 .mgr_height_max = 4096,
3969 .max_lcd_pclk = 170000000,
3970 .max_tv_pclk = 186000000,
3971 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3972 .calc_core_clk = calc_core_clk_44xx,
3974 .gfx_fifo_workaround = true,
3975 .mstandby_workaround = true,
3976 .set_max_preload = true,
3977 .supports_sync_align = true,
3978 .has_writeback = true,
3981 static const struct dispc_features *dispc_get_features(void)
3983 switch (omapdss_get_version()) {
3984 case OMAPDSS_VER_OMAP24xx:
3985 return &omap24xx_dispc_feats;
3987 case OMAPDSS_VER_OMAP34xx_ES1:
3988 return &omap34xx_rev1_0_dispc_feats;
3990 case OMAPDSS_VER_OMAP34xx_ES3:
3991 case OMAPDSS_VER_OMAP3630:
3992 case OMAPDSS_VER_AM35xx:
3993 case OMAPDSS_VER_AM43xx:
3994 return &omap34xx_rev3_0_dispc_feats;
3996 case OMAPDSS_VER_OMAP4430_ES1:
3997 case OMAPDSS_VER_OMAP4430_ES2:
3998 case OMAPDSS_VER_OMAP4:
3999 return &omap44xx_dispc_feats;
4001 case OMAPDSS_VER_OMAP5:
4002 case OMAPDSS_VER_DRA7xx:
4003 return &omap54xx_dispc_feats;
4010 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4012 if (!dispc.is_enabled)
4015 return dispc.user_handler(irq, dispc.user_data);
4018 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4022 if (dispc.user_handler != NULL)
4025 dispc.user_handler = handler;
4026 dispc.user_data = dev_id;
4028 /* ensure the dispc_irq_handler sees the values above */
4031 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4032 IRQF_SHARED, "OMAP DISPC", &dispc);
4034 dispc.user_handler = NULL;
4035 dispc.user_data = NULL;
4040 EXPORT_SYMBOL(dispc_request_irq);
4042 void dispc_free_irq(void *dev_id)
4044 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4046 dispc.user_handler = NULL;
4047 dispc.user_data = NULL;
4049 EXPORT_SYMBOL(dispc_free_irq);
4051 /* DISPC HW IP initialisation */
4052 static int dispc_bind(struct device *dev, struct device *master, void *data)
4054 struct platform_device *pdev = to_platform_device(dev);
4057 struct resource *dispc_mem;
4058 struct device_node *np = pdev->dev.of_node;
4062 spin_lock_init(&dispc.control_lock);
4064 dispc.feat = dispc_get_features();
4068 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4070 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4074 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4075 resource_size(dispc_mem));
4077 DSSERR("can't ioremap DISPC\n");
4081 dispc.irq = platform_get_irq(dispc.pdev, 0);
4082 if (dispc.irq < 0) {
4083 DSSERR("platform_get_irq failed\n");
4087 if (np && of_property_read_bool(np, "syscon-pol")) {
4088 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4089 if (IS_ERR(dispc.syscon_pol)) {
4090 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4091 return PTR_ERR(dispc.syscon_pol);
4094 if (of_property_read_u32_index(np, "syscon-pol", 1,
4095 &dispc.syscon_pol_offset)) {
4096 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4101 pm_runtime_enable(&pdev->dev);
4103 r = dispc_runtime_get();
4105 goto err_runtime_get;
4107 _omap_dispc_initial_config();
4109 rev = dispc_read_reg(DISPC_REVISION);
4110 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4111 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4113 dispc_runtime_put();
4115 dss_init_overlay_managers();
4117 dss_debugfs_create_file("dispc", dispc_dump_regs);
4122 pm_runtime_disable(&pdev->dev);
4126 static void dispc_unbind(struct device *dev, struct device *master,
4129 pm_runtime_disable(dev);
4131 dss_uninit_overlay_managers();
4134 static const struct component_ops dispc_component_ops = {
4136 .unbind = dispc_unbind,
4139 static int dispc_probe(struct platform_device *pdev)
4141 return component_add(&pdev->dev, &dispc_component_ops);
4144 static int dispc_remove(struct platform_device *pdev)
4146 component_del(&pdev->dev, &dispc_component_ops);
4150 static int dispc_runtime_suspend(struct device *dev)
4152 dispc.is_enabled = false;
4153 /* ensure the dispc_irq_handler sees the is_enabled value */
4155 /* wait for current handler to finish before turning the DISPC off */
4156 synchronize_irq(dispc.irq);
4158 dispc_save_context();
4163 static int dispc_runtime_resume(struct device *dev)
4166 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4167 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4168 * _omap_dispc_initial_config(). We can thus use it to detect if
4169 * we have lost register context.
4171 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4172 _omap_dispc_initial_config();
4174 dispc_restore_context();
4177 dispc.is_enabled = true;
4178 /* ensure the dispc_irq_handler sees the is_enabled value */
4184 static const struct dev_pm_ops dispc_pm_ops = {
4185 .runtime_suspend = dispc_runtime_suspend,
4186 .runtime_resume = dispc_runtime_resume,
4189 static const struct of_device_id dispc_of_match[] = {
4190 { .compatible = "ti,omap2-dispc", },
4191 { .compatible = "ti,omap3-dispc", },
4192 { .compatible = "ti,omap4-dispc", },
4193 { .compatible = "ti,omap5-dispc", },
4194 { .compatible = "ti,dra7-dispc", },
4198 static struct platform_driver omap_dispchw_driver = {
4199 .probe = dispc_probe,
4200 .remove = dispc_remove,
4202 .name = "omapdss_dispc",
4203 .pm = &dispc_pm_ops,
4204 .of_match_table = dispc_of_match,
4205 .suppress_bind_attrs = true,
4209 int __init dispc_init_platform_driver(void)
4211 return platform_driver_register(&omap_dispchw_driver);
4214 void dispc_uninit_platform_driver(void)
4216 platform_driver_unregister(&omap_dispchw_driver);