4 * Copyright (C) 2013 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/err.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <video/omapdss.h>
21 struct hdmi_phy_features {
25 unsigned long dcofreq_min;
26 unsigned long max_phy;
29 static const struct hdmi_phy_features *phy_feat;
31 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
33 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
34 hdmi_read_reg(phy->base, r))
36 DUMPPHY(HDMI_TXPHY_TX_CTRL);
37 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
38 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
39 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
40 if (phy_feat->bist_ctrl)
41 DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
44 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)
48 for (i = 0; i < 8; i += 2) {
55 if (dx < 0 || dx >= 8)
58 if (dy < 0 || dy >= 8)
73 phy->lane_function[lane] = i / 2;
74 phy->lane_polarity[lane] = pol;
80 static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
82 static const u16 pad_cfg_list[] = {
111 unsigned lane_cfg_val;
114 for (i = 0; i < 4; ++i)
115 lane_cfg |= phy->lane_function[i] << ((3 - i) * 4);
117 pol_val |= phy->lane_polarity[0] << 0;
118 pol_val |= phy->lane_polarity[1] << 3;
119 pol_val |= phy->lane_polarity[2] << 2;
120 pol_val |= phy->lane_polarity[3] << 1;
122 for (i = 0; i < ARRAY_SIZE(pad_cfg_list); ++i)
123 if (pad_cfg_list[i] == lane_cfg)
126 if (WARN_ON(i == ARRAY_SIZE(pad_cfg_list)))
131 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22);
132 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
135 int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg)
140 * Read address 0 in order to get the SCP reset done completed
141 * Dummy access performed to make sure reset is done
143 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
146 * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
147 * HDMI_PHYPWRCMD_LDOON command.
149 if (phy_feat->bist_ctrl)
150 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
152 if (phy_feat->calc_freqout) {
153 /* DCOCLK/10 is pixel clock, compare pclk with DCOCLK_MIN/10 */
154 u32 dco_min = phy_feat->dcofreq_min / 10;
155 u32 pclk = cfg->timings.pixelclock;
159 else if ((pclk >= dco_min) && (pclk < phy_feat->max_phy))
168 * Write to phy address 0 to configure the clock
169 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
171 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);
173 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
174 hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
176 /* Setup max LDO voltage */
177 if (phy_feat->ldo_voltage)
178 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
180 hdmi_phy_configure_lanes(phy);
185 static const struct hdmi_phy_features omap44xx_phy_feats = {
187 .calc_freqout = false,
189 .dcofreq_min = 500000000,
190 .max_phy = 185675000,
193 static const struct hdmi_phy_features omap54xx_phy_feats = {
195 .calc_freqout = true,
196 .ldo_voltage = false,
197 .dcofreq_min = 750000000,
198 .max_phy = 186000000,
201 static int hdmi_phy_init_features(struct platform_device *pdev)
203 struct hdmi_phy_features *dst;
204 const struct hdmi_phy_features *src;
206 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
208 dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n");
212 switch (omapdss_get_version()) {
213 case OMAPDSS_VER_OMAP4430_ES1:
214 case OMAPDSS_VER_OMAP4430_ES2:
215 case OMAPDSS_VER_OMAP4:
216 src = &omap44xx_phy_feats;
219 case OMAPDSS_VER_OMAP5:
220 src = &omap54xx_phy_feats;
227 memcpy(dst, src, sizeof(*dst));
233 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
236 struct resource *res;
238 r = hdmi_phy_init_features(pdev);
242 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
244 DSSERR("can't get PHY mem resource\n");
248 phy->base = devm_ioremap_resource(&pdev->dev, res);
249 if (IS_ERR(phy->base)) {
250 DSSERR("can't ioremap TX PHY\n");
251 return PTR_ERR(phy->base);