drivers/video/fbdev/omap2/dss/hdmi5_core.c

   1 /*
   2  * OMAP5 HDMI CORE IP driver library
   3  *
   4  * Copyright (C) 2014 Texas Instruments Incorporated
   5  *
   6  * Authors:
   7  *      Yong Zhi
   8  *      Mythri pk
   9  *      Archit Taneja <archit@ti.com>
  10  *      Tomi Valkeinen <tomi.valkeinen@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License version 2 as published by
  14  * the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along with
  22  * this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/err.h>
  28 #include <linux/io.h>
  29 #include <linux/delay.h>
  30 #include <linux/string.h>
  31 #include <linux/seq_file.h>
  32 #include <drm/drm_edid.h>
  33 #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
  34 #include <sound/asound.h>
  35 #include <sound/asoundef.h>
  36 #endif
  37
  38 #include "hdmi5_core.h"
  39
  40 /* only 24 bit color depth used for now */
  41 static const struct csc_table csc_table_deepcolor[] = {
  42         /* HDMI_DEEP_COLOR_24BIT */
  43         [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
  44         /* HDMI_DEEP_COLOR_30BIT */
  45         [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
  46         /* HDMI_DEEP_COLOR_36BIT */
  47         [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
  48         /* FULL RANGE */
  49         [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
  50 };
  51
  52 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
  53 {
  54         void __iomem *base = core->base;
  55         const unsigned long long iclk = 266000000;      /* DSS L3 ICLK */
  56         const unsigned ss_scl_high = 4000;              /* ns */
  57         const unsigned ss_scl_low = 4700;               /* ns */
  58         const unsigned fs_scl_high = 600;               /* ns */
  59         const unsigned fs_scl_low = 1300;               /* ns */
  60         const unsigned sda_hold = 300;                  /* ns */
  61         const unsigned sfr_div = 10;
  62         unsigned long long sfr;
  63         unsigned v;
  64
  65         sfr = iclk / sfr_div;   /* SFR_DIV */
  66         sfr /= 1000;            /* SFR clock in kHz */
  67
  68         /* Reset */
  69         REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
  70         if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
  71                                 0, 0, 1) != 1)
  72                 DSSERR("HDMI I2CM reset failed\n");
  73
  74         /* Standard (0) or Fast (1) Mode */
  75         REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
  76
  77         /* Standard Mode SCL High counter */
  78         v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
  79         REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
  80                         (v >> 8) & 0xff, 7, 0);
  81         REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
  82                         v & 0xff, 7, 0);
  83
  84         /* Standard Mode SCL Low counter */
  85         v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
  86         REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
  87                         (v >> 8) & 0xff, 7, 0);
  88         REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
  89                         v & 0xff, 7, 0);
  90
  91         /* Fast Mode SCL High Counter */
  92         v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
  93         REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
  94                         (v >> 8) & 0xff, 7, 0);
  95         REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
  96                         v & 0xff, 7, 0);
  97
  98         /* Fast Mode SCL Low Counter */
  99         v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
 100         REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
 101                         (v >> 8) & 0xff, 7, 0);
 102         REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
 103                         v & 0xff, 7, 0);
 104
 105         /* SDA Hold Time */
 106         v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
 107         REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
 108
 109         REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
 110         REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
 111
 112         /* NACK_POL to high */
 113         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
 114
 115         /* NACK_MASK to unmasked */
 116         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
 117
 118         /* ARBITRATION_POL to high */
 119         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
 120
 121         /* ARBITRATION_MASK to unmasked */
 122         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
 123
 124         /* DONE_POL to high */
 125         REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
 126
 127         /* DONE_MASK to unmasked */
 128         REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
 129 }
 130
 131 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
 132 {
 133         void __iomem *base = core->base;
 134
 135         /* Mask I2C interrupts */
 136         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
 137         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
 138         REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
 139 }
 140
 141 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
 142 {
 143         void __iomem *base = core->base;
 144         u8 cur_addr;
 145         char checksum = 0;
 146         const int retries = 1000;
 147         u8 seg_ptr = ext / 2;
 148         u8 edidbase = ((ext % 2) * 0x80);
 149
 150         REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
 151
 152         /*
 153          * TODO: We use polling here, although we probably should use proper
 154          * interrupts.
 155          */
 156         for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
 157                 int i;
 158
 159                 /* clear ERROR and DONE */
 160                 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
 161
 162                 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
 163                                 edidbase + cur_addr, 7, 0);
 164
 165                 if (seg_ptr)
 166                         REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
 167                 else
 168                         REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
 169
 170                 for (i = 0; i < retries; ++i) {
 171                         u32 stat;
 172
 173                         stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
 174
 175                         /* I2CM_ERROR */
 176                         if (stat & 1) {
 177                                 DSSERR("HDMI I2C Master Error\n");
 178                                 return -EIO;
 179                         }
 180
 181                         /* I2CM_DONE */
 182                         if (stat & (1 << 1))
 183                                 break;
 184
 185                         usleep_range(250, 1000);
 186                 }
 187
 188                 if (i == retries) {
 189                         DSSERR("HDMI I2C timeout reading EDID\n");
 190                         return -EIO;
 191                 }
 192
 193                 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
 194                 checksum += pedid[cur_addr];
 195         }
 196
 197         return 0;
 198
 199 }
 200
 201 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
 202 {
 203         int r, n, i;
 204         int max_ext_blocks = (len / 128) - 1;
 205
 206         if (len < 128)
 207                 return -EINVAL;
 208
 209         hdmi_core_ddc_init(core);
 210
 211         r = hdmi_core_ddc_edid(core, edid, 0);
 212         if (r)
 213                 goto out;
 214
 215         n = edid[0x7e];
 216
 217         if (n > max_ext_blocks)
 218                 n = max_ext_blocks;
 219
 220         for (i = 1; i <= n; i++) {
 221                 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
 222                 if (r)
 223                         goto out;
 224         }
 225
 226 out:
 227         hdmi_core_ddc_uninit(core);
 228
 229         return r ? r : len;
 230 }
 231
 232 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
 233 {
 234
 235 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
 236                 hdmi_read_reg(core->base, r))
 237
 238         DUMPCORE(HDMI_CORE_FC_INVIDCONF);
 239         DUMPCORE(HDMI_CORE_FC_INHACTIV0);
 240         DUMPCORE(HDMI_CORE_FC_INHACTIV1);
 241         DUMPCORE(HDMI_CORE_FC_INHBLANK0);
 242         DUMPCORE(HDMI_CORE_FC_INHBLANK1);
 243         DUMPCORE(HDMI_CORE_FC_INVACTIV0);
 244         DUMPCORE(HDMI_CORE_FC_INVACTIV1);
 245         DUMPCORE(HDMI_CORE_FC_INVBLANK);
 246         DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
 247         DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
 248         DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
 249         DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
 250         DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
 251         DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
 252         DUMPCORE(HDMI_CORE_FC_CTRLDUR);
 253         DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
 254         DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
 255         DUMPCORE(HDMI_CORE_FC_CH0PREAM);
 256         DUMPCORE(HDMI_CORE_FC_CH1PREAM);
 257         DUMPCORE(HDMI_CORE_FC_CH2PREAM);
 258         DUMPCORE(HDMI_CORE_FC_AVICONF0);
 259         DUMPCORE(HDMI_CORE_FC_AVICONF1);
 260         DUMPCORE(HDMI_CORE_FC_AVICONF2);
 261         DUMPCORE(HDMI_CORE_FC_AVIVID);
 262         DUMPCORE(HDMI_CORE_FC_PRCONF);
 263
 264         DUMPCORE(HDMI_CORE_MC_CLKDIS);
 265         DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
 266         DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
 267         DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
 268         DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
 269
 270         DUMPCORE(HDMI_CORE_I2CM_SLAVE);
 271         DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
 272         DUMPCORE(HDMI_CORE_I2CM_DATAO);
 273         DUMPCORE(HDMI_CORE_I2CM_DATAI);
 274         DUMPCORE(HDMI_CORE_I2CM_OPERATION);
 275         DUMPCORE(HDMI_CORE_I2CM_INT);
 276         DUMPCORE(HDMI_CORE_I2CM_CTLINT);
 277         DUMPCORE(HDMI_CORE_I2CM_DIV);
 278         DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
 279         DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
 280         DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
 281         DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
 282         DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
 283         DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
 284         DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
 285         DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
 286         DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
 287         DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
 288         DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
 289         DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
 290 }
 291
 292 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
 293                         struct hdmi_config *cfg)
 294 {
 295         DSSDBG("hdmi_core_init\n");
 296
 297         /* video core */
 298         video_cfg->data_enable_pol = 1; /* It is always 1*/
 299         video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
 300         video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
 301         video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
 302         video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
 303         video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
 304         video_cfg->hblank = cfg->timings.hfp +
 305                                 cfg->timings.hbp + cfg->timings.hsw - 1;
 306         video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
 307         video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
 308         video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
 309         video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
 310         video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
 311         video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
 312         video_cfg->vblank = cfg->timings.vsw +
 313                                 cfg->timings.vfp + cfg->timings.vbp;
 314         video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
 315         video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
 316 }
 317
 318 /* DSS_HDMI_CORE_VIDEO_CONFIG */
 319 static void hdmi_core_video_config(struct hdmi_core_data *core,
 320                         struct hdmi_core_vid_config *cfg)
 321 {
 322         void __iomem *base = core->base;
 323         unsigned char r = 0;
 324         bool vsync_pol, hsync_pol;
 325
 326         vsync_pol =
 327                 cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
 328         hsync_pol =
 329                 cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
 330
 331         /* Set hsync, vsync and data-enable polarity  */
 332         r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
 333         r = FLD_MOD(r, vsync_pol, 6, 6);
 334         r = FLD_MOD(r, hsync_pol, 5, 5);
 335         r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
 336         r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
 337         r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
 338         hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
 339
 340         /* set x resolution */
 341         REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
 342                         cfg->v_fc_config.timings.x_res >> 8, 4, 0);
 343         REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
 344                         cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
 345
 346         /* set y resolution */
 347         REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
 348                         cfg->v_fc_config.timings.y_res >> 8, 4, 0);
 349         REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
 350                         cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
 351
 352         /* set horizontal blanking pixels */
 353         REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
 354         REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
 355
 356         /* set vertial blanking pixels */
 357         REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
 358
 359         /* set horizontal sync offset */
 360         REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
 361                         cfg->v_fc_config.timings.hfp >> 8, 4, 0);
 362         REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
 363                         cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
 364
 365         /* set vertical sync offset */
 366         REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
 367                         cfg->v_fc_config.timings.vfp, 7, 0);
 368
 369         /* set horizontal sync pulse width */
 370         REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
 371                         (cfg->v_fc_config.timings.hsw >> 8), 1, 0);
 372         REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
 373                         cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
 374
 375         /*  set vertical sync pulse width */
 376         REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
 377                         cfg->v_fc_config.timings.vsw, 5, 0);
 378
 379         /* select DVI mode */
 380         REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
 381                         cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
 382 }
 383
 384 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
 385 {
 386         void __iomem *base = core->base;
 387         int clr_depth = 0;      /* 24 bit color depth */
 388
 389         /* COLOR_DEPTH */
 390         REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
 391         /* BYPASS_EN */
 392         REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
 393         /* PP_EN */
 394         REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
 395         /* YCC422_EN */
 396         REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
 397         /* PP_STUFFING */
 398         REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
 399         /* YCC422_STUFFING */
 400         REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
 401         /* OUTPUT_SELECTOR */
 402         REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
 403 }
 404
 405 static void hdmi_core_config_csc(struct hdmi_core_data *core)
 406 {
 407         int clr_depth = 0;      /* 24 bit color depth */
 408
 409         /* CSC_COLORDEPTH */
 410         REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
 411 }
 412
 413 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
 414 {
 415         int video_mapping = 1;  /* for 24 bit color depth */
 416
 417         /* VIDEO_MAPPING */
 418         REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
 419 }
 420
 421 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
 422         struct hdmi_avi_infoframe *frame)
 423 {
 424         void __iomem *base = core->base;
 425         u8 data[HDMI_INFOFRAME_SIZE(AVI)];
 426         u8 *ptr;
 427         unsigned y, a, b, s;
 428         unsigned c, m, r;
 429         unsigned itc, ec, q, sc;
 430         unsigned vic;
 431         unsigned yq, cn, pr;
 432
 433         hdmi_avi_infoframe_pack(frame, data, sizeof(data));
 434
 435         print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
 436                 HDMI_INFOFRAME_SIZE(AVI), false);
 437
 438         ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
 439
 440         y = (ptr[0] >> 5) & 0x3;
 441         a = (ptr[0] >> 4) & 0x1;
 442         b = (ptr[0] >> 2) & 0x3;
 443         s = (ptr[0] >> 0) & 0x3;
 444
 445         c = (ptr[1] >> 6) & 0x3;
 446         m = (ptr[1] >> 4) & 0x3;
 447         r = (ptr[1] >> 0) & 0x3;
 448
 449         itc = (ptr[2] >> 7) & 0x1;
 450         ec = (ptr[2] >> 4) & 0x7;
 451         q = (ptr[2] >> 2) & 0x3;
 452         sc = (ptr[2] >> 0) & 0x3;
 453
 454         vic = ptr[3];
 455
 456         yq = (ptr[4] >> 6) & 0x3;
 457         cn = (ptr[4] >> 4) & 0x3;
 458         pr = (ptr[4] >> 0) & 0xf;
 459
 460         hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
 461                 (a << 6) | (s << 4) | (b << 2) | (y << 0));
 462
 463         hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
 464                 (c << 6) | (m << 4) | (r << 0));
 465
 466         hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
 467                 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
 468
 469         hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
 470
 471         hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
 472                 (yq << 2) | (cn << 0));
 473
 474         REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
 475 }
 476
 477 static void hdmi_core_csc_config(struct hdmi_core_data *core,
 478                 struct csc_table csc_coeff)
 479 {
 480         void __iomem *base = core->base;
 481
 482         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
 483         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
 484         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
 485         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
 486         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
 487         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
 488         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
 489         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
 490         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
 491         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
 492         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
 493         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
 494         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
 495         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
 496         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
 497         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
 498         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
 499         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
 500         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
 501         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
 502         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
 503         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
 504         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
 505         REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
 506
 507         REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
 508 }
 509
 510 static void hdmi_core_configure_range(struct hdmi_core_data *core)
 511 {
 512         struct csc_table csc_coeff = { 0 };
 513
 514         /* support limited range with 24 bit color depth for now */
 515         csc_coeff = csc_table_deepcolor[0];
 516
 517         hdmi_core_csc_config(core, csc_coeff);
 518 }
 519
 520 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
 521 {
 522         void __iomem *base = core->base;
 523
 524         DSSDBG("hdmi_core_enable_video_path\n");
 525
 526         REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
 527         REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
 528         REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
 529         REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
 530         REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
 531         REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
 532         REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
 533         REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
 534 }
 535
 536 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
 537 {
 538         void __iomem *base = core->base;
 539
 540         /* Master IRQ mask */
 541         REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
 542
 543         /* Mask all the interrupts in HDMI core */
 544
 545         REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
 546         REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
 547         REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
 548         REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
 549
 550         REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
 551         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
 552
 553         REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
 554
 555         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
 556         REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
 557         REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
 558
 559         REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
 560
 561         REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
 562
 563         /* Clear all the current interrupt bits */
 564
 565         REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
 566         REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
 567         REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
 568         REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
 569
 570         REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
 571
 572         REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
 573
 574         REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
 575
 576         REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
 577 }
 578
 579 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
 580 {
 581         /* Unmute interrupts */
 582         REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
 583 }
 584
 585 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
 586 {
 587         void __iomem *base = core->base;
 588
 589         REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
 590         REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
 591         REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
 592         REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
 593         REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
 594         REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
 595         REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
 596         REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
 597         REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
 598
 599         return 0;
 600 }
 601
 602 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
 603                 struct hdmi_config *cfg)
 604 {
 605         struct omap_video_timings video_timing;
 606         struct hdmi_video_format video_format;
 607         struct hdmi_core_vid_config v_core_cfg;
 608
 609         hdmi_core_mask_interrupts(core);
 610
 611         hdmi_core_init(&v_core_cfg, cfg);
 612
 613         hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
 614
 615         hdmi_wp_video_config_timing(wp, &video_timing);
 616
 617         /* video config */
 618         video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
 619
 620         hdmi_wp_video_config_format(wp, &video_format);
 621
 622         hdmi_wp_video_config_interface(wp, &video_timing);
 623
 624         /* support limited range with 24 bit color depth for now */
 625         hdmi_core_configure_range(core);
 626         cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
 627
 628         /*
 629          * configure core video part, set software reset in the core
 630          */
 631         v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
 632
 633         hdmi_core_video_config(core, &v_core_cfg);
 634
 635         hdmi_core_config_video_packetizer(core);
 636         hdmi_core_config_csc(core);
 637         hdmi_core_config_video_sampler(core);
 638
 639         if (cfg->hdmi_dvi_mode == HDMI_HDMI)
 640                 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
 641
 642         hdmi_core_enable_video_path(core);
 643
 644         hdmi_core_enable_interrupts(core);
 645 }
 646
 647
 648 #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
 649
 650 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
 651                         struct hdmi_core_audio_config *cfg)
 652 {
 653         void __iomem *base = core->base;
 654         u8 val;
 655
 656         /* Mute audio before configuring */
 657         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
 658
 659         /* Set the N parameter */
 660         REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
 661         REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
 662         REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
 663
 664         /*
 665          * CTS manual mode. Automatic mode is not supported when using audio
 666          * parallel interface.
 667          */
 668         REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
 669         REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
 670         REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
 671         REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
 672
 673         /* Layout of Audio Sample Packets: 2-channel or multichannels */
 674         if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
 675                 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
 676         else
 677                 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
 678
 679         /* Configure IEC-609580 Validity bits */
 680         /* Channel 0 is valid */
 681         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
 682         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
 683
 684         if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
 685                 val = 1;
 686         else
 687                 val = 0;
 688
 689         /* Channels 1, 2 setting */
 690         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
 691         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
 692         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
 693         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
 694         /* Channel 3 setting */
 695         if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
 696                 val = 1;
 697         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
 698         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
 699
 700         /* Configure IEC-60958 User bits */
 701         /* TODO: should be set by user. */
 702         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
 703
 704         /* Configure IEC-60958 Channel Status word */
 705         /* CGMSA */
 706         val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
 707         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
 708
 709         /* Copyright */
 710         val = (cfg->iec60958_cfg->status[0] &
 711                         IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
 712         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
 713
 714         /* Category */
 715         hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
 716                 cfg->iec60958_cfg->status[1]);
 717
 718         /* PCM audio mode */
 719         val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
 720         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
 721
 722         /* Source number */
 723         val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
 724         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 4);
 725
 726         /* Channel number right 0  */
 727         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
 728         /* Channel number right 1*/
 729         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
 730         /* Channel number right 2  */
 731         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
 732         /* Channel number right 3*/
 733         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
 734         /* Channel number left 0  */
 735         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
 736         /* Channel number left 1*/
 737         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
 738         /* Channel number left 2  */
 739         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
 740         /* Channel number left 3*/
 741         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
 742
 743         /* Clock accuracy and sample rate */
 744         hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
 745                 cfg->iec60958_cfg->status[3]);
 746
 747         /* Original sample rate and word length */
 748         hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
 749                 cfg->iec60958_cfg->status[4]);
 750
 751         /* Enable FIFO empty and full interrupts */
 752         REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
 753
 754         /* Configure GPA */
 755         /* select HBR/SPDIF interfaces */
 756         if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
 757                 /* select HBR/SPDIF interfaces */
 758                 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
 759                 /* enable two channels in GPA */
 760                 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
 761         } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
 762                 /* select HBR/SPDIF interfaces */
 763                 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
 764                 /* enable six channels in GPA */
 765                 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
 766         } else {
 767                 /* select HBR/SPDIF interfaces */
 768                 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
 769                 /* enable eight channels in GPA */
 770                 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
 771         }
 772
 773         /* disable HBR */
 774         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
 775         /* enable PCUV */
 776         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
 777         /* enable GPA FIFO full and empty mask */
 778         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
 779         /* set polarity of GPA FIFO empty interrupts */
 780         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
 781
 782         /* unmute audio */
 783         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
 784 }
 785
 786 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
 787          struct snd_cea_861_aud_if *info_aud)
 788 {
 789         void __iomem *base = core->base;
 790
 791         /* channel count and coding type fields in AUDICONF0 are swapped */
 792         hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
 793                 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
 794                 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
 795
 796         hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
 797         hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
 798         hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, info_aud->db5_dminh_lsv);
 799 }
 800
 801 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
 802                         struct omap_dss_audio *audio, u32 pclk)
 803 {
 804         struct hdmi_audio_format audio_format;
 805         struct hdmi_audio_dma audio_dma;
 806         struct hdmi_core_audio_config core_cfg;
 807         int err, n, cts, channel_count;
 808         unsigned int fs_nr;
 809         bool word_length_16b = false;
 810
 811         if (!audio || !audio->iec || !audio->cea || !core)
 812                 return -EINVAL;
 813
 814         core_cfg.iec60958_cfg = audio->iec;
 815
 816         if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
 817                 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
 818                         word_length_16b = true;
 819
 820         /* only 16-bit word length supported atm */
 821         if (!word_length_16b)
 822                 return -EINVAL;
 823
 824         switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
 825         case IEC958_AES3_CON_FS_32000:
 826                 fs_nr = 32000;
 827                 break;
 828         case IEC958_AES3_CON_FS_44100:
 829                 fs_nr = 44100;
 830                 break;
 831         case IEC958_AES3_CON_FS_48000:
 832                 fs_nr = 48000;
 833                 break;
 834         case IEC958_AES3_CON_FS_88200:
 835                 fs_nr = 88200;
 836                 break;
 837         case IEC958_AES3_CON_FS_96000:
 838                 fs_nr = 96000;
 839                 break;
 840         case IEC958_AES3_CON_FS_176400:
 841                 fs_nr = 176400;
 842                 break;
 843         case IEC958_AES3_CON_FS_192000:
 844                 fs_nr = 192000;
 845                 break;
 846         default:
 847                 return -EINVAL;
 848         }
 849
 850         err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
 851         core_cfg.n = n;
 852         core_cfg.cts = cts;
 853
 854         /* Audio channels settings */
 855         channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
 856                                 + 1;
 857
 858         if (channel_count == 2)
 859                 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
 860         else if (channel_count == 6)
 861                 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
 862         else
 863                 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
 864
 865         /* DMA settings */
 866         if (word_length_16b)
 867                 audio_dma.transfer_size = 0x10;
 868         else
 869                 audio_dma.transfer_size = 0x20;
 870         audio_dma.block_size = 0xC0;
 871         audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
 872         audio_dma.fifo_threshold = 0x20; /* in number of samples */
 873
 874         /* audio FIFO format settings for 16-bit samples*/
 875         audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
 876         audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
 877         audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
 878
 879         /* only LPCM atm */
 880         audio_format.type = HDMI_AUDIO_TYPE_LPCM;
 881
 882         /* disable start/stop signals of IEC 60958 blocks */
 883         audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
 884
 885         /* configure DMA and audio FIFO format*/
 886         hdmi_wp_audio_config_dma(wp, &audio_dma);
 887         hdmi_wp_audio_config_format(wp, &audio_format);
 888
 889         /* configure the core */
 890         hdmi5_core_audio_config(core, &core_cfg);
 891
 892         /* configure CEA 861 audio infoframe */
 893         hdmi5_core_audio_infoframe_cfg(core, audio->cea);
 894
 895         return 0;
 896 }
 897 #endif
 898
 899 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
 900 {
 901         struct resource *res;
 902
 903         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
 904         if (!res) {
 905                 DSSERR("can't get CORE IORESOURCE_MEM HDMI\n");
 906                 return -EINVAL;
 907         }
 908
 909         core->base = devm_ioremap_resource(&pdev->dev, res);
 910         if (IS_ERR(core->base)) {
 911                 DSSERR("can't ioremap HDMI core\n");
 912                 return PTR_ERR(core->base);
 913         }
 914
 915         return 0;
 916 }