drivers/video/fbdev/omap2/dss/hdmi5.c

   1 /*
   2  * HDMI driver for OMAP5
   3  *
   4  * Copyright (C) 2014 Texas Instruments Incorporated
   5  *
   6  * Authors:
   7  *      Yong Zhi
   8  *      Mythri pk
   9  *      Archit Taneja <archit@ti.com>
  10  *      Tomi Valkeinen <tomi.valkeinen@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License version 2 as published by
  14  * the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along with
  22  * this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #define DSS_SUBSYS_NAME "HDMI"
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/err.h>
  30 #include <linux/io.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/mutex.h>
  33 #include <linux/delay.h>
  34 #include <linux/string.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/clk.h>
  38 #include <linux/gpio.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <video/omapdss.h>
  41
  42 #include "hdmi5_core.h"
  43 #include "dss.h"
  44 #include "dss_features.h"
  45
  46 static struct {
  47         struct mutex lock;
  48         struct platform_device *pdev;
  49
  50         struct hdmi_wp_data     wp;
  51         struct hdmi_pll_data    pll;
  52         struct hdmi_phy_data    phy;
  53         struct hdmi_core_data   core;
  54
  55         struct hdmi_config cfg;
  56
  57         struct clk *sys_clk;
  58         struct regulator *vdda_reg;
  59
  60         bool core_enabled;
  61
  62         struct omap_dss_device output;
  63 } hdmi;
  64
  65 static int hdmi_runtime_get(void)
  66 {
  67         int r;
  68
  69         DSSDBG("hdmi_runtime_get\n");
  70
  71         r = pm_runtime_get_sync(&hdmi.pdev->dev);
  72         WARN_ON(r < 0);
  73         if (r < 0)
  74                 return r;
  75
  76         return 0;
  77 }
  78
  79 static void hdmi_runtime_put(void)
  80 {
  81         int r;
  82
  83         DSSDBG("hdmi_runtime_put\n");
  84
  85         r = pm_runtime_put_sync(&hdmi.pdev->dev);
  86         WARN_ON(r < 0 && r != -ENOSYS);
  87 }
  88
  89 static irqreturn_t hdmi_irq_handler(int irq, void *data)
  90 {
  91         struct hdmi_wp_data *wp = data;
  92         u32 irqstatus;
  93
  94         irqstatus = hdmi_wp_get_irqstatus(wp);
  95         hdmi_wp_set_irqstatus(wp, irqstatus);
  96
  97         if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  98                         irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  99                 u32 v;
 100                 /*
 101                  * If we get both connect and disconnect interrupts at the same
 102                  * time, turn off the PHY, clear interrupts, and restart, which
 103                  * raises connect interrupt if a cable is connected, or nothing
 104                  * if cable is not connected.
 105                  */
 106
 107                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
 108
 109                 /*
 110                  * We always get bogus CONNECT & DISCONNECT interrupts when
 111                  * setting the PHY to LDOON. To ignore those, we force the RXDET
 112                  * line to 0 until the PHY power state has been changed.
 113                  */
 114                 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
 115                 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
 116                 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
 117                 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
 118
 119                 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
 120                                 HDMI_IRQ_LINK_DISCONNECT);
 121
 122                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
 123
 124                 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
 125
 126         } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
 127                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
 128         } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
 129                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
 130         }
 131
 132         return IRQ_HANDLED;
 133 }
 134
 135 static int hdmi_init_regulator(void)
 136 {
 137         int r;
 138         struct regulator *reg;
 139
 140         if (hdmi.vdda_reg != NULL)
 141                 return 0;
 142
 143         reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
 144         if (IS_ERR(reg)) {
 145                 DSSERR("can't get VDDA regulator\n");
 146                 return PTR_ERR(reg);
 147         }
 148
 149         if (regulator_can_change_voltage(reg)) {
 150                 r = regulator_set_voltage(reg, 1800000, 1800000);
 151                 if (r) {
 152                         devm_regulator_put(reg);
 153                         DSSWARN("can't set the regulator voltage\n");
 154                         return r;
 155                 }
 156         }
 157
 158         hdmi.vdda_reg = reg;
 159
 160         return 0;
 161 }
 162
 163 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
 164 {
 165         int r;
 166
 167         r = regulator_enable(hdmi.vdda_reg);
 168         if (r)
 169                 return r;
 170
 171         r = hdmi_runtime_get();
 172         if (r)
 173                 goto err_runtime_get;
 174
 175         /* Make selection of HDMI in DSS */
 176         dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
 177
 178         hdmi.core_enabled = true;
 179
 180         return 0;
 181
 182 err_runtime_get:
 183         regulator_disable(hdmi.vdda_reg);
 184
 185         return r;
 186 }
 187
 188 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
 189 {
 190         hdmi.core_enabled = false;
 191
 192         hdmi_runtime_put();
 193         regulator_disable(hdmi.vdda_reg);
 194 }
 195
 196 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
 197 {
 198         int r;
 199         struct omap_video_timings *p;
 200         struct omap_overlay_manager *mgr = hdmi.output.manager;
 201         unsigned long phy;
 202
 203         r = hdmi_power_on_core(dssdev);
 204         if (r)
 205                 return r;
 206
 207         p = &hdmi.cfg.timings;
 208
 209         DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
 210
 211         /* the functions below use kHz pixel clock. TODO: change to Hz */
 212         phy = p->pixelclock / 1000;
 213
 214         hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
 215
 216         /* disable and clear irqs */
 217         hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
 218         hdmi_wp_set_irqstatus(&hdmi.wp,
 219                         hdmi_wp_get_irqstatus(&hdmi.wp));
 220
 221         /* config the PLL and PHY hdmi_set_pll_pwrfirst */
 222         r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
 223         if (r) {
 224                 DSSDBG("Failed to lock PLL\n");
 225                 goto err_pll_enable;
 226         }
 227
 228         r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
 229         if (r) {
 230                 DSSDBG("Failed to start PHY\n");
 231                 goto err_phy_cfg;
 232         }
 233
 234         r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
 235         if (r)
 236                 goto err_phy_pwr;
 237
 238         hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
 239
 240         /* bypass TV gamma table */
 241         dispc_enable_gamma_table(0);
 242
 243         /* tv size */
 244         dss_mgr_set_timings(mgr, p);
 245
 246         r = hdmi_wp_video_start(&hdmi.wp);
 247         if (r)
 248                 goto err_vid_enable;
 249
 250         r = dss_mgr_enable(mgr);
 251         if (r)
 252                 goto err_mgr_enable;
 253
 254         hdmi_wp_set_irqenable(&hdmi.wp,
 255                         HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
 256
 257         return 0;
 258
 259 err_mgr_enable:
 260         hdmi_wp_video_stop(&hdmi.wp);
 261 err_vid_enable:
 262         hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
 263 err_phy_pwr:
 264 err_phy_cfg:
 265         hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
 266 err_pll_enable:
 267         hdmi_power_off_core(dssdev);
 268         return -EIO;
 269 }
 270
 271 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
 272 {
 273         struct omap_overlay_manager *mgr = hdmi.output.manager;
 274
 275         hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
 276
 277         dss_mgr_disable(mgr);
 278
 279         hdmi_wp_video_stop(&hdmi.wp);
 280
 281         hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
 282
 283         hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
 284
 285         hdmi_power_off_core(dssdev);
 286 }
 287
 288 static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
 289                                         struct omap_video_timings *timings)
 290 {
 291         struct omap_dss_device *out = &hdmi.output;
 292
 293         if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
 294                 return -EINVAL;
 295
 296         return 0;
 297 }
 298
 299 static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
 300                 struct omap_video_timings *timings)
 301 {
 302         struct hdmi_cm cm;
 303         const struct hdmi_config *t;
 304
 305         mutex_lock(&hdmi.lock);
 306
 307         cm = hdmi_get_code(timings);
 308         hdmi.cfg.cm = cm;
 309
 310         t = hdmi_get_timings(cm.mode, cm.code);
 311         if (t != NULL) {
 312                 hdmi.cfg = *t;
 313
 314                 dispc_set_tv_pclk(t->timings.pixelclock);
 315         } else {
 316                 hdmi.cfg.timings = *timings;
 317                 hdmi.cfg.cm.code = 0;
 318                 hdmi.cfg.cm.mode = HDMI_DVI;
 319
 320                 dispc_set_tv_pclk(timings->pixelclock);
 321         }
 322
 323         DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ?
 324                         "DVI" : "HDMI", hdmi.cfg.cm.code);
 325
 326         mutex_unlock(&hdmi.lock);
 327 }
 328
 329 static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
 330                 struct omap_video_timings *timings)
 331 {
 332         const struct hdmi_config *cfg;
 333         struct hdmi_cm cm = hdmi.cfg.cm;
 334
 335         cfg = hdmi_get_timings(cm.mode, cm.code);
 336         if (cfg == NULL)
 337                 cfg = hdmi_default_timing();
 338
 339         memcpy(timings, &cfg->timings, sizeof(cfg->timings));
 340 }
 341
 342 static void hdmi_dump_regs(struct seq_file *s)
 343 {
 344         mutex_lock(&hdmi.lock);
 345
 346         if (hdmi_runtime_get()) {
 347                 mutex_unlock(&hdmi.lock);
 348                 return;
 349         }
 350
 351         hdmi_wp_dump(&hdmi.wp, s);
 352         hdmi_pll_dump(&hdmi.pll, s);
 353         hdmi_phy_dump(&hdmi.phy, s);
 354         hdmi5_core_dump(&hdmi.core, s);
 355
 356         hdmi_runtime_put();
 357         mutex_unlock(&hdmi.lock);
 358 }
 359
 360 static int read_edid(u8 *buf, int len)
 361 {
 362         int r;
 363         int idlemode;
 364
 365         mutex_lock(&hdmi.lock);
 366
 367         r = hdmi_runtime_get();
 368         BUG_ON(r);
 369
 370         idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
 371         /* No-idle mode */
 372         REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
 373
 374         r = hdmi5_read_edid(&hdmi.core,  buf, len);
 375
 376         REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
 377
 378         hdmi_runtime_put();
 379         mutex_unlock(&hdmi.lock);
 380
 381         return r;
 382 }
 383
 384 static int hdmi_display_enable(struct omap_dss_device *dssdev)
 385 {
 386         struct omap_dss_device *out = &hdmi.output;
 387         int r = 0;
 388
 389         DSSDBG("ENTER hdmi_display_enable\n");
 390
 391         mutex_lock(&hdmi.lock);
 392
 393         if (out == NULL || out->manager == NULL) {
 394                 DSSERR("failed to enable display: no output/manager\n");
 395                 r = -ENODEV;
 396                 goto err0;
 397         }
 398
 399         r = hdmi_power_on_full(dssdev);
 400         if (r) {
 401                 DSSERR("failed to power on device\n");
 402                 goto err0;
 403         }
 404
 405         mutex_unlock(&hdmi.lock);
 406         return 0;
 407
 408 err0:
 409         mutex_unlock(&hdmi.lock);
 410         return r;
 411 }
 412
 413 static void hdmi_display_disable(struct omap_dss_device *dssdev)
 414 {
 415         DSSDBG("Enter hdmi_display_disable\n");
 416
 417         mutex_lock(&hdmi.lock);
 418
 419         hdmi_power_off_full(dssdev);
 420
 421         mutex_unlock(&hdmi.lock);
 422 }
 423
 424 static int hdmi_core_enable(struct omap_dss_device *dssdev)
 425 {
 426         int r = 0;
 427
 428         DSSDBG("ENTER omapdss_hdmi_core_enable\n");
 429
 430         mutex_lock(&hdmi.lock);
 431
 432         r = hdmi_power_on_core(dssdev);
 433         if (r) {
 434                 DSSERR("failed to power on device\n");
 435                 goto err0;
 436         }
 437
 438         mutex_unlock(&hdmi.lock);
 439         return 0;
 440
 441 err0:
 442         mutex_unlock(&hdmi.lock);
 443         return r;
 444 }
 445
 446 static void hdmi_core_disable(struct omap_dss_device *dssdev)
 447 {
 448         DSSDBG("Enter omapdss_hdmi_core_disable\n");
 449
 450         mutex_lock(&hdmi.lock);
 451
 452         hdmi_power_off_core(dssdev);
 453
 454         mutex_unlock(&hdmi.lock);
 455 }
 456
 457 static int hdmi_get_clocks(struct platform_device *pdev)
 458 {
 459         struct clk *clk;
 460
 461         clk = devm_clk_get(&pdev->dev, "sys_clk");
 462         if (IS_ERR(clk)) {
 463                 DSSERR("can't get sys_clk\n");
 464                 return PTR_ERR(clk);
 465         }
 466
 467         hdmi.sys_clk = clk;
 468
 469         return 0;
 470 }
 471
 472 static int hdmi_connect(struct omap_dss_device *dssdev,
 473                 struct omap_dss_device *dst)
 474 {
 475         struct omap_overlay_manager *mgr;
 476         int r;
 477
 478         r = hdmi_init_regulator();
 479         if (r)
 480                 return r;
 481
 482         mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
 483         if (!mgr)
 484                 return -ENODEV;
 485
 486         r = dss_mgr_connect(mgr, dssdev);
 487         if (r)
 488                 return r;
 489
 490         r = omapdss_output_set_device(dssdev, dst);
 491         if (r) {
 492                 DSSERR("failed to connect output to new device: %s\n",
 493                                 dst->name);
 494                 dss_mgr_disconnect(mgr, dssdev);
 495                 return r;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static void hdmi_disconnect(struct omap_dss_device *dssdev,
 502                 struct omap_dss_device *dst)
 503 {
 504         WARN_ON(dst != dssdev->dst);
 505
 506         if (dst != dssdev->dst)
 507                 return;
 508
 509         omapdss_output_unset_device(dssdev);
 510
 511         if (dssdev->manager)
 512                 dss_mgr_disconnect(dssdev->manager, dssdev);
 513 }
 514
 515 static int hdmi_read_edid(struct omap_dss_device *dssdev,
 516                 u8 *edid, int len)
 517 {
 518         bool need_enable;
 519         int r;
 520
 521         need_enable = hdmi.core_enabled == false;
 522
 523         if (need_enable) {
 524                 r = hdmi_core_enable(dssdev);
 525                 if (r)
 526                         return r;
 527         }
 528
 529         r = read_edid(edid, len);
 530
 531         if (need_enable)
 532                 hdmi_core_disable(dssdev);
 533
 534         return r;
 535 }
 536
 537 #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
 538 static int hdmi_audio_enable(struct omap_dss_device *dssdev)
 539 {
 540         int r;
 541
 542         mutex_lock(&hdmi.lock);
 543
 544         if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
 545                 r = -EPERM;
 546                 goto err;
 547         }
 548
 549         r = hdmi_wp_audio_enable(&hdmi.wp, true);
 550         if (r)
 551                 goto err;
 552
 553         mutex_unlock(&hdmi.lock);
 554         return 0;
 555
 556 err:
 557         mutex_unlock(&hdmi.lock);
 558         return r;
 559 }
 560
 561 static void hdmi_audio_disable(struct omap_dss_device *dssdev)
 562 {
 563         hdmi_wp_audio_enable(&hdmi.wp, false);
 564 }
 565
 566 static int hdmi_audio_start(struct omap_dss_device *dssdev)
 567 {
 568         return hdmi_wp_audio_core_req_enable(&hdmi.wp, true);
 569 }
 570
 571 static void hdmi_audio_stop(struct omap_dss_device *dssdev)
 572 {
 573         hdmi_wp_audio_core_req_enable(&hdmi.wp, false);
 574 }
 575
 576 static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
 577 {
 578         bool r;
 579
 580         mutex_lock(&hdmi.lock);
 581
 582         r = hdmi_mode_has_audio(hdmi.cfg.cm.mode);
 583
 584         mutex_unlock(&hdmi.lock);
 585         return r;
 586 }
 587
 588 static int hdmi_audio_config(struct omap_dss_device *dssdev,
 589                 struct omap_dss_audio *audio)
 590 {
 591         int r;
 592         u32 pclk = hdmi.cfg.timings.pixelclock;
 593
 594         mutex_lock(&hdmi.lock);
 595
 596         if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
 597                 r = -EPERM;
 598                 goto err;
 599         }
 600
 601         r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
 602         if (r)
 603                 goto err;
 604
 605         mutex_unlock(&hdmi.lock);
 606         return 0;
 607
 608 err:
 609         mutex_unlock(&hdmi.lock);
 610         return r;
 611 }
 612 #else
 613 static int hdmi_audio_enable(struct omap_dss_device *dssdev)
 614 {
 615         return -EPERM;
 616 }
 617
 618 static void hdmi_audio_disable(struct omap_dss_device *dssdev)
 619 {
 620 }
 621
 622 static int hdmi_audio_start(struct omap_dss_device *dssdev)
 623 {
 624         return -EPERM;
 625 }
 626
 627 static void hdmi_audio_stop(struct omap_dss_device *dssdev)
 628 {
 629 }
 630
 631 static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
 632 {
 633         return false;
 634 }
 635
 636 static int hdmi_audio_config(struct omap_dss_device *dssdev,
 637                 struct omap_dss_audio *audio)
 638 {
 639         return -EPERM;
 640 }
 641 #endif
 642
 643 static const struct omapdss_hdmi_ops hdmi_ops = {
 644         .connect                = hdmi_connect,
 645         .disconnect             = hdmi_disconnect,
 646
 647         .enable                 = hdmi_display_enable,
 648         .disable                = hdmi_display_disable,
 649
 650         .check_timings          = hdmi_display_check_timing,
 651         .set_timings            = hdmi_display_set_timing,
 652         .get_timings            = hdmi_display_get_timings,
 653
 654         .read_edid              = hdmi_read_edid,
 655
 656         .audio_enable           = hdmi_audio_enable,
 657         .audio_disable          = hdmi_audio_disable,
 658         .audio_start            = hdmi_audio_start,
 659         .audio_stop             = hdmi_audio_stop,
 660         .audio_supported        = hdmi_audio_supported,
 661         .audio_config           = hdmi_audio_config,
 662 };
 663
 664 static void hdmi_init_output(struct platform_device *pdev)
 665 {
 666         struct omap_dss_device *out = &hdmi.output;
 667
 668         out->dev = &pdev->dev;
 669         out->id = OMAP_DSS_OUTPUT_HDMI;
 670         out->output_type = OMAP_DISPLAY_TYPE_HDMI;
 671         out->name = "hdmi.0";
 672         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
 673         out->ops.hdmi = &hdmi_ops;
 674         out->owner = THIS_MODULE;
 675
 676         omapdss_register_output(out);
 677 }
 678
 679 static void __exit hdmi_uninit_output(struct platform_device *pdev)
 680 {
 681         struct omap_dss_device *out = &hdmi.output;
 682
 683         omapdss_unregister_output(out);
 684 }
 685
 686 static int hdmi_probe_of(struct platform_device *pdev)
 687 {
 688         struct device_node *node = pdev->dev.of_node;
 689         struct device_node *ep;
 690         int r;
 691
 692         ep = omapdss_of_get_first_endpoint(node);
 693         if (!ep)
 694                 return 0;
 695
 696         r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
 697         if (r)
 698                 goto err;
 699
 700         of_node_put(ep);
 701         return 0;
 702
 703 err:
 704         of_node_put(ep);
 705         return r;
 706 }
 707
 708 /* HDMI HW IP initialisation */
 709 static int omapdss_hdmihw_probe(struct platform_device *pdev)
 710 {
 711         int r;
 712         int irq;
 713
 714         hdmi.pdev = pdev;
 715
 716         mutex_init(&hdmi.lock);
 717
 718         if (pdev->dev.of_node) {
 719                 r = hdmi_probe_of(pdev);
 720                 if (r)
 721                         return r;
 722         }
 723
 724         r = hdmi_wp_init(pdev, &hdmi.wp);
 725         if (r)
 726                 return r;
 727
 728         r = hdmi_pll_init(pdev, &hdmi.pll);
 729         if (r)
 730                 return r;
 731
 732         r = hdmi_phy_init(pdev, &hdmi.phy);
 733         if (r)
 734                 return r;
 735
 736         r = hdmi5_core_init(pdev, &hdmi.core);
 737         if (r)
 738                 return r;
 739
 740         r = hdmi_get_clocks(pdev);
 741         if (r) {
 742                 DSSERR("can't get clocks\n");
 743                 return r;
 744         }
 745
 746         irq = platform_get_irq(pdev, 0);
 747         if (irq < 0) {
 748                 DSSERR("platform_get_irq failed\n");
 749                 return -ENODEV;
 750         }
 751
 752         r = devm_request_threaded_irq(&pdev->dev, irq,
 753                         NULL, hdmi_irq_handler,
 754                         IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
 755         if (r) {
 756                 DSSERR("HDMI IRQ request failed\n");
 757                 return r;
 758         }
 759
 760         pm_runtime_enable(&pdev->dev);
 761
 762         hdmi_init_output(pdev);
 763
 764         dss_debugfs_create_file("hdmi", hdmi_dump_regs);
 765
 766         return 0;
 767 }
 768
 769 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
 770 {
 771         hdmi_uninit_output(pdev);
 772
 773         pm_runtime_disable(&pdev->dev);
 774
 775         return 0;
 776 }
 777
 778 static int hdmi_runtime_suspend(struct device *dev)
 779 {
 780         clk_disable_unprepare(hdmi.sys_clk);
 781
 782         dispc_runtime_put();
 783
 784         return 0;
 785 }
 786
 787 static int hdmi_runtime_resume(struct device *dev)
 788 {
 789         int r;
 790
 791         r = dispc_runtime_get();
 792         if (r < 0)
 793                 return r;
 794
 795         clk_prepare_enable(hdmi.sys_clk);
 796
 797         return 0;
 798 }
 799
 800 static const struct dev_pm_ops hdmi_pm_ops = {
 801         .runtime_suspend = hdmi_runtime_suspend,
 802         .runtime_resume = hdmi_runtime_resume,
 803 };
 804
 805 static const struct of_device_id hdmi_of_match[] = {
 806         { .compatible = "ti,omap5-hdmi", },
 807         {},
 808 };
 809
 810 static struct platform_driver omapdss_hdmihw_driver = {
 811         .probe          = omapdss_hdmihw_probe,
 812         .remove         = __exit_p(omapdss_hdmihw_remove),
 813         .driver         = {
 814                 .name   = "omapdss_hdmi5",
 815                 .owner  = THIS_MODULE,
 816                 .pm     = &hdmi_pm_ops,
 817                 .of_match_table = hdmi_of_match,
 818         },
 819 };
 820
 821 int __init hdmi5_init_platform_driver(void)
 822 {
 823         return platform_driver_register(&omapdss_hdmihw_driver);
 824 }
 825
 826 void __exit hdmi5_uninit_platform_driver(void)
 827 {
 828         platform_driver_unregister(&omapdss_hdmihw_driver);
 829 }