drivers/video/fbdev/i740fb.c

   1 /*
   2  * i740fb - framebuffer driver for Intel740
   3  * Copyright (c) 2011 Ondrej Zary
   4  *
   5  * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru>
   6  * which was partially based on:
   7  *  VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org>
   8  *      and Petr Vandrovec <VANDROVE@vc.cvut.cz>
   9  *  i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
  10  *      Texas.
  11  *  i740fb by Patrick LERDA, v0.9
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/string.h>
  18 #include <linux/mm.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/fb.h>
  22 #include <linux/init.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci_ids.h>
  25 #include <linux/i2c.h>
  26 #include <linux/i2c-algo-bit.h>
  27 #include <linux/console.h>
  28 #include <video/vga.h>
  29
  30 #include "i740_reg.h"
  31
  32 static char *mode_option;
  33 static int mtrr = 1;
  34
  35 struct i740fb_par {
  36         unsigned char __iomem *regs;
  37         bool has_sgram;
  38         int wc_cookie;
  39         bool ddc_registered;
  40         struct i2c_adapter ddc_adapter;
  41         struct i2c_algo_bit_data ddc_algo;
  42         u32 pseudo_palette[16];
  43         struct mutex open_lock;
  44         unsigned int ref_count;
  45
  46         u8 crtc[VGA_CRT_C];
  47         u8 atc[VGA_ATT_C];
  48         u8 gdc[VGA_GFX_C];
  49         u8 seq[VGA_SEQ_C];
  50         u8 misc;
  51         u8 vss;
  52
  53         /* i740 specific registers */
  54         u8 display_cntl;
  55         u8 pixelpipe_cfg0;
  56         u8 pixelpipe_cfg1;
  57         u8 pixelpipe_cfg2;
  58         u8 video_clk2_m;
  59         u8 video_clk2_n;
  60         u8 video_clk2_mn_msbs;
  61         u8 video_clk2_div_sel;
  62         u8 pll_cntl;
  63         u8 address_mapping;
  64         u8 io_cntl;
  65         u8 bitblt_cntl;
  66         u8 ext_vert_total;
  67         u8 ext_vert_disp_end;
  68         u8 ext_vert_sync_start;
  69         u8 ext_vert_blank_start;
  70         u8 ext_horiz_total;
  71         u8 ext_horiz_blank;
  72         u8 ext_offset;
  73         u8 interlace_cntl;
  74         u32 lmi_fifo_watermark;
  75         u8 ext_start_addr;
  76         u8 ext_start_addr_hi;
  77 };
  78
  79 #define DACSPEED8       203
  80 #define DACSPEED16      163
  81 #define DACSPEED24_SG   136
  82 #define DACSPEED24_SD   128
  83 #define DACSPEED32      86
  84
  85 static const struct fb_fix_screeninfo i740fb_fix = {
  86         .id =           "i740fb",
  87         .type =         FB_TYPE_PACKED_PIXELS,
  88         .visual =       FB_VISUAL_TRUECOLOR,
  89         .xpanstep =     8,
  90         .ypanstep =     1,
  91         .accel =        FB_ACCEL_NONE,
  92 };
  93
  94 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
  95 {
  96         vga_mm_w(par->regs, port, val);
  97 }
  98 static inline u8 i740inb(struct i740fb_par *par, u16 port)
  99 {
 100         return vga_mm_r(par->regs, port);
 101 }
 102 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
 103 {
 104         vga_mm_w_fast(par->regs, port, reg, val);
 105 }
 106 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
 107 {
 108         vga_mm_w(par->regs, port, reg);
 109         return vga_mm_r(par->regs, port+1);
 110 }
 111 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
 112                                    u8 val, u8 mask)
 113 {
 114         vga_mm_w_fast(par->regs, port, reg, (val & mask)
 115                 | (i740inreg(par, port, reg) & ~mask));
 116 }
 117
 118 #define REG_DDC_DRIVE   0x62
 119 #define REG_DDC_STATE   0x63
 120 #define DDC_SCL         (1 << 3)
 121 #define DDC_SDA         (1 << 2)
 122
 123 static void i740fb_ddc_setscl(void *data, int val)
 124 {
 125         struct i740fb_par *par = data;
 126
 127         i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
 128         i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
 129 }
 130
 131 static void i740fb_ddc_setsda(void *data, int val)
 132 {
 133         struct i740fb_par *par = data;
 134
 135         i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
 136         i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
 137 }
 138
 139 static int i740fb_ddc_getscl(void *data)
 140 {
 141         struct i740fb_par *par = data;
 142
 143         i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
 144
 145         return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
 146 }
 147
 148 static int i740fb_ddc_getsda(void *data)
 149 {
 150         struct i740fb_par *par = data;
 151
 152         i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
 153
 154         return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
 155 }
 156
 157 static int i740fb_setup_ddc_bus(struct fb_info *info)
 158 {
 159         struct i740fb_par *par = info->par;
 160
 161         strlcpy(par->ddc_adapter.name, info->fix.id,
 162                 sizeof(par->ddc_adapter.name));
 163         par->ddc_adapter.owner          = THIS_MODULE;
 164         par->ddc_adapter.class          = I2C_CLASS_DDC;
 165         par->ddc_adapter.algo_data      = &par->ddc_algo;
 166         par->ddc_adapter.dev.parent     = info->device;
 167         par->ddc_algo.setsda            = i740fb_ddc_setsda;
 168         par->ddc_algo.setscl            = i740fb_ddc_setscl;
 169         par->ddc_algo.getsda            = i740fb_ddc_getsda;
 170         par->ddc_algo.getscl            = i740fb_ddc_getscl;
 171         par->ddc_algo.udelay            = 10;
 172         par->ddc_algo.timeout           = 20;
 173         par->ddc_algo.data              = par;
 174
 175         i2c_set_adapdata(&par->ddc_adapter, par);
 176
 177         return i2c_bit_add_bus(&par->ddc_adapter);
 178 }
 179
 180 static int i740fb_open(struct fb_info *info, int user)
 181 {
 182         struct i740fb_par *par = info->par;
 183
 184         mutex_lock(&(par->open_lock));
 185         par->ref_count++;
 186         mutex_unlock(&(par->open_lock));
 187
 188         return 0;
 189 }
 190
 191 static int i740fb_release(struct fb_info *info, int user)
 192 {
 193         struct i740fb_par *par = info->par;
 194
 195         mutex_lock(&(par->open_lock));
 196         if (par->ref_count == 0) {
 197                 fb_err(info, "release called with zero refcount\n");
 198                 mutex_unlock(&(par->open_lock));
 199                 return -EINVAL;
 200         }
 201
 202         par->ref_count--;
 203         mutex_unlock(&(par->open_lock));
 204
 205         return 0;
 206 }
 207
 208 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
 209 {
 210         /*
 211          * Would like to calculate these values automatically, but a generic
 212          * algorithm does not seem possible.  Note: These FIFO water mark
 213          * values were tested on several cards and seem to eliminate the
 214          * all of the snow and vertical banding, but fine adjustments will
 215          * probably be required for other cards.
 216          */
 217
 218         u32 wm;
 219
 220         switch (bpp) {
 221         case 8:
 222                 if      (freq > 200)
 223                         wm = 0x18120000;
 224                 else if (freq > 175)
 225                         wm = 0x16110000;
 226                 else if (freq > 135)
 227                         wm = 0x120E0000;
 228                 else
 229                         wm = 0x100D0000;
 230                 break;
 231         case 15:
 232         case 16:
 233                 if (par->has_sgram) {
 234                         if      (freq > 140)
 235                                 wm = 0x2C1D0000;
 236                         else if (freq > 120)
 237                                 wm = 0x2C180000;
 238                         else if (freq > 100)
 239                                 wm = 0x24160000;
 240                         else if (freq >  90)
 241                                 wm = 0x18120000;
 242                         else if (freq >  50)
 243                                 wm = 0x16110000;
 244                         else if (freq >  32)
 245                                 wm = 0x13100000;
 246                         else
 247                                 wm = 0x120E0000;
 248                 } else {
 249                         if      (freq > 160)
 250                                 wm = 0x28200000;
 251                         else if (freq > 140)
 252                                 wm = 0x2A1E0000;
 253                         else if (freq > 130)
 254                                 wm = 0x2B1A0000;
 255                         else if (freq > 120)
 256                                 wm = 0x2C180000;
 257                         else if (freq > 100)
 258                                 wm = 0x24180000;
 259                         else if (freq >  90)
 260                                 wm = 0x18120000;
 261                         else if (freq >  50)
 262                                 wm = 0x16110000;
 263                         else if (freq >  32)
 264                                 wm = 0x13100000;
 265                         else
 266                                 wm = 0x120E0000;
 267                 }
 268                 break;
 269         case 24:
 270                 if (par->has_sgram) {
 271                         if      (freq > 130)
 272                                 wm = 0x31200000;
 273                         else if (freq > 120)
 274                                 wm = 0x2E200000;
 275                         else if (freq > 100)
 276                                 wm = 0x2C1D0000;
 277                         else if (freq >  80)
 278                                 wm = 0x25180000;
 279                         else if (freq >  64)
 280                                 wm = 0x24160000;
 281                         else if (freq >  49)
 282                                 wm = 0x18120000;
 283                         else if (freq >  32)
 284                                 wm = 0x16110000;
 285                         else
 286                                 wm = 0x13100000;
 287                 } else {
 288                         if      (freq > 120)
 289                                 wm = 0x311F0000;
 290                         else if (freq > 100)
 291                                 wm = 0x2C1D0000;
 292                         else if (freq >  80)
 293                                 wm = 0x25180000;
 294                         else if (freq >  64)
 295                                 wm = 0x24160000;
 296                         else if (freq >  49)
 297                                 wm = 0x18120000;
 298                         else if (freq >  32)
 299                                 wm = 0x16110000;
 300                         else
 301                                 wm = 0x13100000;
 302                 }
 303                 break;
 304         case 32:
 305                 if (par->has_sgram) {
 306                         if      (freq >  80)
 307                                 wm = 0x2A200000;
 308                         else if (freq >  60)
 309                                 wm = 0x281A0000;
 310                         else if (freq >  49)
 311                                 wm = 0x25180000;
 312                         else if (freq >  32)
 313                                 wm = 0x18120000;
 314                         else
 315                                 wm = 0x16110000;
 316                 } else {
 317                         if      (freq >  80)
 318                                 wm = 0x29200000;
 319                         else if (freq >  60)
 320                                 wm = 0x281A0000;
 321                         else if (freq >  49)
 322                                 wm = 0x25180000;
 323                         else if (freq >  32)
 324                                 wm = 0x18120000;
 325                         else
 326                                 wm = 0x16110000;
 327                 }
 328                 break;
 329         }
 330
 331         return wm;
 332 }
 333
 334 /* clock calculation from i740fb by Patrick LERDA */
 335
 336 #define I740_RFREQ              1000000
 337 #define TARGET_MAX_N            30
 338 #define I740_FFIX               (1 << 8)
 339 #define I740_RFREQ_FIX          (I740_RFREQ / I740_FFIX)
 340 #define I740_REF_FREQ           (6667 * I740_FFIX / 100)        /* 66.67 MHz */
 341 #define I740_MAX_VCO_FREQ       (450 * I740_FFIX)               /* 450 MHz */
 342
 343 static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
 344 {
 345         const u32 err_max    = freq / (200  * I740_RFREQ / I740_FFIX);
 346         const u32 err_target = freq / (1000 * I740_RFREQ / I740_FFIX);
 347         u32 err_best = 512 * I740_FFIX;
 348         u32 f_err, f_vco;
 349         int m_best = 0, n_best = 0, p_best = 0;
 350         int m, n;
 351
 352         p_best = min(15, ilog2(I740_MAX_VCO_FREQ / (freq / I740_RFREQ_FIX)));
 353         f_vco = (freq * (1 << p_best)) / I740_RFREQ_FIX;
 354         freq = freq / I740_RFREQ_FIX;
 355
 356         n = 2;
 357         do {
 358                 n++;
 359                 m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
 360
 361                 if (m < 3)
 362                         m = 3;
 363
 364                 {
 365                         u32 f_out = (((m * I740_REF_FREQ * 4)
 366                                  / n) + ((1 << p_best) / 2)) / (1 << p_best);
 367
 368                         f_err = (freq - f_out);
 369
 370                         if (abs(f_err) < err_max) {
 371                                 m_best = m;
 372                                 n_best = n;
 373                                 err_best = f_err;
 374                         }
 375                 }
 376         } while ((abs(f_err) >= err_target) &&
 377                  ((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
 378
 379         if (abs(f_err) < err_target) {
 380                 m_best = m;
 381                 n_best = n;
 382         }
 383
 384         par->video_clk2_m = (m_best - 2) & 0xFF;
 385         par->video_clk2_n = (n_best - 2) & 0xFF;
 386         par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
 387                                  | (((m_best - 2) >> 8) & VCO_M_MSBS));
 388         par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1);
 389 }
 390
 391 static int i740fb_decode_var(const struct fb_var_screeninfo *var,
 392                              struct i740fb_par *par, struct fb_info *info)
 393 {
 394         /*
 395          * Get the video params out of 'var'.
 396          * If a value doesn't fit, round it up, if it's too big, return -EINVAL.
 397          */
 398
 399         u32 xres, right, hslen, left, xtotal;
 400         u32 yres, lower, vslen, upper, ytotal;
 401         u32 vxres, xoffset, vyres, yoffset;
 402         u32 bpp, base, dacspeed24, mem;
 403         u8 r7;
 404         int i;
 405
 406         dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
 407                   var->xres, var->yres, var->xres_virtual, var->xres_virtual);
 408         dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
 409                   var->xoffset, var->yoffset, var->bits_per_pixel,
 410                   var->grayscale);
 411         dev_dbg(info->device, " activate: %i, nonstd: %i, vmode: %i\n",
 412                   var->activate, var->nonstd, var->vmode);
 413         dev_dbg(info->device, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
 414                   var->pixclock, var->hsync_len, var->vsync_len);
 415         dev_dbg(info->device, " left: %i, right: %i, up:%i, lower:%i\n",
 416                   var->left_margin, var->right_margin, var->upper_margin,
 417                   var->lower_margin);
 418
 419
 420         bpp = var->bits_per_pixel;
 421         switch (bpp) {
 422         case 1 ... 8:
 423                 bpp = 8;
 424                 if ((1000000 / var->pixclock) > DACSPEED8) {
 425                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
 426                                 1000000 / var->pixclock, DACSPEED8);
 427                         return -EINVAL;
 428                 }
 429                 break;
 430         case 9 ... 15:
 431                 bpp = 15;
 432                 /* fall through */
 433         case 16:
 434                 if ((1000000 / var->pixclock) > DACSPEED16) {
 435                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
 436                                 1000000 / var->pixclock, DACSPEED16);
 437                         return -EINVAL;
 438                 }
 439                 break;
 440         case 17 ... 24:
 441                 bpp = 24;
 442                 dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
 443                 if ((1000000 / var->pixclock) > dacspeed24) {
 444                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
 445                                 1000000 / var->pixclock, dacspeed24);
 446                         return -EINVAL;
 447                 }
 448                 break;
 449         case 25 ... 32:
 450                 bpp = 32;
 451                 if ((1000000 / var->pixclock) > DACSPEED32) {
 452                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
 453                                 1000000 / var->pixclock, DACSPEED32);
 454                         return -EINVAL;
 455                 }
 456                 break;
 457         default:
 458                 return -EINVAL;
 459         }
 460
 461         xres = ALIGN(var->xres, 8);
 462         vxres = ALIGN(var->xres_virtual, 16);
 463         if (vxres < xres)
 464                 vxres = xres;
 465
 466         xoffset = ALIGN(var->xoffset, 8);
 467         if (xres + xoffset > vxres)
 468                 xoffset = vxres - xres;
 469
 470         left = ALIGN(var->left_margin, 8);
 471         right = ALIGN(var->right_margin, 8);
 472         hslen = ALIGN(var->hsync_len, 8);
 473
 474         yres = var->yres;
 475         vyres = var->yres_virtual;
 476         if (yres > vyres)
 477                 vyres = yres;
 478
 479         yoffset = var->yoffset;
 480         if (yres + yoffset > vyres)
 481                 yoffset = vyres - yres;
 482
 483         lower = var->lower_margin;
 484         vslen = var->vsync_len;
 485         upper = var->upper_margin;
 486
 487         mem = vxres * vyres * ((bpp + 1) / 8);
 488         if (mem > info->screen_size) {
 489                 dev_err(info->device, "not enough video memory (%d KB requested, %ld KB available)\n",
 490                         mem >> 10, info->screen_size >> 10);
 491                 return -ENOMEM;
 492         }
 493
 494         if (yoffset + yres > vyres)
 495                 yoffset = vyres - yres;
 496
 497         xtotal = xres + right + hslen + left;
 498         ytotal = yres + lower + vslen + upper;
 499
 500         par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
 501         par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
 502         par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
 503         par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
 504         par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
 505                 | ((((xres + right + hslen) >> 3) & 0x20) << 2);
 506         par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
 507                 | 0x80;
 508
 509         par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
 510
 511         r7 = 0x10;      /* disable linecompare */
 512         if (ytotal & 0x100)
 513                 r7 |= 0x01;
 514         if (ytotal & 0x200)
 515                 r7 |= 0x20;
 516
 517         par->crtc[VGA_CRTC_PRESET_ROW] = 0;
 518         par->crtc[VGA_CRTC_MAX_SCAN] = 0x40;    /* 1 scanline, no linecmp */
 519         if (var->vmode & FB_VMODE_DOUBLE)
 520                 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
 521         par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
 522         par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
 523         par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
 524         par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
 525         par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
 526         if ((yres-1) & 0x100)
 527                 r7 |= 0x02;
 528         if ((yres-1) & 0x200)
 529                 r7 |= 0x40;
 530
 531         par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
 532         par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
 533         if ((yres + lower - 1) & 0x100)
 534                 r7 |= 0x0C;
 535         if ((yres + lower - 1) & 0x200) {
 536                 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
 537                 r7 |= 0x80;
 538         }
 539
 540         /* disabled IRQ */
 541         par->crtc[VGA_CRTC_V_SYNC_END] =
 542                 ((yres + lower - 1 + vslen) & 0x0F) & ~0x10;
 543         /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
 544         par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
 545
 546         par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
 547         par->crtc[VGA_CRTC_MODE] = 0xC3 ;
 548         par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
 549         par->crtc[VGA_CRTC_OVERFLOW] = r7;
 550
 551         par->vss = 0x00;        /* 3DA */
 552
 553         for (i = 0x00; i < 0x10; i++)
 554                 par->atc[i] = i;
 555         par->atc[VGA_ATC_MODE] = 0x81;
 556         par->atc[VGA_ATC_OVERSCAN] = 0x00;      /* 0 for EGA, 0xFF for VGA */
 557         par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
 558         par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
 559
 560         par->misc = 0xC3;
 561         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 562                 par->misc &= ~0x40;
 563         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 564                 par->misc &= ~0x80;
 565
 566         par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
 567         par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
 568         par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
 569         par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
 570
 571         par->gdc[VGA_GFX_SR_VALUE] = 0x00;
 572         par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
 573         par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
 574         par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
 575         par->gdc[VGA_GFX_PLANE_READ] = 0;
 576         par->gdc[VGA_GFX_MODE] = 0x02;
 577         par->gdc[VGA_GFX_MISC] = 0x05;
 578         par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
 579         par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
 580
 581         base = (yoffset * vxres + (xoffset & ~7)) >> 2;
 582         switch (bpp) {
 583         case 8:
 584                 par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
 585                 par->ext_offset = vxres >> 11;
 586                 par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
 587                 par->bitblt_cntl = COLEXP_8BPP;
 588                 break;
 589         case 15: /* 0rrrrrgg gggbbbbb */
 590         case 16: /* rrrrrggg gggbbbbb */
 591                 par->pixelpipe_cfg1 = (var->green.length == 6) ?
 592                         DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
 593                 par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
 594                 par->ext_offset = vxres >> 10;
 595                 par->bitblt_cntl = COLEXP_16BPP;
 596                 base *= 2;
 597                 break;
 598         case 24:
 599                 par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
 600                 par->ext_offset = (vxres * 3) >> 11;
 601                 par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
 602                 par->bitblt_cntl = COLEXP_24BPP;
 603                 base &= 0xFFFFFFFE; /* ...ignore the last bit. */
 604                 base *= 3;
 605                 break;
 606         case 32:
 607                 par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
 608                 par->ext_offset = vxres >> 9;
 609                 par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
 610                 par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
 611                 base *= 4;
 612                 break;
 613         }
 614
 615         par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
 616         par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
 617         par->ext_start_addr =
 618                 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
 619         par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
 620
 621         par->pixelpipe_cfg0 = DAC_8_BIT;
 622
 623         par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
 624         par->io_cntl = EXTENDED_CRTC_CNTL;
 625         par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
 626         par->display_cntl = HIRES_MODE;
 627
 628         /* Set the MCLK freq */
 629         par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
 630
 631         /* Calculate the extended CRTC regs */
 632         par->ext_vert_total = (ytotal - 2) >> 8;
 633         par->ext_vert_disp_end = (yres - 1) >> 8;
 634         par->ext_vert_sync_start = (yres + lower) >> 8;
 635         par->ext_vert_blank_start = (yres + lower) >> 8;
 636         par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
 637         par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
 638
 639         par->interlace_cntl = INTERLACE_DISABLE;
 640
 641         /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
 642         par->atc[VGA_ATC_OVERSCAN] = 0;
 643
 644         /* Calculate VCLK that most closely matches the requested dot clock */
 645         i740_calc_vclk((((u32)1e9) / var->pixclock) * (u32)(1e3), par);
 646
 647         /* Since we program the clocks ourselves, always use VCLK2. */
 648         par->misc |= 0x0C;
 649
 650         /* Calculate the FIFO Watermark and Burst Length. */
 651         par->lmi_fifo_watermark =
 652                 i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
 653
 654         return 0;
 655 }
 656
 657 static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 658 {
 659         switch (var->bits_per_pixel) {
 660         case 8:
 661                 var->red.offset = var->green.offset = var->blue.offset = 0;
 662                 var->red.length = var->green.length = var->blue.length = 8;
 663                 break;
 664         case 16:
 665                 switch (var->green.length) {
 666                 default:
 667                 case 5:
 668                         var->red.offset = 10;
 669                         var->green.offset = 5;
 670                         var->blue.offset = 0;
 671                         var->red.length = 5;
 672                         var->green.length = 5;
 673                         var->blue.length = 5;
 674                         break;
 675                 case 6:
 676                         var->red.offset = 11;
 677                         var->green.offset = 5;
 678                         var->blue.offset = 0;
 679                         var->red.length = var->blue.length = 5;
 680                         break;
 681                 }
 682                 break;
 683         case 24:
 684                 var->red.offset = 16;
 685                 var->green.offset = 8;
 686                 var->blue.offset = 0;
 687                 var->red.length = var->green.length = var->blue.length = 8;
 688                 break;
 689         case 32:
 690                 var->transp.offset = 24;
 691                 var->red.offset = 16;
 692                 var->green.offset = 8;
 693                 var->blue.offset = 0;
 694                 var->transp.length = 8;
 695                 var->red.length = var->green.length = var->blue.length = 8;
 696                 break;
 697         default:
 698                 return -EINVAL;
 699         }
 700
 701         if (var->xres > var->xres_virtual)
 702                 var->xres_virtual = var->xres;
 703
 704         if (var->yres > var->yres_virtual)
 705                 var->yres_virtual = var->yres;
 706
 707         if (info->monspecs.hfmax && info->monspecs.vfmax &&
 708             info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
 709                 return -EINVAL;
 710
 711         return 0;
 712 }
 713
 714 static void vga_protect(struct i740fb_par *par)
 715 {
 716         /* disable the display */
 717         i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
 718
 719         i740inb(par, 0x3DA);
 720         i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */
 721 }
 722
 723 static void vga_unprotect(struct i740fb_par *par)
 724 {
 725         /* reenable display */
 726         i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
 727
 728         i740inb(par, 0x3DA);
 729         i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */
 730 }
 731
 732 static int i740fb_set_par(struct fb_info *info)
 733 {
 734         struct i740fb_par *par = info->par;
 735         u32 itemp;
 736         int i;
 737
 738         i = i740fb_decode_var(&info->var, par, info);
 739         if (i)
 740                 return i;
 741
 742         memset(info->screen_base, 0, info->screen_size);
 743
 744         vga_protect(par);
 745
 746         i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
 747
 748         mdelay(1);
 749
 750         i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
 751         i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
 752         i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
 753         i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
 754
 755         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
 756                         par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
 757
 758         i740inb(par, 0x3DA);
 759         i740outb(par, 0x3C0, 0x00);
 760
 761         /* update misc output register */
 762         i740outb(par, VGA_MIS_W, par->misc | 0x01);
 763
 764         /* synchronous reset on */
 765         i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
 766         /* write sequencer registers */
 767         i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
 768                         par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
 769         for (i = 2; i < VGA_SEQ_C; i++)
 770                 i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
 771
 772         /* synchronous reset off */
 773         i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
 774
 775         /* deprotect CRT registers 0-7 */
 776         i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
 777                         par->crtc[VGA_CRTC_V_SYNC_END]);
 778
 779         /* write CRT registers */
 780         for (i = 0; i < VGA_CRT_C; i++)
 781                 i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
 782
 783         /* write graphics controller registers */
 784         for (i = 0; i < VGA_GFX_C; i++)
 785                 i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
 786
 787         /* write attribute controller registers */
 788         for (i = 0; i < VGA_ATT_C; i++) {
 789                 i740inb(par, VGA_IS1_RC);               /* reset flip-flop */
 790                 i740outb(par, VGA_ATT_IW, i);
 791                 i740outb(par, VGA_ATT_IW, par->atc[i]);
 792         }
 793
 794         i740inb(par, VGA_IS1_RC);
 795         i740outb(par, VGA_ATT_IW, 0x20);
 796
 797         i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
 798         i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
 799         i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
 800                         par->ext_vert_sync_start);
 801         i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
 802                         par->ext_vert_blank_start);
 803         i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
 804         i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
 805         i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
 806         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
 807         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
 808
 809         i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
 810                         par->interlace_cntl, INTERLACE_ENABLE);
 811         i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
 812         i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
 813         i740outreg_mask(par, XRX, DISPLAY_CNTL,
 814                         par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
 815         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
 816         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
 817
 818         i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
 819
 820         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
 821                         par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
 822
 823         itemp = readl(par->regs + FWATER_BLC);
 824         itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
 825         itemp |= par->lmi_fifo_watermark;
 826         writel(itemp, par->regs + FWATER_BLC);
 827
 828         i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
 829
 830         i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
 831         i740outreg_mask(par, XRX, IO_CTNL,
 832                         par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
 833
 834         if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
 835                 i740outb(par, VGA_PEL_MSK, 0xFF);
 836                 i740outb(par, VGA_PEL_IW, 0x00);
 837                 for (i = 0; i < 256; i++) {
 838                         itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
 839                         i740outb(par, VGA_PEL_D, itemp);
 840                         i740outb(par, VGA_PEL_D, itemp);
 841                         i740outb(par, VGA_PEL_D, itemp);
 842                 }
 843         }
 844
 845         /* Wait for screen to stabilize. */
 846         mdelay(50);
 847         vga_unprotect(par);
 848
 849         info->fix.line_length =
 850                         info->var.xres_virtual * info->var.bits_per_pixel / 8;
 851         if (info->var.bits_per_pixel == 8)
 852                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 853         else
 854                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 855
 856         return 0;
 857 }
 858
 859 static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 860                            unsigned blue, unsigned transp,
 861                            struct fb_info *info)
 862 {
 863         u32 r, g, b;
 864
 865         dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
 866                 regno, red, green, blue, transp, info->var.bits_per_pixel);
 867
 868         switch (info->fix.visual) {
 869         case FB_VISUAL_PSEUDOCOLOR:
 870                 if (regno >= 256)
 871                         return -EINVAL;
 872                 i740outb(info->par, VGA_PEL_IW, regno);
 873                 i740outb(info->par, VGA_PEL_D, red >> 8);
 874                 i740outb(info->par, VGA_PEL_D, green >> 8);
 875                 i740outb(info->par, VGA_PEL_D, blue >> 8);
 876                 break;
 877         case FB_VISUAL_TRUECOLOR:
 878                 if (regno >= 16)
 879                         return -EINVAL;
 880                 r = (red >> (16 - info->var.red.length))
 881                         << info->var.red.offset;
 882                 b = (blue >> (16 - info->var.blue.length))
 883                         << info->var.blue.offset;
 884                 g = (green >> (16 - info->var.green.length))
 885                         << info->var.green.offset;
 886                 ((u32 *) info->pseudo_palette)[regno] = r | g | b;
 887                 break;
 888         default:
 889                 return -EINVAL;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int i740fb_pan_display(struct fb_var_screeninfo *var,
 896                                  struct fb_info *info)
 897 {
 898         struct i740fb_par *par = info->par;
 899         u32 base = (var->yoffset * info->var.xres_virtual
 900                  + (var->xoffset & ~7)) >> 2;
 901
 902         dev_dbg(info->device, "pan_display: xoffset: %i yoffset: %i base: %i\n",
 903                 var->xoffset, var->yoffset, base);
 904
 905         switch (info->var.bits_per_pixel) {
 906         case 8:
 907                 break;
 908         case 15:
 909         case 16:
 910                 base *= 2;
 911                 break;
 912         case 24:
 913                 /*
 914                  * The last bit does not seem to have any effect on the start
 915                  * address register in 24bpp mode, so...
 916                  */
 917                 base &= 0xFFFFFFFE; /* ...ignore the last bit. */
 918                 base *= 3;
 919                 break;
 920         case 32:
 921                 base *= 4;
 922                 break;
 923         }
 924
 925         par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
 926         par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
 927         par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
 928         par->ext_start_addr =
 929                         ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
 930
 931         i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO,  base & 0x000000FF);
 932         i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
 933                         (base & 0x0000FF00) >> 8);
 934         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
 935                         (base & 0x3FC00000) >> 22);
 936         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
 937                         ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
 938
 939         return 0;
 940 }
 941
 942 static int i740fb_blank(int blank_mode, struct fb_info *info)
 943 {
 944         struct i740fb_par *par = info->par;
 945
 946         unsigned char SEQ01;
 947         int DPMSSyncSelect;
 948
 949         switch (blank_mode) {
 950         case FB_BLANK_UNBLANK:
 951         case FB_BLANK_NORMAL:
 952                 SEQ01 = 0x00;
 953                 DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
 954                 break;
 955         case FB_BLANK_VSYNC_SUSPEND:
 956                 SEQ01 = 0x20;
 957                 DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
 958                 break;
 959         case FB_BLANK_HSYNC_SUSPEND:
 960                 SEQ01 = 0x20;
 961                 DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
 962                 break;
 963         case FB_BLANK_POWERDOWN:
 964                 SEQ01 = 0x20;
 965                 DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
 966                 break;
 967         default:
 968                 return -EINVAL;
 969         }
 970         /* Turn the screen on/off */
 971         i740outb(par, SRX, 0x01);
 972         SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
 973         i740outb(par, SRX, 0x01);
 974         i740outb(par, SRX + 1, SEQ01);
 975
 976         /* Set the DPMS mode */
 977         i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
 978
 979         /* Let fbcon do a soft blank for us */
 980         return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
 981 }
 982
 983 static struct fb_ops i740fb_ops = {
 984         .owner          = THIS_MODULE,
 985         .fb_open        = i740fb_open,
 986         .fb_release     = i740fb_release,
 987         .fb_check_var   = i740fb_check_var,
 988         .fb_set_par     = i740fb_set_par,
 989         .fb_setcolreg   = i740fb_setcolreg,
 990         .fb_blank       = i740fb_blank,
 991         .fb_pan_display = i740fb_pan_display,
 992         .fb_fillrect    = cfb_fillrect,
 993         .fb_copyarea    = cfb_copyarea,
 994         .fb_imageblit   = cfb_imageblit,
 995 };
 996
 997 /* ------------------------------------------------------------------------- */
 998
 999 static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1000 {
1001         struct fb_info *info;
1002         struct i740fb_par *par;
1003         int ret, tmp;
1004         bool found = false;
1005         u8 *edid;
1006
1007         info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
1008         if (!info) {
1009                 dev_err(&(dev->dev), "cannot allocate framebuffer\n");
1010                 return -ENOMEM;
1011         }
1012
1013         par = info->par;
1014         mutex_init(&par->open_lock);
1015
1016         info->var.activate = FB_ACTIVATE_NOW;
1017         info->var.bits_per_pixel = 8;
1018         info->fbops = &i740fb_ops;
1019         info->pseudo_palette = par->pseudo_palette;
1020
1021         ret = pci_enable_device(dev);
1022         if (ret) {
1023                 dev_err(info->device, "cannot enable PCI device\n");
1024                 goto err_enable_device;
1025         }
1026
1027         ret = pci_request_regions(dev, info->fix.id);
1028         if (ret) {
1029                 dev_err(info->device, "error requesting regions\n");
1030                 goto err_request_regions;
1031         }
1032
1033         info->screen_base = pci_ioremap_wc_bar(dev, 0);
1034         if (!info->screen_base) {
1035                 dev_err(info->device, "error remapping base\n");
1036                 ret = -ENOMEM;
1037                 goto err_ioremap_1;
1038         }
1039
1040         par->regs = pci_ioremap_bar(dev, 1);
1041         if (!par->regs) {
1042                 dev_err(info->device, "error remapping MMIO\n");
1043                 ret = -ENOMEM;
1044                 goto err_ioremap_2;
1045         }
1046
1047         /* detect memory size */
1048         if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1049                                                         == DRAM_ROW_1_SDRAM)
1050                 i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1051         else
1052                 i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1053         info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1054         /* detect memory type */
1055         tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
1056         par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
1057                            (tmp & DRAM_RAS_PRECHARGE));
1058
1059         fb_info(info, "Intel740 on %s, %ld KB %s\n",
1060                 pci_name(dev), info->screen_size >> 10,
1061                 par->has_sgram ? "SGRAM" : "SDRAM");
1062
1063         info->fix = i740fb_fix;
1064         info->fix.mmio_start = pci_resource_start(dev, 1);
1065         info->fix.mmio_len = pci_resource_len(dev, 1);
1066         info->fix.smem_start = pci_resource_start(dev, 0);
1067         info->fix.smem_len = info->screen_size;
1068         info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1069
1070         if (i740fb_setup_ddc_bus(info) == 0) {
1071                 par->ddc_registered = true;
1072                 edid = fb_ddc_read(&par->ddc_adapter);
1073                 if (edid) {
1074                         fb_edid_to_monspecs(edid, &info->monspecs);
1075                         kfree(edid);
1076                         if (!info->monspecs.modedb)
1077                                 dev_err(info->device,
1078                                         "error getting mode database\n");
1079                         else {
1080                                 const struct fb_videomode *m;
1081
1082                                 fb_videomode_to_modelist(
1083                                         info->monspecs.modedb,
1084                                         info->monspecs.modedb_len,
1085                                         &info->modelist);
1086                                 m = fb_find_best_display(&info->monspecs,
1087                                                          &info->modelist);
1088                                 if (m) {
1089                                         fb_videomode_to_var(&info->var, m);
1090                                         /* fill all other info->var's fields */
1091                                         if (!i740fb_check_var(&info->var, info))
1092                                                 found = true;
1093                                 }
1094                         }
1095                 }
1096         }
1097
1098         if (!mode_option && !found)
1099                 mode_option = "640x480-8@60";
1100
1101         if (mode_option) {
1102                 ret = fb_find_mode(&info->var, info, mode_option,
1103                                    info->monspecs.modedb,
1104                                    info->monspecs.modedb_len,
1105                                    NULL, info->var.bits_per_pixel);
1106                 if (!ret || ret == 4) {
1107                         dev_err(info->device, "mode %s not found\n",
1108                                 mode_option);
1109                         ret = -EINVAL;
1110                 }
1111         }
1112
1113         fb_destroy_modedb(info->monspecs.modedb);
1114         info->monspecs.modedb = NULL;
1115
1116         /* maximize virtual vertical size for fast scrolling */
1117         info->var.yres_virtual = info->fix.smem_len * 8 /
1118                         (info->var.bits_per_pixel * info->var.xres_virtual);
1119
1120         if (ret == -EINVAL)
1121                 goto err_find_mode;
1122
1123         ret = fb_alloc_cmap(&info->cmap, 256, 0);
1124         if (ret) {
1125                 dev_err(info->device, "cannot allocate colormap\n");
1126                 goto err_alloc_cmap;
1127         }
1128
1129         ret = register_framebuffer(info);
1130         if (ret) {
1131                 dev_err(info->device, "error registering framebuffer\n");
1132                 goto err_reg_framebuffer;
1133         }
1134
1135         fb_info(info, "%s frame buffer device\n", info->fix.id);
1136         pci_set_drvdata(dev, info);
1137         if (mtrr)
1138                 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1139                                                   info->fix.smem_len);
1140         return 0;
1141
1142 err_reg_framebuffer:
1143         fb_dealloc_cmap(&info->cmap);
1144 err_alloc_cmap:
1145 err_find_mode:
1146         if (par->ddc_registered)
1147                 i2c_del_adapter(&par->ddc_adapter);
1148         pci_iounmap(dev, par->regs);
1149 err_ioremap_2:
1150         pci_iounmap(dev, info->screen_base);
1151 err_ioremap_1:
1152         pci_release_regions(dev);
1153 err_request_regions:
1154 /*      pci_disable_device(dev); */
1155 err_enable_device:
1156         framebuffer_release(info);
1157         return ret;
1158 }
1159
1160 static void i740fb_remove(struct pci_dev *dev)
1161 {
1162         struct fb_info *info = pci_get_drvdata(dev);
1163
1164         if (info) {
1165                 struct i740fb_par *par = info->par;
1166                 arch_phys_wc_del(par->wc_cookie);
1167                 unregister_framebuffer(info);
1168                 fb_dealloc_cmap(&info->cmap);
1169                 if (par->ddc_registered)
1170                         i2c_del_adapter(&par->ddc_adapter);
1171                 pci_iounmap(dev, par->regs);
1172                 pci_iounmap(dev, info->screen_base);
1173                 pci_release_regions(dev);
1174 /*              pci_disable_device(dev); */
1175                 framebuffer_release(info);
1176         }
1177 }
1178
1179 #ifdef CONFIG_PM
1180 static int i740fb_suspend(struct pci_dev *dev, pm_message_t state)
1181 {
1182         struct fb_info *info = pci_get_drvdata(dev);
1183         struct i740fb_par *par = info->par;
1184
1185         /* don't disable console during hibernation and wakeup from it */
1186         if (state.event == PM_EVENT_FREEZE || state.event == PM_EVENT_PRETHAW)
1187                 return 0;
1188
1189         console_lock();
1190         mutex_lock(&(par->open_lock));
1191
1192         /* do nothing if framebuffer is not active */
1193         if (par->ref_count == 0) {
1194                 mutex_unlock(&(par->open_lock));
1195                 console_unlock();
1196                 return 0;
1197         }
1198
1199         fb_set_suspend(info, 1);
1200
1201         pci_save_state(dev);
1202         pci_disable_device(dev);
1203         pci_set_power_state(dev, pci_choose_state(dev, state));
1204
1205         mutex_unlock(&(par->open_lock));
1206         console_unlock();
1207
1208         return 0;
1209 }
1210
1211 static int i740fb_resume(struct pci_dev *dev)
1212 {
1213         struct fb_info *info = pci_get_drvdata(dev);
1214         struct i740fb_par *par = info->par;
1215
1216         console_lock();
1217         mutex_lock(&(par->open_lock));
1218
1219         if (par->ref_count == 0)
1220                 goto fail;
1221
1222         pci_set_power_state(dev, PCI_D0);
1223         pci_restore_state(dev);
1224         if (pci_enable_device(dev))
1225                 goto fail;
1226
1227         i740fb_set_par(info);
1228         fb_set_suspend(info, 0);
1229
1230 fail:
1231         mutex_unlock(&(par->open_lock));
1232         console_unlock();
1233         return 0;
1234 }
1235 #else
1236 #define i740fb_suspend NULL
1237 #define i740fb_resume NULL
1238 #endif /* CONFIG_PM */
1239
1240 #define I740_ID_PCI 0x00d1
1241 #define I740_ID_AGP 0x7800
1242
1243 static const struct pci_device_id i740fb_id_table[] = {
1244         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
1245         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
1246         { 0 }
1247 };
1248 MODULE_DEVICE_TABLE(pci, i740fb_id_table);
1249
1250 static struct pci_driver i740fb_driver = {
1251         .name           = "i740fb",
1252         .id_table       = i740fb_id_table,
1253         .probe          = i740fb_probe,
1254         .remove         = i740fb_remove,
1255         .suspend        = i740fb_suspend,
1256         .resume         = i740fb_resume,
1257 };
1258
1259 #ifndef MODULE
1260 static int  __init i740fb_setup(char *options)
1261 {
1262         char *opt;
1263
1264         if (!options || !*options)
1265                 return 0;
1266
1267         while ((opt = strsep(&options, ",")) != NULL) {
1268                 if (!*opt)
1269                         continue;
1270                 else if (!strncmp(opt, "mtrr:", 5))
1271                         mtrr = simple_strtoul(opt + 5, NULL, 0);
1272                 else
1273                         mode_option = opt;
1274         }
1275
1276         return 0;
1277 }
1278 #endif
1279
1280 static int __init i740fb_init(void)
1281 {
1282 #ifndef MODULE
1283         char *option = NULL;
1284
1285         if (fb_get_options("i740fb", &option))
1286                 return -ENODEV;
1287         i740fb_setup(option);
1288 #endif
1289
1290         return pci_register_driver(&i740fb_driver);
1291 }
1292
1293 static void __exit i740fb_exit(void)
1294 {
1295         pci_unregister_driver(&i740fb_driver);
1296 }
1297
1298 module_init(i740fb_init);
1299 module_exit(i740fb_exit);
1300
1301 MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
1302 MODULE_LICENSE("GPL");
1303 MODULE_DESCRIPTION("fbdev driver for Intel740");
1304
1305 module_param(mode_option, charp, 0444);
1306 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
1307
1308 module_param(mtrr, int, 0444);
1309 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");