drivers/usb/musb/musb_gadget_ep0.c

   1 /*
   2  * MUSB OTG peripheral driver ep0 handling
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2006 by Texas Instruments
   6  * Copyright (C) 2006-2007 Nokia Corporation
   7  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  26  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/list.h>
  38 #include <linux/timer.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/device.h>
  41 #include <linux/interrupt.h>
  42
  43 #include "musb_core.h"
  44
  45 /* ep0 is always musb->endpoints[0].ep_in */
  46 #define next_ep0_request(musb)  next_in_request(&(musb)->endpoints[0])
  47
  48 /*
  49  * locking note:  we use only the controller lock, for simpler correctness.
  50  * It's always held with IRQs blocked.
  51  *
  52  * It protects the ep0 request queue as well as ep0_state, not just the
  53  * controller and indexed registers.  And that lock stays held unless it
  54  * needs to be dropped to allow reentering this driver ... like upcalls to
  55  * the gadget driver, or adjusting endpoint halt status.
  56  */
  57
  58 static char *decode_ep0stage(u8 stage)
  59 {
  60         switch (stage) {
  61         case MUSB_EP0_STAGE_IDLE:       return "idle";
  62         case MUSB_EP0_STAGE_SETUP:      return "setup";
  63         case MUSB_EP0_STAGE_TX:         return "in";
  64         case MUSB_EP0_STAGE_RX:         return "out";
  65         case MUSB_EP0_STAGE_ACKWAIT:    return "wait";
  66         case MUSB_EP0_STAGE_STATUSIN:   return "in/status";
  67         case MUSB_EP0_STAGE_STATUSOUT:  return "out/status";
  68         default:                        return "?";
  69         }
  70 }
  71
  72 /* handle a standard GET_STATUS request
  73  * Context:  caller holds controller lock
  74  */
  75 static int service_tx_status_request(
  76         struct musb *musb,
  77         const struct usb_ctrlrequest *ctrlrequest)
  78 {
  79         void __iomem    *mbase = musb->mregs;
  80         int handled = 1;
  81         u8 result[2], epnum = 0;
  82         const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  83
  84         result[1] = 0;
  85
  86         switch (recip) {
  87         case USB_RECIP_DEVICE:
  88                 result[0] = musb->g.is_selfpowered << USB_DEVICE_SELF_POWERED;
  89                 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  90                 if (musb->g.is_otg) {
  91                         result[0] |= musb->g.b_hnp_enable
  92                                 << USB_DEVICE_B_HNP_ENABLE;
  93                         result[0] |= musb->g.a_alt_hnp_support
  94                                 << USB_DEVICE_A_ALT_HNP_SUPPORT;
  95                         result[0] |= musb->g.a_hnp_support
  96                                 << USB_DEVICE_A_HNP_SUPPORT;
  97                 }
  98                 break;
  99
 100         case USB_RECIP_INTERFACE:
 101                 result[0] = 0;
 102                 break;
 103
 104         case USB_RECIP_ENDPOINT: {
 105                 int             is_in;
 106                 struct musb_ep  *ep;
 107                 u16             tmp;
 108                 void __iomem    *regs;
 109
 110                 epnum = (u8) ctrlrequest->wIndex;
 111                 if (!epnum) {
 112                         result[0] = 0;
 113                         break;
 114                 }
 115
 116                 is_in = epnum & USB_DIR_IN;
 117                 epnum &= 0x0f;
 118                 if (epnum >= MUSB_C_NUM_EPS) {
 119                         handled = -EINVAL;
 120                         break;
 121                 }
 122
 123                 if (is_in)
 124                         ep = &musb->endpoints[epnum].ep_in;
 125                 else
 126                         ep = &musb->endpoints[epnum].ep_out;
 127                 regs = musb->endpoints[epnum].regs;
 128
 129                 if (!ep->desc) {
 130                         handled = -EINVAL;
 131                         break;
 132                 }
 133
 134                 musb_ep_select(mbase, epnum);
 135                 if (is_in)
 136                         tmp = musb_readw(regs, MUSB_TXCSR)
 137                                                 & MUSB_TXCSR_P_SENDSTALL;
 138                 else
 139                         tmp = musb_readw(regs, MUSB_RXCSR)
 140                                                 & MUSB_RXCSR_P_SENDSTALL;
 141                 musb_ep_select(mbase, 0);
 142
 143                 result[0] = tmp ? 1 : 0;
 144                 } break;
 145
 146         default:
 147                 /* class, vendor, etc ... delegate */
 148                 handled = 0;
 149                 break;
 150         }
 151
 152         /* fill up the fifo; caller updates csr0 */
 153         if (handled > 0) {
 154                 u16     len = le16_to_cpu(ctrlrequest->wLength);
 155
 156                 if (len > 2)
 157                         len = 2;
 158                 musb_write_fifo(&musb->endpoints[0], len, result);
 159         }
 160
 161         return handled;
 162 }
 163
 164 /*
 165  * handle a control-IN request, the end0 buffer contains the current request
 166  * that is supposed to be a standard control request. Assumes the fifo to
 167  * be at least 2 bytes long.
 168  *
 169  * @return 0 if the request was NOT HANDLED,
 170  * < 0 when error
 171  * > 0 when the request is processed
 172  *
 173  * Context:  caller holds controller lock
 174  */
 175 static int
 176 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 177 {
 178         int handled = 0;        /* not handled */
 179
 180         if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
 181                         == USB_TYPE_STANDARD) {
 182                 switch (ctrlrequest->bRequest) {
 183                 case USB_REQ_GET_STATUS:
 184                         handled = service_tx_status_request(musb,
 185                                         ctrlrequest);
 186                         break;
 187
 188                 /* case USB_REQ_SYNC_FRAME: */
 189
 190                 default:
 191                         break;
 192                 }
 193         }
 194         return handled;
 195 }
 196
 197 /*
 198  * Context:  caller holds controller lock
 199  */
 200 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 201 {
 202         musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
 203 }
 204
 205 /*
 206  * Tries to start B-device HNP negotiation if enabled via sysfs
 207  */
 208 static inline void musb_try_b_hnp_enable(struct musb *musb)
 209 {
 210         void __iomem    *mbase = musb->mregs;
 211         u8              devctl;
 212
 213         musb_dbg(musb, "HNP: Setting HR");
 214         devctl = musb_readb(mbase, MUSB_DEVCTL);
 215         musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
 216 }
 217
 218 /*
 219  * Handle all control requests with no DATA stage, including standard
 220  * requests such as:
 221  * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
 222  *      always delegated to the gadget driver
 223  * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
 224  *      always handled here, except for class/vendor/... features
 225  *
 226  * Context:  caller holds controller lock
 227  */
 228 static int
 229 service_zero_data_request(struct musb *musb,
 230                 struct usb_ctrlrequest *ctrlrequest)
 231 __releases(musb->lock)
 232 __acquires(musb->lock)
 233 {
 234         int handled = -EINVAL;
 235         void __iomem *mbase = musb->mregs;
 236         const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
 237
 238         /* the gadget driver handles everything except what we MUST handle */
 239         if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
 240                         == USB_TYPE_STANDARD) {
 241                 switch (ctrlrequest->bRequest) {
 242                 case USB_REQ_SET_ADDRESS:
 243                         /* change it after the status stage */
 244                         musb->set_address = true;
 245                         musb->address = (u8) (ctrlrequest->wValue & 0x7f);
 246                         handled = 1;
 247                         break;
 248
 249                 case USB_REQ_CLEAR_FEATURE:
 250                         switch (recip) {
 251                         case USB_RECIP_DEVICE:
 252                                 if (ctrlrequest->wValue
 253                                                 != USB_DEVICE_REMOTE_WAKEUP)
 254                                         break;
 255                                 musb->may_wakeup = 0;
 256                                 handled = 1;
 257                                 break;
 258                         case USB_RECIP_INTERFACE:
 259                                 break;
 260                         case USB_RECIP_ENDPOINT:{
 261                                 const u8                epnum =
 262                                         ctrlrequest->wIndex & 0x0f;
 263                                 struct musb_ep          *musb_ep;
 264                                 struct musb_hw_ep       *ep;
 265                                 struct musb_request     *request;
 266                                 void __iomem            *regs;
 267                                 int                     is_in;
 268                                 u16                     csr;
 269
 270                                 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
 271                                     ctrlrequest->wValue != USB_ENDPOINT_HALT)
 272                                         break;
 273
 274                                 ep = musb->endpoints + epnum;
 275                                 regs = ep->regs;
 276                                 is_in = ctrlrequest->wIndex & USB_DIR_IN;
 277                                 if (is_in)
 278                                         musb_ep = &ep->ep_in;
 279                                 else
 280                                         musb_ep = &ep->ep_out;
 281                                 if (!musb_ep->desc)
 282                                         break;
 283
 284                                 handled = 1;
 285                                 /* Ignore request if endpoint is wedged */
 286                                 if (musb_ep->wedged)
 287                                         break;
 288
 289                                 musb_ep_select(mbase, epnum);
 290                                 if (is_in) {
 291                                         csr  = musb_readw(regs, MUSB_TXCSR);
 292                                         csr |= MUSB_TXCSR_CLRDATATOG |
 293                                                MUSB_TXCSR_P_WZC_BITS;
 294                                         csr &= ~(MUSB_TXCSR_P_SENDSTALL |
 295                                                  MUSB_TXCSR_P_SENTSTALL |
 296                                                  MUSB_TXCSR_TXPKTRDY);
 297                                         musb_writew(regs, MUSB_TXCSR, csr);
 298                                 } else {
 299                                         csr  = musb_readw(regs, MUSB_RXCSR);
 300                                         csr |= MUSB_RXCSR_CLRDATATOG |
 301                                                MUSB_RXCSR_P_WZC_BITS;
 302                                         csr &= ~(MUSB_RXCSR_P_SENDSTALL |
 303                                                  MUSB_RXCSR_P_SENTSTALL);
 304                                         musb_writew(regs, MUSB_RXCSR, csr);
 305                                 }
 306
 307                                 /* Maybe start the first request in the queue */
 308                                 request = next_request(musb_ep);
 309                                 if (!musb_ep->busy && request) {
 310                                         musb_dbg(musb, "restarting the request");
 311                                         musb_ep_restart(musb, request);
 312                                 }
 313
 314                                 /* select ep0 again */
 315                                 musb_ep_select(mbase, 0);
 316                                 } break;
 317                         default:
 318                                 /* class, vendor, etc ... delegate */
 319                                 handled = 0;
 320                                 break;
 321                         }
 322                         break;
 323
 324                 case USB_REQ_SET_FEATURE:
 325                         switch (recip) {
 326                         case USB_RECIP_DEVICE:
 327                                 handled = 1;
 328                                 switch (ctrlrequest->wValue) {
 329                                 case USB_DEVICE_REMOTE_WAKEUP:
 330                                         musb->may_wakeup = 1;
 331                                         break;
 332                                 case USB_DEVICE_TEST_MODE:
 333                                         if (musb->g.speed != USB_SPEED_HIGH)
 334                                                 goto stall;
 335                                         if (ctrlrequest->wIndex & 0xff)
 336                                                 goto stall;
 337
 338                                         switch (ctrlrequest->wIndex >> 8) {
 339                                         case 1:
 340                                                 pr_debug("TEST_J\n");
 341                                                 /* TEST_J */
 342                                                 musb->test_mode_nr =
 343                                                         MUSB_TEST_J;
 344                                                 break;
 345                                         case 2:
 346                                                 /* TEST_K */
 347                                                 pr_debug("TEST_K\n");
 348                                                 musb->test_mode_nr =
 349                                                         MUSB_TEST_K;
 350                                                 break;
 351                                         case 3:
 352                                                 /* TEST_SE0_NAK */
 353                                                 pr_debug("TEST_SE0_NAK\n");
 354                                                 musb->test_mode_nr =
 355                                                         MUSB_TEST_SE0_NAK;
 356                                                 break;
 357                                         case 4:
 358                                                 /* TEST_PACKET */
 359                                                 pr_debug("TEST_PACKET\n");
 360                                                 musb->test_mode_nr =
 361                                                         MUSB_TEST_PACKET;
 362                                                 break;
 363
 364                                         case 0xc0:
 365                                                 /* TEST_FORCE_HS */
 366                                                 pr_debug("TEST_FORCE_HS\n");
 367                                                 musb->test_mode_nr =
 368                                                         MUSB_TEST_FORCE_HS;
 369                                                 break;
 370                                         case 0xc1:
 371                                                 /* TEST_FORCE_FS */
 372                                                 pr_debug("TEST_FORCE_FS\n");
 373                                                 musb->test_mode_nr =
 374                                                         MUSB_TEST_FORCE_FS;
 375                                                 break;
 376                                         case 0xc2:
 377                                                 /* TEST_FIFO_ACCESS */
 378                                                 pr_debug("TEST_FIFO_ACCESS\n");
 379                                                 musb->test_mode_nr =
 380                                                         MUSB_TEST_FIFO_ACCESS;
 381                                                 break;
 382                                         case 0xc3:
 383                                                 /* TEST_FORCE_HOST */
 384                                                 pr_debug("TEST_FORCE_HOST\n");
 385                                                 musb->test_mode_nr =
 386                                                         MUSB_TEST_FORCE_HOST;
 387                                                 break;
 388                                         default:
 389                                                 goto stall;
 390                                         }
 391
 392                                         /* enter test mode after irq */
 393                                         if (handled > 0)
 394                                                 musb->test_mode = true;
 395                                         break;
 396                                 case USB_DEVICE_B_HNP_ENABLE:
 397                                         if (!musb->g.is_otg)
 398                                                 goto stall;
 399                                         musb->g.b_hnp_enable = 1;
 400                                         musb_try_b_hnp_enable(musb);
 401                                         break;
 402                                 case USB_DEVICE_A_HNP_SUPPORT:
 403                                         if (!musb->g.is_otg)
 404                                                 goto stall;
 405                                         musb->g.a_hnp_support = 1;
 406                                         break;
 407                                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
 408                                         if (!musb->g.is_otg)
 409                                                 goto stall;
 410                                         musb->g.a_alt_hnp_support = 1;
 411                                         break;
 412                                 case USB_DEVICE_DEBUG_MODE:
 413                                         handled = 0;
 414                                         break;
 415 stall:
 416                                 default:
 417                                         handled = -EINVAL;
 418                                         break;
 419                                 }
 420                                 break;
 421
 422                         case USB_RECIP_INTERFACE:
 423                                 break;
 424
 425                         case USB_RECIP_ENDPOINT:{
 426                                 const u8                epnum =
 427                                         ctrlrequest->wIndex & 0x0f;
 428                                 struct musb_ep          *musb_ep;
 429                                 struct musb_hw_ep       *ep;
 430                                 void __iomem            *regs;
 431                                 int                     is_in;
 432                                 u16                     csr;
 433
 434                                 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
 435                                     ctrlrequest->wValue != USB_ENDPOINT_HALT)
 436                                         break;
 437
 438                                 ep = musb->endpoints + epnum;
 439                                 regs = ep->regs;
 440                                 is_in = ctrlrequest->wIndex & USB_DIR_IN;
 441                                 if (is_in)
 442                                         musb_ep = &ep->ep_in;
 443                                 else
 444                                         musb_ep = &ep->ep_out;
 445                                 if (!musb_ep->desc)
 446                                         break;
 447
 448                                 musb_ep_select(mbase, epnum);
 449                                 if (is_in) {
 450                                         csr = musb_readw(regs, MUSB_TXCSR);
 451                                         if (csr & MUSB_TXCSR_FIFONOTEMPTY)
 452                                                 csr |= MUSB_TXCSR_FLUSHFIFO;
 453                                         csr |= MUSB_TXCSR_P_SENDSTALL
 454                                                 | MUSB_TXCSR_CLRDATATOG
 455                                                 | MUSB_TXCSR_P_WZC_BITS;
 456                                         musb_writew(regs, MUSB_TXCSR, csr);
 457                                 } else {
 458                                         csr = musb_readw(regs, MUSB_RXCSR);
 459                                         csr |= MUSB_RXCSR_P_SENDSTALL
 460                                                 | MUSB_RXCSR_FLUSHFIFO
 461                                                 | MUSB_RXCSR_CLRDATATOG
 462                                                 | MUSB_RXCSR_P_WZC_BITS;
 463                                         musb_writew(regs, MUSB_RXCSR, csr);
 464                                 }
 465
 466                                 /* select ep0 again */
 467                                 musb_ep_select(mbase, 0);
 468                                 handled = 1;
 469                                 } break;
 470
 471                         default:
 472                                 /* class, vendor, etc ... delegate */
 473                                 handled = 0;
 474                                 break;
 475                         }
 476                         break;
 477                 default:
 478                         /* delegate SET_CONFIGURATION, etc */
 479                         handled = 0;
 480                 }
 481         } else
 482                 handled = 0;
 483         return handled;
 484 }
 485
 486 /* we have an ep0out data packet
 487  * Context:  caller holds controller lock
 488  */
 489 static void ep0_rxstate(struct musb *musb)
 490 {
 491         void __iomem            *regs = musb->control_ep->regs;
 492         struct musb_request     *request;
 493         struct usb_request      *req;
 494         u16                     count, csr;
 495
 496         request = next_ep0_request(musb);
 497         req = &request->request;
 498
 499         /* read packet and ack; or stall because of gadget driver bug:
 500          * should have provided the rx buffer before setup() returned.
 501          */
 502         if (req) {
 503                 void            *buf = req->buf + req->actual;
 504                 unsigned        len = req->length - req->actual;
 505
 506                 /* read the buffer */
 507                 count = musb_readb(regs, MUSB_COUNT0);
 508                 if (count > len) {
 509                         req->status = -EOVERFLOW;
 510                         count = len;
 511                 }
 512                 if (count > 0) {
 513                         musb_read_fifo(&musb->endpoints[0], count, buf);
 514                         req->actual += count;
 515                 }
 516                 csr = MUSB_CSR0_P_SVDRXPKTRDY;
 517                 if (count < 64 || req->actual == req->length) {
 518                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 519                         csr |= MUSB_CSR0_P_DATAEND;
 520                 } else
 521                         req = NULL;
 522         } else
 523                 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
 524
 525
 526         /* Completion handler may choose to stall, e.g. because the
 527          * message just received holds invalid data.
 528          */
 529         if (req) {
 530                 musb->ackpend = csr;
 531                 musb_g_ep0_giveback(musb, req);
 532                 if (!musb->ackpend)
 533                         return;
 534                 musb->ackpend = 0;
 535         }
 536         musb_ep_select(musb->mregs, 0);
 537         musb_writew(regs, MUSB_CSR0, csr);
 538 }
 539
 540 /*
 541  * transmitting to the host (IN), this code might be called from IRQ
 542  * and from kernel thread.
 543  *
 544  * Context:  caller holds controller lock
 545  */
 546 static void ep0_txstate(struct musb *musb)
 547 {
 548         void __iomem            *regs = musb->control_ep->regs;
 549         struct musb_request     *req = next_ep0_request(musb);
 550         struct usb_request      *request;
 551         u16                     csr = MUSB_CSR0_TXPKTRDY;
 552         u8                      *fifo_src;
 553         u8                      fifo_count;
 554
 555         if (!req) {
 556                 /* WARN_ON(1); */
 557                 musb_dbg(musb, "odd; csr0 %04x", musb_readw(regs, MUSB_CSR0));
 558                 return;
 559         }
 560
 561         request = &req->request;
 562
 563         /* load the data */
 564         fifo_src = (u8 *) request->buf + request->actual;
 565         fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
 566                 request->length - request->actual);
 567         musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
 568         request->actual += fifo_count;
 569
 570         /* update the flags */
 571         if (fifo_count < MUSB_MAX_END0_PACKET
 572                         || (request->actual == request->length
 573                                 && !request->zero)) {
 574                 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 575                 csr |= MUSB_CSR0_P_DATAEND;
 576         } else
 577                 request = NULL;
 578
 579         /* report completions as soon as the fifo's loaded; there's no
 580          * win in waiting till this last packet gets acked.  (other than
 581          * very precise fault reporting, needed by USB TMC; possible with
 582          * this hardware, but not usable from portable gadget drivers.)
 583          */
 584         if (request) {
 585                 musb->ackpend = csr;
 586                 musb_g_ep0_giveback(musb, request);
 587                 if (!musb->ackpend)
 588                         return;
 589                 musb->ackpend = 0;
 590         }
 591
 592         /* send it out, triggering a "txpktrdy cleared" irq */
 593         musb_ep_select(musb->mregs, 0);
 594         musb_writew(regs, MUSB_CSR0, csr);
 595 }
 596
 597 /*
 598  * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
 599  * Fields are left in USB byte-order.
 600  *
 601  * Context:  caller holds controller lock.
 602  */
 603 static void
 604 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
 605 {
 606         struct musb_request     *r;
 607         void __iomem            *regs = musb->control_ep->regs;
 608
 609         musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
 610
 611         /* NOTE:  earlier 2.6 versions changed setup packets to host
 612          * order, but now USB packets always stay in USB byte order.
 613          */
 614         musb_dbg(musb, "SETUP req%02x.%02x v%04x i%04x l%d",
 615                 req->bRequestType,
 616                 req->bRequest,
 617                 le16_to_cpu(req->wValue),
 618                 le16_to_cpu(req->wIndex),
 619                 le16_to_cpu(req->wLength));
 620
 621         /* clean up any leftover transfers */
 622         r = next_ep0_request(musb);
 623         if (r)
 624                 musb_g_ep0_giveback(musb, &r->request);
 625
 626         /* For zero-data requests we want to delay the STATUS stage to
 627          * avoid SETUPEND errors.  If we read data (OUT), delay accepting
 628          * packets until there's a buffer to store them in.
 629          *
 630          * If we write data, the controller acts happier if we enable
 631          * the TX FIFO right away, and give the controller a moment
 632          * to switch modes...
 633          */
 634         musb->set_address = false;
 635         musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
 636         if (req->wLength == 0) {
 637                 if (req->bRequestType & USB_DIR_IN)
 638                         musb->ackpend |= MUSB_CSR0_TXPKTRDY;
 639                 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
 640         } else if (req->bRequestType & USB_DIR_IN) {
 641                 musb->ep0_state = MUSB_EP0_STAGE_TX;
 642                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
 643                 while ((musb_readw(regs, MUSB_CSR0)
 644                                 & MUSB_CSR0_RXPKTRDY) != 0)
 645                         cpu_relax();
 646                 musb->ackpend = 0;
 647         } else
 648                 musb->ep0_state = MUSB_EP0_STAGE_RX;
 649 }
 650
 651 static int
 652 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 653 __releases(musb->lock)
 654 __acquires(musb->lock)
 655 {
 656         int retval;
 657         if (!musb->gadget_driver)
 658                 return -EOPNOTSUPP;
 659         spin_unlock(&musb->lock);
 660         retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
 661         spin_lock(&musb->lock);
 662         return retval;
 663 }
 664
 665 /*
 666  * Handle peripheral ep0 interrupt
 667  *
 668  * Context: irq handler; we won't re-enter the driver that way.
 669  */
 670 irqreturn_t musb_g_ep0_irq(struct musb *musb)
 671 {
 672         u16             csr;
 673         u16             len;
 674         void __iomem    *mbase = musb->mregs;
 675         void __iomem    *regs = musb->endpoints[0].regs;
 676         irqreturn_t     retval = IRQ_NONE;
 677
 678         musb_ep_select(mbase, 0);       /* select ep0 */
 679         csr = musb_readw(regs, MUSB_CSR0);
 680         len = musb_readb(regs, MUSB_COUNT0);
 681
 682         musb_dbg(musb, "csr %04x, count %d, ep0stage %s",
 683                         csr, len, decode_ep0stage(musb->ep0_state));
 684
 685         if (csr & MUSB_CSR0_P_DATAEND) {
 686                 /*
 687                  * If DATAEND is set we should not call the callback,
 688                  * hence the status stage is not complete.
 689                  */
 690                 return IRQ_HANDLED;
 691         }
 692
 693         /* I sent a stall.. need to acknowledge it now.. */
 694         if (csr & MUSB_CSR0_P_SENTSTALL) {
 695                 musb_writew(regs, MUSB_CSR0,
 696                                 csr & ~MUSB_CSR0_P_SENTSTALL);
 697                 retval = IRQ_HANDLED;
 698                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 699                 csr = musb_readw(regs, MUSB_CSR0);
 700         }
 701
 702         /* request ended "early" */
 703         if (csr & MUSB_CSR0_P_SETUPEND) {
 704                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
 705                 retval = IRQ_HANDLED;
 706                 /* Transition into the early status phase */
 707                 switch (musb->ep0_state) {
 708                 case MUSB_EP0_STAGE_TX:
 709                         musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 710                         break;
 711                 case MUSB_EP0_STAGE_RX:
 712                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 713                         break;
 714                 default:
 715                         ERR("SetupEnd came in a wrong ep0stage %s\n",
 716                             decode_ep0stage(musb->ep0_state));
 717                 }
 718                 csr = musb_readw(regs, MUSB_CSR0);
 719                 /* NOTE:  request may need completion */
 720         }
 721
 722         /* docs from Mentor only describe tx, rx, and idle/setup states.
 723          * we need to handle nuances around status stages, and also the
 724          * case where status and setup stages come back-to-back ...
 725          */
 726         switch (musb->ep0_state) {
 727
 728         case MUSB_EP0_STAGE_TX:
 729                 /* irq on clearing txpktrdy */
 730                 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
 731                         ep0_txstate(musb);
 732                         retval = IRQ_HANDLED;
 733                 }
 734                 break;
 735
 736         case MUSB_EP0_STAGE_RX:
 737                 /* irq on set rxpktrdy */
 738                 if (csr & MUSB_CSR0_RXPKTRDY) {
 739                         ep0_rxstate(musb);
 740                         retval = IRQ_HANDLED;
 741                 }
 742                 break;
 743
 744         case MUSB_EP0_STAGE_STATUSIN:
 745                 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
 746
 747                 /* update address (if needed) only @ the end of the
 748                  * status phase per usb spec, which also guarantees
 749                  * we get 10 msec to receive this irq... until this
 750                  * is done we won't see the next packet.
 751                  */
 752                 if (musb->set_address) {
 753                         musb->set_address = false;
 754                         musb_writeb(mbase, MUSB_FADDR, musb->address);
 755                 }
 756
 757                 /* enter test mode if needed (exit by reset) */
 758                 else if (musb->test_mode) {
 759                         musb_dbg(musb, "entering TESTMODE");
 760
 761                         if (MUSB_TEST_PACKET == musb->test_mode_nr)
 762                                 musb_load_testpacket(musb);
 763
 764                         musb_writeb(mbase, MUSB_TESTMODE,
 765                                         musb->test_mode_nr);
 766                 }
 767                 /* FALLTHROUGH */
 768
 769         case MUSB_EP0_STAGE_STATUSOUT:
 770                 /* end of sequence #1: write to host (TX state) */
 771                 {
 772                         struct musb_request     *req;
 773
 774                         req = next_ep0_request(musb);
 775                         if (req)
 776                                 musb_g_ep0_giveback(musb, &req->request);
 777                 }
 778
 779                 /*
 780                  * In case when several interrupts can get coalesced,
 781                  * check to see if we've already received a SETUP packet...
 782                  */
 783                 if (csr & MUSB_CSR0_RXPKTRDY)
 784                         goto setup;
 785
 786                 retval = IRQ_HANDLED;
 787                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 788                 break;
 789
 790         case MUSB_EP0_STAGE_IDLE:
 791                 /*
 792                  * This state is typically (but not always) indiscernible
 793                  * from the status states since the corresponding interrupts
 794                  * tend to happen within too little period of time (with only
 795                  * a zero-length packet in between) and so get coalesced...
 796                  */
 797                 retval = IRQ_HANDLED;
 798                 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
 799                 /* FALLTHROUGH */
 800
 801         case MUSB_EP0_STAGE_SETUP:
 802 setup:
 803                 if (csr & MUSB_CSR0_RXPKTRDY) {
 804                         struct usb_ctrlrequest  setup;
 805                         int                     handled = 0;
 806
 807                         if (len != 8) {
 808                                 ERR("SETUP packet len %d != 8 ?\n", len);
 809                                 break;
 810                         }
 811                         musb_read_setup(musb, &setup);
 812                         retval = IRQ_HANDLED;
 813
 814                         /* sometimes the RESET won't be reported */
 815                         if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
 816                                 u8      power;
 817
 818                                 printk(KERN_NOTICE "%s: peripheral reset "
 819                                                 "irq lost!\n",
 820                                                 musb_driver_name);
 821                                 power = musb_readb(mbase, MUSB_POWER);
 822                                 musb->g.speed = (power & MUSB_POWER_HSMODE)
 823                                         ? USB_SPEED_HIGH : USB_SPEED_FULL;
 824
 825                         }
 826
 827                         switch (musb->ep0_state) {
 828
 829                         /* sequence #3 (no data stage), includes requests
 830                          * we can't forward (notably SET_ADDRESS and the
 831                          * device/endpoint feature set/clear operations)
 832                          * plus SET_CONFIGURATION and others we must
 833                          */
 834                         case MUSB_EP0_STAGE_ACKWAIT:
 835                                 handled = service_zero_data_request(
 836                                                 musb, &setup);
 837
 838                                 /*
 839                                  * We're expecting no data in any case, so
 840                                  * always set the DATAEND bit -- doing this
 841                                  * here helps avoid SetupEnd interrupt coming
 842                                  * in the idle stage when we're stalling...
 843                                  */
 844                                 musb->ackpend |= MUSB_CSR0_P_DATAEND;
 845
 846                                 /* status stage might be immediate */
 847                                 if (handled > 0)
 848                                         musb->ep0_state =
 849                                                 MUSB_EP0_STAGE_STATUSIN;
 850                                 break;
 851
 852                         /* sequence #1 (IN to host), includes GET_STATUS
 853                          * requests that we can't forward, GET_DESCRIPTOR
 854                          * and others that we must
 855                          */
 856                         case MUSB_EP0_STAGE_TX:
 857                                 handled = service_in_request(musb, &setup);
 858                                 if (handled > 0) {
 859                                         musb->ackpend = MUSB_CSR0_TXPKTRDY
 860                                                 | MUSB_CSR0_P_DATAEND;
 861                                         musb->ep0_state =
 862                                                 MUSB_EP0_STAGE_STATUSOUT;
 863                                 }
 864                                 break;
 865
 866                         /* sequence #2 (OUT from host), always forward */
 867                         default:                /* MUSB_EP0_STAGE_RX */
 868                                 break;
 869                         }
 870
 871                         musb_dbg(musb, "handled %d, csr %04x, ep0stage %s",
 872                                 handled, csr,
 873                                 decode_ep0stage(musb->ep0_state));
 874
 875                         /* unless we need to delegate this to the gadget
 876                          * driver, we know how to wrap this up:  csr0 has
 877                          * not yet been written.
 878                          */
 879                         if (handled < 0)
 880                                 goto stall;
 881                         else if (handled > 0)
 882                                 goto finish;
 883
 884                         handled = forward_to_driver(musb, &setup);
 885                         if (handled < 0) {
 886                                 musb_ep_select(mbase, 0);
 887 stall:
 888                                 musb_dbg(musb, "stall (%d)", handled);
 889                                 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
 890                                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 891 finish:
 892                                 musb_writew(regs, MUSB_CSR0,
 893                                                 musb->ackpend);
 894                                 musb->ackpend = 0;
 895                         }
 896                 }
 897                 break;
 898
 899         case MUSB_EP0_STAGE_ACKWAIT:
 900                 /* This should not happen. But happens with tusb6010 with
 901                  * g_file_storage and high speed. Do nothing.
 902                  */
 903                 retval = IRQ_HANDLED;
 904                 break;
 905
 906         default:
 907                 /* "can't happen" */
 908                 WARN_ON(1);
 909                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
 910                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 911                 break;
 912         }
 913
 914         return retval;
 915 }
 916
 917
 918 static int
 919 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
 920 {
 921         /* always enabled */
 922         return -EINVAL;
 923 }
 924
 925 static int musb_g_ep0_disable(struct usb_ep *e)
 926 {
 927         /* always enabled */
 928         return -EINVAL;
 929 }
 930
 931 static int
 932 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
 933 {
 934         struct musb_ep          *ep;
 935         struct musb_request     *req;
 936         struct musb             *musb;
 937         int                     status;
 938         unsigned long           lockflags;
 939         void __iomem            *regs;
 940
 941         if (!e || !r)
 942                 return -EINVAL;
 943
 944         ep = to_musb_ep(e);
 945         musb = ep->musb;
 946         regs = musb->control_ep->regs;
 947
 948         req = to_musb_request(r);
 949         req->musb = musb;
 950         req->request.actual = 0;
 951         req->request.status = -EINPROGRESS;
 952         req->tx = ep->is_in;
 953
 954         spin_lock_irqsave(&musb->lock, lockflags);
 955
 956         if (!list_empty(&ep->req_list)) {
 957                 status = -EBUSY;
 958                 goto cleanup;
 959         }
 960
 961         switch (musb->ep0_state) {
 962         case MUSB_EP0_STAGE_RX:         /* control-OUT data */
 963         case MUSB_EP0_STAGE_TX:         /* control-IN data */
 964         case MUSB_EP0_STAGE_ACKWAIT:    /* zero-length data */
 965                 status = 0;
 966                 break;
 967         default:
 968                 musb_dbg(musb, "ep0 request queued in state %d",
 969                                 musb->ep0_state);
 970                 status = -EINVAL;
 971                 goto cleanup;
 972         }
 973
 974         /* add request to the list */
 975         list_add_tail(&req->list, &ep->req_list);
 976
 977         musb_dbg(musb, "queue to %s (%s), length=%d",
 978                         ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
 979                         req->request.length);
 980
 981         musb_ep_select(musb->mregs, 0);
 982
 983         /* sequence #1, IN ... start writing the data */
 984         if (musb->ep0_state == MUSB_EP0_STAGE_TX)
 985                 ep0_txstate(musb);
 986
 987         /* sequence #3, no-data ... issue IN status */
 988         else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
 989                 if (req->request.length)
 990                         status = -EINVAL;
 991                 else {
 992                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 993                         musb_writew(regs, MUSB_CSR0,
 994                                         musb->ackpend | MUSB_CSR0_P_DATAEND);
 995                         musb->ackpend = 0;
 996                         musb_g_ep0_giveback(ep->musb, r);
 997                 }
 998
 999         /* else for sequence #2 (OUT), caller provides a buffer
1000          * before the next packet arrives.  deferred responses
1001          * (after SETUP is acked) are racey.
1002          */
1003         } else if (musb->ackpend) {
1004                 musb_writew(regs, MUSB_CSR0, musb->ackpend);
1005                 musb->ackpend = 0;
1006         }
1007
1008 cleanup:
1009         spin_unlock_irqrestore(&musb->lock, lockflags);
1010         return status;
1011 }
1012
1013 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
1014 {
1015         /* we just won't support this */
1016         return -EINVAL;
1017 }
1018
1019 static int musb_g_ep0_halt(struct usb_ep *e, int value)
1020 {
1021         struct musb_ep          *ep;
1022         struct musb             *musb;
1023         void __iomem            *base, *regs;
1024         unsigned long           flags;
1025         int                     status;
1026         u16                     csr;
1027
1028         if (!e || !value)
1029                 return -EINVAL;
1030
1031         ep = to_musb_ep(e);
1032         musb = ep->musb;
1033         base = musb->mregs;
1034         regs = musb->control_ep->regs;
1035         status = 0;
1036
1037         spin_lock_irqsave(&musb->lock, flags);
1038
1039         if (!list_empty(&ep->req_list)) {
1040                 status = -EBUSY;
1041                 goto cleanup;
1042         }
1043
1044         musb_ep_select(base, 0);
1045         csr = musb->ackpend;
1046
1047         switch (musb->ep0_state) {
1048
1049         /* Stalls are usually issued after parsing SETUP packet, either
1050          * directly in irq context from setup() or else later.
1051          */
1052         case MUSB_EP0_STAGE_TX:         /* control-IN data */
1053         case MUSB_EP0_STAGE_ACKWAIT:    /* STALL for zero-length data */
1054         case MUSB_EP0_STAGE_RX:         /* control-OUT data */
1055                 csr = musb_readw(regs, MUSB_CSR0);
1056                 /* FALLTHROUGH */
1057
1058         /* It's also OK to issue stalls during callbacks when a non-empty
1059          * DATA stage buffer has been read (or even written).
1060          */
1061         case MUSB_EP0_STAGE_STATUSIN:   /* control-OUT status */
1062         case MUSB_EP0_STAGE_STATUSOUT:  /* control-IN status */
1063
1064                 csr |= MUSB_CSR0_P_SENDSTALL;
1065                 musb_writew(regs, MUSB_CSR0, csr);
1066                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1067                 musb->ackpend = 0;
1068                 break;
1069         default:
1070                 musb_dbg(musb, "ep0 can't halt in state %d", musb->ep0_state);
1071                 status = -EINVAL;
1072         }
1073
1074 cleanup:
1075         spin_unlock_irqrestore(&musb->lock, flags);
1076         return status;
1077 }
1078
1079 const struct usb_ep_ops musb_g_ep0_ops = {
1080         .enable         = musb_g_ep0_enable,
1081         .disable        = musb_g_ep0_disable,
1082         .alloc_request  = musb_alloc_request,
1083         .free_request   = musb_free_request,
1084         .queue          = musb_g_ep0_queue,
1085         .dequeue        = musb_g_ep0_dequeue,
1086         .set_halt       = musb_g_ep0_halt,
1087 };