drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  38                                         unsigned int cycle_state, gfp_t flags)
  39 {
  40         struct xhci_segment *seg;
  41         dma_addr_t      dma;
  42         int             i;
  43
  44         seg = kzalloc(sizeof *seg, flags);
  45         if (!seg)
  46                 return NULL;
  47
  48         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  49         if (!seg->trbs) {
  50                 kfree(seg);
  51                 return NULL;
  52         }
  53
  54         memset(seg->trbs, 0, SEGMENT_SIZE);
  55         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
  56         if (cycle_state == 0) {
  57                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
  58                         seg->trbs[i].link.control |= TRB_CYCLE;
  59         }
  60         seg->dma = dma;
  61         seg->next = NULL;
  62
  63         return seg;
  64 }
  65
  66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  67 {
  68         if (seg->trbs) {
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         kfree(seg);
  73 }
  74
  75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
  76                                 struct xhci_segment *first)
  77 {
  78         struct xhci_segment *seg;
  79
  80         seg = first->next;
  81         while (seg != first) {
  82                 struct xhci_segment *next = seg->next;
  83                 xhci_segment_free(xhci, seg);
  84                 seg = next;
  85         }
  86         xhci_segment_free(xhci, first);
  87 }
  88
  89 /*
  90  * Make the prev segment point to the next segment.
  91  *
  92  * Change the last TRB in the prev segment to be a Link TRB which points to the
  93  * DMA address of the next segment.  The caller needs to set any Link TRB
  94  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  95  */
  96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  97                 struct xhci_segment *next, enum xhci_ring_type type)
  98 {
  99         u32 val;
 100
 101         if (!prev || !next)
 102                 return;
 103         prev->next = next;
 104         if (type != TYPE_EVENT) {
 105                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
 106                         cpu_to_le64(next->dma);
 107
 108                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 109                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 110                 val &= ~TRB_TYPE_BITMASK;
 111                 val |= TRB_TYPE(TRB_LINK);
 112                 /* Always set the chain bit with 0.95 hardware */
 113                 /* Set chain bit for isoc rings on AMD 0.96 host */
 114                 if (xhci_link_trb_quirk(xhci) ||
 115                                 (type == TYPE_ISOC &&
 116                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
 117                         val |= TRB_CHAIN;
 118                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 119         }
 120 }
 121
 122 /*
 123  * Link the ring to the new segments.
 124  * Set Toggle Cycle for the new ring if needed.
 125  */
 126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
 127                 struct xhci_segment *first, struct xhci_segment *last,
 128                 unsigned int num_segs)
 129 {
 130         struct xhci_segment *next;
 131
 132         if (!ring || !first || !last)
 133                 return;
 134
 135         next = ring->enq_seg->next;
 136         xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
 137         xhci_link_segments(xhci, last, next, ring->type);
 138         ring->num_segs += num_segs;
 139         ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
 140
 141         if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
 142                 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
 143                         &= ~cpu_to_le32(LINK_TOGGLE);
 144                 last->trbs[TRBS_PER_SEGMENT-1].link.control
 145                         |= cpu_to_le32(LINK_TOGGLE);
 146                 ring->last_seg = last;
 147         }
 148 }
 149
 150 /* XXX: Do we need the hcd structure in all these functions? */
 151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 152 {
 153         if (!ring)
 154                 return;
 155
 156         if (ring->first_seg)
 157                 xhci_free_segments_for_ring(xhci, ring->first_seg);
 158
 159         kfree(ring);
 160 }
 161
 162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
 163                                         unsigned int cycle_state)
 164 {
 165         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 166         ring->enqueue = ring->first_seg->trbs;
 167         ring->enq_seg = ring->first_seg;
 168         ring->dequeue = ring->enqueue;
 169         ring->deq_seg = ring->first_seg;
 170         /* The ring is initialized to 0. The producer must write 1 to the cycle
 171          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 172          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 173          *
 174          * New rings are initialized with cycle state equal to 1; if we are
 175          * handling ring expansion, set the cycle state equal to the old ring.
 176          */
 177         ring->cycle_state = cycle_state;
 178         /* Not necessary for new rings, but needed for re-initialized rings */
 179         ring->enq_updates = 0;
 180         ring->deq_updates = 0;
 181
 182         /*
 183          * Each segment has a link TRB, and leave an extra TRB for SW
 184          * accounting purpose
 185          */
 186         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 187 }
 188
 189 /* Allocate segments and link them for a ring */
 190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
 191                 struct xhci_segment **first, struct xhci_segment **last,
 192                 unsigned int num_segs, unsigned int cycle_state,
 193                 enum xhci_ring_type type, gfp_t flags)
 194 {
 195         struct xhci_segment *prev;
 196
 197         prev = xhci_segment_alloc(xhci, cycle_state, flags);
 198         if (!prev)
 199                 return -ENOMEM;
 200         num_segs--;
 201
 202         *first = prev;
 203         while (num_segs > 0) {
 204                 struct xhci_segment     *next;
 205
 206                 next = xhci_segment_alloc(xhci, cycle_state, flags);
 207                 if (!next) {
 208                         xhci_free_segments_for_ring(xhci, *first);
 209                         return -ENOMEM;
 210                 }
 211                 xhci_link_segments(xhci, prev, next, type);
 212
 213                 prev = next;
 214                 num_segs--;
 215         }
 216         xhci_link_segments(xhci, prev, *first, type);
 217         *last = prev;
 218
 219         return 0;
 220 }
 221
 222 /**
 223  * Create a new ring with zero or more segments.
 224  *
 225  * Link each segment together into a ring.
 226  * Set the end flag and the cycle toggle bit on the last segment.
 227  * See section 4.9.1 and figures 15 and 16.
 228  */
 229 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 230                 unsigned int num_segs, unsigned int cycle_state,
 231                 enum xhci_ring_type type, gfp_t flags)
 232 {
 233         struct xhci_ring        *ring;
 234         int ret;
 235
 236         ring = kzalloc(sizeof *(ring), flags);
 237         if (!ring)
 238                 return NULL;
 239
 240         ring->num_segs = num_segs;
 241         INIT_LIST_HEAD(&ring->td_list);
 242         ring->type = type;
 243         if (num_segs == 0)
 244                 return ring;
 245
 246         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
 247                         &ring->last_seg, num_segs, cycle_state, type, flags);
 248         if (ret)
 249                 goto fail;
 250
 251         /* Only event ring does not use link TRB */
 252         if (type != TYPE_EVENT) {
 253                 /* See section 4.9.2.1 and 6.4.4.1 */
 254                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
 255                         cpu_to_le32(LINK_TOGGLE);
 256         }
 257         xhci_initialize_ring_info(ring, cycle_state);
 258         return ring;
 259
 260 fail:
 261         xhci_ring_free(xhci, ring);
 262         return NULL;
 263 }
 264
 265 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 266                 struct xhci_virt_device *virt_dev,
 267                 unsigned int ep_index)
 268 {
 269         int rings_cached;
 270
 271         rings_cached = virt_dev->num_rings_cached;
 272         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 273                 virt_dev->ring_cache[rings_cached] =
 274                         virt_dev->eps[ep_index].ring;
 275                 virt_dev->num_rings_cached++;
 276                 xhci_dbg(xhci, "Cached old ring, "
 277                                 "%d ring%s cached\n",
 278                                 virt_dev->num_rings_cached,
 279                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 280         } else {
 281                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 282                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 283                                 "freeing ring\n",
 284                                 virt_dev->num_rings_cached);
 285         }
 286         virt_dev->eps[ep_index].ring = NULL;
 287 }
 288
 289 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 290  * pointers to the beginning of the ring.
 291  */
 292 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 293                         struct xhci_ring *ring, unsigned int cycle_state,
 294                         enum xhci_ring_type type)
 295 {
 296         struct xhci_segment     *seg = ring->first_seg;
 297         int i;
 298
 299         do {
 300                 memset(seg->trbs, 0,
 301                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 302                 if (cycle_state == 0) {
 303                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
 304                                 seg->trbs[i].link.control |= TRB_CYCLE;
 305                 }
 306                 /* All endpoint rings have link TRBs */
 307                 xhci_link_segments(xhci, seg, seg->next, type);
 308                 seg = seg->next;
 309         } while (seg != ring->first_seg);
 310         ring->type = type;
 311         xhci_initialize_ring_info(ring, cycle_state);
 312         /* td list should be empty since all URBs have been cancelled,
 313          * but just in case...
 314          */
 315         INIT_LIST_HEAD(&ring->td_list);
 316 }
 317
 318 /*
 319  * Expand an existing ring.
 320  * Look for a cached ring or allocate a new ring which has same segment numbers
 321  * and link the two rings.
 322  */
 323 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
 324                                 unsigned int num_trbs, gfp_t flags)
 325 {
 326         struct xhci_segment     *first;
 327         struct xhci_segment     *last;
 328         unsigned int            num_segs;
 329         unsigned int            num_segs_needed;
 330         int                     ret;
 331
 332         num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
 333                                 (TRBS_PER_SEGMENT - 1);
 334
 335         /* Allocate number of segments we needed, or double the ring size */
 336         num_segs = ring->num_segs > num_segs_needed ?
 337                         ring->num_segs : num_segs_needed;
 338
 339         ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
 340                         num_segs, ring->cycle_state, ring->type, flags);
 341         if (ret)
 342                 return -ENOMEM;
 343
 344         xhci_link_rings(xhci, ring, first, last, num_segs);
 345         xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
 346                         ring->num_segs);
 347
 348         return 0;
 349 }
 350
 351 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 352
 353 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 354                                                     int type, gfp_t flags)
 355 {
 356         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 357         if (!ctx)
 358                 return NULL;
 359
 360         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 361         ctx->type = type;
 362         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 363         if (type == XHCI_CTX_TYPE_INPUT)
 364                 ctx->size += CTX_SIZE(xhci->hcc_params);
 365
 366         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 367         memset(ctx->bytes, 0, ctx->size);
 368         return ctx;
 369 }
 370
 371 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 372                              struct xhci_container_ctx *ctx)
 373 {
 374         if (!ctx)
 375                 return;
 376         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 377         kfree(ctx);
 378 }
 379
 380 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 381                                               struct xhci_container_ctx *ctx)
 382 {
 383         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 384         return (struct xhci_input_control_ctx *)ctx->bytes;
 385 }
 386
 387 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 388                                         struct xhci_container_ctx *ctx)
 389 {
 390         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 391                 return (struct xhci_slot_ctx *)ctx->bytes;
 392
 393         return (struct xhci_slot_ctx *)
 394                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 395 }
 396
 397 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 398                                     struct xhci_container_ctx *ctx,
 399                                     unsigned int ep_index)
 400 {
 401         /* increment ep index by offset of start of ep ctx array */
 402         ep_index++;
 403         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 404                 ep_index++;
 405
 406         return (struct xhci_ep_ctx *)
 407                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 408 }
 409
 410
 411 /***************** Streams structures manipulation *************************/
 412
 413 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 414                 unsigned int num_stream_ctxs,
 415                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 416 {
 417         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 418
 419         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 420                 dma_free_coherent(&pdev->dev,
 421                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 422                                 stream_ctx, dma);
 423         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 424                 return dma_pool_free(xhci->small_streams_pool,
 425                                 stream_ctx, dma);
 426         else
 427                 return dma_pool_free(xhci->medium_streams_pool,
 428                                 stream_ctx, dma);
 429 }
 430
 431 /*
 432  * The stream context array for each endpoint with bulk streams enabled can
 433  * vary in size, based on:
 434  *  - how many streams the endpoint supports,
 435  *  - the maximum primary stream array size the host controller supports,
 436  *  - and how many streams the device driver asks for.
 437  *
 438  * The stream context array must be a power of 2, and can be as small as
 439  * 64 bytes or as large as 1MB.
 440  */
 441 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 442                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 443                 gfp_t mem_flags)
 444 {
 445         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 446
 447         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 448                 return dma_alloc_coherent(&pdev->dev,
 449                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 450                                 dma, mem_flags);
 451         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 452                 return dma_pool_alloc(xhci->small_streams_pool,
 453                                 mem_flags, dma);
 454         else
 455                 return dma_pool_alloc(xhci->medium_streams_pool,
 456                                 mem_flags, dma);
 457 }
 458
 459 struct xhci_ring *xhci_dma_to_transfer_ring(
 460                 struct xhci_virt_ep *ep,
 461                 u64 address)
 462 {
 463         if (ep->ep_state & EP_HAS_STREAMS)
 464                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 465                                 address >> SEGMENT_SHIFT);
 466         return ep->ring;
 467 }
 468
 469 /* Only use this when you know stream_info is valid */
 470 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 471 static struct xhci_ring *dma_to_stream_ring(
 472                 struct xhci_stream_info *stream_info,
 473                 u64 address)
 474 {
 475         return radix_tree_lookup(&stream_info->trb_address_map,
 476                         address >> SEGMENT_SHIFT);
 477 }
 478 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 479
 480 struct xhci_ring *xhci_stream_id_to_ring(
 481                 struct xhci_virt_device *dev,
 482                 unsigned int ep_index,
 483                 unsigned int stream_id)
 484 {
 485         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 486
 487         if (stream_id == 0)
 488                 return ep->ring;
 489         if (!ep->stream_info)
 490                 return NULL;
 491
 492         if (stream_id > ep->stream_info->num_streams)
 493                 return NULL;
 494         return ep->stream_info->stream_rings[stream_id];
 495 }
 496
 497 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 498 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 499                 unsigned int num_streams,
 500                 struct xhci_stream_info *stream_info)
 501 {
 502         u32 cur_stream;
 503         struct xhci_ring *cur_ring;
 504         u64 addr;
 505
 506         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 507                 struct xhci_ring *mapped_ring;
 508                 int trb_size = sizeof(union xhci_trb);
 509
 510                 cur_ring = stream_info->stream_rings[cur_stream];
 511                 for (addr = cur_ring->first_seg->dma;
 512                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 513                                 addr += trb_size) {
 514                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 515                         if (cur_ring != mapped_ring) {
 516                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 517                                                 "didn't map to stream ID %u; "
 518                                                 "mapped to ring %p\n",
 519                                                 (unsigned long long) addr,
 520                                                 cur_stream,
 521                                                 mapped_ring);
 522                                 return -EINVAL;
 523                         }
 524                 }
 525                 /* One TRB after the end of the ring segment shouldn't return a
 526                  * pointer to the current ring (although it may be a part of a
 527                  * different ring).
 528                  */
 529                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 530                 if (mapped_ring != cur_ring) {
 531                         /* One TRB before should also fail */
 532                         addr = cur_ring->first_seg->dma - trb_size;
 533                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 534                 }
 535                 if (mapped_ring == cur_ring) {
 536                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 537                                         "mapped to valid stream ID %u; "
 538                                         "mapped ring = %p\n",
 539                                         (unsigned long long) addr,
 540                                         cur_stream,
 541                                         mapped_ring);
 542                         return -EINVAL;
 543                 }
 544         }
 545         return 0;
 546 }
 547 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 548
 549 /*
 550  * Change an endpoint's internal structure so it supports stream IDs.  The
 551  * number of requested streams includes stream 0, which cannot be used by device
 552  * drivers.
 553  *
 554  * The number of stream contexts in the stream context array may be bigger than
 555  * the number of streams the driver wants to use.  This is because the number of
 556  * stream context array entries must be a power of two.
 557  *
 558  * We need a radix tree for mapping physical addresses of TRBs to which stream
 559  * ID they belong to.  We need to do this because the host controller won't tell
 560  * us which stream ring the TRB came from.  We could store the stream ID in an
 561  * event data TRB, but that doesn't help us for the cancellation case, since the
 562  * endpoint may stop before it reaches that event data TRB.
 563  *
 564  * The radix tree maps the upper portion of the TRB DMA address to a ring
 565  * segment that has the same upper portion of DMA addresses.  For example, say I
 566  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 567  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 568  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 569  * pass the radix tree a key to get the right stream ID:
 570  *
 571  *      0x10c90fff >> 10 = 0x43243
 572  *      0x10c912c0 >> 10 = 0x43244
 573  *      0x10c91400 >> 10 = 0x43245
 574  *
 575  * Obviously, only those TRBs with DMA addresses that are within the segment
 576  * will make the radix tree return the stream ID for that ring.
 577  *
 578  * Caveats for the radix tree:
 579  *
 580  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 581  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 582  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 583  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 584  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 585  * extended systems (where the DMA address can be bigger than 32-bits),
 586  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 587  */
 588 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 589                 unsigned int num_stream_ctxs,
 590                 unsigned int num_streams, gfp_t mem_flags)
 591 {
 592         struct xhci_stream_info *stream_info;
 593         u32 cur_stream;
 594         struct xhci_ring *cur_ring;
 595         unsigned long key;
 596         u64 addr;
 597         int ret;
 598
 599         xhci_dbg(xhci, "Allocating %u streams and %u "
 600                         "stream context array entries.\n",
 601                         num_streams, num_stream_ctxs);
 602         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 603                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 604                 return NULL;
 605         }
 606         xhci->cmd_ring_reserved_trbs++;
 607
 608         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 609         if (!stream_info)
 610                 goto cleanup_trbs;
 611
 612         stream_info->num_streams = num_streams;
 613         stream_info->num_stream_ctxs = num_stream_ctxs;
 614
 615         /* Initialize the array of virtual pointers to stream rings. */
 616         stream_info->stream_rings = kzalloc(
 617                         sizeof(struct xhci_ring *)*num_streams,
 618                         mem_flags);
 619         if (!stream_info->stream_rings)
 620                 goto cleanup_info;
 621
 622         /* Initialize the array of DMA addresses for stream rings for the HW. */
 623         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 624                         num_stream_ctxs, &stream_info->ctx_array_dma,
 625                         mem_flags);
 626         if (!stream_info->stream_ctx_array)
 627                 goto cleanup_ctx;
 628         memset(stream_info->stream_ctx_array, 0,
 629                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 630
 631         /* Allocate everything needed to free the stream rings later */
 632         stream_info->free_streams_command =
 633                 xhci_alloc_command(xhci, true, true, mem_flags);
 634         if (!stream_info->free_streams_command)
 635                 goto cleanup_ctx;
 636
 637         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 638
 639         /* Allocate rings for all the streams that the driver will use,
 640          * and add their segment DMA addresses to the radix tree.
 641          * Stream 0 is reserved.
 642          */
 643         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 644                 stream_info->stream_rings[cur_stream] =
 645                         xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
 646                 cur_ring = stream_info->stream_rings[cur_stream];
 647                 if (!cur_ring)
 648                         goto cleanup_rings;
 649                 cur_ring->stream_id = cur_stream;
 650                 /* Set deq ptr, cycle bit, and stream context type */
 651                 addr = cur_ring->first_seg->dma |
 652                         SCT_FOR_CTX(SCT_PRI_TR) |
 653                         cur_ring->cycle_state;
 654                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 655                         cpu_to_le64(addr);
 656                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 657                                 cur_stream, (unsigned long long) addr);
 658
 659                 key = (unsigned long)
 660                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 661                 ret = radix_tree_insert(&stream_info->trb_address_map,
 662                                 key, cur_ring);
 663                 if (ret) {
 664                         xhci_ring_free(xhci, cur_ring);
 665                         stream_info->stream_rings[cur_stream] = NULL;
 666                         goto cleanup_rings;
 667                 }
 668         }
 669         /* Leave the other unused stream ring pointers in the stream context
 670          * array initialized to zero.  This will cause the xHC to give us an
 671          * error if the device asks for a stream ID we don't have setup (if it
 672          * was any other way, the host controller would assume the ring is
 673          * "empty" and wait forever for data to be queued to that stream ID).
 674          */
 675 #if XHCI_DEBUG
 676         /* Do a little test on the radix tree to make sure it returns the
 677          * correct values.
 678          */
 679         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 680                 goto cleanup_rings;
 681 #endif
 682
 683         return stream_info;
 684
 685 cleanup_rings:
 686         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 687                 cur_ring = stream_info->stream_rings[cur_stream];
 688                 if (cur_ring) {
 689                         addr = cur_ring->first_seg->dma;
 690                         radix_tree_delete(&stream_info->trb_address_map,
 691                                         addr >> SEGMENT_SHIFT);
 692                         xhci_ring_free(xhci, cur_ring);
 693                         stream_info->stream_rings[cur_stream] = NULL;
 694                 }
 695         }
 696         xhci_free_command(xhci, stream_info->free_streams_command);
 697 cleanup_ctx:
 698         kfree(stream_info->stream_rings);
 699 cleanup_info:
 700         kfree(stream_info);
 701 cleanup_trbs:
 702         xhci->cmd_ring_reserved_trbs--;
 703         return NULL;
 704 }
 705 /*
 706  * Sets the MaxPStreams field and the Linear Stream Array field.
 707  * Sets the dequeue pointer to the stream context array.
 708  */
 709 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 710                 struct xhci_ep_ctx *ep_ctx,
 711                 struct xhci_stream_info *stream_info)
 712 {
 713         u32 max_primary_streams;
 714         /* MaxPStreams is the number of stream context array entries, not the
 715          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 716          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 717          */
 718         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 719         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 720                         1 << (max_primary_streams + 1));
 721         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 722         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 723                                        | EP_HAS_LSA);
 724         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 725 }
 726
 727 /*
 728  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 729  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 730  * not at the beginning of the ring).
 731  */
 732 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 733                 struct xhci_ep_ctx *ep_ctx,
 734                 struct xhci_virt_ep *ep)
 735 {
 736         dma_addr_t addr;
 737         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 738         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 739         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 740 }
 741
 742 /* Frees all stream contexts associated with the endpoint,
 743  *
 744  * Caller should fix the endpoint context streams fields.
 745  */
 746 void xhci_free_stream_info(struct xhci_hcd *xhci,
 747                 struct xhci_stream_info *stream_info)
 748 {
 749         int cur_stream;
 750         struct xhci_ring *cur_ring;
 751         dma_addr_t addr;
 752
 753         if (!stream_info)
 754                 return;
 755
 756         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 757                         cur_stream++) {
 758                 cur_ring = stream_info->stream_rings[cur_stream];
 759                 if (cur_ring) {
 760                         addr = cur_ring->first_seg->dma;
 761                         radix_tree_delete(&stream_info->trb_address_map,
 762                                         addr >> SEGMENT_SHIFT);
 763                         xhci_ring_free(xhci, cur_ring);
 764                         stream_info->stream_rings[cur_stream] = NULL;
 765                 }
 766         }
 767         xhci_free_command(xhci, stream_info->free_streams_command);
 768         xhci->cmd_ring_reserved_trbs--;
 769         if (stream_info->stream_ctx_array)
 770                 xhci_free_stream_ctx(xhci,
 771                                 stream_info->num_stream_ctxs,
 772                                 stream_info->stream_ctx_array,
 773                                 stream_info->ctx_array_dma);
 774
 775         if (stream_info)
 776                 kfree(stream_info->stream_rings);
 777         kfree(stream_info);
 778 }
 779
 780
 781 /***************** Device context manipulation *************************/
 782
 783 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 784                 struct xhci_virt_ep *ep)
 785 {
 786         init_timer(&ep->stop_cmd_timer);
 787         ep->stop_cmd_timer.data = (unsigned long) ep;
 788         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 789         ep->xhci = xhci;
 790 }
 791
 792 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 793                 struct xhci_virt_device *virt_dev,
 794                 int slot_id)
 795 {
 796         struct list_head *tt_list_head;
 797         struct xhci_tt_bw_info *tt_info, *next;
 798         bool slot_found = false;
 799
 800         /* If the device never made it past the Set Address stage,
 801          * it may not have the real_port set correctly.
 802          */
 803         if (virt_dev->real_port == 0 ||
 804                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 805                 xhci_dbg(xhci, "Bad real port.\n");
 806                 return;
 807         }
 808
 809         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 810         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 811                 /* Multi-TT hubs will have more than one entry */
 812                 if (tt_info->slot_id == slot_id) {
 813                         slot_found = true;
 814                         list_del(&tt_info->tt_list);
 815                         kfree(tt_info);
 816                 } else if (slot_found) {
 817                         break;
 818                 }
 819         }
 820 }
 821
 822 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 823                 struct xhci_virt_device *virt_dev,
 824                 struct usb_device *hdev,
 825                 struct usb_tt *tt, gfp_t mem_flags)
 826 {
 827         struct xhci_tt_bw_info          *tt_info;
 828         unsigned int                    num_ports;
 829         int                             i, j;
 830
 831         if (!tt->multi)
 832                 num_ports = 1;
 833         else
 834                 num_ports = hdev->maxchild;
 835
 836         for (i = 0; i < num_ports; i++, tt_info++) {
 837                 struct xhci_interval_bw_table *bw_table;
 838
 839                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 840                 if (!tt_info)
 841                         goto free_tts;
 842                 INIT_LIST_HEAD(&tt_info->tt_list);
 843                 list_add(&tt_info->tt_list,
 844                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 845                 tt_info->slot_id = virt_dev->udev->slot_id;
 846                 if (tt->multi)
 847                         tt_info->ttport = i+1;
 848                 bw_table = &tt_info->bw_table;
 849                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 850                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 851         }
 852         return 0;
 853
 854 free_tts:
 855         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 856         return -ENOMEM;
 857 }
 858
 859
 860 /* All the xhci_tds in the ring's TD list should be freed at this point.
 861  * Should be called with xhci->lock held if there is any chance the TT lists
 862  * will be manipulated by the configure endpoint, allocate device, or update
 863  * hub functions while this function is removing the TT entries from the list.
 864  */
 865 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 866 {
 867         struct xhci_virt_device *dev;
 868         int i;
 869         int old_active_eps = 0;
 870
 871         /* Slot ID 0 is reserved */
 872         if (slot_id == 0 || !xhci->devs[slot_id])
 873                 return;
 874
 875         dev = xhci->devs[slot_id];
 876         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 877         if (!dev)
 878                 return;
 879
 880         if (dev->tt_info)
 881                 old_active_eps = dev->tt_info->active_eps;
 882
 883         for (i = 0; i < 31; ++i) {
 884                 if (dev->eps[i].ring)
 885                         xhci_ring_free(xhci, dev->eps[i].ring);
 886                 if (dev->eps[i].stream_info)
 887                         xhci_free_stream_info(xhci,
 888                                         dev->eps[i].stream_info);
 889                 /* Endpoints on the TT/root port lists should have been removed
 890                  * when usb_disable_device() was called for the device.
 891                  * We can't drop them anyway, because the udev might have gone
 892                  * away by this point, and we can't tell what speed it was.
 893                  */
 894                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 895                         xhci_warn(xhci, "Slot %u endpoint %u "
 896                                         "not removed from BW list!\n",
 897                                         slot_id, i);
 898         }
 899         /* If this is a hub, free the TT(s) from the TT list */
 900         xhci_free_tt_info(xhci, dev, slot_id);
 901         /* If necessary, update the number of active TTs on this root port */
 902         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 903
 904         if (dev->ring_cache) {
 905                 for (i = 0; i < dev->num_rings_cached; i++)
 906                         xhci_ring_free(xhci, dev->ring_cache[i]);
 907                 kfree(dev->ring_cache);
 908         }
 909
 910         if (dev->in_ctx)
 911                 xhci_free_container_ctx(xhci, dev->in_ctx);
 912         if (dev->out_ctx)
 913                 xhci_free_container_ctx(xhci, dev->out_ctx);
 914
 915         kfree(xhci->devs[slot_id]);
 916         xhci->devs[slot_id] = NULL;
 917 }
 918
 919 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 920                 struct usb_device *udev, gfp_t flags)
 921 {
 922         struct xhci_virt_device *dev;
 923         int i;
 924
 925         /* Slot ID 0 is reserved */
 926         if (slot_id == 0 || xhci->devs[slot_id]) {
 927                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 928                 return 0;
 929         }
 930
 931         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 932         if (!xhci->devs[slot_id])
 933                 return 0;
 934         dev = xhci->devs[slot_id];
 935
 936         /* Allocate the (output) device context that will be used in the HC. */
 937         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 938         if (!dev->out_ctx)
 939                 goto fail;
 940
 941         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 942                         (unsigned long long)dev->out_ctx->dma);
 943
 944         /* Allocate the (input) device context for address device command */
 945         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 946         if (!dev->in_ctx)
 947                 goto fail;
 948
 949         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 950                         (unsigned long long)dev->in_ctx->dma);
 951
 952         /* Initialize the cancellation list and watchdog timers for each ep */
 953         for (i = 0; i < 31; i++) {
 954                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 955                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 956                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 957         }
 958
 959         /* Allocate endpoint 0 ring */
 960         dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
 961         if (!dev->eps[0].ring)
 962                 goto fail;
 963
 964         /* Allocate pointers to the ring cache */
 965         dev->ring_cache = kzalloc(
 966                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 967                         flags);
 968         if (!dev->ring_cache)
 969                 goto fail;
 970         dev->num_rings_cached = 0;
 971
 972         init_completion(&dev->cmd_completion);
 973         INIT_LIST_HEAD(&dev->cmd_list);
 974         dev->udev = udev;
 975
 976         /* Point to output device context in dcbaa. */
 977         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 978         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 979                  slot_id,
 980                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 981                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 982
 983         return 1;
 984 fail:
 985         xhci_free_virt_device(xhci, slot_id);
 986         return 0;
 987 }
 988
 989 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 990                 struct usb_device *udev)
 991 {
 992         struct xhci_virt_device *virt_dev;
 993         struct xhci_ep_ctx      *ep0_ctx;
 994         struct xhci_ring        *ep_ring;
 995
 996         virt_dev = xhci->devs[udev->slot_id];
 997         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 998         ep_ring = virt_dev->eps[0].ring;
 999         /*
1000          * FIXME we don't keep track of the dequeue pointer very well after a
1001          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1002          * host to our enqueue pointer.  This should only be called after a
1003          * configured device has reset, so all control transfers should have
1004          * been completed or cancelled before the reset.
1005          */
1006         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1007                                                         ep_ring->enqueue)
1008                                    | ep_ring->cycle_state);
1009 }
1010
1011 /*
1012  * The xHCI roothub may have ports of differing speeds in any order in the port
1013  * status registers.  xhci->port_array provides an array of the port speed for
1014  * each offset into the port status registers.
1015  *
1016  * The xHCI hardware wants to know the roothub port number that the USB device
1017  * is attached to (or the roothub port its ancestor hub is attached to).  All we
1018  * know is the index of that port under either the USB 2.0 or the USB 3.0
1019  * roothub, but that doesn't give us the real index into the HW port status
1020  * registers.  Scan through the xHCI roothub port array, looking for the Nth
1021  * entry of the correct port speed.  Return the port number of that entry.
1022  */
1023 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1024                 struct usb_device *udev)
1025 {
1026         struct usb_device *top_dev;
1027         unsigned int num_similar_speed_ports;
1028         unsigned int faked_port_num;
1029         int i;
1030
1031         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1032                         top_dev = top_dev->parent)
1033                 /* Found device below root hub */;
1034         faked_port_num = top_dev->portnum;
1035         for (i = 0, num_similar_speed_ports = 0;
1036                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
1037                 u8 port_speed = xhci->port_array[i];
1038
1039                 /*
1040                  * Skip ports that don't have known speeds, or have duplicate
1041                  * Extended Capabilities port speed entries.
1042                  */
1043                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1044                         continue;
1045
1046                 /*
1047                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1048                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1049                  * matches the device speed, it's a similar speed port.
1050                  */
1051                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
1052                         num_similar_speed_ports++;
1053                 if (num_similar_speed_ports == faked_port_num)
1054                         /* Roothub ports are numbered from 1 to N */
1055                         return i+1;
1056         }
1057         return 0;
1058 }
1059
1060 /* Setup an xHCI virtual device for a Set Address command */
1061 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1062 {
1063         struct xhci_virt_device *dev;
1064         struct xhci_ep_ctx      *ep0_ctx;
1065         struct xhci_slot_ctx    *slot_ctx;
1066         u32                     port_num;
1067         struct usb_device *top_dev;
1068
1069         dev = xhci->devs[udev->slot_id];
1070         /* Slot ID 0 is reserved */
1071         if (udev->slot_id == 0 || !dev) {
1072                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1073                                 udev->slot_id);
1074                 return -EINVAL;
1075         }
1076         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1077         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1078
1079         /* 3) Only the control endpoint is valid - one endpoint context */
1080         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1081         switch (udev->speed) {
1082         case USB_SPEED_SUPER:
1083                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1084                 break;
1085         case USB_SPEED_HIGH:
1086                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1087                 break;
1088         case USB_SPEED_FULL:
1089                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1090                 break;
1091         case USB_SPEED_LOW:
1092                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1093                 break;
1094         case USB_SPEED_WIRELESS:
1095                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1096                 return -EINVAL;
1097                 break;
1098         default:
1099                 /* Speed was set earlier, this shouldn't happen. */
1100                 BUG();
1101         }
1102         /* Find the root hub port this device is under */
1103         port_num = xhci_find_real_port_number(xhci, udev);
1104         if (!port_num)
1105                 return -EINVAL;
1106         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1107         /* Set the port number in the virtual_device to the faked port number */
1108         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1109                         top_dev = top_dev->parent)
1110                 /* Found device below root hub */;
1111         dev->fake_port = top_dev->portnum;
1112         dev->real_port = port_num;
1113         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1114         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1115
1116         /* Find the right bandwidth table that this device will be a part of.
1117          * If this is a full speed device attached directly to a root port (or a
1118          * decendent of one), it counts as a primary bandwidth domain, not a
1119          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1120          * will never be created for the HS root hub.
1121          */
1122         if (!udev->tt || !udev->tt->hub->parent) {
1123                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1124         } else {
1125                 struct xhci_root_port_bw_info *rh_bw;
1126                 struct xhci_tt_bw_info *tt_bw;
1127
1128                 rh_bw = &xhci->rh_bw[port_num - 1];
1129                 /* Find the right TT. */
1130                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1131                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1132                                 continue;
1133
1134                         if (!dev->udev->tt->multi ||
1135                                         (udev->tt->multi &&
1136                                          tt_bw->ttport == dev->udev->ttport)) {
1137                                 dev->bw_table = &tt_bw->bw_table;
1138                                 dev->tt_info = tt_bw;
1139                                 break;
1140                         }
1141                 }
1142                 if (!dev->tt_info)
1143                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1144         }
1145
1146         /* Is this a LS/FS device under an external HS hub? */
1147         if (udev->tt && udev->tt->hub->parent) {
1148                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1149                                                 (udev->ttport << 8));
1150                 if (udev->tt->multi)
1151                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1152         }
1153         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1154         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1155
1156         /* Step 4 - ring already allocated */
1157         /* Step 5 */
1158         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1159         /*
1160          * XXX: Not sure about wireless USB devices.
1161          */
1162         switch (udev->speed) {
1163         case USB_SPEED_SUPER:
1164                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1165                 break;
1166         case USB_SPEED_HIGH:
1167         /* USB core guesses at a 64-byte max packet first for FS devices */
1168         case USB_SPEED_FULL:
1169                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1170                 break;
1171         case USB_SPEED_LOW:
1172                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1173                 break;
1174         case USB_SPEED_WIRELESS:
1175                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1176                 return -EINVAL;
1177                 break;
1178         default:
1179                 /* New speed? */
1180                 BUG();
1181         }
1182         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1183         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1184
1185         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1186                                    dev->eps[0].ring->cycle_state);
1187
1188         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1189
1190         return 0;
1191 }
1192
1193 /*
1194  * Convert interval expressed as 2^(bInterval - 1) == interval into
1195  * straight exponent value 2^n == interval.
1196  *
1197  */
1198 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1199                 struct usb_host_endpoint *ep)
1200 {
1201         unsigned int interval;
1202
1203         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1204         if (interval != ep->desc.bInterval - 1)
1205                 dev_warn(&udev->dev,
1206                          "ep %#x - rounding interval to %d %sframes\n",
1207                          ep->desc.bEndpointAddress,
1208                          1 << interval,
1209                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1210
1211         if (udev->speed == USB_SPEED_FULL) {
1212                 /*
1213                  * Full speed isoc endpoints specify interval in frames,
1214                  * not microframes. We are using microframes everywhere,
1215                  * so adjust accordingly.
1216                  */
1217                 interval += 3;  /* 1 frame = 2^3 uframes */
1218         }
1219
1220         return interval;
1221 }
1222
1223 /*
1224  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1225  * microframes, rounded down to nearest power of 2.
1226  */
1227 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1228                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1229                 unsigned int min_exponent, unsigned int max_exponent)
1230 {
1231         unsigned int interval;
1232
1233         interval = fls(desc_interval) - 1;
1234         interval = clamp_val(interval, min_exponent, max_exponent);
1235         if ((1 << interval) != desc_interval)
1236                 dev_warn(&udev->dev,
1237                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1238                          ep->desc.bEndpointAddress,
1239                          1 << interval,
1240                          desc_interval);
1241
1242         return interval;
1243 }
1244
1245 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1246                 struct usb_host_endpoint *ep)
1247 {
1248         return xhci_microframes_to_exponent(udev, ep,
1249                         ep->desc.bInterval, 0, 15);
1250 }
1251
1252
1253 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1254                 struct usb_host_endpoint *ep)
1255 {
1256         return xhci_microframes_to_exponent(udev, ep,
1257                         ep->desc.bInterval * 8, 3, 10);
1258 }
1259
1260 /* Return the polling or NAK interval.
1261  *
1262  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1263  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1264  *
1265  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1266  * is set to 0.
1267  */
1268 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1269                 struct usb_host_endpoint *ep)
1270 {
1271         unsigned int interval = 0;
1272
1273         switch (udev->speed) {
1274         case USB_SPEED_HIGH:
1275                 /* Max NAK rate */
1276                 if (usb_endpoint_xfer_control(&ep->desc) ||
1277                     usb_endpoint_xfer_bulk(&ep->desc)) {
1278                         interval = xhci_parse_microframe_interval(udev, ep);
1279                         break;
1280                 }
1281                 /* Fall through - SS and HS isoc/int have same decoding */
1282
1283         case USB_SPEED_SUPER:
1284                 if (usb_endpoint_xfer_int(&ep->desc) ||
1285                     usb_endpoint_xfer_isoc(&ep->desc)) {
1286                         interval = xhci_parse_exponent_interval(udev, ep);
1287                 }
1288                 break;
1289
1290         case USB_SPEED_FULL:
1291                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1292                         interval = xhci_parse_exponent_interval(udev, ep);
1293                         break;
1294                 }
1295                 /*
1296                  * Fall through for interrupt endpoint interval decoding
1297                  * since it uses the same rules as low speed interrupt
1298                  * endpoints.
1299                  */
1300
1301         case USB_SPEED_LOW:
1302                 if (usb_endpoint_xfer_int(&ep->desc) ||
1303                     usb_endpoint_xfer_isoc(&ep->desc)) {
1304
1305                         interval = xhci_parse_frame_interval(udev, ep);
1306                 }
1307                 break;
1308
1309         default:
1310                 BUG();
1311         }
1312         return EP_INTERVAL(interval);
1313 }
1314
1315 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1316  * High speed endpoint descriptors can define "the number of additional
1317  * transaction opportunities per microframe", but that goes in the Max Burst
1318  * endpoint context field.
1319  */
1320 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1321                 struct usb_host_endpoint *ep)
1322 {
1323         if (udev->speed != USB_SPEED_SUPER ||
1324                         !usb_endpoint_xfer_isoc(&ep->desc))
1325                 return 0;
1326         return ep->ss_ep_comp.bmAttributes;
1327 }
1328
1329 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1330                 struct usb_host_endpoint *ep)
1331 {
1332         int in;
1333         u32 type;
1334
1335         in = usb_endpoint_dir_in(&ep->desc);
1336         if (usb_endpoint_xfer_control(&ep->desc)) {
1337                 type = EP_TYPE(CTRL_EP);
1338         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1339                 if (in)
1340                         type = EP_TYPE(BULK_IN_EP);
1341                 else
1342                         type = EP_TYPE(BULK_OUT_EP);
1343         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1344                 if (in)
1345                         type = EP_TYPE(ISOC_IN_EP);
1346                 else
1347                         type = EP_TYPE(ISOC_OUT_EP);
1348         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1349                 if (in)
1350                         type = EP_TYPE(INT_IN_EP);
1351                 else
1352                         type = EP_TYPE(INT_OUT_EP);
1353         } else {
1354                 BUG();
1355         }
1356         return type;
1357 }
1358
1359 /* Return the maximum endpoint service interval time (ESIT) payload.
1360  * Basically, this is the maxpacket size, multiplied by the burst size
1361  * and mult size.
1362  */
1363 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1364                 struct usb_device *udev,
1365                 struct usb_host_endpoint *ep)
1366 {
1367         int max_burst;
1368         int max_packet;
1369
1370         /* Only applies for interrupt or isochronous endpoints */
1371         if (usb_endpoint_xfer_control(&ep->desc) ||
1372                         usb_endpoint_xfer_bulk(&ep->desc))
1373                 return 0;
1374
1375         if (udev->speed == USB_SPEED_SUPER)
1376                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1377
1378         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1379         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1380         /* A 0 in max burst means 1 transfer per ESIT */
1381         return max_packet * (max_burst + 1);
1382 }
1383
1384 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1385  * Drivers will have to call usb_alloc_streams() to do that.
1386  */
1387 int xhci_endpoint_init(struct xhci_hcd *xhci,
1388                 struct xhci_virt_device *virt_dev,
1389                 struct usb_device *udev,
1390                 struct usb_host_endpoint *ep,
1391                 gfp_t mem_flags)
1392 {
1393         unsigned int ep_index;
1394         struct xhci_ep_ctx *ep_ctx;
1395         struct xhci_ring *ep_ring;
1396         unsigned int max_packet;
1397         unsigned int max_burst;
1398         enum xhci_ring_type type;
1399         u32 max_esit_payload;
1400
1401         ep_index = xhci_get_endpoint_index(&ep->desc);
1402         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1403
1404         type = usb_endpoint_type(&ep->desc);
1405         /* Set up the endpoint ring */
1406         virt_dev->eps[ep_index].new_ring =
1407                 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1408         if (!virt_dev->eps[ep_index].new_ring) {
1409                 /* Attempt to use the ring cache */
1410                 if (virt_dev->num_rings_cached == 0)
1411                         return -ENOMEM;
1412                 virt_dev->eps[ep_index].new_ring =
1413                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1414                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1415                 virt_dev->num_rings_cached--;
1416                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1417                                         1, type);
1418         }
1419         virt_dev->eps[ep_index].skip = false;
1420         ep_ring = virt_dev->eps[ep_index].new_ring;
1421         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1422
1423         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1424                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1425
1426         /* FIXME dig Mult and streams info out of ep companion desc */
1427
1428         /* Allow 3 retries for everything but isoc;
1429          * CErr shall be set to 0 for Isoch endpoints.
1430          */
1431         if (!usb_endpoint_xfer_isoc(&ep->desc))
1432                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1433         else
1434                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1435
1436         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1437
1438         /* Set the max packet size and max burst */
1439         switch (udev->speed) {
1440         case USB_SPEED_SUPER:
1441                 max_packet = usb_endpoint_maxp(&ep->desc);
1442                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1443                 /* dig out max burst from ep companion desc */
1444                 max_packet = ep->ss_ep_comp.bMaxBurst;
1445                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1446                 break;
1447         case USB_SPEED_HIGH:
1448                 /* bits 11:12 specify the number of additional transaction
1449                  * opportunities per microframe (USB 2.0, section 9.6.6)
1450                  */
1451                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1452                                 usb_endpoint_xfer_int(&ep->desc)) {
1453                         max_burst = (usb_endpoint_maxp(&ep->desc)
1454                                      & 0x1800) >> 11;
1455                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1456                 }
1457                 /* Fall through */
1458         case USB_SPEED_FULL:
1459         case USB_SPEED_LOW:
1460                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1461                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1462                 break;
1463         default:
1464                 BUG();
1465         }
1466         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1467         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1468
1469         /*
1470          * XXX no idea how to calculate the average TRB buffer length for bulk
1471          * endpoints, as the driver gives us no clue how big each scatter gather
1472          * list entry (or buffer) is going to be.
1473          *
1474          * For isochronous and interrupt endpoints, we set it to the max
1475          * available, until we have new API in the USB core to allow drivers to
1476          * declare how much bandwidth they actually need.
1477          *
1478          * Normally, it would be calculated by taking the total of the buffer
1479          * lengths in the TD and then dividing by the number of TRBs in a TD,
1480          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1481          * use Event Data TRBs, and we don't chain in a link TRB on short
1482          * transfers, we're basically dividing by 1.
1483          *
1484          * xHCI 1.0 specification indicates that the Average TRB Length should
1485          * be set to 8 for control endpoints.
1486          */
1487         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1488                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1489         else
1490                 ep_ctx->tx_info |=
1491                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1492
1493         /* FIXME Debug endpoint context */
1494         return 0;
1495 }
1496
1497 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1498                 struct xhci_virt_device *virt_dev,
1499                 struct usb_host_endpoint *ep)
1500 {
1501         unsigned int ep_index;
1502         struct xhci_ep_ctx *ep_ctx;
1503
1504         ep_index = xhci_get_endpoint_index(&ep->desc);
1505         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1506
1507         ep_ctx->ep_info = 0;
1508         ep_ctx->ep_info2 = 0;
1509         ep_ctx->deq = 0;
1510         ep_ctx->tx_info = 0;
1511         /* Don't free the endpoint ring until the set interface or configuration
1512          * request succeeds.
1513          */
1514 }
1515
1516 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1517 {
1518         bw_info->ep_interval = 0;
1519         bw_info->mult = 0;
1520         bw_info->num_packets = 0;
1521         bw_info->max_packet_size = 0;
1522         bw_info->type = 0;
1523         bw_info->max_esit_payload = 0;
1524 }
1525
1526 void xhci_update_bw_info(struct xhci_hcd *xhci,
1527                 struct xhci_container_ctx *in_ctx,
1528                 struct xhci_input_control_ctx *ctrl_ctx,
1529                 struct xhci_virt_device *virt_dev)
1530 {
1531         struct xhci_bw_info *bw_info;
1532         struct xhci_ep_ctx *ep_ctx;
1533         unsigned int ep_type;
1534         int i;
1535
1536         for (i = 1; i < 31; ++i) {
1537                 bw_info = &virt_dev->eps[i].bw_info;
1538
1539                 /* We can't tell what endpoint type is being dropped, but
1540                  * unconditionally clearing the bandwidth info for non-periodic
1541                  * endpoints should be harmless because the info will never be
1542                  * set in the first place.
1543                  */
1544                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1545                         /* Dropped endpoint */
1546                         xhci_clear_endpoint_bw_info(bw_info);
1547                         continue;
1548                 }
1549
1550                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1551                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1552                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1553
1554                         /* Ignore non-periodic endpoints */
1555                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1556                                         ep_type != ISOC_IN_EP &&
1557                                         ep_type != INT_IN_EP)
1558                                 continue;
1559
1560                         /* Added or changed endpoint */
1561                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1562                                         le32_to_cpu(ep_ctx->ep_info));
1563                         /* Number of packets and mult are zero-based in the
1564                          * input context, but we want one-based for the
1565                          * interval table.
1566                          */
1567                         bw_info->mult = CTX_TO_EP_MULT(
1568                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1569                         bw_info->num_packets = CTX_TO_MAX_BURST(
1570                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1571                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1572                                         le32_to_cpu(ep_ctx->ep_info2));
1573                         bw_info->type = ep_type;
1574                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1575                                         le32_to_cpu(ep_ctx->tx_info));
1576                 }
1577         }
1578 }
1579
1580 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1581  * Useful when you want to change one particular aspect of the endpoint and then
1582  * issue a configure endpoint command.
1583  */
1584 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1585                 struct xhci_container_ctx *in_ctx,
1586                 struct xhci_container_ctx *out_ctx,
1587                 unsigned int ep_index)
1588 {
1589         struct xhci_ep_ctx *out_ep_ctx;
1590         struct xhci_ep_ctx *in_ep_ctx;
1591
1592         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1593         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1594
1595         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1596         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1597         in_ep_ctx->deq = out_ep_ctx->deq;
1598         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1599 }
1600
1601 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1602  * Useful when you want to change one particular aspect of the endpoint and then
1603  * issue a configure endpoint command.  Only the context entries field matters,
1604  * but we'll copy the whole thing anyway.
1605  */
1606 void xhci_slot_copy(struct xhci_hcd *xhci,
1607                 struct xhci_container_ctx *in_ctx,
1608                 struct xhci_container_ctx *out_ctx)
1609 {
1610         struct xhci_slot_ctx *in_slot_ctx;
1611         struct xhci_slot_ctx *out_slot_ctx;
1612
1613         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1614         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1615
1616         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1617         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1618         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1619         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1620 }
1621
1622 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1623 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1624 {
1625         int i;
1626         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1627         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1628
1629         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1630
1631         if (!num_sp)
1632                 return 0;
1633
1634         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1635         if (!xhci->scratchpad)
1636                 goto fail_sp;
1637
1638         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1639                                      num_sp * sizeof(u64),
1640                                      &xhci->scratchpad->sp_dma, flags);
1641         if (!xhci->scratchpad->sp_array)
1642                 goto fail_sp2;
1643
1644         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1645         if (!xhci->scratchpad->sp_buffers)
1646                 goto fail_sp3;
1647
1648         xhci->scratchpad->sp_dma_buffers =
1649                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1650
1651         if (!xhci->scratchpad->sp_dma_buffers)
1652                 goto fail_sp4;
1653
1654         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1655         for (i = 0; i < num_sp; i++) {
1656                 dma_addr_t dma;
1657                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1658                                 flags);
1659                 if (!buf)
1660                         goto fail_sp5;
1661
1662                 xhci->scratchpad->sp_array[i] = dma;
1663                 xhci->scratchpad->sp_buffers[i] = buf;
1664                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1665         }
1666
1667         return 0;
1668
1669  fail_sp5:
1670         for (i = i - 1; i >= 0; i--) {
1671                 dma_free_coherent(dev, xhci->page_size,
1672                                     xhci->scratchpad->sp_buffers[i],
1673                                     xhci->scratchpad->sp_dma_buffers[i]);
1674         }
1675         kfree(xhci->scratchpad->sp_dma_buffers);
1676
1677  fail_sp4:
1678         kfree(xhci->scratchpad->sp_buffers);
1679
1680  fail_sp3:
1681         dma_free_coherent(dev, num_sp * sizeof(u64),
1682                             xhci->scratchpad->sp_array,
1683                             xhci->scratchpad->sp_dma);
1684
1685  fail_sp2:
1686         kfree(xhci->scratchpad);
1687         xhci->scratchpad = NULL;
1688
1689  fail_sp:
1690         return -ENOMEM;
1691 }
1692
1693 static void scratchpad_free(struct xhci_hcd *xhci)
1694 {
1695         int num_sp;
1696         int i;
1697         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1698
1699         if (!xhci->scratchpad)
1700                 return;
1701
1702         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1703
1704         for (i = 0; i < num_sp; i++) {
1705                 dma_free_coherent(&pdev->dev, xhci->page_size,
1706                                     xhci->scratchpad->sp_buffers[i],
1707                                     xhci->scratchpad->sp_dma_buffers[i]);
1708         }
1709         kfree(xhci->scratchpad->sp_dma_buffers);
1710         kfree(xhci->scratchpad->sp_buffers);
1711         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1712                             xhci->scratchpad->sp_array,
1713                             xhci->scratchpad->sp_dma);
1714         kfree(xhci->scratchpad);
1715         xhci->scratchpad = NULL;
1716 }
1717
1718 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1719                 bool allocate_in_ctx, bool allocate_completion,
1720                 gfp_t mem_flags)
1721 {
1722         struct xhci_command *command;
1723
1724         command = kzalloc(sizeof(*command), mem_flags);
1725         if (!command)
1726                 return NULL;
1727
1728         if (allocate_in_ctx) {
1729                 command->in_ctx =
1730                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1731                                         mem_flags);
1732                 if (!command->in_ctx) {
1733                         kfree(command);
1734                         return NULL;
1735                 }
1736         }
1737
1738         if (allocate_completion) {
1739                 command->completion =
1740                         kzalloc(sizeof(struct completion), mem_flags);
1741                 if (!command->completion) {
1742                         xhci_free_container_ctx(xhci, command->in_ctx);
1743                         kfree(command);
1744                         return NULL;
1745                 }
1746                 init_completion(command->completion);
1747         }
1748
1749         command->status = 0;
1750         INIT_LIST_HEAD(&command->cmd_list);
1751         return command;
1752 }
1753
1754 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1755 {
1756         if (urb_priv) {
1757                 kfree(urb_priv->td[0]);
1758                 kfree(urb_priv);
1759         }
1760 }
1761
1762 void xhci_free_command(struct xhci_hcd *xhci,
1763                 struct xhci_command *command)
1764 {
1765         xhci_free_container_ctx(xhci,
1766                         command->in_ctx);
1767         kfree(command->completion);
1768         kfree(command);
1769 }
1770
1771 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1772 {
1773         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1774         struct dev_info *dev_info, *next;
1775         unsigned long   flags;
1776         int size;
1777         int i, j, num_ports;
1778
1779         /* Free the Event Ring Segment Table and the actual Event Ring */
1780         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1781         if (xhci->erst.entries)
1782                 dma_free_coherent(&pdev->dev, size,
1783                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1784         xhci->erst.entries = NULL;
1785         xhci_dbg(xhci, "Freed ERST\n");
1786         if (xhci->event_ring)
1787                 xhci_ring_free(xhci, xhci->event_ring);
1788         xhci->event_ring = NULL;
1789         xhci_dbg(xhci, "Freed event ring\n");
1790
1791         if (xhci->lpm_command)
1792                 xhci_free_command(xhci, xhci->lpm_command);
1793         xhci->cmd_ring_reserved_trbs = 0;
1794         if (xhci->cmd_ring)
1795                 xhci_ring_free(xhci, xhci->cmd_ring);
1796         xhci->cmd_ring = NULL;
1797         xhci_dbg(xhci, "Freed command ring\n");
1798
1799         for (i = 1; i < MAX_HC_SLOTS; ++i)
1800                 xhci_free_virt_device(xhci, i);
1801
1802         if (xhci->segment_pool)
1803                 dma_pool_destroy(xhci->segment_pool);
1804         xhci->segment_pool = NULL;
1805         xhci_dbg(xhci, "Freed segment pool\n");
1806
1807         if (xhci->device_pool)
1808                 dma_pool_destroy(xhci->device_pool);
1809         xhci->device_pool = NULL;
1810         xhci_dbg(xhci, "Freed device context pool\n");
1811
1812         if (xhci->small_streams_pool)
1813                 dma_pool_destroy(xhci->small_streams_pool);
1814         xhci->small_streams_pool = NULL;
1815         xhci_dbg(xhci, "Freed small stream array pool\n");
1816
1817         if (xhci->medium_streams_pool)
1818                 dma_pool_destroy(xhci->medium_streams_pool);
1819         xhci->medium_streams_pool = NULL;
1820         xhci_dbg(xhci, "Freed medium stream array pool\n");
1821
1822         if (xhci->dcbaa)
1823                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1824                                 xhci->dcbaa, xhci->dcbaa->dma);
1825         xhci->dcbaa = NULL;
1826
1827         scratchpad_free(xhci);
1828
1829         spin_lock_irqsave(&xhci->lock, flags);
1830         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1831                 list_del(&dev_info->list);
1832                 kfree(dev_info);
1833         }
1834         spin_unlock_irqrestore(&xhci->lock, flags);
1835
1836         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1837         for (i = 0; i < num_ports; i++) {
1838                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1839                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1840                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1841                         while (!list_empty(ep))
1842                                 list_del_init(ep->next);
1843                 }
1844         }
1845
1846         for (i = 0; i < num_ports; i++) {
1847                 struct xhci_tt_bw_info *tt, *n;
1848                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1849                         list_del(&tt->tt_list);
1850                         kfree(tt);
1851                 }
1852         }
1853
1854         xhci->num_usb2_ports = 0;
1855         xhci->num_usb3_ports = 0;
1856         xhci->num_active_eps = 0;
1857         kfree(xhci->usb2_ports);
1858         kfree(xhci->usb3_ports);
1859         kfree(xhci->port_array);
1860         kfree(xhci->rh_bw);
1861
1862         xhci->page_size = 0;
1863         xhci->page_shift = 0;
1864         xhci->bus_state[0].bus_suspended = 0;
1865         xhci->bus_state[1].bus_suspended = 0;
1866 }
1867
1868 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1869                 struct xhci_segment *input_seg,
1870                 union xhci_trb *start_trb,
1871                 union xhci_trb *end_trb,
1872                 dma_addr_t input_dma,
1873                 struct xhci_segment *result_seg,
1874                 char *test_name, int test_number)
1875 {
1876         unsigned long long start_dma;
1877         unsigned long long end_dma;
1878         struct xhci_segment *seg;
1879
1880         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1881         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1882
1883         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1884         if (seg != result_seg) {
1885                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1886                                 test_name, test_number);
1887                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1888                                 "input DMA 0x%llx\n",
1889                                 input_seg,
1890                                 (unsigned long long) input_dma);
1891                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1892                                 "ending TRB %p (0x%llx DMA)\n",
1893                                 start_trb, start_dma,
1894                                 end_trb, end_dma);
1895                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1896                                 result_seg, seg);
1897                 return -1;
1898         }
1899         return 0;
1900 }
1901
1902 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1903 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1904 {
1905         struct {
1906                 dma_addr_t              input_dma;
1907                 struct xhci_segment     *result_seg;
1908         } simple_test_vector [] = {
1909                 /* A zeroed DMA field should fail */
1910                 { 0, NULL },
1911                 /* One TRB before the ring start should fail */
1912                 { xhci->event_ring->first_seg->dma - 16, NULL },
1913                 /* One byte before the ring start should fail */
1914                 { xhci->event_ring->first_seg->dma - 1, NULL },
1915                 /* Starting TRB should succeed */
1916                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1917                 /* Ending TRB should succeed */
1918                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1919                         xhci->event_ring->first_seg },
1920                 /* One byte after the ring end should fail */
1921                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1922                 /* One TRB after the ring end should fail */
1923                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1924                 /* An address of all ones should fail */
1925                 { (dma_addr_t) (~0), NULL },
1926         };
1927         struct {
1928                 struct xhci_segment     *input_seg;
1929                 union xhci_trb          *start_trb;
1930                 union xhci_trb          *end_trb;
1931                 dma_addr_t              input_dma;
1932                 struct xhci_segment     *result_seg;
1933         } complex_test_vector [] = {
1934                 /* Test feeding a valid DMA address from a different ring */
1935                 {       .input_seg = xhci->event_ring->first_seg,
1936                         .start_trb = xhci->event_ring->first_seg->trbs,
1937                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1938                         .input_dma = xhci->cmd_ring->first_seg->dma,
1939                         .result_seg = NULL,
1940                 },
1941                 /* Test feeding a valid end TRB from a different ring */
1942                 {       .input_seg = xhci->event_ring->first_seg,
1943                         .start_trb = xhci->event_ring->first_seg->trbs,
1944                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1945                         .input_dma = xhci->cmd_ring->first_seg->dma,
1946                         .result_seg = NULL,
1947                 },
1948                 /* Test feeding a valid start and end TRB from a different ring */
1949                 {       .input_seg = xhci->event_ring->first_seg,
1950                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1951                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1952                         .input_dma = xhci->cmd_ring->first_seg->dma,
1953                         .result_seg = NULL,
1954                 },
1955                 /* TRB in this ring, but after this TD */
1956                 {       .input_seg = xhci->event_ring->first_seg,
1957                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1958                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1959                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1960                         .result_seg = NULL,
1961                 },
1962                 /* TRB in this ring, but before this TD */
1963                 {       .input_seg = xhci->event_ring->first_seg,
1964                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1965                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1966                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1967                         .result_seg = NULL,
1968                 },
1969                 /* TRB in this ring, but after this wrapped TD */
1970                 {       .input_seg = xhci->event_ring->first_seg,
1971                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1972                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1973                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1974                         .result_seg = NULL,
1975                 },
1976                 /* TRB in this ring, but before this wrapped TD */
1977                 {       .input_seg = xhci->event_ring->first_seg,
1978                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1979                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1980                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1981                         .result_seg = NULL,
1982                 },
1983                 /* TRB not in this ring, and we have a wrapped TD */
1984                 {       .input_seg = xhci->event_ring->first_seg,
1985                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1986                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1987                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1988                         .result_seg = NULL,
1989                 },
1990         };
1991
1992         unsigned int num_tests;
1993         int i, ret;
1994
1995         num_tests = ARRAY_SIZE(simple_test_vector);
1996         for (i = 0; i < num_tests; i++) {
1997                 ret = xhci_test_trb_in_td(xhci,
1998                                 xhci->event_ring->first_seg,
1999                                 xhci->event_ring->first_seg->trbs,
2000                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2001                                 simple_test_vector[i].input_dma,
2002                                 simple_test_vector[i].result_seg,
2003                                 "Simple", i);
2004                 if (ret < 0)
2005                         return ret;
2006         }
2007
2008         num_tests = ARRAY_SIZE(complex_test_vector);
2009         for (i = 0; i < num_tests; i++) {
2010                 ret = xhci_test_trb_in_td(xhci,
2011                                 complex_test_vector[i].input_seg,
2012                                 complex_test_vector[i].start_trb,
2013                                 complex_test_vector[i].end_trb,
2014                                 complex_test_vector[i].input_dma,
2015                                 complex_test_vector[i].result_seg,
2016                                 "Complex", i);
2017                 if (ret < 0)
2018                         return ret;
2019         }
2020         xhci_dbg(xhci, "TRB math tests passed.\n");
2021         return 0;
2022 }
2023
2024 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2025 {
2026         u64 temp;
2027         dma_addr_t deq;
2028
2029         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2030                         xhci->event_ring->dequeue);
2031         if (deq == 0 && !in_interrupt())
2032                 xhci_warn(xhci, "WARN something wrong with SW event ring "
2033                                 "dequeue ptr.\n");
2034         /* Update HC event ring dequeue pointer */
2035         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2036         temp &= ERST_PTR_MASK;
2037         /* Don't clear the EHB bit (which is RW1C) because
2038          * there might be more events to service.
2039          */
2040         temp &= ~ERST_EHB;
2041         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2042                         "preserving EHB bit\n");
2043         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2044                         &xhci->ir_set->erst_dequeue);
2045 }
2046
2047 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2048                 __le32 __iomem *addr, u8 major_revision)
2049 {
2050         u32 temp, port_offset, port_count;
2051         int i;
2052
2053         if (major_revision > 0x03) {
2054                 xhci_warn(xhci, "Ignoring unknown port speed, "
2055                                 "Ext Cap %p, revision = 0x%x\n",
2056                                 addr, major_revision);
2057                 /* Ignoring port protocol we can't understand. FIXME */
2058                 return;
2059         }
2060
2061         /* Port offset and count in the third dword, see section 7.2 */
2062         temp = xhci_readl(xhci, addr + 2);
2063         port_offset = XHCI_EXT_PORT_OFF(temp);
2064         port_count = XHCI_EXT_PORT_COUNT(temp);
2065         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2066                         "count = %u, revision = 0x%x\n",
2067                         addr, port_offset, port_count, major_revision);
2068         /* Port count includes the current port offset */
2069         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2070                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2071                 return;
2072
2073         /* Check the host's USB2 LPM capability */
2074         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2075                         (temp & XHCI_L1C)) {
2076                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2077                 xhci->sw_lpm_support = 1;
2078         }
2079
2080         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2081                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2082                 xhci->sw_lpm_support = 1;
2083                 if (temp & XHCI_HLC) {
2084                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2085                         xhci->hw_lpm_support = 1;
2086                 }
2087         }
2088
2089         port_offset--;
2090         for (i = port_offset; i < (port_offset + port_count); i++) {
2091                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2092                 if (xhci->port_array[i] != 0) {
2093                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2094                                         " port %u\n", addr, i);
2095                         xhci_warn(xhci, "Port was marked as USB %u, "
2096                                         "duplicated as USB %u\n",
2097                                         xhci->port_array[i], major_revision);
2098                         /* Only adjust the roothub port counts if we haven't
2099                          * found a similar duplicate.
2100                          */
2101                         if (xhci->port_array[i] != major_revision &&
2102                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2103                                 if (xhci->port_array[i] == 0x03)
2104                                         xhci->num_usb3_ports--;
2105                                 else
2106                                         xhci->num_usb2_ports--;
2107                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2108                         }
2109                         /* FIXME: Should we disable the port? */
2110                         continue;
2111                 }
2112                 xhci->port_array[i] = major_revision;
2113                 if (major_revision == 0x03)
2114                         xhci->num_usb3_ports++;
2115                 else
2116                         xhci->num_usb2_ports++;
2117         }
2118         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2119 }
2120
2121 /*
2122  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2123  * specify what speeds each port is supposed to be.  We can't count on the port
2124  * speed bits in the PORTSC register being correct until a device is connected,
2125  * but we need to set up the two fake roothubs with the correct number of USB
2126  * 3.0 and USB 2.0 ports at host controller initialization time.
2127  */
2128 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2129 {
2130         __le32 __iomem *addr;
2131         u32 offset;
2132         unsigned int num_ports;
2133         int i, j, port_index;
2134
2135         addr = &xhci->cap_regs->hcc_params;
2136         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2137         if (offset == 0) {
2138                 xhci_err(xhci, "No Extended Capability registers, "
2139                                 "unable to set up roothub.\n");
2140                 return -ENODEV;
2141         }
2142
2143         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2144         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2145         if (!xhci->port_array)
2146                 return -ENOMEM;
2147
2148         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2149         if (!xhci->rh_bw)
2150                 return -ENOMEM;
2151         for (i = 0; i < num_ports; i++) {
2152                 struct xhci_interval_bw_table *bw_table;
2153
2154                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2155                 bw_table = &xhci->rh_bw[i].bw_table;
2156                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2157                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2158         }
2159
2160         /*
2161          * For whatever reason, the first capability offset is from the
2162          * capability register base, not from the HCCPARAMS register.
2163          * See section 5.3.6 for offset calculation.
2164          */
2165         addr = &xhci->cap_regs->hc_capbase + offset;
2166         while (1) {
2167                 u32 cap_id;
2168
2169                 cap_id = xhci_readl(xhci, addr);
2170                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2171                         xhci_add_in_port(xhci, num_ports, addr,
2172                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2173                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2174                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2175                                 == num_ports)
2176                         break;
2177                 /*
2178                  * Once you're into the Extended Capabilities, the offset is
2179                  * always relative to the register holding the offset.
2180                  */
2181                 addr += offset;
2182         }
2183
2184         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2185                 xhci_warn(xhci, "No ports on the roothubs?\n");
2186                 return -ENODEV;
2187         }
2188         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2189                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2190
2191         /* Place limits on the number of roothub ports so that the hub
2192          * descriptors aren't longer than the USB core will allocate.
2193          */
2194         if (xhci->num_usb3_ports > 15) {
2195                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2196                 xhci->num_usb3_ports = 15;
2197         }
2198         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2199                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2200                                 USB_MAXCHILDREN);
2201                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2202         }
2203
2204         /*
2205          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2206          * Not sure how the USB core will handle a hub with no ports...
2207          */
2208         if (xhci->num_usb2_ports) {
2209                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2210                                 xhci->num_usb2_ports, flags);
2211                 if (!xhci->usb2_ports)
2212                         return -ENOMEM;
2213
2214                 port_index = 0;
2215                 for (i = 0; i < num_ports; i++) {
2216                         if (xhci->port_array[i] == 0x03 ||
2217                                         xhci->port_array[i] == 0 ||
2218                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2219                                 continue;
2220
2221                         xhci->usb2_ports[port_index] =
2222                                 &xhci->op_regs->port_status_base +
2223                                 NUM_PORT_REGS*i;
2224                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2225                                         "addr = %p\n", i,
2226                                         xhci->usb2_ports[port_index]);
2227                         port_index++;
2228                         if (port_index == xhci->num_usb2_ports)
2229                                 break;
2230                 }
2231         }
2232         if (xhci->num_usb3_ports) {
2233                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2234                                 xhci->num_usb3_ports, flags);
2235                 if (!xhci->usb3_ports)
2236                         return -ENOMEM;
2237
2238                 port_index = 0;
2239                 for (i = 0; i < num_ports; i++)
2240                         if (xhci->port_array[i] == 0x03) {
2241                                 xhci->usb3_ports[port_index] =
2242                                         &xhci->op_regs->port_status_base +
2243                                         NUM_PORT_REGS*i;
2244                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2245                                                 "addr = %p\n", i,
2246                                                 xhci->usb3_ports[port_index]);
2247                                 port_index++;
2248                                 if (port_index == xhci->num_usb3_ports)
2249                                         break;
2250                         }
2251         }
2252         return 0;
2253 }
2254
2255 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2256 {
2257         dma_addr_t      dma;
2258         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2259         unsigned int    val, val2;
2260         u64             val_64;
2261         struct xhci_segment     *seg;
2262         u32 page_size, temp;
2263         int i;
2264
2265         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2266         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2267         for (i = 0; i < 16; i++) {
2268                 if ((0x1 & page_size) != 0)
2269                         break;
2270                 page_size = page_size >> 1;
2271         }
2272         if (i < 16)
2273                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2274         else
2275                 xhci_warn(xhci, "WARN: no supported page size\n");
2276         /* Use 4K pages, since that's common and the minimum the HC supports */
2277         xhci->page_shift = 12;
2278         xhci->page_size = 1 << xhci->page_shift;
2279         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2280
2281         /*
2282          * Program the Number of Device Slots Enabled field in the CONFIG
2283          * register with the max value of slots the HC can handle.
2284          */
2285         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2286         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2287                         (unsigned int) val);
2288         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2289         val |= (val2 & ~HCS_SLOTS_MASK);
2290         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2291                         (unsigned int) val);
2292         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2293
2294         /*
2295          * Section 5.4.8 - doorbell array must be
2296          * "physically contiguous and 64-byte (cache line) aligned".
2297          */
2298         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2299                         GFP_KERNEL);
2300         if (!xhci->dcbaa)
2301                 goto fail;
2302         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2303         xhci->dcbaa->dma = dma;
2304         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2305                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2306         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2307
2308         /*
2309          * Initialize the ring segment pool.  The ring must be a contiguous
2310          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2311          * however, the command ring segment needs 64-byte aligned segments,
2312          * so we pick the greater alignment need.
2313          */
2314         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2315                         SEGMENT_SIZE, 64, xhci->page_size);
2316
2317         /* See Table 46 and Note on Figure 55 */
2318         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2319                         2112, 64, xhci->page_size);
2320         if (!xhci->segment_pool || !xhci->device_pool)
2321                 goto fail;
2322
2323         /* Linear stream context arrays don't have any boundary restrictions,
2324          * and only need to be 16-byte aligned.
2325          */
2326         xhci->small_streams_pool =
2327                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2328                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2329         xhci->medium_streams_pool =
2330                 dma_pool_create("xHCI 1KB stream ctx arrays",
2331                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2332         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2333          * will be allocated with dma_alloc_coherent()
2334          */
2335
2336         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2337                 goto fail;
2338
2339         /* Set up the command ring to have one segments for now. */
2340         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2341         if (!xhci->cmd_ring)
2342                 goto fail;
2343         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2344         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2345                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2346
2347         /* Set the address in the Command Ring Control register */
2348         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2349         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2350                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2351                 xhci->cmd_ring->cycle_state;
2352         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2353         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2354         xhci_dbg_cmd_ptrs(xhci);
2355
2356         xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2357         if (!xhci->lpm_command)
2358                 goto fail;
2359
2360         /* Reserve one command ring TRB for disabling LPM.
2361          * Since the USB core grabs the shared usb_bus bandwidth mutex before
2362          * disabling LPM, we only need to reserve one TRB for all devices.
2363          */
2364         xhci->cmd_ring_reserved_trbs++;
2365
2366         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2367         val &= DBOFF_MASK;
2368         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2369                         " from cap regs base addr\n", val);
2370         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2371         xhci_dbg_regs(xhci);
2372         xhci_print_run_regs(xhci);
2373         /* Set ir_set to interrupt register set 0 */
2374         xhci->ir_set = &xhci->run_regs->ir_set[0];
2375
2376         /*
2377          * Event ring setup: Allocate a normal ring, but also setup
2378          * the event ring segment table (ERST).  Section 4.9.3.
2379          */
2380         xhci_dbg(xhci, "// Allocating event ring\n");
2381         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2382                                                 flags);
2383         if (!xhci->event_ring)
2384                 goto fail;
2385         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2386                 goto fail;
2387
2388         xhci->erst.entries = dma_alloc_coherent(dev,
2389                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2390                         GFP_KERNEL);
2391         if (!xhci->erst.entries)
2392                 goto fail;
2393         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2394                         (unsigned long long)dma);
2395
2396         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2397         xhci->erst.num_entries = ERST_NUM_SEGS;
2398         xhci->erst.erst_dma_addr = dma;
2399         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2400                         xhci->erst.num_entries,
2401                         xhci->erst.entries,
2402                         (unsigned long long)xhci->erst.erst_dma_addr);
2403
2404         /* set ring base address and size for each segment table entry */
2405         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2406                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2407                 entry->seg_addr = cpu_to_le64(seg->dma);
2408                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2409                 entry->rsvd = 0;
2410                 seg = seg->next;
2411         }
2412
2413         /* set ERST count with the number of entries in the segment table */
2414         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2415         val &= ERST_SIZE_MASK;
2416         val |= ERST_NUM_SEGS;
2417         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2418                         val);
2419         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2420
2421         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2422         /* set the segment table base address */
2423         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2424                         (unsigned long long)xhci->erst.erst_dma_addr);
2425         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2426         val_64 &= ERST_PTR_MASK;
2427         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2428         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2429
2430         /* Set the event ring dequeue address */
2431         xhci_set_hc_event_deq(xhci);
2432         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2433         xhci_print_ir_set(xhci, 0);
2434
2435         /*
2436          * XXX: Might need to set the Interrupter Moderation Register to
2437          * something other than the default (~1ms minimum between interrupts).
2438          * See section 5.5.1.2.
2439          */
2440         init_completion(&xhci->addr_dev);
2441         for (i = 0; i < MAX_HC_SLOTS; ++i)
2442                 xhci->devs[i] = NULL;
2443         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2444                 xhci->bus_state[0].resume_done[i] = 0;
2445                 xhci->bus_state[1].resume_done[i] = 0;
2446         }
2447
2448         if (scratchpad_alloc(xhci, flags))
2449                 goto fail;
2450         if (xhci_setup_port_arrays(xhci, flags))
2451                 goto fail;
2452
2453         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2454
2455         /* Enable USB 3.0 device notifications for function remote wake, which
2456          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2457          * U3 (device suspend).
2458          */
2459         temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2460         temp &= ~DEV_NOTE_MASK;
2461         temp |= DEV_NOTE_FWAKE;
2462         xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2463
2464         return 0;
2465
2466 fail:
2467         xhci_warn(xhci, "Couldn't initialize memory\n");
2468         xhci_halt(xhci);
2469         xhci_reset(xhci);
2470         xhci_mem_cleanup(xhci);
2471         return -ENOMEM;
2472 }