drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         if ((psi & PLT_MASK) == PLT_SYM) {
 143                         /* Symmetric, create SSA RX and TX from one PSI entry */
 144                                 put_unaligned_le32(psi, &buf[offset]);
 145                                 psi |= 1 << 7;  /* turn entry to TX */
 146                                 offset += 4;
 147                                 if (offset >= desc_size + ssa_size)
 148                                         return desc_size + ssa_size;
 149                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 150                                 /* Asymetric RX, flip bits 7:6 for SSA */
 151                                 psi ^= PLT_MASK;
 152                         }
 153                         put_unaligned_le32(psi, &buf[offset]);
 154                         offset += 4;
 155                         if (offset >= desc_size + ssa_size)
 156                                 return desc_size + ssa_size;
 157                 }
 158         }
 159         /* ssa_size is 0 for other than usb 3.1 hosts */
 160         return desc_size + ssa_size;
 161 }
 162
 163 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 164                 struct usb_hub_descriptor *desc, int ports)
 165 {
 166         u16 temp;
 167
 168         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 169         desc->bHubContrCurrent = 0;
 170
 171         desc->bNbrPorts = ports;
 172         temp = 0;
 173         /* Bits 1:0 - support per-port power switching, or power always on */
 174         if (HCC_PPC(xhci->hcc_params))
 175                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 176         else
 177                 temp |= HUB_CHAR_NO_LPSM;
 178         /* Bit  2 - root hubs are not part of a compound device */
 179         /* Bits 4:3 - individual port over current protection */
 180         temp |= HUB_CHAR_INDV_PORT_OCPM;
 181         /* Bits 6:5 - no TTs in root ports */
 182         /* Bit  7 - no port indicators */
 183         desc->wHubCharacteristics = cpu_to_le16(temp);
 184 }
 185
 186 /* Fill in the USB 2.0 roothub descriptor */
 187 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 188                 struct usb_hub_descriptor *desc)
 189 {
 190         int ports;
 191         u16 temp;
 192         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 193         u32 portsc;
 194         unsigned int i;
 195
 196         ports = xhci->num_usb2_ports;
 197
 198         xhci_common_hub_descriptor(xhci, desc, ports);
 199         desc->bDescriptorType = USB_DT_HUB;
 200         temp = 1 + (ports / 8);
 201         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 202
 203         /* The Device Removable bits are reported on a byte granularity.
 204          * If the port doesn't exist within that byte, the bit is set to 0.
 205          */
 206         memset(port_removable, 0, sizeof(port_removable));
 207         for (i = 0; i < ports; i++) {
 208                 portsc = readl(xhci->usb2_ports[i]);
 209                 /* If a device is removable, PORTSC reports a 0, same as in the
 210                  * hub descriptor DeviceRemovable bits.
 211                  */
 212                 if (portsc & PORT_DEV_REMOVE)
 213                         /* This math is hairy because bit 0 of DeviceRemovable
 214                          * is reserved, and bit 1 is for port 1, etc.
 215                          */
 216                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 217         }
 218
 219         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 220          * ports on it.  The USB 2.0 specification says that there are two
 221          * variable length fields at the end of the hub descriptor:
 222          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 223          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 224          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 225          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 226          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 227          * set of ports that actually exist.
 228          */
 229         memset(desc->u.hs.DeviceRemovable, 0xff,
 230                         sizeof(desc->u.hs.DeviceRemovable));
 231         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 232                         sizeof(desc->u.hs.PortPwrCtrlMask));
 233
 234         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 235                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 236                                 sizeof(__u8));
 237 }
 238
 239 /* Fill in the USB 3.0 roothub descriptor */
 240 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 241                 struct usb_hub_descriptor *desc)
 242 {
 243         int ports;
 244         u16 port_removable;
 245         u32 portsc;
 246         unsigned int i;
 247
 248         ports = xhci->num_usb3_ports;
 249         xhci_common_hub_descriptor(xhci, desc, ports);
 250         desc->bDescriptorType = USB_DT_SS_HUB;
 251         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 252
 253         /* header decode latency should be zero for roothubs,
 254          * see section 4.23.5.2.
 255          */
 256         desc->u.ss.bHubHdrDecLat = 0;
 257         desc->u.ss.wHubDelay = 0;
 258
 259         port_removable = 0;
 260         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 261         for (i = 0; i < ports; i++) {
 262                 portsc = readl(xhci->usb3_ports[i]);
 263                 if (portsc & PORT_DEV_REMOVE)
 264                         port_removable |= 1 << (i + 1);
 265         }
 266
 267         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 268 }
 269
 270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 271                 struct usb_hub_descriptor *desc)
 272 {
 273
 274         if (hcd->speed >= HCD_USB3)
 275                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 276         else
 277                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 278
 279 }
 280
 281 static unsigned int xhci_port_speed(unsigned int port_status)
 282 {
 283         if (DEV_LOWSPEED(port_status))
 284                 return USB_PORT_STAT_LOW_SPEED;
 285         if (DEV_HIGHSPEED(port_status))
 286                 return USB_PORT_STAT_HIGH_SPEED;
 287         /*
 288          * FIXME: Yes, we should check for full speed, but the core uses that as
 289          * a default in portspeed() in usb/core/hub.c (which is the only place
 290          * USB_PORT_STAT_*_SPEED is used).
 291          */
 292         return 0;
 293 }
 294
 295 /*
 296  * These bits are Read Only (RO) and should be saved and written to the
 297  * registers: 0, 3, 10:13, 30
 298  * connect status, over-current status, port speed, and device removable.
 299  * connect status and port speed are also sticky - meaning they're in
 300  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 301  */
 302 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 303 /*
 304  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 305  * bits 5:8, 9, 14:15, 25:27
 306  * link state, port power, port indicator state, "wake on" enable state
 307  */
 308 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 309 /*
 310  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 311  * bit 4 (port reset)
 312  */
 313 #define XHCI_PORT_RW1S  ((1<<4))
 314 /*
 315  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 316  * bits 1, 17, 18, 19, 20, 21, 22, 23
 317  * port enable/disable, and
 318  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 319  * over-current, reset, link state, and L1 change
 320  */
 321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 322 /*
 323  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 324  * latched in
 325  */
 326 #define XHCI_PORT_RW    ((1<<16))
 327 /*
 328  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 329  * bits 2, 24, 28:31
 330  */
 331 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 332
 333 /*
 334  * Given a port state, this function returns a value that would result in the
 335  * port being in the same state, if the value was written to the port status
 336  * control register.
 337  * Save Read Only (RO) bits and save read/write bits where
 338  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 339  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 340  */
 341 u32 xhci_port_state_to_neutral(u32 state)
 342 {
 343         /* Save read-only status and port state */
 344         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 345 }
 346
 347 /*
 348  * find slot id based on port number.
 349  * @port: The one-based port number from one of the two split roothubs.
 350  */
 351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 352                 u16 port)
 353 {
 354         int slot_id;
 355         int i;
 356         enum usb_device_speed speed;
 357
 358         slot_id = 0;
 359         for (i = 0; i < MAX_HC_SLOTS; i++) {
 360                 if (!xhci->devs[i])
 361                         continue;
 362                 speed = xhci->devs[i]->udev->speed;
 363                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 364                                 && xhci->devs[i]->fake_port == port) {
 365                         slot_id = i;
 366                         break;
 367                 }
 368         }
 369
 370         return slot_id;
 371 }
 372
 373 /*
 374  * Stop device
 375  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 376  * to complete.
 377  * suspend will set to 1, if suspend bit need to set in command.
 378  */
 379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 380 {
 381         struct xhci_virt_device *virt_dev;
 382         struct xhci_command *cmd;
 383         unsigned long flags;
 384         int ret;
 385         int i;
 386
 387         ret = 0;
 388         virt_dev = xhci->devs[slot_id];
 389         if (!virt_dev)
 390                 return -ENODEV;
 391
 392         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 393         if (!cmd) {
 394                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 395                 return -ENOMEM;
 396         }
 397
 398         spin_lock_irqsave(&xhci->lock, flags);
 399         for (i = LAST_EP_INDEX; i > 0; i--) {
 400                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 401                         struct xhci_command *command;
 402                         command = xhci_alloc_command(xhci, false, false,
 403                                                      GFP_NOWAIT);
 404                         if (!command) {
 405                                 spin_unlock_irqrestore(&xhci->lock, flags);
 406                                 xhci_free_command(xhci, cmd);
 407                                 return -ENOMEM;
 408
 409                         }
 410                         xhci_queue_stop_endpoint(xhci, command, slot_id, i,
 411                                                  suspend);
 412                 }
 413         }
 414         xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 415         xhci_ring_cmd_db(xhci);
 416         spin_unlock_irqrestore(&xhci->lock, flags);
 417
 418         /* Wait for last stop endpoint command to finish */
 419         wait_for_completion(cmd->completion);
 420
 421         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 422                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 423                 ret = -ETIME;
 424         }
 425         xhci_free_command(xhci, cmd);
 426         return ret;
 427 }
 428
 429 /*
 430  * Ring device, it rings the all doorbells unconditionally.
 431  */
 432 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 433 {
 434         int i, s;
 435         struct xhci_virt_ep *ep;
 436
 437         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 438                 ep = &xhci->devs[slot_id]->eps[i];
 439
 440                 if (ep->ep_state & EP_HAS_STREAMS) {
 441                         for (s = 1; s < ep->stream_info->num_streams; s++)
 442                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 443                 } else if (ep->ring && ep->ring->dequeue) {
 444                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 445                 }
 446         }
 447
 448         return;
 449 }
 450
 451 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 452                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 453 {
 454         /* Don't allow the USB core to disable SuperSpeed ports. */
 455         if (hcd->speed >= HCD_USB3) {
 456                 xhci_dbg(xhci, "Ignoring request to disable "
 457                                 "SuperSpeed port.\n");
 458                 return;
 459         }
 460
 461         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 462                 xhci_dbg(xhci,
 463                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 464                 return;
 465         }
 466
 467         /* Write 1 to disable the port */
 468         writel(port_status | PORT_PE, addr);
 469         port_status = readl(addr);
 470         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 471                         wIndex, port_status);
 472 }
 473
 474 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 475                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 476 {
 477         char *port_change_bit;
 478         u32 status;
 479
 480         switch (wValue) {
 481         case USB_PORT_FEAT_C_RESET:
 482                 status = PORT_RC;
 483                 port_change_bit = "reset";
 484                 break;
 485         case USB_PORT_FEAT_C_BH_PORT_RESET:
 486                 status = PORT_WRC;
 487                 port_change_bit = "warm(BH) reset";
 488                 break;
 489         case USB_PORT_FEAT_C_CONNECTION:
 490                 status = PORT_CSC;
 491                 port_change_bit = "connect";
 492                 break;
 493         case USB_PORT_FEAT_C_OVER_CURRENT:
 494                 status = PORT_OCC;
 495                 port_change_bit = "over-current";
 496                 break;
 497         case USB_PORT_FEAT_C_ENABLE:
 498                 status = PORT_PEC;
 499                 port_change_bit = "enable/disable";
 500                 break;
 501         case USB_PORT_FEAT_C_SUSPEND:
 502                 status = PORT_PLC;
 503                 port_change_bit = "suspend/resume";
 504                 break;
 505         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 506                 status = PORT_PLC;
 507                 port_change_bit = "link state";
 508                 break;
 509         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 510                 status = PORT_CEC;
 511                 port_change_bit = "config error";
 512                 break;
 513         default:
 514                 /* Should never happen */
 515                 return;
 516         }
 517         /* Change bits are all write 1 to clear */
 518         writel(port_status | status, addr);
 519         port_status = readl(addr);
 520         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 521                         port_change_bit, wIndex, port_status);
 522 }
 523
 524 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 525 {
 526         int max_ports;
 527         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 528
 529         if (hcd->speed >= HCD_USB3) {
 530                 max_ports = xhci->num_usb3_ports;
 531                 *port_array = xhci->usb3_ports;
 532         } else {
 533                 max_ports = xhci->num_usb2_ports;
 534                 *port_array = xhci->usb2_ports;
 535         }
 536
 537         return max_ports;
 538 }
 539
 540 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 541                                 int port_id, u32 link_state)
 542 {
 543         u32 temp;
 544
 545         temp = readl(port_array[port_id]);
 546         temp = xhci_port_state_to_neutral(temp);
 547         temp &= ~PORT_PLS_MASK;
 548         temp |= PORT_LINK_STROBE | link_state;
 549         writel(temp, port_array[port_id]);
 550 }
 551
 552 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 553                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 554 {
 555         u32 temp;
 556
 557         temp = readl(port_array[port_id]);
 558         temp = xhci_port_state_to_neutral(temp);
 559
 560         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 561                 temp |= PORT_WKCONN_E;
 562         else
 563                 temp &= ~PORT_WKCONN_E;
 564
 565         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 566                 temp |= PORT_WKDISC_E;
 567         else
 568                 temp &= ~PORT_WKDISC_E;
 569
 570         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 571                 temp |= PORT_WKOC_E;
 572         else
 573                 temp &= ~PORT_WKOC_E;
 574
 575         writel(temp, port_array[port_id]);
 576 }
 577
 578 /* Test and clear port RWC bit */
 579 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 580                                 int port_id, u32 port_bit)
 581 {
 582         u32 temp;
 583
 584         temp = readl(port_array[port_id]);
 585         if (temp & port_bit) {
 586                 temp = xhci_port_state_to_neutral(temp);
 587                 temp |= port_bit;
 588                 writel(temp, port_array[port_id]);
 589         }
 590 }
 591
 592 /* Updates Link Status for USB 2.1 port */
 593 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 594 {
 595         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 596                 *status |= USB_PORT_STAT_L1;
 597 }
 598
 599 /* Updates Link Status for super Speed port */
 600 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 601                 u32 *status, u32 status_reg)
 602 {
 603         u32 pls = status_reg & PORT_PLS_MASK;
 604
 605         /* resume state is a xHCI internal state.
 606          * Do not report it to usb core, instead, pretend to be U3,
 607          * thus usb core knows it's not ready for transfer
 608          */
 609         if (pls == XDEV_RESUME) {
 610                 *status |= USB_SS_PORT_LS_U3;
 611                 return;
 612         }
 613
 614         /* When the CAS bit is set then warm reset
 615          * should be performed on port
 616          */
 617         if (status_reg & PORT_CAS) {
 618                 /* The CAS bit can be set while the port is
 619                  * in any link state.
 620                  * Only roothubs have CAS bit, so we
 621                  * pretend to be in compliance mode
 622                  * unless we're already in compliance
 623                  * or the inactive state.
 624                  */
 625                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 626                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 627                         pls = USB_SS_PORT_LS_COMP_MOD;
 628                 }
 629                 /* Return also connection bit -
 630                  * hub state machine resets port
 631                  * when this bit is set.
 632                  */
 633                 pls |= USB_PORT_STAT_CONNECTION;
 634         } else {
 635                 /*
 636                  * If CAS bit isn't set but the Port is already at
 637                  * Compliance Mode, fake a connection so the USB core
 638                  * notices the Compliance state and resets the port.
 639                  * This resolves an issue generated by the SN65LVPE502CP
 640                  * in which sometimes the port enters compliance mode
 641                  * caused by a delay on the host-device negotiation.
 642                  */
 643                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 644                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 645                         pls |= USB_PORT_STAT_CONNECTION;
 646         }
 647
 648         /* update status field */
 649         *status |= pls;
 650 }
 651
 652 /*
 653  * Function for Compliance Mode Quirk.
 654  *
 655  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 656  * the compliance mode timer is deleted. A port won't enter
 657  * compliance mode if it has previously entered U0.
 658  */
 659 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 660                                     u16 wIndex)
 661 {
 662         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 663         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 664
 665         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 666                 return;
 667
 668         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 669                 xhci->port_status_u0 |= 1 << wIndex;
 670                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 671                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 672                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 673                                 "All USB3 ports have entered U0 already!");
 674                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 675                                 "Compliance Mode Recovery Timer Deleted.");
 676                 }
 677         }
 678 }
 679
 680 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 681 {
 682         u32 ext_stat = 0;
 683         int speed_id;
 684
 685         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 686         speed_id = DEV_PORT_SPEED(raw_port_status);
 687         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 688         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 689
 690         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 691         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 692
 693         return ext_stat;
 694 }
 695
 696 /*
 697  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 698  * 3.0 hubs use.
 699  *
 700  * Possible side effects:
 701  *  - Mark a port as being done with device resume,
 702  *    and ring the endpoint doorbells.
 703  *  - Stop the Synopsys redriver Compliance Mode polling.
 704  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 705  */
 706 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 707                 struct xhci_bus_state *bus_state,
 708                 __le32 __iomem **port_array,
 709                 u16 wIndex, u32 raw_port_status,
 710                 unsigned long flags)
 711         __releases(&xhci->lock)
 712         __acquires(&xhci->lock)
 713 {
 714         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 715         u32 status = 0;
 716         int slot_id;
 717
 718         /* wPortChange bits */
 719         if (raw_port_status & PORT_CSC)
 720                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 721         if (raw_port_status & PORT_PEC)
 722                 status |= USB_PORT_STAT_C_ENABLE << 16;
 723         if ((raw_port_status & PORT_OCC))
 724                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 725         if ((raw_port_status & PORT_RC))
 726                 status |= USB_PORT_STAT_C_RESET << 16;
 727         /* USB3.0 only */
 728         if (hcd->speed >= HCD_USB3) {
 729                 /* Port link change with port in resume state should not be
 730                  * reported to usbcore, as this is an internal state to be
 731                  * handled by xhci driver. Reporting PLC to usbcore may
 732                  * cause usbcore clearing PLC first and port change event
 733                  * irq won't be generated.
 734                  */
 735                 if ((raw_port_status & PORT_PLC) &&
 736                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 737                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 738                 if ((raw_port_status & PORT_WRC))
 739                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 740                 if ((raw_port_status & PORT_CEC))
 741                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 742         }
 743
 744         if (hcd->speed < HCD_USB3) {
 745                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 746                                 && (raw_port_status & PORT_POWER))
 747                         status |= USB_PORT_STAT_SUSPEND;
 748         }
 749         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 750                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 751                 if ((raw_port_status & PORT_RESET) ||
 752                                 !(raw_port_status & PORT_PE))
 753                         return 0xffffffff;
 754                 /* did port event handler already start resume timing? */
 755                 if (!bus_state->resume_done[wIndex]) {
 756                         /* If not, maybe we are in a host initated resume? */
 757                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 758                                 /* Host initated resume doesn't time the resume
 759                                  * signalling using resume_done[].
 760                                  * It manually sets RESUME state, sleeps 20ms
 761                                  * and sets U0 state. This should probably be
 762                                  * changed, but not right now.
 763                                  */
 764                         } else {
 765                                 /* port resume was discovered now and here,
 766                                  * start resume timing
 767                                  */
 768                                 unsigned long timeout = jiffies +
 769                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 770
 771                                 set_bit(wIndex, &bus_state->resuming_ports);
 772                                 bus_state->resume_done[wIndex] = timeout;
 773                                 mod_timer(&hcd->rh_timer, timeout);
 774                         }
 775                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 776                 } else if (time_after_eq(jiffies,
 777                                          bus_state->resume_done[wIndex])) {
 778                         int time_left;
 779
 780                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 781                                         wIndex + 1);
 782                         bus_state->resume_done[wIndex] = 0;
 783                         clear_bit(wIndex, &bus_state->resuming_ports);
 784
 785                         set_bit(wIndex, &bus_state->rexit_ports);
 786
 787                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 788                                                 PORT_PLC);
 789                         xhci_set_link_state(xhci, port_array, wIndex,
 790                                         XDEV_U0);
 791
 792                         spin_unlock_irqrestore(&xhci->lock, flags);
 793                         time_left = wait_for_completion_timeout(
 794                                         &bus_state->rexit_done[wIndex],
 795                                         msecs_to_jiffies(
 796                                                 XHCI_MAX_REXIT_TIMEOUT));
 797                         spin_lock_irqsave(&xhci->lock, flags);
 798
 799                         if (time_left) {
 800                                 slot_id = xhci_find_slot_id_by_port(hcd,
 801                                                 xhci, wIndex + 1);
 802                                 if (!slot_id) {
 803                                         xhci_dbg(xhci, "slot_id is zero\n");
 804                                         return 0xffffffff;
 805                                 }
 806                                 xhci_ring_device(xhci, slot_id);
 807                         } else {
 808                                 int port_status = readl(port_array[wIndex]);
 809                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 810                                                 XHCI_MAX_REXIT_TIMEOUT,
 811                                                 port_status);
 812                                 status |= USB_PORT_STAT_SUSPEND;
 813                                 clear_bit(wIndex, &bus_state->rexit_ports);
 814                         }
 815
 816                         bus_state->port_c_suspend |= 1 << wIndex;
 817                         bus_state->suspended_ports &= ~(1 << wIndex);
 818                 } else {
 819                         /*
 820                          * The resume has been signaling for less than
 821                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 822                          * let the usbcore check port status again and clear
 823                          * resume signaling later.
 824                          */
 825                         status |= USB_PORT_STAT_SUSPEND;
 826                 }
 827         }
 828         /*
 829          * Clear stale usb2 resume signalling variables in case port changed
 830          * state during resume signalling. For example on error
 831          */
 832         if ((bus_state->resume_done[wIndex] ||
 833              test_bit(wIndex, &bus_state->resuming_ports)) &&
 834             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 835             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 836                 bus_state->resume_done[wIndex] = 0;
 837                 clear_bit(wIndex, &bus_state->resuming_ports);
 838         }
 839
 840
 841         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 842             (raw_port_status & PORT_POWER)) {
 843                 if (bus_state->suspended_ports & (1 << wIndex)) {
 844                         bus_state->suspended_ports &= ~(1 << wIndex);
 845                         if (hcd->speed < HCD_USB3)
 846                                 bus_state->port_c_suspend |= 1 << wIndex;
 847                 }
 848                 bus_state->resume_done[wIndex] = 0;
 849                 clear_bit(wIndex, &bus_state->resuming_ports);
 850         }
 851         if (raw_port_status & PORT_CONNECT) {
 852                 status |= USB_PORT_STAT_CONNECTION;
 853                 status |= xhci_port_speed(raw_port_status);
 854         }
 855         if (raw_port_status & PORT_PE)
 856                 status |= USB_PORT_STAT_ENABLE;
 857         if (raw_port_status & PORT_OC)
 858                 status |= USB_PORT_STAT_OVERCURRENT;
 859         if (raw_port_status & PORT_RESET)
 860                 status |= USB_PORT_STAT_RESET;
 861         if (raw_port_status & PORT_POWER) {
 862                 if (hcd->speed >= HCD_USB3)
 863                         status |= USB_SS_PORT_STAT_POWER;
 864                 else
 865                         status |= USB_PORT_STAT_POWER;
 866         }
 867         /* Update Port Link State */
 868         if (hcd->speed >= HCD_USB3) {
 869                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 870                 /*
 871                  * Verify if all USB3 Ports Have entered U0 already.
 872                  * Delete Compliance Mode Timer if so.
 873                  */
 874                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 875         } else {
 876                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 877         }
 878         if (bus_state->port_c_suspend & (1 << wIndex))
 879                 status |= USB_PORT_STAT_C_SUSPEND << 16;
 880
 881         return status;
 882 }
 883
 884 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 885                 u16 wIndex, char *buf, u16 wLength)
 886 {
 887         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 888         int max_ports;
 889         unsigned long flags;
 890         u32 temp, status;
 891         int retval = 0;
 892         __le32 __iomem **port_array;
 893         int slot_id;
 894         struct xhci_bus_state *bus_state;
 895         u16 link_state = 0;
 896         u16 wake_mask = 0;
 897         u16 timeout = 0;
 898
 899         max_ports = xhci_get_ports(hcd, &port_array);
 900         bus_state = &xhci->bus_state[hcd_index(hcd)];
 901
 902         spin_lock_irqsave(&xhci->lock, flags);
 903         switch (typeReq) {
 904         case GetHubStatus:
 905                 /* No power source, over-current reported per port */
 906                 memset(buf, 0, 4);
 907                 break;
 908         case GetHubDescriptor:
 909                 /* Check to make sure userspace is asking for the USB 3.0 hub
 910                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 911                  * endpoint, like external hubs do.
 912                  */
 913                 if (hcd->speed >= HCD_USB3 &&
 914                                 (wLength < USB_DT_SS_HUB_SIZE ||
 915                                  wValue != (USB_DT_SS_HUB << 8))) {
 916                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 917                                         "USB 3.0 roothub.\n");
 918                         goto error;
 919                 }
 920                 xhci_hub_descriptor(hcd, xhci,
 921                                 (struct usb_hub_descriptor *) buf);
 922                 break;
 923         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 924                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 925                         goto error;
 926
 927                 if (hcd->speed < HCD_USB3)
 928                         goto error;
 929
 930                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
 931                 spin_unlock_irqrestore(&xhci->lock, flags);
 932                 return retval;
 933         case GetPortStatus:
 934                 if (!wIndex || wIndex > max_ports)
 935                         goto error;
 936                 wIndex--;
 937                 temp = readl(port_array[wIndex]);
 938                 if (temp == 0xffffffff) {
 939                         retval = -ENODEV;
 940                         break;
 941                 }
 942                 status = xhci_get_port_status(hcd, bus_state, port_array,
 943                                 wIndex, temp, flags);
 944                 if (status == 0xffffffff)
 945                         goto error;
 946
 947                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 948                                 wIndex, temp);
 949                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 950
 951                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 952                 /* if USB 3.1 extended port status return additional 4 bytes */
 953                 if (wValue == 0x02) {
 954                         u32 port_li;
 955
 956                         if (hcd->speed < HCD_USB31 || wLength != 8) {
 957                                 xhci_err(xhci, "get ext port status invalid parameter\n");
 958                                 retval = -EINVAL;
 959                                 break;
 960                         }
 961                         port_li = readl(port_array[wIndex] + PORTLI);
 962                         status = xhci_get_ext_port_status(temp, port_li);
 963                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
 964                 }
 965                 break;
 966         case SetPortFeature:
 967                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 968                         link_state = (wIndex & 0xff00) >> 3;
 969                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 970                         wake_mask = wIndex & 0xff00;
 971                 /* The MSB of wIndex is the U1/U2 timeout */
 972                 timeout = (wIndex & 0xff00) >> 8;
 973                 wIndex &= 0xff;
 974                 if (!wIndex || wIndex > max_ports)
 975                         goto error;
 976                 wIndex--;
 977                 temp = readl(port_array[wIndex]);
 978                 if (temp == 0xffffffff) {
 979                         retval = -ENODEV;
 980                         break;
 981                 }
 982                 temp = xhci_port_state_to_neutral(temp);
 983                 /* FIXME: What new port features do we need to support? */
 984                 switch (wValue) {
 985                 case USB_PORT_FEAT_SUSPEND:
 986                         temp = readl(port_array[wIndex]);
 987                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 988                                 /* Resume the port to U0 first */
 989                                 xhci_set_link_state(xhci, port_array, wIndex,
 990                                                         XDEV_U0);
 991                                 spin_unlock_irqrestore(&xhci->lock, flags);
 992                                 msleep(10);
 993                                 spin_lock_irqsave(&xhci->lock, flags);
 994                         }
 995                         /* In spec software should not attempt to suspend
 996                          * a port unless the port reports that it is in the
 997                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 998                          */
 999                         temp = readl(port_array[wIndex]);
1000                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1001                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1002                                 xhci_warn(xhci, "USB core suspending device "
1003                                           "not in U0/U1/U2.\n");
1004                                 goto error;
1005                         }
1006
1007                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1008                                         wIndex + 1);
1009                         if (!slot_id) {
1010                                 xhci_warn(xhci, "slot_id is zero\n");
1011                                 goto error;
1012                         }
1013                         /* unlock to execute stop endpoint commands */
1014                         spin_unlock_irqrestore(&xhci->lock, flags);
1015                         xhci_stop_device(xhci, slot_id, 1);
1016                         spin_lock_irqsave(&xhci->lock, flags);
1017
1018                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1019
1020                         spin_unlock_irqrestore(&xhci->lock, flags);
1021                         msleep(10); /* wait device to enter */
1022                         spin_lock_irqsave(&xhci->lock, flags);
1023
1024                         temp = readl(port_array[wIndex]);
1025                         bus_state->suspended_ports |= 1 << wIndex;
1026                         break;
1027                 case USB_PORT_FEAT_LINK_STATE:
1028                         temp = readl(port_array[wIndex]);
1029
1030                         /* Disable port */
1031                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1032                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1033                                 temp = xhci_port_state_to_neutral(temp);
1034                                 /*
1035                                  * Clear all change bits, so that we get a new
1036                                  * connection event.
1037                                  */
1038                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1039                                         PORT_OCC | PORT_RC | PORT_PLC |
1040                                         PORT_CEC;
1041                                 writel(temp | PORT_PE, port_array[wIndex]);
1042                                 temp = readl(port_array[wIndex]);
1043                                 break;
1044                         }
1045
1046                         /* Put link in RxDetect (enable port) */
1047                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1048                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1049                                 xhci_set_link_state(xhci, port_array, wIndex,
1050                                                 link_state);
1051                                 temp = readl(port_array[wIndex]);
1052                                 break;
1053                         }
1054
1055                         /* Software should not attempt to set
1056                          * port link state above '3' (U3) and the port
1057                          * must be enabled.
1058                          */
1059                         if ((temp & PORT_PE) == 0 ||
1060                                 (link_state > USB_SS_PORT_LS_U3)) {
1061                                 xhci_warn(xhci, "Cannot set link state.\n");
1062                                 goto error;
1063                         }
1064
1065                         if (link_state == USB_SS_PORT_LS_U3) {
1066                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1067                                                 wIndex + 1);
1068                                 if (slot_id) {
1069                                         /* unlock to execute stop endpoint
1070                                          * commands */
1071                                         spin_unlock_irqrestore(&xhci->lock,
1072                                                                 flags);
1073                                         xhci_stop_device(xhci, slot_id, 1);
1074                                         spin_lock_irqsave(&xhci->lock, flags);
1075                                 }
1076                         }
1077
1078                         xhci_set_link_state(xhci, port_array, wIndex,
1079                                                 link_state);
1080
1081                         spin_unlock_irqrestore(&xhci->lock, flags);
1082                         msleep(20); /* wait device to enter */
1083                         spin_lock_irqsave(&xhci->lock, flags);
1084
1085                         temp = readl(port_array[wIndex]);
1086                         if (link_state == USB_SS_PORT_LS_U3)
1087                                 bus_state->suspended_ports |= 1 << wIndex;
1088                         break;
1089                 case USB_PORT_FEAT_POWER:
1090                         /*
1091                          * Turn on ports, even if there isn't per-port switching.
1092                          * HC will report connect events even before this is set.
1093                          * However, hub_wq will ignore the roothub events until
1094                          * the roothub is registered.
1095                          */
1096                         writel(temp | PORT_POWER, port_array[wIndex]);
1097
1098                         temp = readl(port_array[wIndex]);
1099                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
1100
1101                         spin_unlock_irqrestore(&xhci->lock, flags);
1102                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1103                                         wIndex);
1104                         if (temp)
1105                                 usb_acpi_set_power_state(hcd->self.root_hub,
1106                                                 wIndex, true);
1107                         spin_lock_irqsave(&xhci->lock, flags);
1108                         break;
1109                 case USB_PORT_FEAT_RESET:
1110                         temp = (temp | PORT_RESET);
1111                         writel(temp, port_array[wIndex]);
1112
1113                         temp = readl(port_array[wIndex]);
1114                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1115                         break;
1116                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1117                         xhci_set_remote_wake_mask(xhci, port_array,
1118                                         wIndex, wake_mask);
1119                         temp = readl(port_array[wIndex]);
1120                         xhci_dbg(xhci, "set port remote wake mask, "
1121                                         "actual port %d status  = 0x%x\n",
1122                                         wIndex, temp);
1123                         break;
1124                 case USB_PORT_FEAT_BH_PORT_RESET:
1125                         temp |= PORT_WR;
1126                         writel(temp, port_array[wIndex]);
1127
1128                         temp = readl(port_array[wIndex]);
1129                         break;
1130                 case USB_PORT_FEAT_U1_TIMEOUT:
1131                         if (hcd->speed < HCD_USB3)
1132                                 goto error;
1133                         temp = readl(port_array[wIndex] + PORTPMSC);
1134                         temp &= ~PORT_U1_TIMEOUT_MASK;
1135                         temp |= PORT_U1_TIMEOUT(timeout);
1136                         writel(temp, port_array[wIndex] + PORTPMSC);
1137                         break;
1138                 case USB_PORT_FEAT_U2_TIMEOUT:
1139                         if (hcd->speed < HCD_USB3)
1140                                 goto error;
1141                         temp = readl(port_array[wIndex] + PORTPMSC);
1142                         temp &= ~PORT_U2_TIMEOUT_MASK;
1143                         temp |= PORT_U2_TIMEOUT(timeout);
1144                         writel(temp, port_array[wIndex] + PORTPMSC);
1145                         break;
1146                 default:
1147                         goto error;
1148                 }
1149                 /* unblock any posted writes */
1150                 temp = readl(port_array[wIndex]);
1151                 break;
1152         case ClearPortFeature:
1153                 if (!wIndex || wIndex > max_ports)
1154                         goto error;
1155                 wIndex--;
1156                 temp = readl(port_array[wIndex]);
1157                 if (temp == 0xffffffff) {
1158                         retval = -ENODEV;
1159                         break;
1160                 }
1161                 /* FIXME: What new port features do we need to support? */
1162                 temp = xhci_port_state_to_neutral(temp);
1163                 switch (wValue) {
1164                 case USB_PORT_FEAT_SUSPEND:
1165                         temp = readl(port_array[wIndex]);
1166                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1167                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1168                         if (temp & PORT_RESET)
1169                                 goto error;
1170                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1171                                 if ((temp & PORT_PE) == 0)
1172                                         goto error;
1173
1174                                 set_bit(wIndex, &bus_state->resuming_ports);
1175                                 xhci_set_link_state(xhci, port_array, wIndex,
1176                                                         XDEV_RESUME);
1177                                 spin_unlock_irqrestore(&xhci->lock, flags);
1178                                 msleep(USB_RESUME_TIMEOUT);
1179                                 spin_lock_irqsave(&xhci->lock, flags);
1180                                 xhci_set_link_state(xhci, port_array, wIndex,
1181                                                         XDEV_U0);
1182                                 clear_bit(wIndex, &bus_state->resuming_ports);
1183                         }
1184                         bus_state->port_c_suspend |= 1 << wIndex;
1185
1186                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1187                                         wIndex + 1);
1188                         if (!slot_id) {
1189                                 xhci_dbg(xhci, "slot_id is zero\n");
1190                                 goto error;
1191                         }
1192                         xhci_ring_device(xhci, slot_id);
1193                         break;
1194                 case USB_PORT_FEAT_C_SUSPEND:
1195                         bus_state->port_c_suspend &= ~(1 << wIndex);
1196                 case USB_PORT_FEAT_C_RESET:
1197                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1198                 case USB_PORT_FEAT_C_CONNECTION:
1199                 case USB_PORT_FEAT_C_OVER_CURRENT:
1200                 case USB_PORT_FEAT_C_ENABLE:
1201                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1202                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1203                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1204                                         port_array[wIndex], temp);
1205                         break;
1206                 case USB_PORT_FEAT_ENABLE:
1207                         xhci_disable_port(hcd, xhci, wIndex,
1208                                         port_array[wIndex], temp);
1209                         break;
1210                 case USB_PORT_FEAT_POWER:
1211                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1212
1213                         spin_unlock_irqrestore(&xhci->lock, flags);
1214                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1215                                         wIndex);
1216                         if (temp)
1217                                 usb_acpi_set_power_state(hcd->self.root_hub,
1218                                                 wIndex, false);
1219                         spin_lock_irqsave(&xhci->lock, flags);
1220                         break;
1221                 default:
1222                         goto error;
1223                 }
1224                 break;
1225         default:
1226 error:
1227                 /* "stall" on error */
1228                 retval = -EPIPE;
1229         }
1230         spin_unlock_irqrestore(&xhci->lock, flags);
1231         return retval;
1232 }
1233
1234 /*
1235  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1236  * Ports are 0-indexed from the HCD point of view,
1237  * and 1-indexed from the USB core pointer of view.
1238  *
1239  * Note that the status change bits will be cleared as soon as a port status
1240  * change event is generated, so we use the saved status from that event.
1241  */
1242 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1243 {
1244         unsigned long flags;
1245         u32 temp, status;
1246         u32 mask;
1247         int i, retval;
1248         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1249         int max_ports;
1250         __le32 __iomem **port_array;
1251         struct xhci_bus_state *bus_state;
1252         bool reset_change = false;
1253
1254         max_ports = xhci_get_ports(hcd, &port_array);
1255         bus_state = &xhci->bus_state[hcd_index(hcd)];
1256
1257         /* Initial status is no changes */
1258         retval = (max_ports + 8) / 8;
1259         memset(buf, 0, retval);
1260
1261         /*
1262          * Inform the usbcore about resume-in-progress by returning
1263          * a non-zero value even if there are no status changes.
1264          */
1265         status = bus_state->resuming_ports;
1266
1267         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1268
1269         spin_lock_irqsave(&xhci->lock, flags);
1270         /* For each port, did anything change?  If so, set that bit in buf. */
1271         for (i = 0; i < max_ports; i++) {
1272                 temp = readl(port_array[i]);
1273                 if (temp == 0xffffffff) {
1274                         retval = -ENODEV;
1275                         break;
1276                 }
1277                 if ((temp & mask) != 0 ||
1278                         (bus_state->port_c_suspend & 1 << i) ||
1279                         (bus_state->resume_done[i] && time_after_eq(
1280                             jiffies, bus_state->resume_done[i]))) {
1281                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1282                         status = 1;
1283                 }
1284                 if ((temp & PORT_RC))
1285                         reset_change = true;
1286         }
1287         if (!status && !reset_change) {
1288                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1289                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1290         }
1291         spin_unlock_irqrestore(&xhci->lock, flags);
1292         return status ? retval : 0;
1293 }
1294
1295 #ifdef CONFIG_PM
1296
1297 int xhci_bus_suspend(struct usb_hcd *hcd)
1298 {
1299         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1300         int max_ports, port_index;
1301         __le32 __iomem **port_array;
1302         struct xhci_bus_state *bus_state;
1303         unsigned long flags;
1304
1305         max_ports = xhci_get_ports(hcd, &port_array);
1306         bus_state = &xhci->bus_state[hcd_index(hcd)];
1307
1308         spin_lock_irqsave(&xhci->lock, flags);
1309
1310         if (hcd->self.root_hub->do_remote_wakeup) {
1311                 if (bus_state->resuming_ports ||        /* USB2 */
1312                     bus_state->port_remote_wakeup) {    /* USB3 */
1313                         spin_unlock_irqrestore(&xhci->lock, flags);
1314                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1315                         return -EBUSY;
1316                 }
1317         }
1318
1319         port_index = max_ports;
1320         bus_state->bus_suspended = 0;
1321         while (port_index--) {
1322                 /* suspend the port if the port is not suspended */
1323                 u32 t1, t2;
1324                 int slot_id;
1325
1326                 t1 = readl(port_array[port_index]);
1327                 t2 = xhci_port_state_to_neutral(t1);
1328
1329                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1330                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1331                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1332                                         port_index + 1);
1333                         if (slot_id) {
1334                                 spin_unlock_irqrestore(&xhci->lock, flags);
1335                                 xhci_stop_device(xhci, slot_id, 1);
1336                                 spin_lock_irqsave(&xhci->lock, flags);
1337                         }
1338                         t2 &= ~PORT_PLS_MASK;
1339                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1340                         set_bit(port_index, &bus_state->bus_suspended);
1341                 }
1342                 /* USB core sets remote wake mask for USB 3.0 hubs,
1343                  * including the USB 3.0 roothub, but only if CONFIG_PM
1344                  * is enabled, so also enable remote wake here.
1345                  */
1346                 if (hcd->self.root_hub->do_remote_wakeup) {
1347                         if (t1 & PORT_CONNECT) {
1348                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1349                                 t2 &= ~PORT_WKCONN_E;
1350                         } else {
1351                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1352                                 t2 &= ~PORT_WKDISC_E;
1353                         }
1354                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1355                             (hcd->speed < HCD_USB3))
1356                                 t2 &= ~PORT_WAKE_BITS;
1357                 } else
1358                         t2 &= ~PORT_WAKE_BITS;
1359
1360                 t1 = xhci_port_state_to_neutral(t1);
1361                 if (t1 != t2)
1362                         writel(t2, port_array[port_index]);
1363         }
1364         hcd->state = HC_STATE_SUSPENDED;
1365         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1366         spin_unlock_irqrestore(&xhci->lock, flags);
1367         return 0;
1368 }
1369
1370 /*
1371  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1372  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1373  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1374  */
1375 static bool xhci_port_missing_cas_quirk(int port_index,
1376                                              __le32 __iomem **port_array)
1377 {
1378         u32 portsc;
1379
1380         portsc = readl(port_array[port_index]);
1381
1382         /* if any of these are set we are not stuck */
1383         if (portsc & (PORT_CONNECT | PORT_CAS))
1384                 return false;
1385
1386         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1387             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1388                 return false;
1389
1390         /* clear wakeup/change bits, and do a warm port reset */
1391         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1392         portsc |= PORT_WR;
1393         writel(portsc, port_array[port_index]);
1394         /* flush write */
1395         readl(port_array[port_index]);
1396         return true;
1397 }
1398
1399 int xhci_bus_resume(struct usb_hcd *hcd)
1400 {
1401         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1402         int max_ports, port_index;
1403         __le32 __iomem **port_array;
1404         struct xhci_bus_state *bus_state;
1405         u32 temp;
1406         unsigned long flags;
1407         unsigned long port_was_suspended = 0;
1408         bool need_usb2_u3_exit = false;
1409         int slot_id;
1410         int sret;
1411
1412         max_ports = xhci_get_ports(hcd, &port_array);
1413         bus_state = &xhci->bus_state[hcd_index(hcd)];
1414
1415         if (time_before(jiffies, bus_state->next_statechange))
1416                 msleep(5);
1417
1418         spin_lock_irqsave(&xhci->lock, flags);
1419         if (!HCD_HW_ACCESSIBLE(hcd)) {
1420                 spin_unlock_irqrestore(&xhci->lock, flags);
1421                 return -ESHUTDOWN;
1422         }
1423
1424         /* delay the irqs */
1425         temp = readl(&xhci->op_regs->command);
1426         temp &= ~CMD_EIE;
1427         writel(temp, &xhci->op_regs->command);
1428
1429         port_index = max_ports;
1430         while (port_index--) {
1431                 /* Check whether need resume ports. If needed
1432                    resume port and disable remote wakeup */
1433                 u32 temp;
1434
1435                 temp = readl(port_array[port_index]);
1436
1437                 /* warm reset CAS limited ports stuck in polling/compliance */
1438                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1439                     (hcd->speed >= HCD_USB3) &&
1440                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1441                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1442                         continue;
1443                 }
1444                 if (DEV_SUPERSPEED_ANY(temp))
1445                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1446                 else
1447                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1448                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1449                     (temp & PORT_PLS_MASK)) {
1450                         set_bit(port_index, &port_was_suspended);
1451                         if (!DEV_SUPERSPEED_ANY(temp)) {
1452                                 xhci_set_link_state(xhci, port_array,
1453                                                 port_index, XDEV_RESUME);
1454                                 need_usb2_u3_exit = true;
1455                         }
1456                 } else
1457                         writel(temp, port_array[port_index]);
1458         }
1459
1460         if (need_usb2_u3_exit) {
1461                 spin_unlock_irqrestore(&xhci->lock, flags);
1462                 msleep(USB_RESUME_TIMEOUT);
1463                 spin_lock_irqsave(&xhci->lock, flags);
1464         }
1465
1466         port_index = max_ports;
1467         while (port_index--) {
1468                 if (!(port_was_suspended & BIT(port_index)))
1469                         continue;
1470                 /* Clear PLC to poll it later after XDEV_U0 */
1471                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1472                 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1473         }
1474
1475         port_index = max_ports;
1476         while (port_index--) {
1477                 if (!(port_was_suspended & BIT(port_index)))
1478                         continue;
1479                 /* Poll and Clear PLC */
1480                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1481                                       PORT_PLC, 10 * 1000);
1482                 if (sret)
1483                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1484                                   port_index);
1485                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1486                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1487                 if (slot_id)
1488                         xhci_ring_device(xhci, slot_id);
1489         }
1490
1491         (void) readl(&xhci->op_regs->command);
1492
1493         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1494         /* re-enable irqs */
1495         temp = readl(&xhci->op_regs->command);
1496         temp |= CMD_EIE;
1497         writel(temp, &xhci->op_regs->command);
1498         temp = readl(&xhci->op_regs->command);
1499
1500         spin_unlock_irqrestore(&xhci->lock, flags);
1501         return 0;
1502 }
1503
1504 #endif  /* CONFIG_PM */