drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #undef  DEBUG
  16 #undef  VERBOSE
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/timer.h>
  27 #include <linux/list.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/proc_fs.h>
  30 #include <linux/mm.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/usb/ch9.h>
  34 #include <linux/usb/gadget.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/clk.h>
  38 #include <linux/err.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/io.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/irq.h>
  44 #include <asm/unaligned.h>
  45 #include <asm/mach-types.h>
  46
  47 #include <linux/omap-dma.h>
  48
  49 #include <mach/usb.h>
  50
  51 #include "omap_udc.h"
  52
  53 #undef  USB_TRACE
  54
  55 /* bulk DMA seems to be behaving for both IN and OUT */
  56 #define USE_DMA
  57
  58 /* ISO too */
  59 #define USE_ISO
  60
  61 #define DRIVER_DESC     "OMAP UDC driver"
  62 #define DRIVER_VERSION  "4 October 2004"
  63
  64 #define OMAP_DMA_USB_W2FC_TX0           29
  65 #define OMAP_DMA_USB_W2FC_RX0           26
  66
  67 /*
  68  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  69  * D+ pullup to allow enumeration.  That's too early for the gadget
  70  * framework to use from usb_endpoint_enable(), which happens after
  71  * enumeration as part of activating an interface.  (But if we add an
  72  * optional new "UDC not yet running" state to the gadget driver model,
  73  * even just during driver binding, the endpoint autoconfig logic is the
  74  * natural spot to manufacture new endpoints.)
  75  *
  76  * So instead of using endpoint enable calls to control the hardware setup,
  77  * this driver defines a "fifo mode" parameter.  It's used during driver
  78  * initialization to choose among a set of pre-defined endpoint configs.
  79  * See omap_udc_setup() for available modes, or to add others.  That code
  80  * lives in an init section, so use this driver as a module if you need
  81  * to change the fifo mode after the kernel boots.
  82  *
  83  * Gadget drivers normally ignore endpoints they don't care about, and
  84  * won't include them in configuration descriptors.  That means only
  85  * misbehaving hosts would even notice they exist.
  86  */
  87 #ifdef  USE_ISO
  88 static unsigned fifo_mode = 3;
  89 #else
  90 static unsigned fifo_mode;
  91 #endif
  92
  93 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
  94  * boot parameter "omap_udc:fifo_mode=42"
  95  */
  96 module_param(fifo_mode, uint, 0);
  97 MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
  98
  99 #ifdef  USE_DMA
 100 static bool use_dma = 1;
 101
 102 /* "modprobe omap_udc use_dma=y", or else as a kernel
 103  * boot parameter "omap_udc:use_dma=y"
 104  */
 105 module_param(use_dma, bool, 0);
 106 MODULE_PARM_DESC(use_dma, "enable/disable DMA");
 107 #else   /* !USE_DMA */
 108
 109 /* save a bit of code */
 110 #define use_dma         0
 111 #endif  /* !USE_DMA */
 112
 113
 114 static const char driver_name[] = "omap_udc";
 115 static const char driver_desc[] = DRIVER_DESC;
 116
 117 /*-------------------------------------------------------------------------*/
 118
 119 /* there's a notion of "current endpoint" for modifying endpoint
 120  * state, and PIO access to its FIFO.
 121  */
 122
 123 static void use_ep(struct omap_ep *ep, u16 select)
 124 {
 125         u16     num = ep->bEndpointAddress & 0x0f;
 126
 127         if (ep->bEndpointAddress & USB_DIR_IN)
 128                 num |= UDC_EP_DIR;
 129         omap_writew(num | select, UDC_EP_NUM);
 130         /* when select, MUST deselect later !! */
 131 }
 132
 133 static inline void deselect_ep(void)
 134 {
 135         u16 w;
 136
 137         w = omap_readw(UDC_EP_NUM);
 138         w &= ~UDC_EP_SEL;
 139         omap_writew(w, UDC_EP_NUM);
 140         /* 6 wait states before TX will happen */
 141 }
 142
 143 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 144
 145 /*-------------------------------------------------------------------------*/
 146
 147 static int omap_ep_enable(struct usb_ep *_ep,
 148                 const struct usb_endpoint_descriptor *desc)
 149 {
 150         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 151         struct omap_udc *udc;
 152         unsigned long   flags;
 153         u16             maxp;
 154
 155         /* catch various bogus parameters */
 156         if (!_ep || !desc
 157                         || desc->bDescriptorType != USB_DT_ENDPOINT
 158                         || ep->bEndpointAddress != desc->bEndpointAddress
 159                         || ep->maxpacket < usb_endpoint_maxp(desc)) {
 160                 DBG("%s, bad ep or descriptor\n", __func__);
 161                 return -EINVAL;
 162         }
 163         maxp = usb_endpoint_maxp(desc);
 164         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 165                                 && maxp != ep->maxpacket)
 166                         || usb_endpoint_maxp(desc) > ep->maxpacket
 167                         || !desc->wMaxPacketSize) {
 168                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 169                 return -ERANGE;
 170         }
 171
 172 #ifdef  USE_ISO
 173         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 174                                 && desc->bInterval != 1)) {
 175                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 176                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 177                                 1 << (desc->bInterval - 1));
 178                 return -EDOM;
 179         }
 180 #else
 181         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 182                 DBG("%s, ISO nyet\n", _ep->name);
 183                 return -EDOM;
 184         }
 185 #endif
 186
 187         /* xfer types must match, except that interrupt ~= bulk */
 188         if (ep->bmAttributes != desc->bmAttributes
 189                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 190                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 191                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 192                 return -EINVAL;
 193         }
 194
 195         udc = ep->udc;
 196         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 197                 DBG("%s, bogus device state\n", __func__);
 198                 return -ESHUTDOWN;
 199         }
 200
 201         spin_lock_irqsave(&udc->lock, flags);
 202
 203         ep->ep.desc = desc;
 204         ep->irqs = 0;
 205         ep->stopped = 0;
 206         ep->ep.maxpacket = maxp;
 207
 208         /* set endpoint to initial state */
 209         ep->dma_channel = 0;
 210         ep->has_dma = 0;
 211         ep->lch = -1;
 212         use_ep(ep, UDC_EP_SEL);
 213         omap_writew(udc->clr_halt, UDC_CTRL);
 214         ep->ackwait = 0;
 215         deselect_ep();
 216
 217         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 218                 list_add(&ep->iso, &udc->iso);
 219
 220         /* maybe assign a DMA channel to this endpoint */
 221         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 222                 /* FIXME ISO can dma, but prefers first channel */
 223                 dma_channel_claim(ep, 0);
 224
 225         /* PIO OUT may RX packets */
 226         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 227                         && !ep->has_dma
 228                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 229                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 230                 ep->ackwait = 1 + ep->double_buf;
 231         }
 232
 233         spin_unlock_irqrestore(&udc->lock, flags);
 234         VDBG("%s enabled\n", _ep->name);
 235         return 0;
 236 }
 237
 238 static void nuke(struct omap_ep *, int status);
 239
 240 static int omap_ep_disable(struct usb_ep *_ep)
 241 {
 242         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 243         unsigned long   flags;
 244
 245         if (!_ep || !ep->ep.desc) {
 246                 DBG("%s, %s not enabled\n", __func__,
 247                         _ep ? ep->ep.name : NULL);
 248                 return -EINVAL;
 249         }
 250
 251         spin_lock_irqsave(&ep->udc->lock, flags);
 252         ep->ep.desc = NULL;
 253         nuke(ep, -ESHUTDOWN);
 254         ep->ep.maxpacket = ep->maxpacket;
 255         ep->has_dma = 0;
 256         omap_writew(UDC_SET_HALT, UDC_CTRL);
 257         list_del_init(&ep->iso);
 258         del_timer(&ep->timer);
 259
 260         spin_unlock_irqrestore(&ep->udc->lock, flags);
 261
 262         VDBG("%s disabled\n", _ep->name);
 263         return 0;
 264 }
 265
 266 /*-------------------------------------------------------------------------*/
 267
 268 static struct usb_request *
 269 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 270 {
 271         struct omap_req *req;
 272
 273         req = kzalloc(sizeof(*req), gfp_flags);
 274         if (!req)
 275                 return NULL;
 276
 277         INIT_LIST_HEAD(&req->queue);
 278
 279         return &req->req;
 280 }
 281
 282 static void
 283 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 284 {
 285         struct omap_req *req = container_of(_req, struct omap_req, req);
 286
 287         kfree(req);
 288 }
 289
 290 /*-------------------------------------------------------------------------*/
 291
 292 static void
 293 done(struct omap_ep *ep, struct omap_req *req, int status)
 294 {
 295         struct omap_udc         *udc = ep->udc;
 296         unsigned                stopped = ep->stopped;
 297
 298         list_del_init(&req->queue);
 299
 300         if (req->req.status == -EINPROGRESS)
 301                 req->req.status = status;
 302         else
 303                 status = req->req.status;
 304
 305         if (use_dma && ep->has_dma)
 306                 usb_gadget_unmap_request(&udc->gadget, &req->req,
 307                                 (ep->bEndpointAddress & USB_DIR_IN));
 308
 309 #ifndef USB_TRACE
 310         if (status && status != -ESHUTDOWN)
 311 #endif
 312                 VDBG("complete %s req %p stat %d len %u/%u\n",
 313                         ep->ep.name, &req->req, status,
 314                         req->req.actual, req->req.length);
 315
 316         /* don't modify queue heads during completion callback */
 317         ep->stopped = 1;
 318         spin_unlock(&ep->udc->lock);
 319         req->req.complete(&ep->ep, &req->req);
 320         spin_lock(&ep->udc->lock);
 321         ep->stopped = stopped;
 322 }
 323
 324 /*-------------------------------------------------------------------------*/
 325
 326 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 327 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 328
 329 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 330 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 331
 332 static inline int
 333 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 334 {
 335         unsigned        len;
 336         u16             *wp;
 337
 338         len = min(req->req.length - req->req.actual, max);
 339         req->req.actual += len;
 340
 341         max = len;
 342         if (likely((((int)buf) & 1) == 0)) {
 343                 wp = (u16 *)buf;
 344                 while (max >= 2) {
 345                         omap_writew(*wp++, UDC_DATA);
 346                         max -= 2;
 347                 }
 348                 buf = (u8 *)wp;
 349         }
 350         while (max--)
 351                 omap_writeb(*buf++, UDC_DATA);
 352         return len;
 353 }
 354
 355 /* FIXME change r/w fifo calling convention */
 356
 357
 358 /* return:  0 = still running, 1 = completed, negative = errno */
 359 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 360 {
 361         u8              *buf;
 362         unsigned        count;
 363         int             is_last;
 364         u16             ep_stat;
 365
 366         buf = req->req.buf + req->req.actual;
 367         prefetch(buf);
 368
 369         /* PIO-IN isn't double buffered except for iso */
 370         ep_stat = omap_readw(UDC_STAT_FLG);
 371         if (ep_stat & UDC_FIFO_UNWRITABLE)
 372                 return 0;
 373
 374         count = ep->ep.maxpacket;
 375         count = write_packet(buf, req, count);
 376         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 377         ep->ackwait = 1;
 378
 379         /* last packet is often short (sometimes a zlp) */
 380         if (count != ep->ep.maxpacket)
 381                 is_last = 1;
 382         else if (req->req.length == req->req.actual
 383                         && !req->req.zero)
 384                 is_last = 1;
 385         else
 386                 is_last = 0;
 387
 388         /* NOTE:  requests complete when all IN data is in a
 389          * FIFO (or sometimes later, if a zlp was needed).
 390          * Use usb_ep_fifo_status() where needed.
 391          */
 392         if (is_last)
 393                 done(ep, req, 0);
 394         return is_last;
 395 }
 396
 397 static inline int
 398 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 399 {
 400         unsigned        len;
 401         u16             *wp;
 402
 403         len = min(req->req.length - req->req.actual, avail);
 404         req->req.actual += len;
 405         avail = len;
 406
 407         if (likely((((int)buf) & 1) == 0)) {
 408                 wp = (u16 *)buf;
 409                 while (avail >= 2) {
 410                         *wp++ = omap_readw(UDC_DATA);
 411                         avail -= 2;
 412                 }
 413                 buf = (u8 *)wp;
 414         }
 415         while (avail--)
 416                 *buf++ = omap_readb(UDC_DATA);
 417         return len;
 418 }
 419
 420 /* return:  0 = still running, 1 = queue empty, negative = errno */
 421 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 422 {
 423         u8              *buf;
 424         unsigned        count, avail;
 425         int             is_last;
 426
 427         buf = req->req.buf + req->req.actual;
 428         prefetchw(buf);
 429
 430         for (;;) {
 431                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
 432
 433                 is_last = 0;
 434                 if (ep_stat & FIFO_EMPTY) {
 435                         if (!ep->double_buf)
 436                                 break;
 437                         ep->fnf = 1;
 438                 }
 439                 if (ep_stat & UDC_EP_HALTED)
 440                         break;
 441
 442                 if (ep_stat & UDC_FIFO_FULL)
 443                         avail = ep->ep.maxpacket;
 444                 else  {
 445                         avail = omap_readw(UDC_RXFSTAT);
 446                         ep->fnf = ep->double_buf;
 447                 }
 448                 count = read_packet(buf, req, avail);
 449
 450                 /* partial packet reads may not be errors */
 451                 if (count < ep->ep.maxpacket) {
 452                         is_last = 1;
 453                         /* overflowed this request?  flush extra data */
 454                         if (count != avail) {
 455                                 req->req.status = -EOVERFLOW;
 456                                 avail -= count;
 457                                 while (avail--)
 458                                         omap_readw(UDC_DATA);
 459                         }
 460                 } else if (req->req.length == req->req.actual)
 461                         is_last = 1;
 462                 else
 463                         is_last = 0;
 464
 465                 if (!ep->bEndpointAddress)
 466                         break;
 467                 if (is_last)
 468                         done(ep, req, 0);
 469                 break;
 470         }
 471         return is_last;
 472 }
 473
 474 /*-------------------------------------------------------------------------*/
 475
 476 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 477 {
 478         dma_addr_t      end;
 479
 480         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 481          * the last transfer's bytecount by more than a FIFO's worth.
 482          */
 483         if (cpu_is_omap15xx())
 484                 return 0;
 485
 486         end = omap_get_dma_src_pos(ep->lch);
 487         if (end == ep->dma_counter)
 488                 return 0;
 489
 490         end |= start & (0xffff << 16);
 491         if (end < start)
 492                 end += 0x10000;
 493         return end - start;
 494 }
 495
 496 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 497 {
 498         dma_addr_t      end;
 499
 500         end = omap_get_dma_dst_pos(ep->lch);
 501         if (end == ep->dma_counter)
 502                 return 0;
 503
 504         end |= start & (0xffff << 16);
 505         if (cpu_is_omap15xx())
 506                 end++;
 507         if (end < start)
 508                 end += 0x10000;
 509         return end - start;
 510 }
 511
 512
 513 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 514  * When DMA completion isn't request completion, the UDC continues with
 515  * the next DMA transfer for that USB transfer.
 516  */
 517
 518 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 519 {
 520         u16             txdma_ctrl, w;
 521         unsigned        length = req->req.length - req->req.actual;
 522         const int       sync_mode = cpu_is_omap15xx()
 523                                 ? OMAP_DMA_SYNC_FRAME
 524                                 : OMAP_DMA_SYNC_ELEMENT;
 525         int             dma_trigger = 0;
 526
 527         /* measure length in either bytes or packets */
 528         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 529                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 530                 txdma_ctrl = UDC_TXN_EOT | length;
 531                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 532                                 length, 1, sync_mode, dma_trigger, 0);
 533         } else {
 534                 length = min(length / ep->maxpacket,
 535                                 (unsigned) UDC_TXN_TSC + 1);
 536                 txdma_ctrl = length;
 537                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 538                                 ep->ep.maxpacket >> 1, length, sync_mode,
 539                                 dma_trigger, 0);
 540                 length *= ep->maxpacket;
 541         }
 542         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 543                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 544                 0, 0);
 545
 546         omap_start_dma(ep->lch);
 547         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 548         w = omap_readw(UDC_DMA_IRQ_EN);
 549         w |= UDC_TX_DONE_IE(ep->dma_channel);
 550         omap_writew(w, UDC_DMA_IRQ_EN);
 551         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 552         req->dma_bytes = length;
 553 }
 554
 555 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 556 {
 557         u16 w;
 558
 559         if (status == 0) {
 560                 req->req.actual += req->dma_bytes;
 561
 562                 /* return if this request needs to send data or zlp */
 563                 if (req->req.actual < req->req.length)
 564                         return;
 565                 if (req->req.zero
 566                                 && req->dma_bytes != 0
 567                                 && (req->req.actual % ep->maxpacket) == 0)
 568                         return;
 569         } else
 570                 req->req.actual += dma_src_len(ep, req->req.dma
 571                                                         + req->req.actual);
 572
 573         /* tx completion */
 574         omap_stop_dma(ep->lch);
 575         w = omap_readw(UDC_DMA_IRQ_EN);
 576         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 577         omap_writew(w, UDC_DMA_IRQ_EN);
 578         done(ep, req, status);
 579 }
 580
 581 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 582 {
 583         unsigned packets = req->req.length - req->req.actual;
 584         int dma_trigger = 0;
 585         u16 w;
 586
 587         /* set up this DMA transfer, enable the fifo, start */
 588         packets /= ep->ep.maxpacket;
 589         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 590         req->dma_bytes = packets * ep->ep.maxpacket;
 591         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 592                         ep->ep.maxpacket >> 1, packets,
 593                         OMAP_DMA_SYNC_ELEMENT,
 594                         dma_trigger, 0);
 595         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 596                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 597                 0, 0);
 598         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 599
 600         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 601         w = omap_readw(UDC_DMA_IRQ_EN);
 602         w |= UDC_RX_EOT_IE(ep->dma_channel);
 603         omap_writew(w, UDC_DMA_IRQ_EN);
 604         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 605         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 606
 607         omap_start_dma(ep->lch);
 608 }
 609
 610 static void
 611 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 612 {
 613         u16     count, w;
 614
 615         if (status == 0)
 616                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 617         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 618         count += req->req.actual;
 619         if (one)
 620                 count--;
 621         if (count <= req->req.length)
 622                 req->req.actual = count;
 623
 624         if (count != req->dma_bytes || status)
 625                 omap_stop_dma(ep->lch);
 626
 627         /* if this wasn't short, request may need another transfer */
 628         else if (req->req.actual < req->req.length)
 629                 return;
 630
 631         /* rx completion */
 632         w = omap_readw(UDC_DMA_IRQ_EN);
 633         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 634         omap_writew(w, UDC_DMA_IRQ_EN);
 635         done(ep, req, status);
 636 }
 637
 638 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 639 {
 640         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
 641         struct omap_ep  *ep;
 642         struct omap_req *req;
 643
 644         /* IN dma: tx to host */
 645         if (irq_src & UDC_TXN_DONE) {
 646                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 647                 ep->irqs++;
 648                 /* can see TXN_DONE after dma abort */
 649                 if (!list_empty(&ep->queue)) {
 650                         req = container_of(ep->queue.next,
 651                                                 struct omap_req, queue);
 652                         finish_in_dma(ep, req, 0);
 653                 }
 654                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 655
 656                 if (!list_empty(&ep->queue)) {
 657                         req = container_of(ep->queue.next,
 658                                         struct omap_req, queue);
 659                         next_in_dma(ep, req);
 660                 }
 661         }
 662
 663         /* OUT dma: rx from host */
 664         if (irq_src & UDC_RXN_EOT) {
 665                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 666                 ep->irqs++;
 667                 /* can see RXN_EOT after dma abort */
 668                 if (!list_empty(&ep->queue)) {
 669                         req = container_of(ep->queue.next,
 670                                         struct omap_req, queue);
 671                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 672                 }
 673                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 674
 675                 if (!list_empty(&ep->queue)) {
 676                         req = container_of(ep->queue.next,
 677                                         struct omap_req, queue);
 678                         next_out_dma(ep, req);
 679                 }
 680         }
 681
 682         if (irq_src & UDC_RXN_CNT) {
 683                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 684                 ep->irqs++;
 685                 /* omap15xx does this unasked... */
 686                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 687                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 688         }
 689 }
 690
 691 static void dma_error(int lch, u16 ch_status, void *data)
 692 {
 693         struct omap_ep  *ep = data;
 694
 695         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 696         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 697         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 698
 699         /* complete current transfer ... */
 700 }
 701
 702 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 703 {
 704         u16     reg;
 705         int     status, restart, is_in;
 706         int     dma_channel;
 707
 708         is_in = ep->bEndpointAddress & USB_DIR_IN;
 709         if (is_in)
 710                 reg = omap_readw(UDC_TXDMA_CFG);
 711         else
 712                 reg = omap_readw(UDC_RXDMA_CFG);
 713         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 714
 715         ep->dma_channel = 0;
 716         ep->lch = -1;
 717         if (channel == 0 || channel > 3) {
 718                 if ((reg & 0x0f00) == 0)
 719                         channel = 3;
 720                 else if ((reg & 0x00f0) == 0)
 721                         channel = 2;
 722                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 723                         channel = 1;
 724                 else {
 725                         status = -EMLINK;
 726                         goto just_restart;
 727                 }
 728         }
 729         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 730         ep->dma_channel = channel;
 731
 732         if (is_in) {
 733                 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 734                 status = omap_request_dma(dma_channel,
 735                         ep->ep.name, dma_error, ep, &ep->lch);
 736                 if (status == 0) {
 737                         omap_writew(reg, UDC_TXDMA_CFG);
 738                         /* EMIFF or SDRC */
 739                         omap_set_dma_src_burst_mode(ep->lch,
 740                                                 OMAP_DMA_DATA_BURST_4);
 741                         omap_set_dma_src_data_pack(ep->lch, 1);
 742                         /* TIPB */
 743                         omap_set_dma_dest_params(ep->lch,
 744                                 OMAP_DMA_PORT_TIPB,
 745                                 OMAP_DMA_AMODE_CONSTANT,
 746                                 UDC_DATA_DMA,
 747                                 0, 0);
 748                 }
 749         } else {
 750                 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 751                 status = omap_request_dma(dma_channel,
 752                         ep->ep.name, dma_error, ep, &ep->lch);
 753                 if (status == 0) {
 754                         omap_writew(reg, UDC_RXDMA_CFG);
 755                         /* TIPB */
 756                         omap_set_dma_src_params(ep->lch,
 757                                 OMAP_DMA_PORT_TIPB,
 758                                 OMAP_DMA_AMODE_CONSTANT,
 759                                 UDC_DATA_DMA,
 760                                 0, 0);
 761                         /* EMIFF or SDRC */
 762                         omap_set_dma_dest_burst_mode(ep->lch,
 763                                                 OMAP_DMA_DATA_BURST_4);
 764                         omap_set_dma_dest_data_pack(ep->lch, 1);
 765                 }
 766         }
 767         if (status)
 768                 ep->dma_channel = 0;
 769         else {
 770                 ep->has_dma = 1;
 771                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 772
 773                 /* channel type P: hw synch (fifo) */
 774                 if (!cpu_is_omap15xx())
 775                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 776         }
 777
 778 just_restart:
 779         /* restart any queue, even if the claim failed  */
 780         restart = !ep->stopped && !list_empty(&ep->queue);
 781
 782         if (status)
 783                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 784                         restart ? " (restart)" : "");
 785         else
 786                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 787                         is_in ? 't' : 'r',
 788                         ep->dma_channel - 1, ep->lch,
 789                         restart ? " (restart)" : "");
 790
 791         if (restart) {
 792                 struct omap_req *req;
 793                 req = container_of(ep->queue.next, struct omap_req, queue);
 794                 if (ep->has_dma)
 795                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 796                 else {
 797                         use_ep(ep, UDC_EP_SEL);
 798                         (is_in ? write_fifo : read_fifo)(ep, req);
 799                         deselect_ep();
 800                         if (!is_in) {
 801                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 802                                 ep->ackwait = 1 + ep->double_buf;
 803                         }
 804                         /* IN: 6 wait states before it'll tx */
 805                 }
 806         }
 807 }
 808
 809 static void dma_channel_release(struct omap_ep *ep)
 810 {
 811         int             shift = 4 * (ep->dma_channel - 1);
 812         u16             mask = 0x0f << shift;
 813         struct omap_req *req;
 814         int             active;
 815
 816         /* abort any active usb transfer request */
 817         if (!list_empty(&ep->queue))
 818                 req = container_of(ep->queue.next, struct omap_req, queue);
 819         else
 820                 req = NULL;
 821
 822         active = omap_get_dma_active_status(ep->lch);
 823
 824         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 825                         active ? "active" : "idle",
 826                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 827                         ep->dma_channel - 1, req);
 828
 829         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 830          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 831          */
 832
 833         /* wait till current packet DMA finishes, and fifo empties */
 834         if (ep->bEndpointAddress & USB_DIR_IN) {
 835                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 836                                         UDC_TXDMA_CFG);
 837
 838                 if (req) {
 839                         finish_in_dma(ep, req, -ECONNRESET);
 840
 841                         /* clear FIFO; hosts probably won't empty it */
 842                         use_ep(ep, UDC_EP_SEL);
 843                         omap_writew(UDC_CLR_EP, UDC_CTRL);
 844                         deselect_ep();
 845                 }
 846                 while (omap_readw(UDC_TXDMA_CFG) & mask)
 847                         udelay(10);
 848         } else {
 849                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 850                                         UDC_RXDMA_CFG);
 851
 852                 /* dma empties the fifo */
 853                 while (omap_readw(UDC_RXDMA_CFG) & mask)
 854                         udelay(10);
 855                 if (req)
 856                         finish_out_dma(ep, req, -ECONNRESET, 0);
 857         }
 858         omap_free_dma(ep->lch);
 859         ep->dma_channel = 0;
 860         ep->lch = -1;
 861         /* has_dma still set, till endpoint is fully quiesced */
 862 }
 863
 864
 865 /*-------------------------------------------------------------------------*/
 866
 867 static int
 868 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 869 {
 870         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 871         struct omap_req *req = container_of(_req, struct omap_req, req);
 872         struct omap_udc *udc;
 873         unsigned long   flags;
 874         int             is_iso = 0;
 875
 876         /* catch various bogus parameters */
 877         if (!_req || !req->req.complete || !req->req.buf
 878                         || !list_empty(&req->queue)) {
 879                 DBG("%s, bad params\n", __func__);
 880                 return -EINVAL;
 881         }
 882         if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
 883                 DBG("%s, bad ep\n", __func__);
 884                 return -EINVAL;
 885         }
 886         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 887                 if (req->req.length > ep->ep.maxpacket)
 888                         return -EMSGSIZE;
 889                 is_iso = 1;
 890         }
 891
 892         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 893          * have a hard time with partial packet reads...  reject it.
 894          */
 895         if (use_dma
 896                         && ep->has_dma
 897                         && ep->bEndpointAddress != 0
 898                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 899                         && (req->req.length % ep->ep.maxpacket) != 0) {
 900                 DBG("%s, no partial packet OUT reads\n", __func__);
 901                 return -EMSGSIZE;
 902         }
 903
 904         udc = ep->udc;
 905         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 906                 return -ESHUTDOWN;
 907
 908         if (use_dma && ep->has_dma)
 909                 usb_gadget_map_request(&udc->gadget, &req->req,
 910                                 (ep->bEndpointAddress & USB_DIR_IN));
 911
 912         VDBG("%s queue req %p, len %d buf %p\n",
 913                 ep->ep.name, _req, _req->length, _req->buf);
 914
 915         spin_lock_irqsave(&udc->lock, flags);
 916
 917         req->req.status = -EINPROGRESS;
 918         req->req.actual = 0;
 919
 920         /* maybe kickstart non-iso i/o queues */
 921         if (is_iso) {
 922                 u16 w;
 923
 924                 w = omap_readw(UDC_IRQ_EN);
 925                 w |= UDC_SOF_IE;
 926                 omap_writew(w, UDC_IRQ_EN);
 927         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 928                 int     is_in;
 929
 930                 if (ep->bEndpointAddress == 0) {
 931                         if (!udc->ep0_pending || !list_empty(&ep->queue)) {
 932                                 spin_unlock_irqrestore(&udc->lock, flags);
 933                                 return -EL2HLT;
 934                         }
 935
 936                         /* empty DATA stage? */
 937                         is_in = udc->ep0_in;
 938                         if (!req->req.length) {
 939
 940                                 /* chip became CONFIGURED or ADDRESSED
 941                                  * earlier; drivers may already have queued
 942                                  * requests to non-control endpoints
 943                                  */
 944                                 if (udc->ep0_set_config) {
 945                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
 946
 947                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 948                                         if (!udc->ep0_reset_config)
 949                                                 irq_en |= UDC_EPN_RX_IE
 950                                                         | UDC_EPN_TX_IE;
 951                                         omap_writew(irq_en, UDC_IRQ_EN);
 952                                 }
 953
 954                                 /* STATUS for zero length DATA stages is
 955                                  * always an IN ... even for IN transfers,
 956                                  * a weird case which seem to stall OMAP.
 957                                  */
 958                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 959                                                 UDC_EP_NUM);
 960                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
 961                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 962                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
 963
 964                                 /* cleanup */
 965                                 udc->ep0_pending = 0;
 966                                 done(ep, req, 0);
 967                                 req = NULL;
 968
 969                         /* non-empty DATA stage */
 970                         } else if (is_in) {
 971                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 972                                                 UDC_EP_NUM);
 973                         } else {
 974                                 if (udc->ep0_setup)
 975                                         goto irq_wait;
 976                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
 977                         }
 978                 } else {
 979                         is_in = ep->bEndpointAddress & USB_DIR_IN;
 980                         if (!ep->has_dma)
 981                                 use_ep(ep, UDC_EP_SEL);
 982                         /* if ISO: SOF IRQs must be enabled/disabled! */
 983                 }
 984
 985                 if (ep->has_dma)
 986                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 987                 else if (req) {
 988                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
 989                                 req = NULL;
 990                         deselect_ep();
 991                         if (!is_in) {
 992                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 993                                 ep->ackwait = 1 + ep->double_buf;
 994                         }
 995                         /* IN: 6 wait states before it'll tx */
 996                 }
 997         }
 998
 999 irq_wait:
1000         /* irq handler advances the queue */
1001         if (req != NULL)
1002                 list_add_tail(&req->queue, &ep->queue);
1003         spin_unlock_irqrestore(&udc->lock, flags);
1004
1005         return 0;
1006 }
1007
1008 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1009 {
1010         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1011         struct omap_req *req;
1012         unsigned long   flags;
1013
1014         if (!_ep || !_req)
1015                 return -EINVAL;
1016
1017         spin_lock_irqsave(&ep->udc->lock, flags);
1018
1019         /* make sure it's actually queued on this endpoint */
1020         list_for_each_entry(req, &ep->queue, queue) {
1021                 if (&req->req == _req)
1022                         break;
1023         }
1024         if (&req->req != _req) {
1025                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1026                 return -EINVAL;
1027         }
1028
1029         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1030                 int channel = ep->dma_channel;
1031
1032                 /* releasing the channel cancels the request,
1033                  * reclaiming the channel restarts the queue
1034                  */
1035                 dma_channel_release(ep);
1036                 dma_channel_claim(ep, channel);
1037         } else
1038                 done(ep, req, -ECONNRESET);
1039         spin_unlock_irqrestore(&ep->udc->lock, flags);
1040         return 0;
1041 }
1042
1043 /*-------------------------------------------------------------------------*/
1044
1045 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1046 {
1047         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1048         unsigned long   flags;
1049         int             status = -EOPNOTSUPP;
1050
1051         spin_lock_irqsave(&ep->udc->lock, flags);
1052
1053         /* just use protocol stalls for ep0; real halts are annoying */
1054         if (ep->bEndpointAddress == 0) {
1055                 if (!ep->udc->ep0_pending)
1056                         status = -EINVAL;
1057                 else if (value) {
1058                         if (ep->udc->ep0_set_config) {
1059                                 WARNING("error changing config?\n");
1060                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1061                         }
1062                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1063                         ep->udc->ep0_pending = 0;
1064                         status = 0;
1065                 } else /* NOP */
1066                         status = 0;
1067
1068         /* otherwise, all active non-ISO endpoints can halt */
1069         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1070
1071                 /* IN endpoints must already be idle */
1072                 if ((ep->bEndpointAddress & USB_DIR_IN)
1073                                 && !list_empty(&ep->queue)) {
1074                         status = -EAGAIN;
1075                         goto done;
1076                 }
1077
1078                 if (value) {
1079                         int     channel;
1080
1081                         if (use_dma && ep->dma_channel
1082                                         && !list_empty(&ep->queue)) {
1083                                 channel = ep->dma_channel;
1084                                 dma_channel_release(ep);
1085                         } else
1086                                 channel = 0;
1087
1088                         use_ep(ep, UDC_EP_SEL);
1089                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1090                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1091                                 status = 0;
1092                         } else
1093                                 status = -EAGAIN;
1094                         deselect_ep();
1095
1096                         if (channel)
1097                                 dma_channel_claim(ep, channel);
1098                 } else {
1099                         use_ep(ep, 0);
1100                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1101                         ep->ackwait = 0;
1102                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1103                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1104                                 ep->ackwait = 1 + ep->double_buf;
1105                         }
1106                 }
1107         }
1108 done:
1109         VDBG("%s %s halt stat %d\n", ep->ep.name,
1110                 value ? "set" : "clear", status);
1111
1112         spin_unlock_irqrestore(&ep->udc->lock, flags);
1113         return status;
1114 }
1115
1116 static struct usb_ep_ops omap_ep_ops = {
1117         .enable         = omap_ep_enable,
1118         .disable        = omap_ep_disable,
1119
1120         .alloc_request  = omap_alloc_request,
1121         .free_request   = omap_free_request,
1122
1123         .queue          = omap_ep_queue,
1124         .dequeue        = omap_ep_dequeue,
1125
1126         .set_halt       = omap_ep_set_halt,
1127         /* fifo_status ... report bytes in fifo */
1128         /* fifo_flush ... flush fifo */
1129 };
1130
1131 /*-------------------------------------------------------------------------*/
1132
1133 static int omap_get_frame(struct usb_gadget *gadget)
1134 {
1135         u16     sof = omap_readw(UDC_SOF);
1136         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1137 }
1138
1139 static int omap_wakeup(struct usb_gadget *gadget)
1140 {
1141         struct omap_udc *udc;
1142         unsigned long   flags;
1143         int             retval = -EHOSTUNREACH;
1144
1145         udc = container_of(gadget, struct omap_udc, gadget);
1146
1147         spin_lock_irqsave(&udc->lock, flags);
1148         if (udc->devstat & UDC_SUS) {
1149                 /* NOTE:  OTG spec erratum says that OTG devices may
1150                  * issue wakeups without host enable.
1151                  */
1152                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1153                         DBG("remote wakeup...\n");
1154                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1155                         retval = 0;
1156                 }
1157
1158         /* NOTE:  non-OTG systems may use SRP TOO... */
1159         } else if (!(udc->devstat & UDC_ATT)) {
1160                 if (!IS_ERR_OR_NULL(udc->transceiver))
1161                         retval = otg_start_srp(udc->transceiver->otg);
1162         }
1163         spin_unlock_irqrestore(&udc->lock, flags);
1164
1165         return retval;
1166 }
1167
1168 static int
1169 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1170 {
1171         struct omap_udc *udc;
1172         unsigned long   flags;
1173         u16             syscon1;
1174
1175         udc = container_of(gadget, struct omap_udc, gadget);
1176         spin_lock_irqsave(&udc->lock, flags);
1177         syscon1 = omap_readw(UDC_SYSCON1);
1178         if (is_selfpowered)
1179                 syscon1 |= UDC_SELF_PWR;
1180         else
1181                 syscon1 &= ~UDC_SELF_PWR;
1182         omap_writew(syscon1, UDC_SYSCON1);
1183         spin_unlock_irqrestore(&udc->lock, flags);
1184
1185         return 0;
1186 }
1187
1188 static int can_pullup(struct omap_udc *udc)
1189 {
1190         return udc->driver && udc->softconnect && udc->vbus_active;
1191 }
1192
1193 static void pullup_enable(struct omap_udc *udc)
1194 {
1195         u16 w;
1196
1197         w = omap_readw(UDC_SYSCON1);
1198         w |= UDC_PULLUP_EN;
1199         omap_writew(w, UDC_SYSCON1);
1200         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1201                 u32 l;
1202
1203                 l = omap_readl(OTG_CTRL);
1204                 l |= OTG_BSESSVLD;
1205                 omap_writel(l, OTG_CTRL);
1206         }
1207         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1208 }
1209
1210 static void pullup_disable(struct omap_udc *udc)
1211 {
1212         u16 w;
1213
1214         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1215                 u32 l;
1216
1217                 l = omap_readl(OTG_CTRL);
1218                 l &= ~OTG_BSESSVLD;
1219                 omap_writel(l, OTG_CTRL);
1220         }
1221         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1222         w = omap_readw(UDC_SYSCON1);
1223         w &= ~UDC_PULLUP_EN;
1224         omap_writew(w, UDC_SYSCON1);
1225 }
1226
1227 static struct omap_udc *udc;
1228
1229 static void omap_udc_enable_clock(int enable)
1230 {
1231         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1232                 return;
1233
1234         if (enable) {
1235                 clk_enable(udc->dc_clk);
1236                 clk_enable(udc->hhc_clk);
1237                 udelay(100);
1238         } else {
1239                 clk_disable(udc->hhc_clk);
1240                 clk_disable(udc->dc_clk);
1241         }
1242 }
1243
1244 /*
1245  * Called by whatever detects VBUS sessions:  external transceiver
1246  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1247  */
1248 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1249 {
1250         struct omap_udc *udc;
1251         unsigned long   flags;
1252         u32 l;
1253
1254         udc = container_of(gadget, struct omap_udc, gadget);
1255         spin_lock_irqsave(&udc->lock, flags);
1256         VDBG("VBUS %s\n", is_active ? "on" : "off");
1257         udc->vbus_active = (is_active != 0);
1258         if (cpu_is_omap15xx()) {
1259                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1260                 l = omap_readl(FUNC_MUX_CTRL_0);
1261                 if (is_active)
1262                         l |= VBUS_CTRL_1510;
1263                 else
1264                         l &= ~VBUS_CTRL_1510;
1265                 omap_writel(l, FUNC_MUX_CTRL_0);
1266         }
1267         if (udc->dc_clk != NULL && is_active) {
1268                 if (!udc->clk_requested) {
1269                         omap_udc_enable_clock(1);
1270                         udc->clk_requested = 1;
1271                 }
1272         }
1273         if (can_pullup(udc))
1274                 pullup_enable(udc);
1275         else
1276                 pullup_disable(udc);
1277         if (udc->dc_clk != NULL && !is_active) {
1278                 if (udc->clk_requested) {
1279                         omap_udc_enable_clock(0);
1280                         udc->clk_requested = 0;
1281                 }
1282         }
1283         spin_unlock_irqrestore(&udc->lock, flags);
1284         return 0;
1285 }
1286
1287 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1288 {
1289         struct omap_udc *udc;
1290
1291         udc = container_of(gadget, struct omap_udc, gadget);
1292         if (!IS_ERR_OR_NULL(udc->transceiver))
1293                 return usb_phy_set_power(udc->transceiver, mA);
1294         return -EOPNOTSUPP;
1295 }
1296
1297 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1298 {
1299         struct omap_udc *udc;
1300         unsigned long   flags;
1301
1302         udc = container_of(gadget, struct omap_udc, gadget);
1303         spin_lock_irqsave(&udc->lock, flags);
1304         udc->softconnect = (is_on != 0);
1305         if (can_pullup(udc))
1306                 pullup_enable(udc);
1307         else
1308                 pullup_disable(udc);
1309         spin_unlock_irqrestore(&udc->lock, flags);
1310         return 0;
1311 }
1312
1313 static int omap_udc_start(struct usb_gadget *g,
1314                 struct usb_gadget_driver *driver);
1315 static int omap_udc_stop(struct usb_gadget *g,
1316                 struct usb_gadget_driver *driver);
1317
1318 static const struct usb_gadget_ops omap_gadget_ops = {
1319         .get_frame              = omap_get_frame,
1320         .wakeup                 = omap_wakeup,
1321         .set_selfpowered        = omap_set_selfpowered,
1322         .vbus_session           = omap_vbus_session,
1323         .vbus_draw              = omap_vbus_draw,
1324         .pullup                 = omap_pullup,
1325         .udc_start              = omap_udc_start,
1326         .udc_stop               = omap_udc_stop,
1327 };
1328
1329 /*-------------------------------------------------------------------------*/
1330
1331 /* dequeue ALL requests; caller holds udc->lock */
1332 static void nuke(struct omap_ep *ep, int status)
1333 {
1334         struct omap_req *req;
1335
1336         ep->stopped = 1;
1337
1338         if (use_dma && ep->dma_channel)
1339                 dma_channel_release(ep);
1340
1341         use_ep(ep, 0);
1342         omap_writew(UDC_CLR_EP, UDC_CTRL);
1343         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1344                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1345
1346         while (!list_empty(&ep->queue)) {
1347                 req = list_entry(ep->queue.next, struct omap_req, queue);
1348                 done(ep, req, status);
1349         }
1350 }
1351
1352 /* caller holds udc->lock */
1353 static void udc_quiesce(struct omap_udc *udc)
1354 {
1355         struct omap_ep  *ep;
1356
1357         udc->gadget.speed = USB_SPEED_UNKNOWN;
1358         nuke(&udc->ep[0], -ESHUTDOWN);
1359         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1360                 nuke(ep, -ESHUTDOWN);
1361 }
1362
1363 /*-------------------------------------------------------------------------*/
1364
1365 static void update_otg(struct omap_udc *udc)
1366 {
1367         u16     devstat;
1368
1369         if (!gadget_is_otg(&udc->gadget))
1370                 return;
1371
1372         if (omap_readl(OTG_CTRL) & OTG_ID)
1373                 devstat = omap_readw(UDC_DEVSTAT);
1374         else
1375                 devstat = 0;
1376
1377         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1378         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1379         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1380
1381         /* Enable HNP early, avoiding races on suspend irq path.
1382          * ASSUMES OTG state machine B_BUS_REQ input is true.
1383          */
1384         if (udc->gadget.b_hnp_enable) {
1385                 u32 l;
1386
1387                 l = omap_readl(OTG_CTRL);
1388                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1389                 l &= ~OTG_PULLUP;
1390                 omap_writel(l, OTG_CTRL);
1391         }
1392 }
1393
1394 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1395 {
1396         struct omap_ep  *ep0 = &udc->ep[0];
1397         struct omap_req *req = NULL;
1398
1399         ep0->irqs++;
1400
1401         /* Clear any pending requests and then scrub any rx/tx state
1402          * before starting to handle the SETUP request.
1403          */
1404         if (irq_src & UDC_SETUP) {
1405                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1406
1407                 nuke(ep0, 0);
1408                 if (ack) {
1409                         omap_writew(ack, UDC_IRQ_SRC);
1410                         irq_src = UDC_SETUP;
1411                 }
1412         }
1413
1414         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1415          * This driver uses only uses protocol stalls (ep0 never halts),
1416          * and if we got this far the gadget driver already had a
1417          * chance to stall.  Tries to be forgiving of host oddities.
1418          *
1419          * NOTE:  the last chance gadget drivers have to stall control
1420          * requests is during their request completion callback.
1421          */
1422         if (!list_empty(&ep0->queue))
1423                 req = container_of(ep0->queue.next, struct omap_req, queue);
1424
1425         /* IN == TX to host */
1426         if (irq_src & UDC_EP0_TX) {
1427                 int     stat;
1428
1429                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1430                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1431                 stat = omap_readw(UDC_STAT_FLG);
1432                 if (stat & UDC_ACK) {
1433                         if (udc->ep0_in) {
1434                                 /* write next IN packet from response,
1435                                  * or set up the status stage.
1436                                  */
1437                                 if (req)
1438                                         stat = write_fifo(ep0, req);
1439                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1440                                 if (!req && udc->ep0_pending) {
1441                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1442                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1443                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1444                                         omap_writew(0, UDC_EP_NUM);
1445                                         udc->ep0_pending = 0;
1446                                 } /* else:  6 wait states before it'll tx */
1447                         } else {
1448                                 /* ack status stage of OUT transfer */
1449                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1450                                 if (req)
1451                                         done(ep0, req, 0);
1452                         }
1453                         req = NULL;
1454                 } else if (stat & UDC_STALL) {
1455                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1456                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1457                 } else {
1458                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1459                 }
1460         }
1461
1462         /* OUT == RX from host */
1463         if (irq_src & UDC_EP0_RX) {
1464                 int     stat;
1465
1466                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1467                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1468                 stat = omap_readw(UDC_STAT_FLG);
1469                 if (stat & UDC_ACK) {
1470                         if (!udc->ep0_in) {
1471                                 stat = 0;
1472                                 /* read next OUT packet of request, maybe
1473                                  * reactiviting the fifo; stall on errors.
1474                                  */
1475                                 stat = read_fifo(ep0, req);
1476                                 if (!req || stat < 0) {
1477                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1478                                         udc->ep0_pending = 0;
1479                                         stat = 0;
1480                                 } else if (stat == 0)
1481                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1482                                 omap_writew(0, UDC_EP_NUM);
1483
1484                                 /* activate status stage */
1485                                 if (stat == 1) {
1486                                         done(ep0, req, 0);
1487                                         /* that may have STALLed ep0... */
1488                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1489                                                         UDC_EP_NUM);
1490                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1491                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1492                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1493                                         udc->ep0_pending = 0;
1494                                 }
1495                         } else {
1496                                 /* ack status stage of IN transfer */
1497                                 omap_writew(0, UDC_EP_NUM);
1498                                 if (req)
1499                                         done(ep0, req, 0);
1500                         }
1501                 } else if (stat & UDC_STALL) {
1502                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1503                         omap_writew(0, UDC_EP_NUM);
1504                 } else {
1505                         omap_writew(0, UDC_EP_NUM);
1506                 }
1507         }
1508
1509         /* SETUP starts all control transfers */
1510         if (irq_src & UDC_SETUP) {
1511                 union u {
1512                         u16                     word[4];
1513                         struct usb_ctrlrequest  r;
1514                 } u;
1515                 int                     status = -EINVAL;
1516                 struct omap_ep          *ep;
1517
1518                 /* read the (latest) SETUP message */
1519                 do {
1520                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1521                         /* two bytes at a time */
1522                         u.word[0] = omap_readw(UDC_DATA);
1523                         u.word[1] = omap_readw(UDC_DATA);
1524                         u.word[2] = omap_readw(UDC_DATA);
1525                         u.word[3] = omap_readw(UDC_DATA);
1526                         omap_writew(0, UDC_EP_NUM);
1527                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1528
1529 #define w_value         le16_to_cpu(u.r.wValue)
1530 #define w_index         le16_to_cpu(u.r.wIndex)
1531 #define w_length        le16_to_cpu(u.r.wLength)
1532
1533                 /* Delegate almost all control requests to the gadget driver,
1534                  * except for a handful of ch9 status/feature requests that
1535                  * hardware doesn't autodecode _and_ the gadget API hides.
1536                  */
1537                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1538                 udc->ep0_set_config = 0;
1539                 udc->ep0_pending = 1;
1540                 ep0->stopped = 0;
1541                 ep0->ackwait = 0;
1542                 switch (u.r.bRequest) {
1543                 case USB_REQ_SET_CONFIGURATION:
1544                         /* udc needs to know when ep != 0 is valid */
1545                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1546                                 goto delegate;
1547                         if (w_length != 0)
1548                                 goto do_stall;
1549                         udc->ep0_set_config = 1;
1550                         udc->ep0_reset_config = (w_value == 0);
1551                         VDBG("set config %d\n", w_value);
1552
1553                         /* update udc NOW since gadget driver may start
1554                          * queueing requests immediately; clear config
1555                          * later if it fails the request.
1556                          */
1557                         if (udc->ep0_reset_config)
1558                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1559                         else
1560                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1561                         update_otg(udc);
1562                         goto delegate;
1563                 case USB_REQ_CLEAR_FEATURE:
1564                         /* clear endpoint halt */
1565                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1566                                 goto delegate;
1567                         if (w_value != USB_ENDPOINT_HALT
1568                                         || w_length != 0)
1569                                 goto do_stall;
1570                         ep = &udc->ep[w_index & 0xf];
1571                         if (ep != ep0) {
1572                                 if (w_index & USB_DIR_IN)
1573                                         ep += 16;
1574                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1575                                                 || !ep->ep.desc)
1576                                         goto do_stall;
1577                                 use_ep(ep, 0);
1578                                 omap_writew(udc->clr_halt, UDC_CTRL);
1579                                 ep->ackwait = 0;
1580                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1581                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1582                                         ep->ackwait = 1 + ep->double_buf;
1583                                 }
1584                                 /* NOTE:  assumes the host behaves sanely,
1585                                  * only clearing real halts.  Else we may
1586                                  * need to kill pending transfers and then
1587                                  * restart the queue... very messy for DMA!
1588                                  */
1589                         }
1590                         VDBG("%s halt cleared by host\n", ep->name);
1591                         goto ep0out_status_stage;
1592                 case USB_REQ_SET_FEATURE:
1593                         /* set endpoint halt */
1594                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1595                                 goto delegate;
1596                         if (w_value != USB_ENDPOINT_HALT
1597                                         || w_length != 0)
1598                                 goto do_stall;
1599                         ep = &udc->ep[w_index & 0xf];
1600                         if (w_index & USB_DIR_IN)
1601                                 ep += 16;
1602                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1603                                         || ep == ep0 || !ep->ep.desc)
1604                                 goto do_stall;
1605                         if (use_dma && ep->has_dma) {
1606                                 /* this has rude side-effects (aborts) and
1607                                  * can't really work if DMA-IN is active
1608                                  */
1609                                 DBG("%s host set_halt, NYET\n", ep->name);
1610                                 goto do_stall;
1611                         }
1612                         use_ep(ep, 0);
1613                         /* can't halt if fifo isn't empty... */
1614                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1615                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1616                         VDBG("%s halted by host\n", ep->name);
1617 ep0out_status_stage:
1618                         status = 0;
1619                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1620                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1621                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1622                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1623                         udc->ep0_pending = 0;
1624                         break;
1625                 case USB_REQ_GET_STATUS:
1626                         /* USB_ENDPOINT_HALT status? */
1627                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1628                                 goto intf_status;
1629
1630                         /* ep0 never stalls */
1631                         if (!(w_index & 0xf))
1632                                 goto zero_status;
1633
1634                         /* only active endpoints count */
1635                         ep = &udc->ep[w_index & 0xf];
1636                         if (w_index & USB_DIR_IN)
1637                                 ep += 16;
1638                         if (!ep->ep.desc)
1639                                 goto do_stall;
1640
1641                         /* iso never stalls */
1642                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1643                                 goto zero_status;
1644
1645                         /* FIXME don't assume non-halted endpoints!! */
1646                         ERR("%s status, can't report\n", ep->ep.name);
1647                         goto do_stall;
1648
1649 intf_status:
1650                         /* return interface status.  if we were pedantic,
1651                          * we'd detect non-existent interfaces, and stall.
1652                          */
1653                         if (u.r.bRequestType
1654                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1655                                 goto delegate;
1656
1657 zero_status:
1658                         /* return two zero bytes */
1659                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1660                         omap_writew(0, UDC_DATA);
1661                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1662                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1663                         status = 0;
1664                         VDBG("GET_STATUS, interface %d\n", w_index);
1665                         /* next, status stage */
1666                         break;
1667                 default:
1668 delegate:
1669                         /* activate the ep0out fifo right away */
1670                         if (!udc->ep0_in && w_length) {
1671                                 omap_writew(0, UDC_EP_NUM);
1672                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1673                         }
1674
1675                         /* gadget drivers see class/vendor specific requests,
1676                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1677                          * and more
1678                          */
1679                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1680                                 u.r.bRequestType, u.r.bRequest,
1681                                 w_value, w_index, w_length);
1682
1683 #undef  w_value
1684 #undef  w_index
1685 #undef  w_length
1686
1687                         /* The gadget driver may return an error here,
1688                          * causing an immediate protocol stall.
1689                          *
1690                          * Else it must issue a response, either queueing a
1691                          * response buffer for the DATA stage, or halting ep0
1692                          * (causing a protocol stall, not a real halt).  A
1693                          * zero length buffer means no DATA stage.
1694                          *
1695                          * It's fine to issue that response after the setup()
1696                          * call returns, and this IRQ was handled.
1697                          */
1698                         udc->ep0_setup = 1;
1699                         spin_unlock(&udc->lock);
1700                         status = udc->driver->setup(&udc->gadget, &u.r);
1701                         spin_lock(&udc->lock);
1702                         udc->ep0_setup = 0;
1703                 }
1704
1705                 if (status < 0) {
1706 do_stall:
1707                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1708                                         u.r.bRequestType, u.r.bRequest, status);
1709                         if (udc->ep0_set_config) {
1710                                 if (udc->ep0_reset_config)
1711                                         WARNING("error resetting config?\n");
1712                                 else
1713                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1714                         }
1715                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1716                         udc->ep0_pending = 0;
1717                 }
1718         }
1719 }
1720
1721 /*-------------------------------------------------------------------------*/
1722
1723 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1724
1725 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1726 {
1727         u16     devstat, change;
1728
1729         devstat = omap_readw(UDC_DEVSTAT);
1730         change = devstat ^ udc->devstat;
1731         udc->devstat = devstat;
1732
1733         if (change & (UDC_USB_RESET|UDC_ATT)) {
1734                 udc_quiesce(udc);
1735
1736                 if (change & UDC_ATT) {
1737                         /* driver for any external transceiver will
1738                          * have called omap_vbus_session() already
1739                          */
1740                         if (devstat & UDC_ATT) {
1741                                 udc->gadget.speed = USB_SPEED_FULL;
1742                                 VDBG("connect\n");
1743                                 if (IS_ERR_OR_NULL(udc->transceiver))
1744                                         pullup_enable(udc);
1745                                 /* if (driver->connect) call it */
1746                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1747                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1748                                 if (IS_ERR_OR_NULL(udc->transceiver))
1749                                         pullup_disable(udc);
1750                                 DBG("disconnect, gadget %s\n",
1751                                         udc->driver->driver.name);
1752                                 if (udc->driver->disconnect) {
1753                                         spin_unlock(&udc->lock);
1754                                         udc->driver->disconnect(&udc->gadget);
1755                                         spin_lock(&udc->lock);
1756                                 }
1757                         }
1758                         change &= ~UDC_ATT;
1759                 }
1760
1761                 if (change & UDC_USB_RESET) {
1762                         if (devstat & UDC_USB_RESET) {
1763                                 VDBG("RESET=1\n");
1764                         } else {
1765                                 udc->gadget.speed = USB_SPEED_FULL;
1766                                 INFO("USB reset done, gadget %s\n",
1767                                         udc->driver->driver.name);
1768                                 /* ep0 traffic is legal from now on */
1769                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1770                                                 UDC_IRQ_EN);
1771                         }
1772                         change &= ~UDC_USB_RESET;
1773                 }
1774         }
1775         if (change & UDC_SUS) {
1776                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1777                         /* FIXME tell isp1301 to suspend/resume (?) */
1778                         if (devstat & UDC_SUS) {
1779                                 VDBG("suspend\n");
1780                                 update_otg(udc);
1781                                 /* HNP could be under way already */
1782                                 if (udc->gadget.speed == USB_SPEED_FULL
1783                                                 && udc->driver->suspend) {
1784                                         spin_unlock(&udc->lock);
1785                                         udc->driver->suspend(&udc->gadget);
1786                                         spin_lock(&udc->lock);
1787                                 }
1788                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1789                                         usb_phy_set_suspend(
1790                                                         udc->transceiver, 1);
1791                         } else {
1792                                 VDBG("resume\n");
1793                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1794                                         usb_phy_set_suspend(
1795                                                         udc->transceiver, 0);
1796                                 if (udc->gadget.speed == USB_SPEED_FULL
1797                                                 && udc->driver->resume) {
1798                                         spin_unlock(&udc->lock);
1799                                         udc->driver->resume(&udc->gadget);
1800                                         spin_lock(&udc->lock);
1801                                 }
1802                         }
1803                 }
1804                 change &= ~UDC_SUS;
1805         }
1806         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1807                 update_otg(udc);
1808                 change &= ~OTG_FLAGS;
1809         }
1810
1811         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1812         if (change)
1813                 VDBG("devstat %03x, ignore change %03x\n",
1814                         devstat,  change);
1815
1816         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1817 }
1818
1819 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1820 {
1821         struct omap_udc *udc = _udc;
1822         u16             irq_src;
1823         irqreturn_t     status = IRQ_NONE;
1824         unsigned long   flags;
1825
1826         spin_lock_irqsave(&udc->lock, flags);
1827         irq_src = omap_readw(UDC_IRQ_SRC);
1828
1829         /* Device state change (usb ch9 stuff) */
1830         if (irq_src & UDC_DS_CHG) {
1831                 devstate_irq(_udc, irq_src);
1832                 status = IRQ_HANDLED;
1833                 irq_src &= ~UDC_DS_CHG;
1834         }
1835
1836         /* EP0 control transfers */
1837         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1838                 ep0_irq(_udc, irq_src);
1839                 status = IRQ_HANDLED;
1840                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1841         }
1842
1843         /* DMA transfer completion */
1844         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1845                 dma_irq(_udc, irq_src);
1846                 status = IRQ_HANDLED;
1847                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1848         }
1849
1850         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1851         if (irq_src)
1852                 DBG("udc_irq, unhandled %03x\n", irq_src);
1853         spin_unlock_irqrestore(&udc->lock, flags);
1854
1855         return status;
1856 }
1857
1858 /* workaround for seemingly-lost IRQs for RX ACKs... */
1859 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1860 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1861
1862 static void pio_out_timer(unsigned long _ep)
1863 {
1864         struct omap_ep  *ep = (void *) _ep;
1865         unsigned long   flags;
1866         u16             stat_flg;
1867
1868         spin_lock_irqsave(&ep->udc->lock, flags);
1869         if (!list_empty(&ep->queue) && ep->ackwait) {
1870                 use_ep(ep, UDC_EP_SEL);
1871                 stat_flg = omap_readw(UDC_STAT_FLG);
1872
1873                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1874                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1875                         struct omap_req *req;
1876
1877                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1878                         req = container_of(ep->queue.next,
1879                                         struct omap_req, queue);
1880                         (void) read_fifo(ep, req);
1881                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1882                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1883                         ep->ackwait = 1 + ep->double_buf;
1884                 } else
1885                         deselect_ep();
1886         }
1887         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1888         spin_unlock_irqrestore(&ep->udc->lock, flags);
1889 }
1890
1891 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1892 {
1893         u16             epn_stat, irq_src;
1894         irqreturn_t     status = IRQ_NONE;
1895         struct omap_ep  *ep;
1896         int             epnum;
1897         struct omap_udc *udc = _dev;
1898         struct omap_req *req;
1899         unsigned long   flags;
1900
1901         spin_lock_irqsave(&udc->lock, flags);
1902         epn_stat = omap_readw(UDC_EPN_STAT);
1903         irq_src = omap_readw(UDC_IRQ_SRC);
1904
1905         /* handle OUT first, to avoid some wasteful NAKs */
1906         if (irq_src & UDC_EPN_RX) {
1907                 epnum = (epn_stat >> 8) & 0x0f;
1908                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1909                 status = IRQ_HANDLED;
1910                 ep = &udc->ep[epnum];
1911                 ep->irqs++;
1912
1913                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1914                 ep->fnf = 0;
1915                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1916                         ep->ackwait--;
1917                         if (!list_empty(&ep->queue)) {
1918                                 int stat;
1919                                 req = container_of(ep->queue.next,
1920                                                 struct omap_req, queue);
1921                                 stat = read_fifo(ep, req);
1922                                 if (!ep->double_buf)
1923                                         ep->fnf = 1;
1924                         }
1925                 }
1926                 /* min 6 clock delay before clearing EP_SEL ... */
1927                 epn_stat = omap_readw(UDC_EPN_STAT);
1928                 epn_stat = omap_readw(UDC_EPN_STAT);
1929                 omap_writew(epnum, UDC_EP_NUM);
1930
1931                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1932                  * reduces lossage; timer still needed though (sigh).
1933                  */
1934                 if (ep->fnf) {
1935                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1936                         ep->ackwait = 1 + ep->double_buf;
1937                 }
1938                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1939         }
1940
1941         /* then IN transfers */
1942         else if (irq_src & UDC_EPN_TX) {
1943                 epnum = epn_stat & 0x0f;
1944                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1945                 status = IRQ_HANDLED;
1946                 ep = &udc->ep[16 + epnum];
1947                 ep->irqs++;
1948
1949                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1950                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1951                         ep->ackwait = 0;
1952                         if (!list_empty(&ep->queue)) {
1953                                 req = container_of(ep->queue.next,
1954                                                 struct omap_req, queue);
1955                                 (void) write_fifo(ep, req);
1956                         }
1957                 }
1958                 /* min 6 clock delay before clearing EP_SEL ... */
1959                 epn_stat = omap_readw(UDC_EPN_STAT);
1960                 epn_stat = omap_readw(UDC_EPN_STAT);
1961                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1962                 /* then 6 clocks before it'd tx */
1963         }
1964
1965         spin_unlock_irqrestore(&udc->lock, flags);
1966         return status;
1967 }
1968
1969 #ifdef  USE_ISO
1970 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1971 {
1972         struct omap_udc *udc = _dev;
1973         struct omap_ep  *ep;
1974         int             pending = 0;
1975         unsigned long   flags;
1976
1977         spin_lock_irqsave(&udc->lock, flags);
1978
1979         /* handle all non-DMA ISO transfers */
1980         list_for_each_entry(ep, &udc->iso, iso) {
1981                 u16             stat;
1982                 struct omap_req *req;
1983
1984                 if (ep->has_dma || list_empty(&ep->queue))
1985                         continue;
1986                 req = list_entry(ep->queue.next, struct omap_req, queue);
1987
1988                 use_ep(ep, UDC_EP_SEL);
1989                 stat = omap_readw(UDC_STAT_FLG);
1990
1991                 /* NOTE: like the other controller drivers, this isn't
1992                  * currently reporting lost or damaged frames.
1993                  */
1994                 if (ep->bEndpointAddress & USB_DIR_IN) {
1995                         if (stat & UDC_MISS_IN)
1996                                 /* done(ep, req, -EPROTO) */;
1997                         else
1998                                 write_fifo(ep, req);
1999                 } else {
2000                         int     status = 0;
2001
2002                         if (stat & UDC_NO_RXPACKET)
2003                                 status = -EREMOTEIO;
2004                         else if (stat & UDC_ISO_ERR)
2005                                 status = -EILSEQ;
2006                         else if (stat & UDC_DATA_FLUSH)
2007                                 status = -ENOSR;
2008
2009                         if (status)
2010                                 /* done(ep, req, status) */;
2011                         else
2012                                 read_fifo(ep, req);
2013                 }
2014                 deselect_ep();
2015                 /* 6 wait states before next EP */
2016
2017                 ep->irqs++;
2018                 if (!list_empty(&ep->queue))
2019                         pending = 1;
2020         }
2021         if (!pending) {
2022                 u16 w;
2023
2024                 w = omap_readw(UDC_IRQ_EN);
2025                 w &= ~UDC_SOF_IE;
2026                 omap_writew(w, UDC_IRQ_EN);
2027         }
2028         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2029
2030         spin_unlock_irqrestore(&udc->lock, flags);
2031         return IRQ_HANDLED;
2032 }
2033 #endif
2034
2035 /*-------------------------------------------------------------------------*/
2036
2037 static inline int machine_without_vbus_sense(void)
2038 {
2039         return machine_is_omap_innovator()
2040                 || machine_is_omap_osk()
2041                 || machine_is_sx1()
2042                 /* No known omap7xx boards with vbus sense */
2043                 || cpu_is_omap7xx();
2044 }
2045
2046 static int omap_udc_start(struct usb_gadget *g,
2047                 struct usb_gadget_driver *driver)
2048 {
2049         int             status = -ENODEV;
2050         struct omap_ep  *ep;
2051         unsigned long   flags;
2052
2053
2054         spin_lock_irqsave(&udc->lock, flags);
2055         /* reset state */
2056         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2057                 ep->irqs = 0;
2058                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2059                         continue;
2060                 use_ep(ep, 0);
2061                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2062         }
2063         udc->ep0_pending = 0;
2064         udc->ep[0].irqs = 0;
2065         udc->softconnect = 1;
2066
2067         /* hook up the driver */
2068         driver->driver.bus = NULL;
2069         udc->driver = driver;
2070         spin_unlock_irqrestore(&udc->lock, flags);
2071
2072         if (udc->dc_clk != NULL)
2073                 omap_udc_enable_clock(1);
2074
2075         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2076
2077         /* connect to bus through transceiver */
2078         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2079                 status = otg_set_peripheral(udc->transceiver->otg,
2080                                                 &udc->gadget);
2081                 if (status < 0) {
2082                         ERR("can't bind to transceiver\n");
2083                         if (driver->unbind) {
2084                                 driver->unbind(&udc->gadget);
2085                                 udc->driver = NULL;
2086                         }
2087                         goto done;
2088                 }
2089         } else {
2090                 if (can_pullup(udc))
2091                         pullup_enable(udc);
2092                 else
2093                         pullup_disable(udc);
2094         }
2095
2096         /* boards that don't have VBUS sensing can't autogate 48MHz;
2097          * can't enter deep sleep while a gadget driver is active.
2098          */
2099         if (machine_without_vbus_sense())
2100                 omap_vbus_session(&udc->gadget, 1);
2101
2102 done:
2103         if (udc->dc_clk != NULL)
2104                 omap_udc_enable_clock(0);
2105
2106         return status;
2107 }
2108
2109 static int omap_udc_stop(struct usb_gadget *g,
2110                 struct usb_gadget_driver *driver)
2111 {
2112         unsigned long   flags;
2113         int             status = -ENODEV;
2114
2115         if (udc->dc_clk != NULL)
2116                 omap_udc_enable_clock(1);
2117
2118         if (machine_without_vbus_sense())
2119                 omap_vbus_session(&udc->gadget, 0);
2120
2121         if (!IS_ERR_OR_NULL(udc->transceiver))
2122                 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2123         else
2124                 pullup_disable(udc);
2125
2126         spin_lock_irqsave(&udc->lock, flags);
2127         udc_quiesce(udc);
2128         spin_unlock_irqrestore(&udc->lock, flags);
2129
2130         udc->driver = NULL;
2131
2132         if (udc->dc_clk != NULL)
2133                 omap_udc_enable_clock(0);
2134
2135         return status;
2136 }
2137
2138 /*-------------------------------------------------------------------------*/
2139
2140 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2141
2142 #include <linux/seq_file.h>
2143
2144 static const char proc_filename[] = "driver/udc";
2145
2146 #define FOURBITS "%s%s%s%s"
2147 #define EIGHTBITS "%s%s%s%s%s%s%s%s"
2148
2149 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2150 {
2151         u16             stat_flg;
2152         struct omap_req *req;
2153         char            buf[20];
2154
2155         use_ep(ep, 0);
2156
2157         if (use_dma && ep->has_dma)
2158                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2159                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2160                         ep->dma_channel - 1, ep->lch);
2161         else
2162                 buf[0] = 0;
2163
2164         stat_flg = omap_readw(UDC_STAT_FLG);
2165         seq_printf(s,
2166                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2167                 ep->name, buf,
2168                 ep->double_buf ? "dbuf " : "",
2169                 ({ char *s;
2170                 switch (ep->ackwait) {
2171                 case 0:
2172                         s = "";
2173                         break;
2174                 case 1:
2175                         s = "(ackw) ";
2176                         break;
2177                 case 2:
2178                         s = "(ackw2) ";
2179                         break;
2180                 default:
2181                         s = "(?) ";
2182                         break;
2183                 } s; }),
2184                 ep->irqs, stat_flg,
2185                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2186                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2187                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2188                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2189                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2190                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2191                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2192                 (stat_flg & UDC_STALL) ? "STALL " : "",
2193                 (stat_flg & UDC_NAK) ? "NAK " : "",
2194                 (stat_flg & UDC_ACK) ? "ACK " : "",
2195                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2196                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2197                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2198
2199         if (list_empty(&ep->queue))
2200                 seq_printf(s, "\t(queue empty)\n");
2201         else
2202                 list_for_each_entry(req, &ep->queue, queue) {
2203                         unsigned        length = req->req.actual;
2204
2205                         if (use_dma && buf[0]) {
2206                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2207                                                 ? dma_src_len : dma_dest_len)
2208                                         (ep, req->req.dma + length);
2209                                 buf[0] = 0;
2210                         }
2211                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2212                                         &req->req, length,
2213                                         req->req.length, req->req.buf);
2214                 }
2215 }
2216
2217 static char *trx_mode(unsigned m, int enabled)
2218 {
2219         switch (m) {
2220         case 0:
2221                 return enabled ? "*6wire" : "unused";
2222         case 1:
2223                 return "4wire";
2224         case 2:
2225                 return "3wire";
2226         case 3:
2227                 return "6wire";
2228         default:
2229                 return "unknown";
2230         }
2231 }
2232
2233 static int proc_otg_show(struct seq_file *s)
2234 {
2235         u32             tmp;
2236         u32             trans = 0;
2237         char            *ctrl_name = "(UNKNOWN)";
2238
2239         tmp = omap_readl(OTG_REV);
2240         ctrl_name = "tranceiver_ctrl";
2241         trans = omap_readw(USB_TRANSCEIVER_CTRL);
2242         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2243                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2244         tmp = omap_readw(OTG_SYSCON_1);
2245         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2246                         FOURBITS "\n", tmp,
2247                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2248                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2249                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2250                         ? "internal"
2251                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2252                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2253                 (tmp & HST_IDLE_EN) ? " !host" : "",
2254                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2255                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2256         tmp = omap_readl(OTG_SYSCON_2);
2257         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2258                         " b_ase_brst=%d hmc=%d\n", tmp,
2259                 (tmp & OTG_EN) ? " otg_en" : "",
2260                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2261                 /* much more SRP stuff */
2262                 (tmp & SRP_DATA) ? " srp_data" : "",
2263                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2264                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2265                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2266                 (tmp & UHOST_EN) ? " uhost_en" : "",
2267                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2268                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2269                 B_ASE_BRST(tmp),
2270                 OTG_HMC(tmp));
2271         tmp = omap_readl(OTG_CTRL);
2272         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2273                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2274                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2275                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2276                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2277                 (tmp & OTG_ID) ? " id" : "",
2278                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2279                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2280                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2281                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2282                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2283                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2284                 (tmp & OTG_PULLDOWN) ? " down" : "",
2285                 (tmp & OTG_PULLUP) ? " up" : "",
2286                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2287                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2288                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2289                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2290                 );
2291         tmp = omap_readw(OTG_IRQ_EN);
2292         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2293         tmp = omap_readw(OTG_IRQ_SRC);
2294         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2295         tmp = omap_readw(OTG_OUTCTRL);
2296         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2297         tmp = omap_readw(OTG_TEST);
2298         seq_printf(s, "otg_test    %04x" "\n", tmp);
2299         return 0;
2300 }
2301
2302 static int proc_udc_show(struct seq_file *s, void *_)
2303 {
2304         u32             tmp;
2305         struct omap_ep  *ep;
2306         unsigned long   flags;
2307
2308         spin_lock_irqsave(&udc->lock, flags);
2309
2310         seq_printf(s, "%s, version: " DRIVER_VERSION
2311 #ifdef  USE_ISO
2312                 " (iso)"
2313 #endif
2314                 "%s\n",
2315                 driver_desc,
2316                 use_dma ?  " (dma)" : "");
2317
2318         tmp = omap_readw(UDC_REV) & 0xff;
2319         seq_printf(s,
2320                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2321                 "hmc %d, transceiver %s\n",
2322                 tmp >> 4, tmp & 0xf,
2323                 fifo_mode,
2324                 udc->driver ? udc->driver->driver.name : "(none)",
2325                 HMC,
2326                 udc->transceiver
2327                         ? udc->transceiver->label
2328                         : (cpu_is_omap1710()
2329                                 ? "external" : "(none)"));
2330         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2331                 omap_readw(ULPD_CLOCK_CTRL),
2332                 omap_readw(ULPD_SOFT_REQ),
2333                 omap_readw(ULPD_STATUS_REQ));
2334
2335         /* OTG controller registers */
2336         if (!cpu_is_omap15xx())
2337                 proc_otg_show(s);
2338
2339         tmp = omap_readw(UDC_SYSCON1);
2340         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2341                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2342                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2343                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2344                 (tmp & UDC_NAK_EN) ? " nak" : "",
2345                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2346                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2347                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2348                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2349         /* syscon2 is write-only */
2350
2351         /* UDC controller registers */
2352         if (!(tmp & UDC_PULLUP_EN)) {
2353                 seq_printf(s, "(suspended)\n");
2354                 spin_unlock_irqrestore(&udc->lock, flags);
2355                 return 0;
2356         }
2357
2358         tmp = omap_readw(UDC_DEVSTAT);
2359         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2360                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2361                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2362                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2363                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2364                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2365                 (tmp & UDC_SUS) ? " SUS" : "",
2366                 (tmp & UDC_CFG) ? " CFG" : "",
2367                 (tmp & UDC_ADD) ? " ADD" : "",
2368                 (tmp & UDC_DEF) ? " DEF" : "",
2369                 (tmp & UDC_ATT) ? " ATT" : "");
2370         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2371         tmp = omap_readw(UDC_IRQ_EN);
2372         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2373                 (tmp & UDC_SOF_IE) ? " sof" : "",
2374                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2375                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2376                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2377                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2378         tmp = omap_readw(UDC_IRQ_SRC);
2379         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2380                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2381                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2382                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2383                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2384                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2385                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2386                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2387                 (tmp & UDC_SETUP) ? " setup" : "",
2388                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2389                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2390         if (use_dma) {
2391                 unsigned i;
2392
2393                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2394                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2395                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2396                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2397                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2398
2399                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2400                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2401                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2402
2403                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2404                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2405                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2406
2407                 tmp = omap_readw(UDC_RXDMA_CFG);
2408                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2409                 if (tmp) {
2410                         for (i = 0; i < 3; i++) {
2411                                 if ((tmp & (0x0f << (i * 4))) == 0)
2412                                         continue;
2413                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2414                                                 omap_readw(UDC_RXDMA(i + 1)));
2415                         }
2416                 }
2417                 tmp = omap_readw(UDC_TXDMA_CFG);
2418                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2419                 if (tmp) {
2420                         for (i = 0; i < 3; i++) {
2421                                 if (!(tmp & (0x0f << (i * 4))))
2422                                         continue;
2423                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2424                                                 omap_readw(UDC_TXDMA(i + 1)));
2425                         }
2426                 }
2427         }
2428
2429         tmp = omap_readw(UDC_DEVSTAT);
2430         if (tmp & UDC_ATT) {
2431                 proc_ep_show(s, &udc->ep[0]);
2432                 if (tmp & UDC_ADD) {
2433                         list_for_each_entry(ep, &udc->gadget.ep_list,
2434                                         ep.ep_list) {
2435                                 if (ep->ep.desc)
2436                                         proc_ep_show(s, ep);
2437                         }
2438                 }
2439         }
2440         spin_unlock_irqrestore(&udc->lock, flags);
2441         return 0;
2442 }
2443
2444 static int proc_udc_open(struct inode *inode, struct file *file)
2445 {
2446         return single_open(file, proc_udc_show, NULL);
2447 }
2448
2449 static const struct file_operations proc_ops = {
2450         .owner          = THIS_MODULE,
2451         .open           = proc_udc_open,
2452         .read           = seq_read,
2453         .llseek         = seq_lseek,
2454         .release        = single_release,
2455 };
2456
2457 static void create_proc_file(void)
2458 {
2459         proc_create(proc_filename, 0, NULL, &proc_ops);
2460 }
2461
2462 static void remove_proc_file(void)
2463 {
2464         remove_proc_entry(proc_filename, NULL);
2465 }
2466
2467 #else
2468
2469 static inline void create_proc_file(void) {}
2470 static inline void remove_proc_file(void) {}
2471
2472 #endif
2473
2474 /*-------------------------------------------------------------------------*/
2475
2476 /* Before this controller can enumerate, we need to pick an endpoint
2477  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2478  * buffer space among the endpoints we'll be operating.
2479  *
2480  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2481  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2482  * capability yet though.
2483  */
2484 static unsigned
2485 omap_ep_setup(char *name, u8 addr, u8 type,
2486                 unsigned buf, unsigned maxp, int dbuf)
2487 {
2488         struct omap_ep  *ep;
2489         u16             epn_rxtx = 0;
2490
2491         /* OUT endpoints first, then IN */
2492         ep = &udc->ep[addr & 0xf];
2493         if (addr & USB_DIR_IN)
2494                 ep += 16;
2495
2496         /* in case of ep init table bugs */
2497         BUG_ON(ep->name[0]);
2498
2499         /* chip setup ... bit values are same for IN, OUT */
2500         if (type == USB_ENDPOINT_XFER_ISOC) {
2501                 switch (maxp) {
2502                 case 8:
2503                         epn_rxtx = 0 << 12;
2504                         break;
2505                 case 16:
2506                         epn_rxtx = 1 << 12;
2507                         break;
2508                 case 32:
2509                         epn_rxtx = 2 << 12;
2510                         break;
2511                 case 64:
2512                         epn_rxtx = 3 << 12;
2513                         break;
2514                 case 128:
2515                         epn_rxtx = 4 << 12;
2516                         break;
2517                 case 256:
2518                         epn_rxtx = 5 << 12;
2519                         break;
2520                 case 512:
2521                         epn_rxtx = 6 << 12;
2522                         break;
2523                 default:
2524                         BUG();
2525                 }
2526                 epn_rxtx |= UDC_EPN_RX_ISO;
2527                 dbuf = 1;
2528         } else {
2529                 /* double-buffering "not supported" on 15xx,
2530                  * and ignored for PIO-IN on newer chips
2531                  * (for more reliable behavior)
2532                  */
2533                 if (!use_dma || cpu_is_omap15xx())
2534                         dbuf = 0;
2535
2536                 switch (maxp) {
2537                 case 8:
2538                         epn_rxtx = 0 << 12;
2539                         break;
2540                 case 16:
2541                         epn_rxtx = 1 << 12;
2542                         break;
2543                 case 32:
2544                         epn_rxtx = 2 << 12;
2545                         break;
2546                 case 64:
2547                         epn_rxtx = 3 << 12;
2548                         break;
2549                 default:
2550                         BUG();
2551                 }
2552                 if (dbuf && addr)
2553                         epn_rxtx |= UDC_EPN_RX_DB;
2554                 init_timer(&ep->timer);
2555                 ep->timer.function = pio_out_timer;
2556                 ep->timer.data = (unsigned long) ep;
2557         }
2558         if (addr)
2559                 epn_rxtx |= UDC_EPN_RX_VALID;
2560         BUG_ON(buf & 0x07);
2561         epn_rxtx |= buf >> 3;
2562
2563         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2564                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2565
2566         if (addr & USB_DIR_IN)
2567                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2568         else
2569                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2570
2571         /* next endpoint's buffer starts after this one's */
2572         buf += maxp;
2573         if (dbuf)
2574                 buf += maxp;
2575         BUG_ON(buf > 2048);
2576
2577         /* set up driver data structures */
2578         BUG_ON(strlen(name) >= sizeof ep->name);
2579         strlcpy(ep->name, name, sizeof ep->name);
2580         INIT_LIST_HEAD(&ep->queue);
2581         INIT_LIST_HEAD(&ep->iso);
2582         ep->bEndpointAddress = addr;
2583         ep->bmAttributes = type;
2584         ep->double_buf = dbuf;
2585         ep->udc = udc;
2586
2587         ep->ep.name = ep->name;
2588         ep->ep.ops = &omap_ep_ops;
2589         ep->ep.maxpacket = ep->maxpacket = maxp;
2590         list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2591
2592         return buf;
2593 }
2594
2595 static void omap_udc_release(struct device *dev)
2596 {
2597         complete(udc->done);
2598         kfree(udc);
2599         udc = NULL;
2600 }
2601
2602 static int
2603 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2604 {
2605         unsigned        tmp, buf;
2606
2607         /* abolish any previous hardware state */
2608         omap_writew(0, UDC_SYSCON1);
2609         omap_writew(0, UDC_IRQ_EN);
2610         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2611         omap_writew(0, UDC_DMA_IRQ_EN);
2612         omap_writew(0, UDC_RXDMA_CFG);
2613         omap_writew(0, UDC_TXDMA_CFG);
2614
2615         /* UDC_PULLUP_EN gates the chip clock */
2616         /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2617
2618         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2619         if (!udc)
2620                 return -ENOMEM;
2621
2622         spin_lock_init(&udc->lock);
2623
2624         udc->gadget.ops = &omap_gadget_ops;
2625         udc->gadget.ep0 = &udc->ep[0].ep;
2626         INIT_LIST_HEAD(&udc->gadget.ep_list);
2627         INIT_LIST_HEAD(&udc->iso);
2628         udc->gadget.speed = USB_SPEED_UNKNOWN;
2629         udc->gadget.max_speed = USB_SPEED_FULL;
2630         udc->gadget.name = driver_name;
2631         udc->transceiver = xceiv;
2632
2633         /* ep0 is special; put it right after the SETUP buffer */
2634         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2635                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2636         list_del_init(&udc->ep[0].ep.ep_list);
2637
2638         /* initially disable all non-ep0 endpoints */
2639         for (tmp = 1; tmp < 15; tmp++) {
2640                 omap_writew(0, UDC_EP_RX(tmp));
2641                 omap_writew(0, UDC_EP_TX(tmp));
2642         }
2643
2644 #define OMAP_BULK_EP(name, addr) \
2645         buf = omap_ep_setup(name "-bulk", addr, \
2646                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2647 #define OMAP_INT_EP(name, addr, maxp) \
2648         buf = omap_ep_setup(name "-int", addr, \
2649                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2650 #define OMAP_ISO_EP(name, addr, maxp) \
2651         buf = omap_ep_setup(name "-iso", addr, \
2652                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2653
2654         switch (fifo_mode) {
2655         case 0:
2656                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2657                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2658                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2659                 break;
2660         case 1:
2661                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2662                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2663                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2664
2665                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2666                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2667                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2668
2669                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2670                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2671                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2672
2673                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2674                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2675                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2676
2677                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2678                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2679                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2680                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2681
2682                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2683                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2684                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2685                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2686
2687                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2688                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2689
2690                 break;
2691
2692 #ifdef  USE_ISO
2693         case 2:                 /* mixed iso/bulk */
2694                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2695                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2696                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2697                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2698
2699                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2700
2701                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2702                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2703                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2704                 break;
2705         case 3:                 /* mixed bulk/iso */
2706                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2707                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2708                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2709
2710                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2711                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2712                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2713
2714                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2715                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2716                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2717                 break;
2718 #endif
2719
2720         /* add more modes as needed */
2721
2722         default:
2723                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2724                 return -ENODEV;
2725         }
2726         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2727         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2728         return 0;
2729 }
2730
2731 static int omap_udc_probe(struct platform_device *pdev)
2732 {
2733         int                     status = -ENODEV;
2734         int                     hmc;
2735         struct usb_phy          *xceiv = NULL;
2736         const char              *type = NULL;
2737         struct omap_usb_config  *config = pdev->dev.platform_data;
2738         struct clk              *dc_clk = NULL;
2739         struct clk              *hhc_clk = NULL;
2740
2741         if (cpu_is_omap7xx())
2742                 use_dma = 0;
2743
2744         /* NOTE:  "knows" the order of the resources! */
2745         if (!request_mem_region(pdev->resource[0].start,
2746                         pdev->resource[0].end - pdev->resource[0].start + 1,
2747                         driver_name)) {
2748                 DBG("request_mem_region failed\n");
2749                 return -EBUSY;
2750         }
2751
2752         if (cpu_is_omap16xx()) {
2753                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2754                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2755                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2756                 /* can't use omap_udc_enable_clock yet */
2757                 clk_enable(dc_clk);
2758                 clk_enable(hhc_clk);
2759                 udelay(100);
2760         }
2761
2762         if (cpu_is_omap7xx()) {
2763                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2764                 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2765                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2766                 /* can't use omap_udc_enable_clock yet */
2767                 clk_enable(dc_clk);
2768                 clk_enable(hhc_clk);
2769                 udelay(100);
2770         }
2771
2772         INFO("OMAP UDC rev %d.%d%s\n",
2773                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2774                 config->otg ? ", Mini-AB" : "");
2775
2776         /* use the mode given to us by board init code */
2777         if (cpu_is_omap15xx()) {
2778                 hmc = HMC_1510;
2779                 type = "(unknown)";
2780
2781                 if (machine_without_vbus_sense()) {
2782                         /* just set up software VBUS detect, and then
2783                          * later rig it so we always report VBUS.
2784                          * FIXME without really sensing VBUS, we can't
2785                          * know when to turn PULLUP_EN on/off; and that
2786                          * means we always "need" the 48MHz clock.
2787                          */
2788                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2789                         tmp &= ~VBUS_CTRL_1510;
2790                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2791                         tmp |= VBUS_MODE_1510;
2792                         tmp &= ~VBUS_CTRL_1510;
2793                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2794                 }
2795         } else {
2796                 /* The transceiver may package some GPIO logic or handle
2797                  * loopback and/or transceiverless setup; if we find one,
2798                  * use it.  Except for OTG, we don't _need_ to talk to one;
2799                  * but not having one probably means no VBUS detection.
2800                  */
2801                 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2802                 if (!IS_ERR_OR_NULL(xceiv))
2803                         type = xceiv->label;
2804                 else if (config->otg) {
2805                         DBG("OTG requires external transceiver!\n");
2806                         goto cleanup0;
2807                 }
2808
2809                 hmc = HMC_1610;
2810
2811                 switch (hmc) {
2812                 case 0:                 /* POWERUP DEFAULT == 0 */
2813                 case 4:
2814                 case 12:
2815                 case 20:
2816                         if (!cpu_is_omap1710()) {
2817                                 type = "integrated";
2818                                 break;
2819                         }
2820                         /* FALL THROUGH */
2821                 case 3:
2822                 case 11:
2823                 case 16:
2824                 case 19:
2825                 case 25:
2826                         if (IS_ERR_OR_NULL(xceiv)) {
2827                                 DBG("external transceiver not registered!\n");
2828                                 type = "unknown";
2829                         }
2830                         break;
2831                 case 21:                        /* internal loopback */
2832                         type = "loopback";
2833                         break;
2834                 case 14:                        /* transceiverless */
2835                         if (cpu_is_omap1710())
2836                                 goto bad_on_1710;
2837                         /* FALL THROUGH */
2838                 case 13:
2839                 case 15:
2840                         type = "no";
2841                         break;
2842
2843                 default:
2844 bad_on_1710:
2845                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2846                         goto cleanup0;
2847                 }
2848         }
2849
2850         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2851
2852         /* a "gadget" abstracts/virtualizes the controller */
2853         status = omap_udc_setup(pdev, xceiv);
2854         if (status)
2855                 goto cleanup0;
2856
2857         xceiv = NULL;
2858         /* "udc" is now valid */
2859         pullup_disable(udc);
2860 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2861         udc->gadget.is_otg = (config->otg != 0);
2862 #endif
2863
2864         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2865         if (omap_readw(UDC_REV) >= 0x61)
2866                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2867         else
2868                 udc->clr_halt = UDC_RESET_EP;
2869
2870         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2871         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2872                         0, driver_name, udc);
2873         if (status != 0) {
2874                 ERR("can't get irq %d, err %d\n",
2875                         (int) pdev->resource[1].start, status);
2876                 goto cleanup1;
2877         }
2878
2879         /* USB "non-iso" IRQ (PIO for all but ep0) */
2880         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2881                         0, "omap_udc pio", udc);
2882         if (status != 0) {
2883                 ERR("can't get irq %d, err %d\n",
2884                         (int) pdev->resource[2].start, status);
2885                 goto cleanup2;
2886         }
2887 #ifdef  USE_ISO
2888         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2889                         0, "omap_udc iso", udc);
2890         if (status != 0) {
2891                 ERR("can't get irq %d, err %d\n",
2892                         (int) pdev->resource[3].start, status);
2893                 goto cleanup3;
2894         }
2895 #endif
2896         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2897                 udc->dc_clk = dc_clk;
2898                 udc->hhc_clk = hhc_clk;
2899                 clk_disable(hhc_clk);
2900                 clk_disable(dc_clk);
2901         }
2902
2903         create_proc_file();
2904         status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2905                         omap_udc_release);
2906         if (status)
2907                 goto cleanup4;
2908
2909         return 0;
2910
2911 cleanup4:
2912         remove_proc_file();
2913
2914 #ifdef  USE_ISO
2915 cleanup3:
2916         free_irq(pdev->resource[2].start, udc);
2917 #endif
2918
2919 cleanup2:
2920         free_irq(pdev->resource[1].start, udc);
2921
2922 cleanup1:
2923         kfree(udc);
2924         udc = NULL;
2925
2926 cleanup0:
2927         if (!IS_ERR_OR_NULL(xceiv))
2928                 usb_put_phy(xceiv);
2929
2930         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2931                 clk_disable(hhc_clk);
2932                 clk_disable(dc_clk);
2933                 clk_put(hhc_clk);
2934                 clk_put(dc_clk);
2935         }
2936
2937         release_mem_region(pdev->resource[0].start,
2938                         pdev->resource[0].end - pdev->resource[0].start + 1);
2939
2940         return status;
2941 }
2942
2943 static int omap_udc_remove(struct platform_device *pdev)
2944 {
2945         DECLARE_COMPLETION_ONSTACK(done);
2946
2947         if (!udc)
2948                 return -ENODEV;
2949
2950         usb_del_gadget_udc(&udc->gadget);
2951         if (udc->driver)
2952                 return -EBUSY;
2953
2954         udc->done = &done;
2955
2956         pullup_disable(udc);
2957         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2958                 usb_put_phy(udc->transceiver);
2959                 udc->transceiver = NULL;
2960         }
2961         omap_writew(0, UDC_SYSCON1);
2962
2963         remove_proc_file();
2964
2965 #ifdef  USE_ISO
2966         free_irq(pdev->resource[3].start, udc);
2967 #endif
2968         free_irq(pdev->resource[2].start, udc);
2969         free_irq(pdev->resource[1].start, udc);
2970
2971         if (udc->dc_clk) {
2972                 if (udc->clk_requested)
2973                         omap_udc_enable_clock(0);
2974                 clk_put(udc->hhc_clk);
2975                 clk_put(udc->dc_clk);
2976         }
2977
2978         release_mem_region(pdev->resource[0].start,
2979                         pdev->resource[0].end - pdev->resource[0].start + 1);
2980
2981         wait_for_completion(&done);
2982
2983         return 0;
2984 }
2985
2986 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2987  * system is forced into deep sleep
2988  *
2989  * REVISIT we should probably reject suspend requests when there's a host
2990  * session active, rather than disconnecting, at least on boards that can
2991  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
2992  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2993  * may involve talking to an external transceiver (e.g. isp1301).
2994  */
2995
2996 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2997 {
2998         u32     devstat;
2999
3000         devstat = omap_readw(UDC_DEVSTAT);
3001
3002         /* we're requesting 48 MHz clock if the pullup is enabled
3003          * (== we're attached to the host) and we're not suspended,
3004          * which would prevent entry to deep sleep...
3005          */
3006         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3007                 WARNING("session active; suspend requires disconnect\n");
3008                 omap_pullup(&udc->gadget, 0);
3009         }
3010
3011         return 0;
3012 }
3013
3014 static int omap_udc_resume(struct platform_device *dev)
3015 {
3016         DBG("resume + wakeup/SRP\n");
3017         omap_pullup(&udc->gadget, 1);
3018
3019         /* maybe the host would enumerate us if we nudged it */
3020         msleep(100);
3021         return omap_wakeup(&udc->gadget);
3022 }
3023
3024 /*-------------------------------------------------------------------------*/
3025
3026 static struct platform_driver udc_driver = {
3027         .probe          = omap_udc_probe,
3028         .remove         = omap_udc_remove,
3029         .suspend        = omap_udc_suspend,
3030         .resume         = omap_udc_resume,
3031         .driver         = {
3032                 .owner  = THIS_MODULE,
3033                 .name   = (char *) driver_name,
3034         },
3035 };
3036
3037 module_platform_driver(udc_driver);
3038
3039 MODULE_DESCRIPTION(DRIVER_DESC);
3040 MODULE_LICENSE("GPL");
3041 MODULE_ALIAS("platform:omap_udc");