drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51 #include <linux/usb/composite.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  58 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  59                 struct dwc3_ep *dep, struct dwc3_request *req);
  60
  61 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  62 {
  63         switch (state) {
  64         case EP0_UNCONNECTED:
  65                 return "Unconnected";
  66         case EP0_SETUP_PHASE:
  67                 return "Setup Phase";
  68         case EP0_DATA_PHASE:
  69                 return "Data Phase";
  70         case EP0_STATUS_PHASE:
  71                 return "Status Phase";
  72         default:
  73                 return "UNKNOWN";
  74         }
  75 }
  76
  77 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  78                 u32 len, u32 type)
  79 {
  80         struct dwc3_gadget_ep_cmd_params params;
  81         struct dwc3_trb                 *trb;
  82         struct dwc3_ep                  *dep;
  83
  84         int                             ret;
  85
  86         dep = dwc->eps[epnum];
  87         if (dep->flags & DWC3_EP_BUSY) {
  88                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  89                 return 0;
  90         }
  91
  92         trb = dwc->ep0_trb;
  93
  94         trb->bpl = lower_32_bits(buf_dma);
  95         trb->bph = upper_32_bits(buf_dma);
  96         trb->size = len;
  97         trb->ctrl = type;
  98
  99         trb->ctrl |= (DWC3_TRB_CTRL_HWO
 100                         | DWC3_TRB_CTRL_LST
 101                         | DWC3_TRB_CTRL_IOC
 102                         | DWC3_TRB_CTRL_ISP_IMI);
 103
 104         memset(&params, 0, sizeof(params));
 105         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 106         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 107
 108         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 109                         DWC3_DEPCMD_STARTTRANSFER, &params);
 110         if (ret < 0) {
 111                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 112                 return ret;
 113         }
 114
 115         dep->flags |= DWC3_EP_BUSY;
 116         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 117                         dep->number);
 118
 119         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 120
 121         return 0;
 122 }
 123
 124 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 125                 struct dwc3_request *req)
 126 {
 127         struct dwc3             *dwc = dep->dwc;
 128
 129         req->request.actual     = 0;
 130         req->request.status     = -EINPROGRESS;
 131         req->epnum              = dep->number;
 132
 133         list_add_tail(&req->list, &dep->request_list);
 134
 135         /*
 136          * Gadget driver might not be quick enough to queue a request
 137          * before we get a Transfer Not Ready event on this endpoint.
 138          *
 139          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 140          * flag is set, it's telling us that as soon as Gadget queues the
 141          * required request, we should kick the transfer here because the
 142          * IRQ we were waiting for is long gone.
 143          */
 144         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 145                 unsigned        direction;
 146
 147                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 148
 149                 if (dwc->ep0state != EP0_DATA_PHASE) {
 150                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 151                         return 0;
 152                 }
 153
 154                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 155
 156                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 157                                 DWC3_EP0_DIR_IN);
 158
 159                 return 0;
 160         }
 161
 162         /*
 163          * In case gadget driver asked us to delay the STATUS phase,
 164          * handle it here.
 165          */
 166         if (dwc->delayed_status) {
 167                 unsigned        direction;
 168
 169                 direction = !dwc->ep0_expect_in;
 170                 dwc->delayed_status = false;
 171
 172                 if (dwc->ep0state == EP0_STATUS_PHASE)
 173                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 174                 else
 175                         dev_dbg(dwc->dev, "too early for delayed status\n");
 176
 177                 return 0;
 178         }
 179
 180         /*
 181          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 182          *
 183          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 184          * come before issueing Start Transfer command, but if we do, we will
 185          * miss situations where the host starts another SETUP phase instead of
 186          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 187          * Layer Compliance Suite.
 188          *
 189          * The problem surfaces due to the fact that in case of back-to-back
 190          * SETUP packets there will be no XferNotReady(DATA) generated and we
 191          * will be stuck waiting for XferNotReady(DATA) forever.
 192          *
 193          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 194          * it tells us to start Data Phase right away. It also mentions that if
 195          * we receive a SETUP phase instead of the DATA phase, core will issue
 196          * XferComplete for the DATA phase, before actually initiating it in
 197          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 198          * can only be used to print some debugging logs, as the core expects
 199          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 200          * just so it completes right away, without transferring anything and,
 201          * only then, we can go back to the SETUP phase.
 202          *
 203          * Because of this scenario, SNPS decided to change the programming
 204          * model of control transfers and support on-demand transfers only for
 205          * the STATUS phase. To fix the issue we have now, we will always wait
 206          * for gadget driver to queue the DATA phase's struct usb_request, then
 207          * start it right away.
 208          *
 209          * If we're actually in a 2-stage transfer, we will wait for
 210          * XferNotReady(STATUS).
 211          */
 212         if (dwc->three_stage_setup) {
 213                 unsigned        direction;
 214
 215                 direction = dwc->ep0_expect_in;
 216                 dwc->ep0state = EP0_DATA_PHASE;
 217
 218                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 219
 220                 dep->flags &= ~DWC3_EP0_DIR_IN;
 221         }
 222
 223         return 0;
 224 }
 225
 226 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 227                 gfp_t gfp_flags)
 228 {
 229         struct dwc3_request             *req = to_dwc3_request(request);
 230         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 231         struct dwc3                     *dwc = dep->dwc;
 232
 233         unsigned long                   flags;
 234
 235         int                             ret;
 236
 237         spin_lock_irqsave(&dwc->lock, flags);
 238         if (!dep->endpoint.desc) {
 239                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 240                                 request, dep->name);
 241                 ret = -ESHUTDOWN;
 242                 goto out;
 243         }
 244
 245         /* we share one TRB for ep0/1 */
 246         if (!list_empty(&dep->request_list)) {
 247                 ret = -EBUSY;
 248                 goto out;
 249         }
 250
 251         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 252                         request, dep->name, request->length,
 253                         dwc3_ep0_state_string(dwc->ep0state));
 254
 255         ret = __dwc3_gadget_ep0_queue(dep, req);
 256
 257 out:
 258         spin_unlock_irqrestore(&dwc->lock, flags);
 259
 260         return ret;
 261 }
 262
 263 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 264 {
 265         struct dwc3_ep          *dep;
 266
 267         /* reinitialize physical ep1 */
 268         dep = dwc->eps[1];
 269         dep->flags = DWC3_EP_ENABLED;
 270
 271         /* stall is always issued on EP0 */
 272         dep = dwc->eps[0];
 273         __dwc3_gadget_ep_set_halt(dep, 1, false);
 274         dep->flags = DWC3_EP_ENABLED;
 275         dwc->delayed_status = false;
 276
 277         if (!list_empty(&dep->request_list)) {
 278                 struct dwc3_request     *req;
 279
 280                 req = next_request(&dep->request_list);
 281                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 282         }
 283
 284         dwc->ep0state = EP0_SETUP_PHASE;
 285         dwc3_ep0_out_start(dwc);
 286 }
 287
 288 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 289 {
 290         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 291         struct dwc3                     *dwc = dep->dwc;
 292
 293         dwc3_ep0_stall_and_restart(dwc);
 294
 295         return 0;
 296 }
 297
 298 void dwc3_ep0_out_start(struct dwc3 *dwc)
 299 {
 300         int                             ret;
 301
 302         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 303                         DWC3_TRBCTL_CONTROL_SETUP);
 304         WARN_ON(ret < 0);
 305 }
 306
 307 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 308 {
 309         struct dwc3_ep          *dep;
 310         u32                     windex = le16_to_cpu(wIndex_le);
 311         u32                     epnum;
 312
 313         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 314         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 315                 epnum |= 1;
 316
 317         dep = dwc->eps[epnum];
 318         if (dep->flags & DWC3_EP_ENABLED)
 319                 return dep;
 320
 321         return NULL;
 322 }
 323
 324 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 325 {
 326 }
 327 /*
 328  * ch 9.4.5
 329  */
 330 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 331                 struct usb_ctrlrequest *ctrl)
 332 {
 333         struct dwc3_ep          *dep;
 334         u32                     recip;
 335         u32                     reg;
 336         u16                     usb_status = 0;
 337         __le16                  *response_pkt;
 338
 339         recip = ctrl->bRequestType & USB_RECIP_MASK;
 340         switch (recip) {
 341         case USB_RECIP_DEVICE:
 342                 /*
 343                  * LTM will be set once we know how to set this in HW.
 344                  */
 345                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 346
 347                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 348                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 349                         if (reg & DWC3_DCTL_INITU1ENA)
 350                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 351                         if (reg & DWC3_DCTL_INITU2ENA)
 352                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 353                 }
 354
 355                 break;
 356
 357         case USB_RECIP_INTERFACE:
 358                 /*
 359                  * Function Remote Wake Capable D0
 360                  * Function Remote Wakeup       D1
 361                  */
 362                 break;
 363
 364         case USB_RECIP_ENDPOINT:
 365                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 366                 if (!dep)
 367                         return -EINVAL;
 368
 369                 if (dep->flags & DWC3_EP_STALL)
 370                         usb_status = 1 << USB_ENDPOINT_HALT;
 371                 break;
 372         default:
 373                 return -EINVAL;
 374         };
 375
 376         response_pkt = (__le16 *) dwc->setup_buf;
 377         *response_pkt = cpu_to_le16(usb_status);
 378
 379         dep = dwc->eps[0];
 380         dwc->ep0_usb_req.dep = dep;
 381         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 382         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 383         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 384
 385         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 386 }
 387
 388 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 389                 struct usb_ctrlrequest *ctrl, int set)
 390 {
 391         struct dwc3_ep          *dep;
 392         u32                     recip;
 393         u32                     wValue;
 394         u32                     wIndex;
 395         u32                     reg;
 396         int                     ret;
 397         enum usb_device_state   state;
 398
 399         wValue = le16_to_cpu(ctrl->wValue);
 400         wIndex = le16_to_cpu(ctrl->wIndex);
 401         recip = ctrl->bRequestType & USB_RECIP_MASK;
 402         state = dwc->gadget.state;
 403
 404         switch (recip) {
 405         case USB_RECIP_DEVICE:
 406
 407                 switch (wValue) {
 408                 case USB_DEVICE_REMOTE_WAKEUP:
 409                         break;
 410                 /*
 411                  * 9.4.1 says only only for SS, in AddressState only for
 412                  * default control pipe
 413                  */
 414                 case USB_DEVICE_U1_ENABLE:
 415                         if (state != USB_STATE_CONFIGURED)
 416                                 return -EINVAL;
 417                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 418                                 return -EINVAL;
 419
 420                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 421                         if (set)
 422                                 reg |= DWC3_DCTL_INITU1ENA;
 423                         else
 424                                 reg &= ~DWC3_DCTL_INITU1ENA;
 425                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 426                         break;
 427
 428                 case USB_DEVICE_U2_ENABLE:
 429                         if (state != USB_STATE_CONFIGURED)
 430                                 return -EINVAL;
 431                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 432                                 return -EINVAL;
 433
 434                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435                         if (set)
 436                                 reg |= DWC3_DCTL_INITU2ENA;
 437                         else
 438                                 reg &= ~DWC3_DCTL_INITU2ENA;
 439                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440                         break;
 441
 442                 case USB_DEVICE_LTM_ENABLE:
 443                         return -EINVAL;
 444                         break;
 445
 446                 case USB_DEVICE_TEST_MODE:
 447                         if ((wIndex & 0xff) != 0)
 448                                 return -EINVAL;
 449                         if (!set)
 450                                 return -EINVAL;
 451
 452                         dwc->test_mode_nr = wIndex >> 8;
 453                         dwc->test_mode = true;
 454                         break;
 455                 default:
 456                         return -EINVAL;
 457                 }
 458                 break;
 459
 460         case USB_RECIP_INTERFACE:
 461                 switch (wValue) {
 462                 case USB_INTRF_FUNC_SUSPEND:
 463                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 464                                 /* XXX enable Low power suspend */
 465                                 ;
 466                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 467                                 /* XXX enable remote wakeup */
 468                                 ;
 469                         break;
 470                 default:
 471                         return -EINVAL;
 472                 }
 473                 break;
 474
 475         case USB_RECIP_ENDPOINT:
 476                 switch (wValue) {
 477                 case USB_ENDPOINT_HALT:
 478                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 479                         if (!dep)
 480                                 return -EINVAL;
 481                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 482                                 break;
 483                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 484                         if (ret)
 485                                 return -EINVAL;
 486                         break;
 487                 default:
 488                         return -EINVAL;
 489                 }
 490                 break;
 491
 492         default:
 493                 return -EINVAL;
 494         };
 495
 496         return 0;
 497 }
 498
 499 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 500 {
 501         enum usb_device_state state = dwc->gadget.state;
 502         u32 addr;
 503         u32 reg;
 504
 505         addr = le16_to_cpu(ctrl->wValue);
 506         if (addr > 127) {
 507                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 508                 return -EINVAL;
 509         }
 510
 511         if (state == USB_STATE_CONFIGURED) {
 512                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 513                 return -EINVAL;
 514         }
 515
 516         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 517         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 518         reg |= DWC3_DCFG_DEVADDR(addr);
 519         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 520
 521         if (addr)
 522                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 523         else
 524                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 525
 526         return 0;
 527 }
 528
 529 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 530 {
 531         int ret;
 532
 533         spin_unlock(&dwc->lock);
 534         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 535         spin_lock(&dwc->lock);
 536         return ret;
 537 }
 538
 539 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 540 {
 541         enum usb_device_state state = dwc->gadget.state;
 542         u32 cfg;
 543         int ret;
 544         u32 reg;
 545
 546         dwc->start_config_issued = false;
 547         cfg = le16_to_cpu(ctrl->wValue);
 548
 549         switch (state) {
 550         case USB_STATE_DEFAULT:
 551                 return -EINVAL;
 552                 break;
 553
 554         case USB_STATE_ADDRESS:
 555                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 556                 /* if the cfg matches and the cfg is non zero */
 557                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 558                         usb_gadget_set_state(&dwc->gadget,
 559                                         USB_STATE_CONFIGURED);
 560
 561                         /*
 562                          * Enable transition to U1/U2 state when
 563                          * nothing is pending from application.
 564                          */
 565                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 566                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 567                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 568
 569                         dwc->resize_fifos = true;
 570                         dev_dbg(dwc->dev, "resize fifos flag SET\n");
 571                 }
 572                 break;
 573
 574         case USB_STATE_CONFIGURED:
 575                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 576                 if (!cfg)
 577                         usb_gadget_set_state(&dwc->gadget,
 578                                         USB_STATE_ADDRESS);
 579                 break;
 580         default:
 581                 ret = -EINVAL;
 582         }
 583         return ret;
 584 }
 585
 586 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 587 {
 588         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 589         struct dwc3     *dwc = dep->dwc;
 590
 591         u32             param = 0;
 592         u32             reg;
 593
 594         struct timing {
 595                 u8      u1sel;
 596                 u8      u1pel;
 597                 u16     u2sel;
 598                 u16     u2pel;
 599         } __packed timing;
 600
 601         int             ret;
 602
 603         memcpy(&timing, req->buf, sizeof(timing));
 604
 605         dwc->u1sel = timing.u1sel;
 606         dwc->u1pel = timing.u1pel;
 607         dwc->u2sel = le16_to_cpu(timing.u2sel);
 608         dwc->u2pel = le16_to_cpu(timing.u2pel);
 609
 610         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 611         if (reg & DWC3_DCTL_INITU2ENA)
 612                 param = dwc->u2pel;
 613         if (reg & DWC3_DCTL_INITU1ENA)
 614                 param = dwc->u1pel;
 615
 616         /*
 617          * According to Synopsys Databook, if parameter is
 618          * greater than 125, a value of zero should be
 619          * programmed in the register.
 620          */
 621         if (param > 125)
 622                 param = 0;
 623
 624         /* now that we have the time, issue DGCMD Set Sel */
 625         ret = dwc3_send_gadget_generic_command(dwc,
 626                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 627         WARN_ON(ret < 0);
 628 }
 629
 630 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 631 {
 632         struct dwc3_ep  *dep;
 633         enum usb_device_state state = dwc->gadget.state;
 634         u16             wLength;
 635         u16             wValue;
 636
 637         if (state == USB_STATE_DEFAULT)
 638                 return -EINVAL;
 639
 640         wValue = le16_to_cpu(ctrl->wValue);
 641         wLength = le16_to_cpu(ctrl->wLength);
 642
 643         if (wLength != 6) {
 644                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 645                                 wLength);
 646                 return -EINVAL;
 647         }
 648
 649         /*
 650          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 651          * queue a usb_request for 6 bytes.
 652          *
 653          * Remember, though, this controller can't handle non-wMaxPacketSize
 654          * aligned transfers on the OUT direction, so we queue a request for
 655          * wMaxPacketSize instead.
 656          */
 657         dep = dwc->eps[0];
 658         dwc->ep0_usb_req.dep = dep;
 659         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 660         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 661         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 662
 663         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 664 }
 665
 666 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 667 {
 668         u16             wLength;
 669         u16             wValue;
 670         u16             wIndex;
 671
 672         wValue = le16_to_cpu(ctrl->wValue);
 673         wLength = le16_to_cpu(ctrl->wLength);
 674         wIndex = le16_to_cpu(ctrl->wIndex);
 675
 676         if (wIndex || wLength)
 677                 return -EINVAL;
 678
 679         /*
 680          * REVISIT It's unclear from Databook what to do with this
 681          * value. For now, just cache it.
 682          */
 683         dwc->isoch_delay = wValue;
 684
 685         return 0;
 686 }
 687
 688 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 689 {
 690         int ret;
 691
 692         switch (ctrl->bRequest) {
 693         case USB_REQ_GET_STATUS:
 694                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 695                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 696                 break;
 697         case USB_REQ_CLEAR_FEATURE:
 698                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 699                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 700                 break;
 701         case USB_REQ_SET_FEATURE:
 702                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 703                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 704                 break;
 705         case USB_REQ_SET_ADDRESS:
 706                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 707                 ret = dwc3_ep0_set_address(dwc, ctrl);
 708                 break;
 709         case USB_REQ_SET_CONFIGURATION:
 710                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 711                 ret = dwc3_ep0_set_config(dwc, ctrl);
 712                 break;
 713         case USB_REQ_SET_SEL:
 714                 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
 715                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 716                 break;
 717         case USB_REQ_SET_ISOCH_DELAY:
 718                 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
 719                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 720                 break;
 721         default:
 722                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 723                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 724                 break;
 725         };
 726
 727         return ret;
 728 }
 729
 730 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 731                 const struct dwc3_event_depevt *event)
 732 {
 733         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 734         int ret = -EINVAL;
 735         u32 len;
 736
 737         if (!dwc->gadget_driver)
 738                 goto out;
 739
 740         len = le16_to_cpu(ctrl->wLength);
 741         if (!len) {
 742                 dwc->three_stage_setup = false;
 743                 dwc->ep0_expect_in = false;
 744                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 745         } else {
 746                 dwc->three_stage_setup = true;
 747                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 748                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 749         }
 750
 751         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 752                 ret = dwc3_ep0_std_request(dwc, ctrl);
 753         else
 754                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 755
 756         if (ret == USB_GADGET_DELAYED_STATUS)
 757                 dwc->delayed_status = true;
 758
 759 out:
 760         if (ret < 0)
 761                 dwc3_ep0_stall_and_restart(dwc);
 762 }
 763
 764 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 765                 const struct dwc3_event_depevt *event)
 766 {
 767         struct dwc3_request     *r = NULL;
 768         struct usb_request      *ur;
 769         struct dwc3_trb         *trb;
 770         struct dwc3_ep          *ep0;
 771         u32                     transferred;
 772         u32                     status;
 773         u32                     length;
 774         u8                      epnum;
 775
 776         epnum = event->endpoint_number;
 777         ep0 = dwc->eps[0];
 778
 779         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 780
 781         r = next_request(&ep0->request_list);
 782         ur = &r->request;
 783
 784         trb = dwc->ep0_trb;
 785
 786         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 787         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 788                 dev_dbg(dwc->dev, "Setup Pending received\n");
 789
 790                 if (r)
 791                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 792
 793                 return;
 794         }
 795
 796         length = trb->size & DWC3_TRB_SIZE_MASK;
 797
 798         if (dwc->ep0_bounced) {
 799                 unsigned transfer_size = ur->length;
 800                 unsigned maxp = ep0->endpoint.maxpacket;
 801
 802                 transfer_size += (maxp - (transfer_size % maxp));
 803                 transferred = min_t(u32, ur->length,
 804                                 transfer_size - length);
 805                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 806         } else {
 807                 transferred = ur->length - length;
 808         }
 809
 810         ur->actual += transferred;
 811
 812         if ((epnum & 1) && ur->actual < ur->length) {
 813                 /* for some reason we did not get everything out */
 814
 815                 dwc3_ep0_stall_and_restart(dwc);
 816         } else {
 817                 /*
 818                  * handle the case where we have to send a zero packet. This
 819                  * seems to be case when req.length > maxpacket. Could it be?
 820                  */
 821                 if (r)
 822                         dwc3_gadget_giveback(ep0, r, 0);
 823         }
 824 }
 825
 826 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 827                 const struct dwc3_event_depevt *event)
 828 {
 829         struct dwc3_request     *r;
 830         struct dwc3_ep          *dep;
 831         struct dwc3_trb         *trb;
 832         u32                     status;
 833
 834         dep = dwc->eps[0];
 835         trb = dwc->ep0_trb;
 836
 837         if (!list_empty(&dep->request_list)) {
 838                 r = next_request(&dep->request_list);
 839
 840                 dwc3_gadget_giveback(dep, r, 0);
 841         }
 842
 843         if (dwc->test_mode) {
 844                 int ret;
 845
 846                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 847                 if (ret < 0) {
 848                         dev_dbg(dwc->dev, "Invalid Test #%d\n",
 849                                         dwc->test_mode_nr);
 850                         dwc3_ep0_stall_and_restart(dwc);
 851                         return;
 852                 }
 853         }
 854
 855         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 856         if (status == DWC3_TRBSTS_SETUP_PENDING)
 857                 dev_dbg(dwc->dev, "Setup Pending received\n");
 858
 859         dwc->ep0state = EP0_SETUP_PHASE;
 860         dwc3_ep0_out_start(dwc);
 861 }
 862
 863 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 864                         const struct dwc3_event_depevt *event)
 865 {
 866         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 867
 868         dep->flags &= ~DWC3_EP_BUSY;
 869         dep->resource_index = 0;
 870         dwc->setup_packet_pending = false;
 871
 872         switch (dwc->ep0state) {
 873         case EP0_SETUP_PHASE:
 874                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 875                 dwc3_ep0_inspect_setup(dwc, event);
 876                 break;
 877
 878         case EP0_DATA_PHASE:
 879                 dev_vdbg(dwc->dev, "Data Phase\n");
 880                 dwc3_ep0_complete_data(dwc, event);
 881                 break;
 882
 883         case EP0_STATUS_PHASE:
 884                 dev_vdbg(dwc->dev, "Status Phase\n");
 885                 dwc3_ep0_complete_status(dwc, event);
 886                 break;
 887         default:
 888                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 889         }
 890 }
 891
 892 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 893                 struct dwc3_ep *dep, struct dwc3_request *req)
 894 {
 895         int                     ret;
 896
 897         req->direction = !!dep->number;
 898
 899         if (req->request.length == 0) {
 900                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 901                                 dwc->ctrl_req_addr, 0,
 902                                 DWC3_TRBCTL_CONTROL_DATA);
 903         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 904                         && (dep->number == 0)) {
 905                 u32     transfer_size;
 906                 u32     maxpacket;
 907
 908                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 909                                 dep->number);
 910                 if (ret) {
 911                         dev_dbg(dwc->dev, "failed to map request\n");
 912                         return;
 913                 }
 914
 915                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 916
 917                 maxpacket = dep->endpoint.maxpacket;
 918                 transfer_size = roundup(req->request.length, maxpacket);
 919
 920                 dwc->ep0_bounced = true;
 921
 922                 /*
 923                  * REVISIT in case request length is bigger than
 924                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 925                  * TRBs to handle the transfer.
 926                  */
 927                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 928                                 dwc->ep0_bounce_addr, transfer_size,
 929                                 DWC3_TRBCTL_CONTROL_DATA);
 930         } else {
 931                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 932                                 dep->number);
 933                 if (ret) {
 934                         dev_dbg(dwc->dev, "failed to map request\n");
 935                         return;
 936                 }
 937
 938                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 939                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 940         }
 941
 942         WARN_ON(ret < 0);
 943 }
 944
 945 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 946 {
 947         struct dwc3             *dwc = dep->dwc;
 948         u32                     type;
 949
 950         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 951                 : DWC3_TRBCTL_CONTROL_STATUS2;
 952
 953         return dwc3_ep0_start_trans(dwc, dep->number,
 954                         dwc->ctrl_req_addr, 0, type);
 955 }
 956
 957 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 958 {
 959         if (dwc->resize_fifos) {
 960                 dev_dbg(dwc->dev, "starting to resize fifos\n");
 961                 dwc3_gadget_resize_tx_fifos(dwc);
 962                 dwc->resize_fifos = 0;
 963         }
 964
 965         WARN_ON(dwc3_ep0_start_control_status(dep));
 966 }
 967
 968 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 969                 const struct dwc3_event_depevt *event)
 970 {
 971         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 972
 973         __dwc3_ep0_do_control_status(dwc, dep);
 974 }
 975
 976 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
 977 {
 978         struct dwc3_gadget_ep_cmd_params params;
 979         u32                     cmd;
 980         int                     ret;
 981
 982         if (!dep->resource_index)
 983                 return;
 984
 985         cmd = DWC3_DEPCMD_ENDTRANSFER;
 986         cmd |= DWC3_DEPCMD_CMDIOC;
 987         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
 988         memset(&params, 0, sizeof(params));
 989         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 990         WARN_ON_ONCE(ret);
 991         dep->resource_index = 0;
 992 }
 993
 994 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 995                 const struct dwc3_event_depevt *event)
 996 {
 997         dwc->setup_packet_pending = true;
 998
 999         switch (event->status) {
1000         case DEPEVT_STATUS_CONTROL_DATA:
1001                 dev_vdbg(dwc->dev, "Control Data\n");
1002
1003                 /*
1004                  * We already have a DATA transfer in the controller's cache,
1005                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1006                  * it's for the wrong direction.
1007                  *
1008                  * In that case, we must issue END_TRANSFER command to the Data
1009                  * Phase we already have started and issue SetStall on the
1010                  * control endpoint.
1011                  */
1012                 if (dwc->ep0_expect_in != event->endpoint_number) {
1013                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1014
1015                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
1016                         dwc3_ep0_end_control_data(dwc, dep);
1017                         dwc3_ep0_stall_and_restart(dwc);
1018                         return;
1019                 }
1020
1021                 break;
1022
1023         case DEPEVT_STATUS_CONTROL_STATUS:
1024                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1025                         return;
1026
1027                 dev_vdbg(dwc->dev, "Control Status\n");
1028
1029                 dwc->ep0state = EP0_STATUS_PHASE;
1030
1031                 if (dwc->delayed_status) {
1032                         WARN_ON_ONCE(event->endpoint_number != 1);
1033                         dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
1034                         return;
1035                 }
1036
1037                 dwc3_ep0_do_control_status(dwc, event);
1038         }
1039 }
1040
1041 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1042                 const struct dwc3_event_depevt *event)
1043 {
1044         u8                      epnum = event->endpoint_number;
1045
1046         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1047                         dwc3_ep_event_string(event->endpoint_event),
1048                         epnum >> 1, (epnum & 1) ? "in" : "out",
1049                         dwc3_ep0_state_string(dwc->ep0state));
1050
1051         switch (event->endpoint_event) {
1052         case DWC3_DEPEVT_XFERCOMPLETE:
1053                 dwc3_ep0_xfer_complete(dwc, event);
1054                 break;
1055
1056         case DWC3_DEPEVT_XFERNOTREADY:
1057                 dwc3_ep0_xfernotready(dwc, event);
1058                 break;
1059
1060         case DWC3_DEPEVT_XFERINPROGRESS:
1061         case DWC3_DEPEVT_RXTXFIFOEVT:
1062         case DWC3_DEPEVT_STREAMEVT:
1063         case DWC3_DEPEVT_EPCMDCMPLT:
1064                 break;
1065         }
1066 }