2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - STALL_IN: non-empty bulk-in pipes cannot be halted
27 * if defined mass storage compliance succeeds but with warnings
31 * if undefined usbtest 13 fails
32 * - TRACE: enable function tracing (depends on DEBUG)
35 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
36 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
37 * - Normal & LPM support
40 * - OK: 0-12, 13 (STALL_IN defined) & 14
41 * - Not Supported: 15 & 16 (ISO)
44 * - Suspend & Remote Wakeup
46 #include <linux/delay.h>
47 #include <linux/device.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/extcon.h>
50 #include <linux/phy/phy.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/idr.h>
54 #include <linux/interrupt.h>
56 #include <linux/kernel.h>
57 #include <linux/slab.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/usb/ch9.h>
60 #include <linux/usb/gadget.h>
61 #include <linux/usb/otg.h>
62 #include <linux/usb/chipidea.h>
63 #include <linux/usb/of.h>
65 #include <linux/phy.h>
66 #include <linux/regulator/consumer.h>
67 #include <linux/usb/ehci_def.h>
76 /* Controller register map */
77 static const u8 ci_regs_nolpm[] = {
78 [CAP_CAPLENGTH] = 0x00U,
79 [CAP_HCCPARAMS] = 0x08U,
80 [CAP_DCCPARAMS] = 0x24U,
81 [CAP_TESTMODE] = 0x38U,
85 [OP_DEVICEADDR] = 0x14U,
86 [OP_ENDPTLISTADDR] = 0x18U,
88 [OP_BURSTSIZE] = 0x20U,
93 [OP_ENDPTSETUPSTAT] = 0x6CU,
94 [OP_ENDPTPRIME] = 0x70U,
95 [OP_ENDPTFLUSH] = 0x74U,
96 [OP_ENDPTSTAT] = 0x78U,
97 [OP_ENDPTCOMPLETE] = 0x7CU,
98 [OP_ENDPTCTRL] = 0x80U,
101 static const u8 ci_regs_lpm[] = {
102 [CAP_CAPLENGTH] = 0x00U,
103 [CAP_HCCPARAMS] = 0x08U,
104 [CAP_DCCPARAMS] = 0x24U,
105 [CAP_TESTMODE] = 0xFCU,
108 [OP_USBINTR] = 0x08U,
109 [OP_DEVICEADDR] = 0x14U,
110 [OP_ENDPTLISTADDR] = 0x18U,
112 [OP_BURSTSIZE] = 0x20U,
116 [OP_USBMODE] = 0xC8U,
117 [OP_ENDPTSETUPSTAT] = 0xD8U,
118 [OP_ENDPTPRIME] = 0xDCU,
119 [OP_ENDPTFLUSH] = 0xE0U,
120 [OP_ENDPTSTAT] = 0xE4U,
121 [OP_ENDPTCOMPLETE] = 0xE8U,
122 [OP_ENDPTCTRL] = 0xECU,
125 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
129 for (i = 0; i < OP_ENDPTCTRL; i++)
130 ci->hw_bank.regmap[i] =
131 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
132 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
134 for (; i <= OP_LAST; i++)
135 ci->hw_bank.regmap[i] = ci->hw_bank.op +
136 4 * (i - OP_ENDPTCTRL) +
138 ? ci_regs_lpm[OP_ENDPTCTRL]
139 : ci_regs_nolpm[OP_ENDPTCTRL]);
143 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
145 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
146 enum ci_revision rev = CI_REVISION_UNKNOWN;
149 rev = hw_read_id_reg(ci, ID_ID, REVISION)
151 rev += CI_REVISION_20;
152 } else if (ver == 0x0) {
153 rev = CI_REVISION_1X;
160 * hw_read_intr_enable: returns interrupt enable register
162 * @ci: the controller
164 * This function returns register data
166 u32 hw_read_intr_enable(struct ci_hdrc *ci)
168 return hw_read(ci, OP_USBINTR, ~0);
172 * hw_read_intr_status: returns interrupt status register
174 * @ci: the controller
176 * This function returns register data
178 u32 hw_read_intr_status(struct ci_hdrc *ci)
180 return hw_read(ci, OP_USBSTS, ~0);
184 * hw_port_test_set: writes port test mode (execute without interruption)
187 * This function returns an error code
189 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
191 const u8 TEST_MODE_MAX = 7;
193 if (mode > TEST_MODE_MAX)
196 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
201 * hw_port_test_get: reads port test mode value
203 * @ci: the controller
205 * This function returns port test mode value
207 u8 hw_port_test_get(struct ci_hdrc *ci)
209 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
212 static void hw_wait_phy_stable(void)
215 * The phy needs some delay to output the stable status from low
216 * power mode. And for OTGSC, the status inputs are debounced
217 * using a 1 ms time constant, so, delay 2ms for controller to get
218 * the stable status, like vbus and id when the phy leaves low power.
220 usleep_range(2000, 2500);
223 /* The PHY enters/leaves low power mode */
224 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
226 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
227 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
230 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
231 PORTSC_PHCD(ci->hw_bank.lpm));
232 else if (!enable && lpm)
233 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
237 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
241 /* bank is a module variable */
242 ci->hw_bank.abs = base;
244 ci->hw_bank.cap = ci->hw_bank.abs;
245 ci->hw_bank.cap += ci->platdata->capoffset;
246 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
248 hw_alloc_regmap(ci, false);
249 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
250 __ffs(HCCPARAMS_LEN);
251 ci->hw_bank.lpm = reg;
253 hw_alloc_regmap(ci, !!reg);
254 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
255 ci->hw_bank.size += OP_LAST;
256 ci->hw_bank.size /= sizeof(u32);
258 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
259 __ffs(DCCPARAMS_DEN);
260 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
262 if (ci->hw_ep_max > ENDPT_MAX)
265 ci_hdrc_enter_lpm(ci, false);
267 /* Disable all interrupts bits */
268 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
270 /* Clear all interrupts status bits*/
271 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
273 ci->rev = ci_get_revision(ci);
276 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
277 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
279 /* setup lock mode ? */
281 /* ENDPTSETUPSTAT is '0' by default */
283 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
288 static void hw_phymode_configure(struct ci_hdrc *ci)
290 u32 portsc, lpm, sts = 0;
292 switch (ci->platdata->phy_mode) {
293 case USBPHY_INTERFACE_MODE_UTMI:
294 portsc = PORTSC_PTS(PTS_UTMI);
295 lpm = DEVLC_PTS(PTS_UTMI);
297 case USBPHY_INTERFACE_MODE_UTMIW:
298 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
299 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
301 case USBPHY_INTERFACE_MODE_ULPI:
302 portsc = PORTSC_PTS(PTS_ULPI);
303 lpm = DEVLC_PTS(PTS_ULPI);
305 case USBPHY_INTERFACE_MODE_SERIAL:
306 portsc = PORTSC_PTS(PTS_SERIAL);
307 lpm = DEVLC_PTS(PTS_SERIAL);
310 case USBPHY_INTERFACE_MODE_HSIC:
311 portsc = PORTSC_PTS(PTS_HSIC);
312 lpm = DEVLC_PTS(PTS_HSIC);
318 if (ci->hw_bank.lpm) {
319 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
321 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
323 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
325 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
330 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
332 * @ci: the controller
334 * This function returns an error code if the phy failed to init
336 static int _ci_usb_phy_init(struct ci_hdrc *ci)
341 ret = phy_init(ci->phy);
345 ret = phy_power_on(ci->phy);
351 ret = usb_phy_init(ci->usb_phy);
358 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
360 * @ci: the controller
362 static void ci_usb_phy_exit(struct ci_hdrc *ci)
365 phy_power_off(ci->phy);
368 usb_phy_shutdown(ci->usb_phy);
373 * ci_usb_phy_init: initialize phy according to different phy type
374 * @ci: the controller
376 * This function returns an error code if usb_phy_init has failed
378 static int ci_usb_phy_init(struct ci_hdrc *ci)
382 switch (ci->platdata->phy_mode) {
383 case USBPHY_INTERFACE_MODE_UTMI:
384 case USBPHY_INTERFACE_MODE_UTMIW:
385 case USBPHY_INTERFACE_MODE_HSIC:
386 ret = _ci_usb_phy_init(ci);
388 hw_wait_phy_stable();
391 hw_phymode_configure(ci);
393 case USBPHY_INTERFACE_MODE_ULPI:
394 case USBPHY_INTERFACE_MODE_SERIAL:
395 hw_phymode_configure(ci);
396 ret = _ci_usb_phy_init(ci);
401 ret = _ci_usb_phy_init(ci);
403 hw_wait_phy_stable();
411 * ci_platform_configure: do controller configure
412 * @ci: the controller
415 void ci_platform_configure(struct ci_hdrc *ci)
417 bool is_device_mode, is_host_mode;
419 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
420 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
422 if (is_device_mode &&
423 (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING))
424 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
427 (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING))
428 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
430 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
432 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
434 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
437 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
438 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
440 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
442 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
443 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
444 ci->platdata->ahb_burst_config);
446 /* override burst size, take effect only when ahb_burst_config is 0 */
447 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
448 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
449 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
450 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
452 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
453 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
454 ci->platdata->rx_burst_size);
459 * hw_controller_reset: do controller reset
460 * @ci: the controller
462 * This function returns an error code
464 static int hw_controller_reset(struct ci_hdrc *ci)
468 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
469 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
479 * hw_device_reset: resets chip (execute without interruption)
480 * @ci: the controller
482 * This function returns an error code
484 int hw_device_reset(struct ci_hdrc *ci)
488 /* should flush & stop before reset */
489 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
490 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
492 ret = hw_controller_reset(ci);
494 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
498 if (ci->platdata->notify_event)
499 ci->platdata->notify_event(ci,
500 CI_HDRC_CONTROLLER_RESET_EVENT);
502 /* USBMODE should be configured step by step */
503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
504 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
506 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
508 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
509 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
510 pr_err("lpm = %i", ci->hw_bank.lpm);
514 ci_platform_configure(ci);
519 static irqreturn_t ci_irq(int irq, void *data)
521 struct ci_hdrc *ci = data;
522 irqreturn_t ret = IRQ_NONE;
526 disable_irq_nosync(irq);
527 ci->wakeup_int = true;
528 pm_runtime_get(ci->dev);
533 otgsc = hw_read_otgsc(ci, ~0);
534 if (ci_otg_is_fsm_mode(ci)) {
535 ret = ci_otg_fsm_irq(ci);
536 if (ret == IRQ_HANDLED)
542 * Handle id change interrupt, it indicates device/host function
545 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
547 /* Clear ID change irq status */
548 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
549 ci_otg_queue_work(ci);
554 * Handle vbus change interrupt, it indicates device connection
555 * and disconnection events.
557 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
558 ci->b_sess_valid_event = true;
560 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
561 ci_otg_queue_work(ci);
565 /* Handle device/host interrupt */
566 if (ci->role != CI_ROLE_END)
567 ret = ci_role(ci)->irq(ci);
572 static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
575 struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb);
576 struct ci_hdrc *ci = vbus->ci;
583 vbus->changed = true;
589 static int ci_id_notifier(struct notifier_block *nb, unsigned long event,
592 struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb);
593 struct ci_hdrc *ci = id->ci;
606 static int ci_get_platdata(struct device *dev,
607 struct ci_hdrc_platform_data *platdata)
609 struct extcon_dev *ext_vbus, *ext_id;
610 struct ci_hdrc_cable *cable;
613 if (!platdata->phy_mode)
614 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
616 if (!platdata->dr_mode)
617 platdata->dr_mode = usb_get_dr_mode(dev);
619 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
620 platdata->dr_mode = USB_DR_MODE_OTG;
622 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
623 /* Get the vbus regulator */
624 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
625 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
626 return -EPROBE_DEFER;
627 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
628 /* no vbus regulator is needed */
629 platdata->reg_vbus = NULL;
630 } else if (IS_ERR(platdata->reg_vbus)) {
631 dev_err(dev, "Getting regulator error: %ld\n",
632 PTR_ERR(platdata->reg_vbus));
633 return PTR_ERR(platdata->reg_vbus);
635 /* Get TPL support */
636 if (!platdata->tpl_support)
637 platdata->tpl_support =
638 of_usb_host_tpl_support(dev->of_node);
641 if (platdata->dr_mode == USB_DR_MODE_OTG) {
642 /* We can support HNP and SRP of OTG 2.0 */
643 platdata->ci_otg_caps.otg_rev = 0x0200;
644 platdata->ci_otg_caps.hnp_support = true;
645 platdata->ci_otg_caps.srp_support = true;
647 /* Update otg capabilities by DT properties */
648 ret = of_usb_update_otg_caps(dev->of_node,
649 &platdata->ci_otg_caps);
654 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
655 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
657 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
658 &platdata->phy_clkgate_delay_us);
660 platdata->itc_setting = 1;
662 of_property_read_u32(dev->of_node, "itc-setting",
663 &platdata->itc_setting);
665 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
666 &platdata->ahb_burst_config);
668 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
669 } else if (ret != -EINVAL) {
670 dev_err(dev, "failed to get ahb-burst-config\n");
674 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
675 &platdata->tx_burst_size);
677 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
678 } else if (ret != -EINVAL) {
679 dev_err(dev, "failed to get tx-burst-size-dword\n");
683 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
684 &platdata->rx_burst_size);
686 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
687 } else if (ret != -EINVAL) {
688 dev_err(dev, "failed to get rx-burst-size-dword\n");
692 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
693 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
695 ext_id = ERR_PTR(-ENODEV);
696 ext_vbus = ERR_PTR(-ENODEV);
697 if (of_property_read_bool(dev->of_node, "extcon")) {
698 /* Each one of them is not mandatory */
699 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
700 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
701 return PTR_ERR(ext_vbus);
703 ext_id = extcon_get_edev_by_phandle(dev, 1);
704 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
705 return PTR_ERR(ext_id);
708 cable = &platdata->vbus_extcon;
709 cable->nb.notifier_call = ci_vbus_notifier;
710 cable->edev = ext_vbus;
712 if (!IS_ERR(ext_vbus)) {
713 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB);
717 cable->state = false;
720 cable = &platdata->id_extcon;
721 cable->nb.notifier_call = ci_id_notifier;
722 cable->edev = ext_id;
724 if (!IS_ERR(ext_id)) {
725 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB_HOST);
727 cable->state = false;
734 static int ci_extcon_register(struct ci_hdrc *ci)
736 struct ci_hdrc_cable *id, *vbus;
739 id = &ci->platdata->id_extcon;
741 if (!IS_ERR(id->edev)) {
742 ret = extcon_register_notifier(id->edev, EXTCON_USB_HOST,
745 dev_err(ci->dev, "register ID failed\n");
750 vbus = &ci->platdata->vbus_extcon;
752 if (!IS_ERR(vbus->edev)) {
753 ret = extcon_register_notifier(vbus->edev, EXTCON_USB,
756 extcon_unregister_notifier(id->edev, EXTCON_USB_HOST,
758 dev_err(ci->dev, "register VBUS failed\n");
766 static void ci_extcon_unregister(struct ci_hdrc *ci)
768 struct ci_hdrc_cable *cable;
770 cable = &ci->platdata->id_extcon;
771 if (!IS_ERR(cable->edev))
772 extcon_unregister_notifier(cable->edev, EXTCON_USB_HOST,
775 cable = &ci->platdata->vbus_extcon;
776 if (!IS_ERR(cable->edev))
777 extcon_unregister_notifier(cable->edev, EXTCON_USB, &cable->nb);
780 static DEFINE_IDA(ci_ida);
782 struct platform_device *ci_hdrc_add_device(struct device *dev,
783 struct resource *res, int nres,
784 struct ci_hdrc_platform_data *platdata)
786 struct platform_device *pdev;
789 ret = ci_get_platdata(dev, platdata);
793 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
797 pdev = platform_device_alloc("ci_hdrc", id);
803 pdev->dev.parent = dev;
804 pdev->dev.dma_mask = dev->dma_mask;
805 pdev->dev.dma_parms = dev->dma_parms;
806 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
808 ret = platform_device_add_resources(pdev, res, nres);
812 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
816 ret = platform_device_add(pdev);
823 platform_device_put(pdev);
825 ida_simple_remove(&ci_ida, id);
828 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
830 void ci_hdrc_remove_device(struct platform_device *pdev)
833 platform_device_unregister(pdev);
834 ida_simple_remove(&ci_ida, id);
836 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
838 static inline void ci_role_destroy(struct ci_hdrc *ci)
840 ci_hdrc_gadget_destroy(ci);
841 ci_hdrc_host_destroy(ci);
842 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
843 ci_hdrc_otg_destroy(ci);
846 static void ci_get_otg_capable(struct ci_hdrc *ci)
848 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
851 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
852 DCCPARAMS_DC | DCCPARAMS_HC)
853 == (DCCPARAMS_DC | DCCPARAMS_HC));
855 dev_dbg(ci->dev, "It is OTG capable controller\n");
856 /* Disable and clear all OTG irq */
857 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
858 OTGSC_INT_STATUS_BITS);
862 static int ci_hdrc_probe(struct platform_device *pdev)
864 struct device *dev = &pdev->dev;
866 struct resource *res;
869 enum usb_dr_mode dr_mode;
871 if (!dev_get_platdata(dev)) {
872 dev_err(dev, "platform data missing\n");
876 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
877 base = devm_ioremap_resource(dev, res);
879 return PTR_ERR(base);
881 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
885 spin_lock_init(&ci->lock);
887 ci->platdata = dev_get_platdata(dev);
888 ci->imx28_write_fix = !!(ci->platdata->flags &
889 CI_HDRC_IMX28_WRITE_FIX);
890 ci->supports_runtime_pm = !!(ci->platdata->flags &
891 CI_HDRC_SUPPORTS_RUNTIME_PM);
893 ret = hw_device_init(ci, base);
895 dev_err(dev, "can't initialize hardware\n");
899 if (ci->platdata->phy) {
900 ci->phy = ci->platdata->phy;
901 } else if (ci->platdata->usb_phy) {
902 ci->usb_phy = ci->platdata->usb_phy;
904 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, "phys",
906 ci->phy = devm_phy_get(dev->parent, "usb-phy");
908 /* Fallback to grabbing any registered USB2 PHY */
909 if (IS_ERR(ci->usb_phy) &&
910 PTR_ERR(ci->usb_phy) != -EPROBE_DEFER)
911 ci->usb_phy = devm_usb_get_phy(dev->parent,
914 /* if both generic PHY and USB PHY layers aren't enabled */
915 if (PTR_ERR(ci->phy) == -ENOSYS &&
916 PTR_ERR(ci->usb_phy) == -ENXIO)
919 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
920 return -EPROBE_DEFER;
924 else if (IS_ERR(ci->usb_phy))
928 ret = ci_usb_phy_init(ci);
930 dev_err(dev, "unable to init phy: %d\n", ret);
934 ci->hw_bank.phys = res->start;
936 ci->irq = platform_get_irq(pdev, 0);
938 dev_err(dev, "missing IRQ\n");
943 ci_get_otg_capable(ci);
945 dr_mode = ci->platdata->dr_mode;
946 /* initialize role(s) before the interrupt is requested */
947 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
948 ret = ci_hdrc_host_init(ci);
951 dev_info(dev, "doesn't support host\n");
957 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
958 ret = ci_hdrc_gadget_init(ci);
961 dev_info(dev, "doesn't support gadget\n");
967 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
968 dev_err(dev, "no supported roles\n");
973 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
974 ret = ci_hdrc_otg_init(ci);
976 dev_err(dev, "init otg fails, ret = %d\n", ret);
981 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
983 ci->role = ci_otg_role(ci);
984 /* Enable ID change irq */
985 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
988 * If the controller is not OTG capable, but support
989 * role switch, the defalt role is gadget, and the
990 * user can switch it through debugfs.
992 ci->role = CI_ROLE_GADGET;
995 ci->role = ci->roles[CI_ROLE_HOST]
1000 if (!ci_otg_is_fsm_mode(ci)) {
1001 /* only update vbus status for peripheral */
1002 if (ci->role == CI_ROLE_GADGET)
1003 ci_handle_vbus_change(ci);
1005 ret = ci_role_start(ci, ci->role);
1007 dev_err(dev, "can't start %s role\n",
1013 platform_set_drvdata(pdev, ci);
1014 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1015 ci->platdata->name, ci);
1019 ret = ci_extcon_register(ci);
1023 if (ci->supports_runtime_pm) {
1024 pm_runtime_set_active(&pdev->dev);
1025 pm_runtime_enable(&pdev->dev);
1026 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1027 pm_runtime_mark_last_busy(ci->dev);
1028 pm_runtime_use_autosuspend(&pdev->dev);
1031 if (ci_otg_is_fsm_mode(ci))
1032 ci_hdrc_otg_fsm_start(ci);
1034 device_set_wakeup_capable(&pdev->dev, true);
1036 ret = dbg_create_files(ci);
1040 ci_extcon_unregister(ci);
1042 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1043 ci_hdrc_otg_destroy(ci);
1045 ci_hdrc_gadget_destroy(ci);
1047 ci_hdrc_host_destroy(ci);
1049 ci_usb_phy_exit(ci);
1054 static int ci_hdrc_remove(struct platform_device *pdev)
1056 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1058 if (ci->supports_runtime_pm) {
1059 pm_runtime_get_sync(&pdev->dev);
1060 pm_runtime_disable(&pdev->dev);
1061 pm_runtime_put_noidle(&pdev->dev);
1064 dbg_remove_files(ci);
1065 ci_extcon_unregister(ci);
1066 ci_role_destroy(ci);
1067 ci_hdrc_enter_lpm(ci, true);
1068 ci_usb_phy_exit(ci);
1074 /* Prepare wakeup by SRP before suspend */
1075 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1077 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1078 !hw_read_otgsc(ci, OTGSC_ID)) {
1079 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1081 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1086 /* Handle SRP when wakeup by data pulse */
1087 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1089 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1090 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1091 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1092 ci->fsm.a_srp_det = 1;
1093 ci->fsm.a_bus_drop = 0;
1097 ci_otg_queue_work(ci);
1101 static void ci_controller_suspend(struct ci_hdrc *ci)
1103 disable_irq(ci->irq);
1104 ci_hdrc_enter_lpm(ci, true);
1105 if (ci->platdata->phy_clkgate_delay_us)
1106 usleep_range(ci->platdata->phy_clkgate_delay_us,
1107 ci->platdata->phy_clkgate_delay_us + 50);
1108 usb_phy_set_suspend(ci->usb_phy, 1);
1110 enable_irq(ci->irq);
1113 static int ci_controller_resume(struct device *dev)
1115 struct ci_hdrc *ci = dev_get_drvdata(dev);
1117 dev_dbg(dev, "at %s\n", __func__);
1124 ci_hdrc_enter_lpm(ci, false);
1126 usb_phy_set_suspend(ci->usb_phy, 0);
1127 usb_phy_set_wakeup(ci->usb_phy, false);
1128 hw_wait_phy_stable();
1132 if (ci->wakeup_int) {
1133 ci->wakeup_int = false;
1134 pm_runtime_mark_last_busy(ci->dev);
1135 pm_runtime_put_autosuspend(ci->dev);
1136 enable_irq(ci->irq);
1137 if (ci_otg_is_fsm_mode(ci))
1138 ci_otg_fsm_wakeup_by_srp(ci);
1144 #ifdef CONFIG_PM_SLEEP
1145 static int ci_suspend(struct device *dev)
1147 struct ci_hdrc *ci = dev_get_drvdata(dev);
1150 flush_workqueue(ci->wq);
1152 * Controller needs to be active during suspend, otherwise the core
1153 * may run resume when the parent is at suspend if other driver's
1154 * suspend fails, it occurs before parent's suspend has not started,
1155 * but the core suspend has finished.
1158 pm_runtime_resume(dev);
1165 if (device_may_wakeup(dev)) {
1166 if (ci_otg_is_fsm_mode(ci))
1167 ci_otg_fsm_suspend_for_srp(ci);
1169 usb_phy_set_wakeup(ci->usb_phy, true);
1170 enable_irq_wake(ci->irq);
1173 ci_controller_suspend(ci);
1178 static int ci_resume(struct device *dev)
1180 struct ci_hdrc *ci = dev_get_drvdata(dev);
1183 if (device_may_wakeup(dev))
1184 disable_irq_wake(ci->irq);
1186 ret = ci_controller_resume(dev);
1190 if (ci->supports_runtime_pm) {
1191 pm_runtime_disable(dev);
1192 pm_runtime_set_active(dev);
1193 pm_runtime_enable(dev);
1198 #endif /* CONFIG_PM_SLEEP */
1200 static int ci_runtime_suspend(struct device *dev)
1202 struct ci_hdrc *ci = dev_get_drvdata(dev);
1204 dev_dbg(dev, "at %s\n", __func__);
1211 if (ci_otg_is_fsm_mode(ci))
1212 ci_otg_fsm_suspend_for_srp(ci);
1214 usb_phy_set_wakeup(ci->usb_phy, true);
1215 ci_controller_suspend(ci);
1220 static int ci_runtime_resume(struct device *dev)
1222 return ci_controller_resume(dev);
1225 #endif /* CONFIG_PM */
1226 static const struct dev_pm_ops ci_pm_ops = {
1227 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1228 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1231 static struct platform_driver ci_hdrc_driver = {
1232 .probe = ci_hdrc_probe,
1233 .remove = ci_hdrc_remove,
1240 static int __init ci_hdrc_platform_register(void)
1242 ci_hdrc_host_driver_init();
1243 return platform_driver_register(&ci_hdrc_driver);
1245 module_init(ci_hdrc_platform_register);
1247 static void __exit ci_hdrc_platform_unregister(void)
1249 platform_driver_unregister(&ci_hdrc_driver);
1251 module_exit(ci_hdrc_platform_unregister);
1253 MODULE_ALIAS("platform:ci_hdrc");
1254 MODULE_LICENSE("GPL v2");
1255 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1256 MODULE_DESCRIPTION("ChipIdea HDRC Driver");