drivers/tty/serial/pch_uart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   6 #define SUPPORT_SYSRQ
   7 #endif
   8 #include <linux/kernel.h>
   9 #include <linux/serial_reg.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <linux/pci.h>
  13 #include <linux/console.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/tty.h>
  16 #include <linux/tty_flip.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/dmi.h>
  20 #include <linux/nmi.h>
  21 #include <linux/delay.h>
  22 #include <linux/of.h>
  23
  24 #include <linux/debugfs.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34         PCH_UART_HANDLED_LS_INT_SHIFT,
  35 };
  36
  37 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  38
  39 /* Set the max number of UART port
  40  * Intel EG20T PCH: 4 port
  41  * LAPIS Semiconductor ML7213 IOH: 3 port
  42  * LAPIS Semiconductor ML7223 IOH: 2 port
  43 */
  44 #define PCH_UART_NR     4
  45
  46 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  47 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  48 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  49                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  51                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  52 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  53
  54 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  55
  56 #define PCH_UART_RBR            0x00
  57 #define PCH_UART_THR            0x00
  58
  59 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  60                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  61 #define PCH_UART_IER_ERBFI      0x00000001
  62 #define PCH_UART_IER_ETBEI      0x00000002
  63 #define PCH_UART_IER_ELSI       0x00000004
  64 #define PCH_UART_IER_EDSSI      0x00000008
  65
  66 #define PCH_UART_IIR_IP                 0x00000001
  67 #define PCH_UART_IIR_IID                0x00000006
  68 #define PCH_UART_IIR_MSI                0x00000000
  69 #define PCH_UART_IIR_TRI                0x00000002
  70 #define PCH_UART_IIR_RRI                0x00000004
  71 #define PCH_UART_IIR_REI                0x00000006
  72 #define PCH_UART_IIR_TOI                0x00000008
  73 #define PCH_UART_IIR_FIFO256            0x00000020
  74 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  75 #define PCH_UART_IIR_FE                 0x000000C0
  76
  77 #define PCH_UART_FCR_FIFOE              0x00000001
  78 #define PCH_UART_FCR_RFR                0x00000002
  79 #define PCH_UART_FCR_TFR                0x00000004
  80 #define PCH_UART_FCR_DMS                0x00000008
  81 #define PCH_UART_FCR_FIFO256            0x00000020
  82 #define PCH_UART_FCR_RFTL               0x000000C0
  83
  84 #define PCH_UART_FCR_RFTL1              0x00000000
  85 #define PCH_UART_FCR_RFTL64             0x00000040
  86 #define PCH_UART_FCR_RFTL128            0x00000080
  87 #define PCH_UART_FCR_RFTL224            0x000000C0
  88 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  89 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  90 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  91 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  92 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  93 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  94 #define PCH_UART_FCR_RFTL_SHIFT         6
  95
  96 #define PCH_UART_LCR_WLS        0x00000003
  97 #define PCH_UART_LCR_STB        0x00000004
  98 #define PCH_UART_LCR_PEN        0x00000008
  99 #define PCH_UART_LCR_EPS        0x00000010
 100 #define PCH_UART_LCR_SP         0x00000020
 101 #define PCH_UART_LCR_SB         0x00000040
 102 #define PCH_UART_LCR_DLAB       0x00000080
 103 #define PCH_UART_LCR_NP         0x00000000
 104 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 105 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 106 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 107 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 108                                 PCH_UART_LCR_SP)
 109
 110 #define PCH_UART_LCR_5BIT       0x00000000
 111 #define PCH_UART_LCR_6BIT       0x00000001
 112 #define PCH_UART_LCR_7BIT       0x00000002
 113 #define PCH_UART_LCR_8BIT       0x00000003
 114
 115 #define PCH_UART_MCR_DTR        0x00000001
 116 #define PCH_UART_MCR_RTS        0x00000002
 117 #define PCH_UART_MCR_OUT        0x0000000C
 118 #define PCH_UART_MCR_LOOP       0x00000010
 119 #define PCH_UART_MCR_AFE        0x00000020
 120
 121 #define PCH_UART_LSR_DR         0x00000001
 122 #define PCH_UART_LSR_ERR        (1<<7)
 123
 124 #define PCH_UART_MSR_DCTS       0x00000001
 125 #define PCH_UART_MSR_DDSR       0x00000002
 126 #define PCH_UART_MSR_TERI       0x00000004
 127 #define PCH_UART_MSR_DDCD       0x00000008
 128 #define PCH_UART_MSR_CTS        0x00000010
 129 #define PCH_UART_MSR_DSR        0x00000020
 130 #define PCH_UART_MSR_RI         0x00000040
 131 #define PCH_UART_MSR_DCD        0x00000080
 132 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 133                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 134
 135 #define PCH_UART_DLL            0x00
 136 #define PCH_UART_DLM            0x01
 137
 138 #define PCH_UART_BRCSR          0x0E
 139
 140 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 141 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 142 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 143 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 144 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 145
 146 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 147 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 148 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 149 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 150 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 151 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 152 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 153 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 154 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 155 #define PCH_UART_HAL_STB1               0
 156 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 157
 158 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 159 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 160 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 161                                         PCH_UART_HAL_CLR_RX_FIFO)
 162
 163 #define PCH_UART_HAL_DMA_MODE0          0
 164 #define PCH_UART_HAL_FIFO_DIS           0
 165 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 166 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 167                                         PCH_UART_FCR_FIFO256)
 168 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 169 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 170 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 171 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 172 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 173 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 174 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 175 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 176 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 177 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 178 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 179 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 180 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 181 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 182
 183 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 184 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 185 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 186 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 187 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 188
 189 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 190 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 191 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 192 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 193 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 194
 195 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 196
 197 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 198 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 199 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 200 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 201 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 202 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 203
 204 struct pch_uart_buffer {
 205         unsigned char *buf;
 206         int size;
 207 };
 208
 209 struct eg20t_port {
 210         struct uart_port port;
 211         int port_type;
 212         void __iomem *membase;
 213         resource_size_t mapbase;
 214         unsigned int iobase;
 215         struct pci_dev *pdev;
 216         int fifo_size;
 217         unsigned int uartclk;
 218         int start_tx;
 219         int start_rx;
 220         int tx_empty;
 221         int trigger;
 222         int trigger_level;
 223         struct pch_uart_buffer rxbuf;
 224         unsigned int dmsr;
 225         unsigned int fcr;
 226         unsigned int mcr;
 227         unsigned int use_dma;
 228         struct dma_async_tx_descriptor  *desc_tx;
 229         struct dma_async_tx_descriptor  *desc_rx;
 230         struct pch_dma_slave            param_tx;
 231         struct pch_dma_slave            param_rx;
 232         struct dma_chan                 *chan_tx;
 233         struct dma_chan                 *chan_rx;
 234         struct scatterlist              *sg_tx_p;
 235         int                             nent;
 236         int                             orig_nent;
 237         struct scatterlist              sg_rx;
 238         int                             tx_dma_use;
 239         void                            *rx_buf_virt;
 240         dma_addr_t                      rx_buf_dma;
 241
 242         struct dentry   *debugfs;
 243 #define IRQ_NAME_SIZE 17
 244         char                            irq_name[IRQ_NAME_SIZE];
 245
 246         /* protect the eg20t_port private structure and io access to membase */
 247         spinlock_t lock;
 248 };
 249
 250 /**
 251  * struct pch_uart_driver_data - private data structure for UART-DMA
 252  * @port_type:                  The type of UART port
 253  * @line_no:                    UART port line number (0, 1, 2...)
 254  */
 255 struct pch_uart_driver_data {
 256         int port_type;
 257         int line_no;
 258 };
 259
 260 enum pch_uart_num_t {
 261         pch_et20t_uart0 = 0,
 262         pch_et20t_uart1,
 263         pch_et20t_uart2,
 264         pch_et20t_uart3,
 265         pch_ml7213_uart0,
 266         pch_ml7213_uart1,
 267         pch_ml7213_uart2,
 268         pch_ml7223_uart0,
 269         pch_ml7223_uart1,
 270         pch_ml7831_uart0,
 271         pch_ml7831_uart1,
 272 };
 273
 274 static struct pch_uart_driver_data drv_dat[] = {
 275         [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
 276         [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
 277         [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
 278         [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
 279         [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
 280         [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
 281         [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
 282         [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
 283         [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
 284         [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
 285         [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
 286 };
 287
 288 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 289 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 290 #endif
 291 static unsigned int default_baud = 9600;
 292 static unsigned int user_uartclk = 0;
 293 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 294 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 295 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 296 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 297
 298 #ifdef CONFIG_DEBUG_FS
 299
 300 #define PCH_REGS_BUFSIZE        1024
 301
 302
 303 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 304                                 size_t count, loff_t *ppos)
 305 {
 306         struct eg20t_port *priv = file->private_data;
 307         char *buf;
 308         u32 len = 0;
 309         ssize_t ret;
 310         unsigned char lcr;
 311
 312         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 313         if (!buf)
 314                 return 0;
 315
 316         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 317                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 318
 319         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 320                         "=================================\n");
 321         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 322                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 323         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 324                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 325         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 326                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 327         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 328                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 329         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 330                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 331         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 332                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "BRCSR: \t0x%02x\n",
 335                         ioread8(priv->membase + PCH_UART_BRCSR));
 336
 337         lcr = ioread8(priv->membase + UART_LCR);
 338         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 341         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 343         iowrite8(lcr, priv->membase + UART_LCR);
 344
 345         if (len > PCH_REGS_BUFSIZE)
 346                 len = PCH_REGS_BUFSIZE;
 347
 348         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 349         kfree(buf);
 350         return ret;
 351 }
 352
 353 static const struct file_operations port_regs_ops = {
 354         .owner          = THIS_MODULE,
 355         .open           = simple_open,
 356         .read           = port_show_regs,
 357         .llseek         = default_llseek,
 358 };
 359 #endif  /* CONFIG_DEBUG_FS */
 360
 361 static const struct dmi_system_id pch_uart_dmi_table[] = {
 362         {
 363                 .ident = "CM-iTC",
 364                 {
 365                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 366                 },
 367                 (void *)CMITC_UARTCLK,
 368         },
 369         {
 370                 .ident = "FRI2",
 371                 {
 372                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 373                 },
 374                 (void *)FRI2_64_UARTCLK,
 375         },
 376         {
 377                 .ident = "Fish River Island II",
 378                 {
 379                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 380                 },
 381                 (void *)FRI2_48_UARTCLK,
 382         },
 383         {
 384                 .ident = "COMe-mTT",
 385                 {
 386                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 387                 },
 388                 (void *)NTC1_UARTCLK,
 389         },
 390         {
 391                 .ident = "nanoETXexpress-TT",
 392                 {
 393                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 394                 },
 395                 (void *)NTC1_UARTCLK,
 396         },
 397         {
 398                 .ident = "MinnowBoard",
 399                 {
 400                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 401                 },
 402                 (void *)MINNOW_UARTCLK,
 403         },
 404         { }
 405 };
 406
 407 /* Return UART clock, checking for board specific clocks. */
 408 static unsigned int pch_uart_get_uartclk(void)
 409 {
 410         const struct dmi_system_id *d;
 411
 412         if (user_uartclk)
 413                 return user_uartclk;
 414
 415         d = dmi_first_match(pch_uart_dmi_table);
 416         if (d)
 417                 return (unsigned long)d->driver_data;
 418
 419         return DEFAULT_UARTCLK;
 420 }
 421
 422 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 423                                           unsigned int flag)
 424 {
 425         u8 ier = ioread8(priv->membase + UART_IER);
 426         ier |= flag & PCH_UART_IER_MASK;
 427         iowrite8(ier, priv->membase + UART_IER);
 428 }
 429
 430 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 431                                            unsigned int flag)
 432 {
 433         u8 ier = ioread8(priv->membase + UART_IER);
 434         ier &= ~(flag & PCH_UART_IER_MASK);
 435         iowrite8(ier, priv->membase + UART_IER);
 436 }
 437
 438 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 439                                  unsigned int parity, unsigned int bits,
 440                                  unsigned int stb)
 441 {
 442         unsigned int dll, dlm, lcr;
 443         int div;
 444
 445         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 446         if (div < 0 || USHRT_MAX <= div) {
 447                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 448                 return -EINVAL;
 449         }
 450
 451         dll = (unsigned int)div & 0x00FFU;
 452         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 453
 454         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 455                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 456                 return -EINVAL;
 457         }
 458
 459         if (bits & ~PCH_UART_LCR_WLS) {
 460                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 461                 return -EINVAL;
 462         }
 463
 464         if (stb & ~PCH_UART_LCR_STB) {
 465                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 466                 return -EINVAL;
 467         }
 468
 469         lcr = parity;
 470         lcr |= bits;
 471         lcr |= stb;
 472
 473         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 474                  __func__, baud, div, lcr, jiffies);
 475         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 476         iowrite8(dll, priv->membase + PCH_UART_DLL);
 477         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 478         iowrite8(lcr, priv->membase + UART_LCR);
 479
 480         return 0;
 481 }
 482
 483 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 484                                     unsigned int flag)
 485 {
 486         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 487                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 488                         __func__, flag);
 489                 return -EINVAL;
 490         }
 491
 492         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 493         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 494                  priv->membase + UART_FCR);
 495         iowrite8(priv->fcr, priv->membase + UART_FCR);
 496
 497         return 0;
 498 }
 499
 500 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 501                                  unsigned int dmamode,
 502                                  unsigned int fifo_size, unsigned int trigger)
 503 {
 504         u8 fcr;
 505
 506         if (dmamode & ~PCH_UART_FCR_DMS) {
 507                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 508                         __func__, dmamode);
 509                 return -EINVAL;
 510         }
 511
 512         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 513                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 514                         __func__, fifo_size);
 515                 return -EINVAL;
 516         }
 517
 518         if (trigger & ~PCH_UART_FCR_RFTL) {
 519                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 520                         __func__, trigger);
 521                 return -EINVAL;
 522         }
 523
 524         switch (priv->fifo_size) {
 525         case 256:
 526                 priv->trigger_level =
 527                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 528                 break;
 529         case 64:
 530                 priv->trigger_level =
 531                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 532                 break;
 533         case 16:
 534                 priv->trigger_level =
 535                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 536                 break;
 537         default:
 538                 priv->trigger_level =
 539                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 540                 break;
 541         }
 542         fcr =
 543             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 544         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 545         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 546                  priv->membase + UART_FCR);
 547         iowrite8(fcr, priv->membase + UART_FCR);
 548         priv->fcr = fcr;
 549
 550         return 0;
 551 }
 552
 553 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 554 {
 555         unsigned int msr = ioread8(priv->membase + UART_MSR);
 556         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 557         return (u8)msr;
 558 }
 559
 560 static void pch_uart_hal_write(struct eg20t_port *priv,
 561                               const unsigned char *buf, int tx_size)
 562 {
 563         int i;
 564         unsigned int thr;
 565
 566         for (i = 0; i < tx_size;) {
 567                 thr = buf[i++];
 568                 iowrite8(thr, priv->membase + PCH_UART_THR);
 569         }
 570 }
 571
 572 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 573                              int rx_size)
 574 {
 575         int i;
 576         u8 rbr, lsr;
 577         struct uart_port *port = &priv->port;
 578
 579         lsr = ioread8(priv->membase + UART_LSR);
 580         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 581              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 582              lsr = ioread8(priv->membase + UART_LSR)) {
 583                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 584
 585                 if (lsr & UART_LSR_BI) {
 586                         port->icount.brk++;
 587                         if (uart_handle_break(port))
 588                                 continue;
 589                 }
 590 #ifdef SUPPORT_SYSRQ
 591                 if (port->sysrq) {
 592                         if (uart_handle_sysrq_char(port, rbr))
 593                                 continue;
 594                 }
 595 #endif
 596
 597                 buf[i++] = rbr;
 598         }
 599         return i;
 600 }
 601
 602 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 603 {
 604         return ioread8(priv->membase + UART_IIR) &\
 605                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 606 }
 607
 608 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 609 {
 610         return ioread8(priv->membase + UART_LSR);
 611 }
 612
 613 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 614 {
 615         unsigned int lcr;
 616
 617         lcr = ioread8(priv->membase + UART_LCR);
 618         if (on)
 619                 lcr |= PCH_UART_LCR_SB;
 620         else
 621                 lcr &= ~PCH_UART_LCR_SB;
 622
 623         iowrite8(lcr, priv->membase + UART_LCR);
 624 }
 625
 626 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 627                    int size)
 628 {
 629         struct uart_port *port = &priv->port;
 630         struct tty_port *tport = &port->state->port;
 631
 632         tty_insert_flip_string(tport, buf, size);
 633         tty_flip_buffer_push(tport);
 634
 635         return 0;
 636 }
 637
 638 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 639 {
 640         int ret = 0;
 641         struct uart_port *port = &priv->port;
 642
 643         if (port->x_char) {
 644                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 645                         __func__, port->x_char, jiffies);
 646                 buf[0] = port->x_char;
 647                 port->x_char = 0;
 648                 ret = 1;
 649         }
 650
 651         return ret;
 652 }
 653
 654 static int dma_push_rx(struct eg20t_port *priv, int size)
 655 {
 656         int room;
 657         struct uart_port *port = &priv->port;
 658         struct tty_port *tport = &port->state->port;
 659
 660         room = tty_buffer_request_room(tport, size);
 661
 662         if (room < size)
 663                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 664                          size - room);
 665         if (!room)
 666                 return 0;
 667
 668         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 669
 670         port->icount.rx += room;
 671
 672         return room;
 673 }
 674
 675 static void pch_free_dma(struct uart_port *port)
 676 {
 677         struct eg20t_port *priv;
 678         priv = container_of(port, struct eg20t_port, port);
 679
 680         if (priv->chan_tx) {
 681                 dma_release_channel(priv->chan_tx);
 682                 priv->chan_tx = NULL;
 683         }
 684         if (priv->chan_rx) {
 685                 dma_release_channel(priv->chan_rx);
 686                 priv->chan_rx = NULL;
 687         }
 688
 689         if (priv->rx_buf_dma) {
 690                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 691                                   priv->rx_buf_dma);
 692                 priv->rx_buf_virt = NULL;
 693                 priv->rx_buf_dma = 0;
 694         }
 695
 696         return;
 697 }
 698
 699 static bool filter(struct dma_chan *chan, void *slave)
 700 {
 701         struct pch_dma_slave *param = slave;
 702
 703         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 704                                                   chan->device->dev)) {
 705                 chan->private = param;
 706                 return true;
 707         } else {
 708                 return false;
 709         }
 710 }
 711
 712 static void pch_request_dma(struct uart_port *port)
 713 {
 714         dma_cap_mask_t mask;
 715         struct dma_chan *chan;
 716         struct pci_dev *dma_dev;
 717         struct pch_dma_slave *param;
 718         struct eg20t_port *priv =
 719                                 container_of(port, struct eg20t_port, port);
 720         dma_cap_zero(mask);
 721         dma_cap_set(DMA_SLAVE, mask);
 722
 723         /* Get DMA's dev information */
 724         dma_dev = pci_get_slot(priv->pdev->bus,
 725                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 726
 727         /* Set Tx DMA */
 728         param = &priv->param_tx;
 729         param->dma_dev = &dma_dev->dev;
 730         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 731
 732         param->tx_reg = port->mapbase + UART_TX;
 733         chan = dma_request_channel(mask, filter, param);
 734         if (!chan) {
 735                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 736                         __func__);
 737                 return;
 738         }
 739         priv->chan_tx = chan;
 740
 741         /* Set Rx DMA */
 742         param = &priv->param_rx;
 743         param->dma_dev = &dma_dev->dev;
 744         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 745
 746         param->rx_reg = port->mapbase + UART_RX;
 747         chan = dma_request_channel(mask, filter, param);
 748         if (!chan) {
 749                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 750                         __func__);
 751                 dma_release_channel(priv->chan_tx);
 752                 priv->chan_tx = NULL;
 753                 return;
 754         }
 755
 756         /* Get Consistent memory for DMA */
 757         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 758                                     &priv->rx_buf_dma, GFP_KERNEL);
 759         priv->chan_rx = chan;
 760 }
 761
 762 static void pch_dma_rx_complete(void *arg)
 763 {
 764         struct eg20t_port *priv = arg;
 765         struct uart_port *port = &priv->port;
 766         int count;
 767
 768         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 769         count = dma_push_rx(priv, priv->trigger_level);
 770         if (count)
 771                 tty_flip_buffer_push(&port->state->port);
 772         async_tx_ack(priv->desc_rx);
 773         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 774                                             PCH_UART_HAL_RX_ERR_INT);
 775 }
 776
 777 static void pch_dma_tx_complete(void *arg)
 778 {
 779         struct eg20t_port *priv = arg;
 780         struct uart_port *port = &priv->port;
 781         struct circ_buf *xmit = &port->state->xmit;
 782         struct scatterlist *sg = priv->sg_tx_p;
 783         int i;
 784
 785         for (i = 0; i < priv->nent; i++, sg++) {
 786                 xmit->tail += sg_dma_len(sg);
 787                 port->icount.tx += sg_dma_len(sg);
 788         }
 789         xmit->tail &= UART_XMIT_SIZE - 1;
 790         async_tx_ack(priv->desc_tx);
 791         dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
 792         priv->tx_dma_use = 0;
 793         priv->nent = 0;
 794         priv->orig_nent = 0;
 795         kfree(priv->sg_tx_p);
 796         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 797 }
 798
 799 static int pop_tx(struct eg20t_port *priv, int size)
 800 {
 801         int count = 0;
 802         struct uart_port *port = &priv->port;
 803         struct circ_buf *xmit = &port->state->xmit;
 804
 805         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 806                 goto pop_tx_end;
 807
 808         do {
 809                 int cnt_to_end =
 810                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 811                 int sz = min(size - count, cnt_to_end);
 812                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 813                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 814                 count += sz;
 815         } while (!uart_circ_empty(xmit) && count < size);
 816
 817 pop_tx_end:
 818         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 819                  count, size - count, jiffies);
 820
 821         return count;
 822 }
 823
 824 static int handle_rx_to(struct eg20t_port *priv)
 825 {
 826         struct pch_uart_buffer *buf;
 827         int rx_size;
 828         int ret;
 829         if (!priv->start_rx) {
 830                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 831                                                      PCH_UART_HAL_RX_ERR_INT);
 832                 return 0;
 833         }
 834         buf = &priv->rxbuf;
 835         do {
 836                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 837                 ret = push_rx(priv, buf->buf, rx_size);
 838                 if (ret)
 839                         return 0;
 840         } while (rx_size == buf->size);
 841
 842         return PCH_UART_HANDLED_RX_INT;
 843 }
 844
 845 static int handle_rx(struct eg20t_port *priv)
 846 {
 847         return handle_rx_to(priv);
 848 }
 849
 850 static int dma_handle_rx(struct eg20t_port *priv)
 851 {
 852         struct uart_port *port = &priv->port;
 853         struct dma_async_tx_descriptor *desc;
 854         struct scatterlist *sg;
 855
 856         priv = container_of(port, struct eg20t_port, port);
 857         sg = &priv->sg_rx;
 858
 859         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 860
 861         sg_dma_len(sg) = priv->trigger_level;
 862
 863         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 864                      sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
 865
 866         sg_dma_address(sg) = priv->rx_buf_dma;
 867
 868         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 869                         sg, 1, DMA_DEV_TO_MEM,
 870                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 871
 872         if (!desc)
 873                 return 0;
 874
 875         priv->desc_rx = desc;
 876         desc->callback = pch_dma_rx_complete;
 877         desc->callback_param = priv;
 878         desc->tx_submit(desc);
 879         dma_async_issue_pending(priv->chan_rx);
 880
 881         return PCH_UART_HANDLED_RX_INT;
 882 }
 883
 884 static unsigned int handle_tx(struct eg20t_port *priv)
 885 {
 886         struct uart_port *port = &priv->port;
 887         struct circ_buf *xmit = &port->state->xmit;
 888         int fifo_size;
 889         int tx_size;
 890         int size;
 891         int tx_empty;
 892
 893         if (!priv->start_tx) {
 894                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 895                         __func__, jiffies);
 896                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 897                 priv->tx_empty = 1;
 898                 return 0;
 899         }
 900
 901         fifo_size = max(priv->fifo_size, 1);
 902         tx_empty = 1;
 903         if (pop_tx_x(priv, xmit->buf)) {
 904                 pch_uart_hal_write(priv, xmit->buf, 1);
 905                 port->icount.tx++;
 906                 tx_empty = 0;
 907                 fifo_size--;
 908         }
 909         size = min(xmit->head - xmit->tail, fifo_size);
 910         if (size < 0)
 911                 size = fifo_size;
 912
 913         tx_size = pop_tx(priv, size);
 914         if (tx_size > 0) {
 915                 port->icount.tx += tx_size;
 916                 tx_empty = 0;
 917         }
 918
 919         priv->tx_empty = tx_empty;
 920
 921         if (tx_empty) {
 922                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 923                 uart_write_wakeup(port);
 924         }
 925
 926         return PCH_UART_HANDLED_TX_INT;
 927 }
 928
 929 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 930 {
 931         struct uart_port *port = &priv->port;
 932         struct circ_buf *xmit = &port->state->xmit;
 933         struct scatterlist *sg;
 934         int nent;
 935         int fifo_size;
 936         struct dma_async_tx_descriptor *desc;
 937         int num;
 938         int i;
 939         int bytes;
 940         int size;
 941         int rem;
 942
 943         if (!priv->start_tx) {
 944                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 945                         __func__, jiffies);
 946                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 947                 priv->tx_empty = 1;
 948                 return 0;
 949         }
 950
 951         if (priv->tx_dma_use) {
 952                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 953                         __func__, jiffies);
 954                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 955                 priv->tx_empty = 1;
 956                 return 0;
 957         }
 958
 959         fifo_size = max(priv->fifo_size, 1);
 960         if (pop_tx_x(priv, xmit->buf)) {
 961                 pch_uart_hal_write(priv, xmit->buf, 1);
 962                 port->icount.tx++;
 963                 fifo_size--;
 964         }
 965
 966         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 967                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 968                              xmit->tail, UART_XMIT_SIZE));
 969         if (!bytes) {
 970                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 971                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 972                 uart_write_wakeup(port);
 973                 return 0;
 974         }
 975
 976         if (bytes > fifo_size) {
 977                 num = bytes / fifo_size + 1;
 978                 size = fifo_size;
 979                 rem = bytes % fifo_size;
 980         } else {
 981                 num = 1;
 982                 size = bytes;
 983                 rem = bytes;
 984         }
 985
 986         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 987                 __func__, num, size, rem);
 988
 989         priv->tx_dma_use = 1;
 990
 991         priv->sg_tx_p = kcalloc(num, sizeof(struct scatterlist), GFP_ATOMIC);
 992         if (!priv->sg_tx_p) {
 993                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 994                 return 0;
 995         }
 996
 997         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 998         sg = priv->sg_tx_p;
 999
1000         for (i = 0; i < num; i++, sg++) {
1001                 if (i == (num - 1))
1002                         sg_set_page(sg, virt_to_page(xmit->buf),
1003                                     rem, fifo_size * i);
1004                 else
1005                         sg_set_page(sg, virt_to_page(xmit->buf),
1006                                     size, fifo_size * i);
1007         }
1008
1009         sg = priv->sg_tx_p;
1010         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1011         if (!nent) {
1012                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1013                 return 0;
1014         }
1015         priv->orig_nent = num;
1016         priv->nent = nent;
1017
1018         for (i = 0; i < nent; i++, sg++) {
1019                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1020                               fifo_size * i;
1021                 sg_dma_address(sg) = (sg_dma_address(sg) &
1022                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1023                 if (i == (nent - 1))
1024                         sg_dma_len(sg) = rem;
1025                 else
1026                         sg_dma_len(sg) = size;
1027         }
1028
1029         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1030                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1031                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1032         if (!desc) {
1033                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1034                         __func__);
1035                 return 0;
1036         }
1037         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1038         priv->desc_tx = desc;
1039         desc->callback = pch_dma_tx_complete;
1040         desc->callback_param = priv;
1041
1042         desc->tx_submit(desc);
1043
1044         dma_async_issue_pending(priv->chan_tx);
1045
1046         return PCH_UART_HANDLED_TX_INT;
1047 }
1048
1049 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1050 {
1051         struct uart_port *port = &priv->port;
1052         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1053         char   *error_msg[5] = {};
1054         int    i = 0;
1055
1056         if (lsr & PCH_UART_LSR_ERR)
1057                 error_msg[i++] = "Error data in FIFO\n";
1058
1059         if (lsr & UART_LSR_FE) {
1060                 port->icount.frame++;
1061                 error_msg[i++] = "  Framing Error\n";
1062         }
1063
1064         if (lsr & UART_LSR_PE) {
1065                 port->icount.parity++;
1066                 error_msg[i++] = "  Parity Error\n";
1067         }
1068
1069         if (lsr & UART_LSR_OE) {
1070                 port->icount.overrun++;
1071                 error_msg[i++] = "  Overrun Error\n";
1072         }
1073
1074         if (tty == NULL) {
1075                 for (i = 0; error_msg[i] != NULL; i++)
1076                         dev_err(&priv->pdev->dev, error_msg[i]);
1077         } else {
1078                 tty_kref_put(tty);
1079         }
1080 }
1081
1082 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1083 {
1084         struct eg20t_port *priv = dev_id;
1085         unsigned int handled;
1086         u8 lsr;
1087         int ret = 0;
1088         unsigned char iid;
1089         unsigned long flags;
1090         int next = 1;
1091         u8 msr;
1092
1093         spin_lock_irqsave(&priv->lock, flags);
1094         handled = 0;
1095         while (next) {
1096                 iid = pch_uart_hal_get_iid(priv);
1097                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1098                         break;
1099                 switch (iid) {
1100                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1101                         lsr = pch_uart_hal_get_line_status(priv);
1102                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1103                                                 UART_LSR_PE | UART_LSR_OE)) {
1104                                 pch_uart_err_ir(priv, lsr);
1105                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1106                         } else {
1107                                 ret = PCH_UART_HANDLED_LS_INT;
1108                         }
1109                         break;
1110                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1111                         if (priv->use_dma) {
1112                                 pch_uart_hal_disable_interrupt(priv,
1113                                                 PCH_UART_HAL_RX_INT |
1114                                                 PCH_UART_HAL_RX_ERR_INT);
1115                                 ret = dma_handle_rx(priv);
1116                                 if (!ret)
1117                                         pch_uart_hal_enable_interrupt(priv,
1118                                                 PCH_UART_HAL_RX_INT |
1119                                                 PCH_UART_HAL_RX_ERR_INT);
1120                         } else {
1121                                 ret = handle_rx(priv);
1122                         }
1123                         break;
1124                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1125                                                    (FIFO Timeout) */
1126                         ret = handle_rx_to(priv);
1127                         break;
1128                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1129                                                    Empty */
1130                         if (priv->use_dma)
1131                                 ret = dma_handle_tx(priv);
1132                         else
1133                                 ret = handle_tx(priv);
1134                         break;
1135                 case PCH_UART_IID_MS:   /* Modem Status */
1136                         msr = pch_uart_hal_get_modem(priv);
1137                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1138                                      means final interrupt */
1139                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1140                                 break;
1141                         ret |= PCH_UART_HANDLED_MS_INT;
1142                         break;
1143                 default:        /* Never junp to this label */
1144                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1145                                 iid, jiffies);
1146                         ret = -1;
1147                         next = 0;
1148                         break;
1149                 }
1150                 handled |= (unsigned int)ret;
1151         }
1152
1153         spin_unlock_irqrestore(&priv->lock, flags);
1154         return IRQ_RETVAL(handled);
1155 }
1156
1157 /* This function tests whether the transmitter fifo and shifter for the port
1158                                                 described by 'port' is empty. */
1159 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1160 {
1161         struct eg20t_port *priv;
1162
1163         priv = container_of(port, struct eg20t_port, port);
1164         if (priv->tx_empty)
1165                 return TIOCSER_TEMT;
1166         else
1167                 return 0;
1168 }
1169
1170 /* Returns the current state of modem control inputs. */
1171 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1172 {
1173         struct eg20t_port *priv;
1174         u8 modem;
1175         unsigned int ret = 0;
1176
1177         priv = container_of(port, struct eg20t_port, port);
1178         modem = pch_uart_hal_get_modem(priv);
1179
1180         if (modem & UART_MSR_DCD)
1181                 ret |= TIOCM_CAR;
1182
1183         if (modem & UART_MSR_RI)
1184                 ret |= TIOCM_RNG;
1185
1186         if (modem & UART_MSR_DSR)
1187                 ret |= TIOCM_DSR;
1188
1189         if (modem & UART_MSR_CTS)
1190                 ret |= TIOCM_CTS;
1191
1192         return ret;
1193 }
1194
1195 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1196 {
1197         u32 mcr = 0;
1198         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1199
1200         if (mctrl & TIOCM_DTR)
1201                 mcr |= UART_MCR_DTR;
1202         if (mctrl & TIOCM_RTS)
1203                 mcr |= UART_MCR_RTS;
1204         if (mctrl & TIOCM_LOOP)
1205                 mcr |= UART_MCR_LOOP;
1206
1207         if (priv->mcr & UART_MCR_AFE)
1208                 mcr |= UART_MCR_AFE;
1209
1210         if (mctrl)
1211                 iowrite8(mcr, priv->membase + UART_MCR);
1212 }
1213
1214 static void pch_uart_stop_tx(struct uart_port *port)
1215 {
1216         struct eg20t_port *priv;
1217         priv = container_of(port, struct eg20t_port, port);
1218         priv->start_tx = 0;
1219         priv->tx_dma_use = 0;
1220 }
1221
1222 static void pch_uart_start_tx(struct uart_port *port)
1223 {
1224         struct eg20t_port *priv;
1225
1226         priv = container_of(port, struct eg20t_port, port);
1227
1228         if (priv->use_dma) {
1229                 if (priv->tx_dma_use) {
1230                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1231                                 __func__);
1232                         return;
1233                 }
1234         }
1235
1236         priv->start_tx = 1;
1237         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1238 }
1239
1240 static void pch_uart_stop_rx(struct uart_port *port)
1241 {
1242         struct eg20t_port *priv;
1243         priv = container_of(port, struct eg20t_port, port);
1244         priv->start_rx = 0;
1245         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1246                                              PCH_UART_HAL_RX_ERR_INT);
1247 }
1248
1249 /* Enable the modem status interrupts. */
1250 static void pch_uart_enable_ms(struct uart_port *port)
1251 {
1252         struct eg20t_port *priv;
1253         priv = container_of(port, struct eg20t_port, port);
1254         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1255 }
1256
1257 /* Control the transmission of a break signal. */
1258 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1259 {
1260         struct eg20t_port *priv;
1261         unsigned long flags;
1262
1263         priv = container_of(port, struct eg20t_port, port);
1264         spin_lock_irqsave(&priv->lock, flags);
1265         pch_uart_hal_set_break(priv, ctl);
1266         spin_unlock_irqrestore(&priv->lock, flags);
1267 }
1268
1269 /* Grab any interrupt resources and initialise any low level driver state. */
1270 static int pch_uart_startup(struct uart_port *port)
1271 {
1272         struct eg20t_port *priv;
1273         int ret;
1274         int fifo_size;
1275         int trigger_level;
1276
1277         priv = container_of(port, struct eg20t_port, port);
1278         priv->tx_empty = 1;
1279
1280         if (port->uartclk)
1281                 priv->uartclk = port->uartclk;
1282         else
1283                 port->uartclk = priv->uartclk;
1284
1285         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1286         ret = pch_uart_hal_set_line(priv, default_baud,
1287                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1288                               PCH_UART_HAL_STB1);
1289         if (ret)
1290                 return ret;
1291
1292         switch (priv->fifo_size) {
1293         case 256:
1294                 fifo_size = PCH_UART_HAL_FIFO256;
1295                 break;
1296         case 64:
1297                 fifo_size = PCH_UART_HAL_FIFO64;
1298                 break;
1299         case 16:
1300                 fifo_size = PCH_UART_HAL_FIFO16;
1301                 break;
1302         case 1:
1303         default:
1304                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1305                 break;
1306         }
1307
1308         switch (priv->trigger) {
1309         case PCH_UART_HAL_TRIGGER1:
1310                 trigger_level = 1;
1311                 break;
1312         case PCH_UART_HAL_TRIGGER_L:
1313                 trigger_level = priv->fifo_size / 4;
1314                 break;
1315         case PCH_UART_HAL_TRIGGER_M:
1316                 trigger_level = priv->fifo_size / 2;
1317                 break;
1318         case PCH_UART_HAL_TRIGGER_H:
1319         default:
1320                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1321                 break;
1322         }
1323
1324         priv->trigger_level = trigger_level;
1325         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1326                                     fifo_size, priv->trigger);
1327         if (ret < 0)
1328                 return ret;
1329
1330         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1331                         priv->irq_name, priv);
1332         if (ret < 0)
1333                 return ret;
1334
1335         if (priv->use_dma)
1336                 pch_request_dma(port);
1337
1338         priv->start_rx = 1;
1339         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1340                                             PCH_UART_HAL_RX_ERR_INT);
1341         uart_update_timeout(port, CS8, default_baud);
1342
1343         return 0;
1344 }
1345
1346 static void pch_uart_shutdown(struct uart_port *port)
1347 {
1348         struct eg20t_port *priv;
1349         int ret;
1350
1351         priv = container_of(port, struct eg20t_port, port);
1352         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1353         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1354         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1355                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1356         if (ret)
1357                 dev_err(priv->port.dev,
1358                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1359
1360         pch_free_dma(port);
1361
1362         free_irq(priv->port.irq, priv);
1363 }
1364
1365 /* Change the port parameters, including word length, parity, stop
1366  *bits.  Update read_status_mask and ignore_status_mask to indicate
1367  *the types of events we are interested in receiving.  */
1368 static void pch_uart_set_termios(struct uart_port *port,
1369                                  struct ktermios *termios, struct ktermios *old)
1370 {
1371         int rtn;
1372         unsigned int baud, parity, bits, stb;
1373         struct eg20t_port *priv;
1374         unsigned long flags;
1375
1376         priv = container_of(port, struct eg20t_port, port);
1377         switch (termios->c_cflag & CSIZE) {
1378         case CS5:
1379                 bits = PCH_UART_HAL_5BIT;
1380                 break;
1381         case CS6:
1382                 bits = PCH_UART_HAL_6BIT;
1383                 break;
1384         case CS7:
1385                 bits = PCH_UART_HAL_7BIT;
1386                 break;
1387         default:                /* CS8 */
1388                 bits = PCH_UART_HAL_8BIT;
1389                 break;
1390         }
1391         if (termios->c_cflag & CSTOPB)
1392                 stb = PCH_UART_HAL_STB2;
1393         else
1394                 stb = PCH_UART_HAL_STB1;
1395
1396         if (termios->c_cflag & PARENB) {
1397                 if (termios->c_cflag & PARODD)
1398                         parity = PCH_UART_HAL_PARITY_ODD;
1399                 else
1400                         parity = PCH_UART_HAL_PARITY_EVEN;
1401
1402         } else
1403                 parity = PCH_UART_HAL_PARITY_NONE;
1404
1405         /* Only UART0 has auto hardware flow function */
1406         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1407                 priv->mcr |= UART_MCR_AFE;
1408         else
1409                 priv->mcr &= ~UART_MCR_AFE;
1410
1411         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1412
1413         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1414
1415         spin_lock_irqsave(&priv->lock, flags);
1416         spin_lock(&port->lock);
1417
1418         uart_update_timeout(port, termios->c_cflag, baud);
1419         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1420         if (rtn)
1421                 goto out;
1422
1423         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1424         /* Don't rewrite B0 */
1425         if (tty_termios_baud_rate(termios))
1426                 tty_termios_encode_baud_rate(termios, baud, baud);
1427
1428 out:
1429         spin_unlock(&port->lock);
1430         spin_unlock_irqrestore(&priv->lock, flags);
1431 }
1432
1433 static const char *pch_uart_type(struct uart_port *port)
1434 {
1435         return KBUILD_MODNAME;
1436 }
1437
1438 static void pch_uart_release_port(struct uart_port *port)
1439 {
1440         struct eg20t_port *priv;
1441
1442         priv = container_of(port, struct eg20t_port, port);
1443         pci_iounmap(priv->pdev, priv->membase);
1444         pci_release_regions(priv->pdev);
1445 }
1446
1447 static int pch_uart_request_port(struct uart_port *port)
1448 {
1449         struct eg20t_port *priv;
1450         int ret;
1451         void __iomem *membase;
1452
1453         priv = container_of(port, struct eg20t_port, port);
1454         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1455         if (ret < 0)
1456                 return -EBUSY;
1457
1458         membase = pci_iomap(priv->pdev, 1, 0);
1459         if (!membase) {
1460                 pci_release_regions(priv->pdev);
1461                 return -EBUSY;
1462         }
1463         priv->membase = port->membase = membase;
1464
1465         return 0;
1466 }
1467
1468 static void pch_uart_config_port(struct uart_port *port, int type)
1469 {
1470         struct eg20t_port *priv;
1471
1472         priv = container_of(port, struct eg20t_port, port);
1473         if (type & UART_CONFIG_TYPE) {
1474                 port->type = priv->port_type;
1475                 pch_uart_request_port(port);
1476         }
1477 }
1478
1479 static int pch_uart_verify_port(struct uart_port *port,
1480                                 struct serial_struct *serinfo)
1481 {
1482         struct eg20t_port *priv;
1483
1484         priv = container_of(port, struct eg20t_port, port);
1485         if (serinfo->flags & UPF_LOW_LATENCY) {
1486                 dev_info(priv->port.dev,
1487                         "PCH UART : Use PIO Mode (without DMA)\n");
1488                 priv->use_dma = 0;
1489                 serinfo->flags &= ~UPF_LOW_LATENCY;
1490         } else {
1491 #ifndef CONFIG_PCH_DMA
1492                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1493                         __func__);
1494                 return -EOPNOTSUPP;
1495 #endif
1496                 if (!priv->use_dma) {
1497                         pch_request_dma(port);
1498                         if (priv->chan_rx)
1499                                 priv->use_dma = 1;
1500                 }
1501                 dev_info(priv->port.dev, "PCH UART: %s\n",
1502                                 priv->use_dma ?
1503                                 "Use DMA Mode" : "No DMA");
1504         }
1505
1506         return 0;
1507 }
1508
1509 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1510 /*
1511  *      Wait for transmitter & holding register to empty
1512  */
1513 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1514 {
1515         unsigned int status, tmout = 10000;
1516
1517         /* Wait up to 10ms for the character(s) to be sent. */
1518         for (;;) {
1519                 status = ioread8(up->membase + UART_LSR);
1520
1521                 if ((status & bits) == bits)
1522                         break;
1523                 if (--tmout == 0)
1524                         break;
1525                 udelay(1);
1526         }
1527
1528         /* Wait up to 1s for flow control if necessary */
1529         if (up->port.flags & UPF_CONS_FLOW) {
1530                 unsigned int tmout;
1531                 for (tmout = 1000000; tmout; tmout--) {
1532                         unsigned int msr = ioread8(up->membase + UART_MSR);
1533                         if (msr & UART_MSR_CTS)
1534                                 break;
1535                         udelay(1);
1536                         touch_nmi_watchdog();
1537                 }
1538         }
1539 }
1540 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1541
1542 #ifdef CONFIG_CONSOLE_POLL
1543 /*
1544  * Console polling routines for communicate via uart while
1545  * in an interrupt or debug context.
1546  */
1547 static int pch_uart_get_poll_char(struct uart_port *port)
1548 {
1549         struct eg20t_port *priv =
1550                 container_of(port, struct eg20t_port, port);
1551         u8 lsr = ioread8(priv->membase + UART_LSR);
1552
1553         if (!(lsr & UART_LSR_DR))
1554                 return NO_POLL_CHAR;
1555
1556         return ioread8(priv->membase + PCH_UART_RBR);
1557 }
1558
1559
1560 static void pch_uart_put_poll_char(struct uart_port *port,
1561                          unsigned char c)
1562 {
1563         unsigned int ier;
1564         struct eg20t_port *priv =
1565                 container_of(port, struct eg20t_port, port);
1566
1567         /*
1568          * First save the IER then disable the interrupts
1569          */
1570         ier = ioread8(priv->membase + UART_IER);
1571         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1572
1573         wait_for_xmitr(priv, UART_LSR_THRE);
1574         /*
1575          * Send the character out.
1576          */
1577         iowrite8(c, priv->membase + PCH_UART_THR);
1578
1579         /*
1580          * Finally, wait for transmitter to become empty
1581          * and restore the IER
1582          */
1583         wait_for_xmitr(priv, BOTH_EMPTY);
1584         iowrite8(ier, priv->membase + UART_IER);
1585 }
1586 #endif /* CONFIG_CONSOLE_POLL */
1587
1588 static const struct uart_ops pch_uart_ops = {
1589         .tx_empty = pch_uart_tx_empty,
1590         .set_mctrl = pch_uart_set_mctrl,
1591         .get_mctrl = pch_uart_get_mctrl,
1592         .stop_tx = pch_uart_stop_tx,
1593         .start_tx = pch_uart_start_tx,
1594         .stop_rx = pch_uart_stop_rx,
1595         .enable_ms = pch_uart_enable_ms,
1596         .break_ctl = pch_uart_break_ctl,
1597         .startup = pch_uart_startup,
1598         .shutdown = pch_uart_shutdown,
1599         .set_termios = pch_uart_set_termios,
1600 /*      .pm             = pch_uart_pm,          Not supported yet */
1601         .type = pch_uart_type,
1602         .release_port = pch_uart_release_port,
1603         .request_port = pch_uart_request_port,
1604         .config_port = pch_uart_config_port,
1605         .verify_port = pch_uart_verify_port,
1606 #ifdef CONFIG_CONSOLE_POLL
1607         .poll_get_char = pch_uart_get_poll_char,
1608         .poll_put_char = pch_uart_put_poll_char,
1609 #endif
1610 };
1611
1612 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1613
1614 static void pch_console_putchar(struct uart_port *port, int ch)
1615 {
1616         struct eg20t_port *priv =
1617                 container_of(port, struct eg20t_port, port);
1618
1619         wait_for_xmitr(priv, UART_LSR_THRE);
1620         iowrite8(ch, priv->membase + PCH_UART_THR);
1621 }
1622
1623 /*
1624  *      Print a string to the serial port trying not to disturb
1625  *      any possible real use of the port...
1626  *
1627  *      The console_lock must be held when we get here.
1628  */
1629 static void
1630 pch_console_write(struct console *co, const char *s, unsigned int count)
1631 {
1632         struct eg20t_port *priv;
1633         unsigned long flags;
1634         int priv_locked = 1;
1635         int port_locked = 1;
1636         u8 ier;
1637
1638         priv = pch_uart_ports[co->index];
1639
1640         touch_nmi_watchdog();
1641
1642         local_irq_save(flags);
1643         if (priv->port.sysrq) {
1644                 /* call to uart_handle_sysrq_char already took the priv lock */
1645                 priv_locked = 0;
1646                 /* serial8250_handle_port() already took the port lock */
1647                 port_locked = 0;
1648         } else if (oops_in_progress) {
1649                 priv_locked = spin_trylock(&priv->lock);
1650                 port_locked = spin_trylock(&priv->port.lock);
1651         } else {
1652                 spin_lock(&priv->lock);
1653                 spin_lock(&priv->port.lock);
1654         }
1655
1656         /*
1657          *      First save the IER then disable the interrupts
1658          */
1659         ier = ioread8(priv->membase + UART_IER);
1660
1661         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1662
1663         uart_console_write(&priv->port, s, count, pch_console_putchar);
1664
1665         /*
1666          *      Finally, wait for transmitter to become empty
1667          *      and restore the IER
1668          */
1669         wait_for_xmitr(priv, BOTH_EMPTY);
1670         iowrite8(ier, priv->membase + UART_IER);
1671
1672         if (port_locked)
1673                 spin_unlock(&priv->port.lock);
1674         if (priv_locked)
1675                 spin_unlock(&priv->lock);
1676         local_irq_restore(flags);
1677 }
1678
1679 static int __init pch_console_setup(struct console *co, char *options)
1680 {
1681         struct uart_port *port;
1682         int baud = default_baud;
1683         int bits = 8;
1684         int parity = 'n';
1685         int flow = 'n';
1686
1687         /*
1688          * Check whether an invalid uart number has been specified, and
1689          * if so, search for the first available port that does have
1690          * console support.
1691          */
1692         if (co->index >= PCH_UART_NR)
1693                 co->index = 0;
1694         port = &pch_uart_ports[co->index]->port;
1695
1696         if (!port || (!port->iobase && !port->membase))
1697                 return -ENODEV;
1698
1699         port->uartclk = pch_uart_get_uartclk();
1700
1701         if (options)
1702                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1703
1704         return uart_set_options(port, co, baud, parity, bits, flow);
1705 }
1706
1707 static struct uart_driver pch_uart_driver;
1708
1709 static struct console pch_console = {
1710         .name           = PCH_UART_DRIVER_DEVICE,
1711         .write          = pch_console_write,
1712         .device         = uart_console_device,
1713         .setup          = pch_console_setup,
1714         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1715         .index          = -1,
1716         .data           = &pch_uart_driver,
1717 };
1718
1719 #define PCH_CONSOLE     (&pch_console)
1720 #else
1721 #define PCH_CONSOLE     NULL
1722 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1723
1724 static struct uart_driver pch_uart_driver = {
1725         .owner = THIS_MODULE,
1726         .driver_name = KBUILD_MODNAME,
1727         .dev_name = PCH_UART_DRIVER_DEVICE,
1728         .major = 0,
1729         .minor = 0,
1730         .nr = PCH_UART_NR,
1731         .cons = PCH_CONSOLE,
1732 };
1733
1734 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1735                                              const struct pci_device_id *id)
1736 {
1737         struct eg20t_port *priv;
1738         int ret;
1739         unsigned int iobase;
1740         unsigned int mapbase;
1741         unsigned char *rxbuf;
1742         int fifosize;
1743         int port_type;
1744         struct pch_uart_driver_data *board;
1745 #ifdef CONFIG_DEBUG_FS
1746         char name[32];  /* for debugfs file name */
1747 #endif
1748
1749         board = &drv_dat[id->driver_data];
1750         port_type = board->port_type;
1751
1752         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1753         if (priv == NULL)
1754                 goto init_port_alloc_err;
1755
1756         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1757         if (!rxbuf)
1758                 goto init_port_free_txbuf;
1759
1760         switch (port_type) {
1761         case PORT_PCH_8LINE:
1762                 fifosize = 256; /* EG20T/ML7213: UART0 */
1763                 break;
1764         case PORT_PCH_2LINE:
1765                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1766                 break;
1767         default:
1768                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1769                 goto init_port_hal_free;
1770         }
1771
1772         pci_enable_msi(pdev);
1773         pci_set_master(pdev);
1774
1775         spin_lock_init(&priv->lock);
1776
1777         iobase = pci_resource_start(pdev, 0);
1778         mapbase = pci_resource_start(pdev, 1);
1779         priv->mapbase = mapbase;
1780         priv->iobase = iobase;
1781         priv->pdev = pdev;
1782         priv->tx_empty = 1;
1783         priv->rxbuf.buf = rxbuf;
1784         priv->rxbuf.size = PAGE_SIZE;
1785
1786         priv->fifo_size = fifosize;
1787         priv->uartclk = pch_uart_get_uartclk();
1788         priv->port_type = port_type;
1789         priv->port.dev = &pdev->dev;
1790         priv->port.iobase = iobase;
1791         priv->port.membase = NULL;
1792         priv->port.mapbase = mapbase;
1793         priv->port.irq = pdev->irq;
1794         priv->port.iotype = UPIO_PORT;
1795         priv->port.ops = &pch_uart_ops;
1796         priv->port.flags = UPF_BOOT_AUTOCONF;
1797         priv->port.fifosize = fifosize;
1798         priv->port.line = board->line_no;
1799         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1800
1801         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1802                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1803                  priv->port.line);
1804
1805         spin_lock_init(&priv->port.lock);
1806
1807         pci_set_drvdata(pdev, priv);
1808         priv->trigger_level = 1;
1809         priv->fcr = 0;
1810
1811         if (pdev->dev.of_node)
1812                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1813                                          , &user_uartclk);
1814
1815 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1816         pch_uart_ports[board->line_no] = priv;
1817 #endif
1818         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1819         if (ret < 0)
1820                 goto init_port_hal_free;
1821
1822 #ifdef CONFIG_DEBUG_FS
1823         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1824         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1825                                 NULL, priv, &port_regs_ops);
1826 #endif
1827
1828         return priv;
1829
1830 init_port_hal_free:
1831 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1832         pch_uart_ports[board->line_no] = NULL;
1833 #endif
1834         free_page((unsigned long)rxbuf);
1835 init_port_free_txbuf:
1836         kfree(priv);
1837 init_port_alloc_err:
1838
1839         return NULL;
1840 }
1841
1842 static void pch_uart_exit_port(struct eg20t_port *priv)
1843 {
1844
1845 #ifdef CONFIG_DEBUG_FS
1846         debugfs_remove(priv->debugfs);
1847 #endif
1848         uart_remove_one_port(&pch_uart_driver, &priv->port);
1849         free_page((unsigned long)priv->rxbuf.buf);
1850 }
1851
1852 static void pch_uart_pci_remove(struct pci_dev *pdev)
1853 {
1854         struct eg20t_port *priv = pci_get_drvdata(pdev);
1855
1856         pci_disable_msi(pdev);
1857
1858 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1859         pch_uart_ports[priv->port.line] = NULL;
1860 #endif
1861         pch_uart_exit_port(priv);
1862         pci_disable_device(pdev);
1863         kfree(priv);
1864         return;
1865 }
1866 #ifdef CONFIG_PM
1867 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1868 {
1869         struct eg20t_port *priv = pci_get_drvdata(pdev);
1870
1871         uart_suspend_port(&pch_uart_driver, &priv->port);
1872
1873         pci_save_state(pdev);
1874         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1875         return 0;
1876 }
1877
1878 static int pch_uart_pci_resume(struct pci_dev *pdev)
1879 {
1880         struct eg20t_port *priv = pci_get_drvdata(pdev);
1881         int ret;
1882
1883         pci_set_power_state(pdev, PCI_D0);
1884         pci_restore_state(pdev);
1885
1886         ret = pci_enable_device(pdev);
1887         if (ret) {
1888                 dev_err(&pdev->dev,
1889                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1890                 return ret;
1891         }
1892
1893         uart_resume_port(&pch_uart_driver, &priv->port);
1894
1895         return 0;
1896 }
1897 #else
1898 #define pch_uart_pci_suspend NULL
1899 #define pch_uart_pci_resume NULL
1900 #endif
1901
1902 static const struct pci_device_id pch_uart_pci_id[] = {
1903         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1904          .driver_data = pch_et20t_uart0},
1905         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1906          .driver_data = pch_et20t_uart1},
1907         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1908          .driver_data = pch_et20t_uart2},
1909         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1910          .driver_data = pch_et20t_uart3},
1911         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1912          .driver_data = pch_ml7213_uart0},
1913         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1914          .driver_data = pch_ml7213_uart1},
1915         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1916          .driver_data = pch_ml7213_uart2},
1917         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1918          .driver_data = pch_ml7223_uart0},
1919         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1920          .driver_data = pch_ml7223_uart1},
1921         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1922          .driver_data = pch_ml7831_uart0},
1923         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1924          .driver_data = pch_ml7831_uart1},
1925         {0,},
1926 };
1927
1928 static int pch_uart_pci_probe(struct pci_dev *pdev,
1929                                         const struct pci_device_id *id)
1930 {
1931         int ret;
1932         struct eg20t_port *priv;
1933
1934         ret = pci_enable_device(pdev);
1935         if (ret < 0)
1936                 goto probe_error;
1937
1938         priv = pch_uart_init_port(pdev, id);
1939         if (!priv) {
1940                 ret = -EBUSY;
1941                 goto probe_disable_device;
1942         }
1943         pci_set_drvdata(pdev, priv);
1944
1945         return ret;
1946
1947 probe_disable_device:
1948         pci_disable_msi(pdev);
1949         pci_disable_device(pdev);
1950 probe_error:
1951         return ret;
1952 }
1953
1954 static struct pci_driver pch_uart_pci_driver = {
1955         .name = "pch_uart",
1956         .id_table = pch_uart_pci_id,
1957         .probe = pch_uart_pci_probe,
1958         .remove = pch_uart_pci_remove,
1959         .suspend = pch_uart_pci_suspend,
1960         .resume = pch_uart_pci_resume,
1961 };
1962
1963 static int __init pch_uart_module_init(void)
1964 {
1965         int ret;
1966
1967         /* register as UART driver */
1968         ret = uart_register_driver(&pch_uart_driver);
1969         if (ret < 0)
1970                 return ret;
1971
1972         /* register as PCI driver */
1973         ret = pci_register_driver(&pch_uart_pci_driver);
1974         if (ret < 0)
1975                 uart_unregister_driver(&pch_uart_driver);
1976
1977         return ret;
1978 }
1979 module_init(pch_uart_module_init);
1980
1981 static void __exit pch_uart_module_exit(void)
1982 {
1983         pci_unregister_driver(&pch_uart_pci_driver);
1984         uart_unregister_driver(&pch_uart_driver);
1985 }
1986 module_exit(pch_uart_module_exit);
1987
1988 MODULE_LICENSE("GPL v2");
1989 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1990 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1991
1992 module_param(default_baud, uint, S_IRUGO);
1993 MODULE_PARM_DESC(default_baud,
1994                  "Default BAUD for initial driver state and console (default 9600)");
1995 module_param(user_uartclk, uint, S_IRUGO);
1996 MODULE_PARM_DESC(user_uartclk,
1997                  "Override UART default or board specific UART clock");