drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   9 #define SUPPORT_SYSRQ
  10 #endif
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dmapool.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/slab.h>
  25 #include <linux/tty_flip.h>
  26
  27 /* All registers are 8-bit width */
  28 #define UARTBDH                 0x00
  29 #define UARTBDL                 0x01
  30 #define UARTCR1                 0x02
  31 #define UARTCR2                 0x03
  32 #define UARTSR1                 0x04
  33 #define UARTCR3                 0x06
  34 #define UARTDR                  0x07
  35 #define UARTCR4                 0x0a
  36 #define UARTCR5                 0x0b
  37 #define UARTMODEM               0x0d
  38 #define UARTPFIFO               0x10
  39 #define UARTCFIFO               0x11
  40 #define UARTSFIFO               0x12
  41 #define UARTTWFIFO              0x13
  42 #define UARTTCFIFO              0x14
  43 #define UARTRWFIFO              0x15
  44
  45 #define UARTBDH_LBKDIE          0x80
  46 #define UARTBDH_RXEDGIE         0x40
  47 #define UARTBDH_SBR_MASK        0x1f
  48
  49 #define UARTCR1_LOOPS           0x80
  50 #define UARTCR1_RSRC            0x20
  51 #define UARTCR1_M               0x10
  52 #define UARTCR1_WAKE            0x08
  53 #define UARTCR1_ILT             0x04
  54 #define UARTCR1_PE              0x02
  55 #define UARTCR1_PT              0x01
  56
  57 #define UARTCR2_TIE             0x80
  58 #define UARTCR2_TCIE            0x40
  59 #define UARTCR2_RIE             0x20
  60 #define UARTCR2_ILIE            0x10
  61 #define UARTCR2_TE              0x08
  62 #define UARTCR2_RE              0x04
  63 #define UARTCR2_RWU             0x02
  64 #define UARTCR2_SBK             0x01
  65
  66 #define UARTSR1_TDRE            0x80
  67 #define UARTSR1_TC              0x40
  68 #define UARTSR1_RDRF            0x20
  69 #define UARTSR1_IDLE            0x10
  70 #define UARTSR1_OR              0x08
  71 #define UARTSR1_NF              0x04
  72 #define UARTSR1_FE              0x02
  73 #define UARTSR1_PE              0x01
  74
  75 #define UARTCR3_R8              0x80
  76 #define UARTCR3_T8              0x40
  77 #define UARTCR3_TXDIR           0x20
  78 #define UARTCR3_TXINV           0x10
  79 #define UARTCR3_ORIE            0x08
  80 #define UARTCR3_NEIE            0x04
  81 #define UARTCR3_FEIE            0x02
  82 #define UARTCR3_PEIE            0x01
  83
  84 #define UARTCR4_MAEN1           0x80
  85 #define UARTCR4_MAEN2           0x40
  86 #define UARTCR4_M10             0x20
  87 #define UARTCR4_BRFA_MASK       0x1f
  88 #define UARTCR4_BRFA_OFF        0
  89
  90 #define UARTCR5_TDMAS           0x80
  91 #define UARTCR5_RDMAS           0x20
  92
  93 #define UARTMODEM_RXRTSE        0x08
  94 #define UARTMODEM_TXRTSPOL      0x04
  95 #define UARTMODEM_TXRTSE        0x02
  96 #define UARTMODEM_TXCTSE        0x01
  97
  98 #define UARTPFIFO_TXFE          0x80
  99 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 100 #define UARTPFIFO_TXSIZE_OFF    4
 101 #define UARTPFIFO_RXFE          0x08
 102 #define UARTPFIFO_RXSIZE_OFF    0
 103
 104 #define UARTCFIFO_TXFLUSH       0x80
 105 #define UARTCFIFO_RXFLUSH       0x40
 106 #define UARTCFIFO_RXOFE         0x04
 107 #define UARTCFIFO_TXOFE         0x02
 108 #define UARTCFIFO_RXUFE         0x01
 109
 110 #define UARTSFIFO_TXEMPT        0x80
 111 #define UARTSFIFO_RXEMPT        0x40
 112 #define UARTSFIFO_RXOF          0x04
 113 #define UARTSFIFO_TXOF          0x02
 114 #define UARTSFIFO_RXUF          0x01
 115
 116 /* 32-bit register definition */
 117 #define UARTBAUD                0x00
 118 #define UARTSTAT                0x04
 119 #define UARTCTRL                0x08
 120 #define UARTDATA                0x0C
 121 #define UARTMATCH               0x10
 122 #define UARTMODIR               0x14
 123 #define UARTFIFO                0x18
 124 #define UARTWATER               0x1c
 125
 126 #define UARTBAUD_MAEN1          0x80000000
 127 #define UARTBAUD_MAEN2          0x40000000
 128 #define UARTBAUD_M10            0x20000000
 129 #define UARTBAUD_TDMAE          0x00800000
 130 #define UARTBAUD_RDMAE          0x00200000
 131 #define UARTBAUD_MATCFG         0x00400000
 132 #define UARTBAUD_BOTHEDGE       0x00020000
 133 #define UARTBAUD_RESYNCDIS      0x00010000
 134 #define UARTBAUD_LBKDIE         0x00008000
 135 #define UARTBAUD_RXEDGIE        0x00004000
 136 #define UARTBAUD_SBNS           0x00002000
 137 #define UARTBAUD_SBR            0x00000000
 138 #define UARTBAUD_SBR_MASK       0x1fff
 139 #define UARTBAUD_OSR_MASK       0x1f
 140 #define UARTBAUD_OSR_SHIFT      24
 141
 142 #define UARTSTAT_LBKDIF         0x80000000
 143 #define UARTSTAT_RXEDGIF        0x40000000
 144 #define UARTSTAT_MSBF           0x20000000
 145 #define UARTSTAT_RXINV          0x10000000
 146 #define UARTSTAT_RWUID          0x08000000
 147 #define UARTSTAT_BRK13          0x04000000
 148 #define UARTSTAT_LBKDE          0x02000000
 149 #define UARTSTAT_RAF            0x01000000
 150 #define UARTSTAT_TDRE           0x00800000
 151 #define UARTSTAT_TC             0x00400000
 152 #define UARTSTAT_RDRF           0x00200000
 153 #define UARTSTAT_IDLE           0x00100000
 154 #define UARTSTAT_OR             0x00080000
 155 #define UARTSTAT_NF             0x00040000
 156 #define UARTSTAT_FE             0x00020000
 157 #define UARTSTAT_PE             0x00010000
 158 #define UARTSTAT_MA1F           0x00008000
 159 #define UARTSTAT_M21F           0x00004000
 160
 161 #define UARTCTRL_R8T9           0x80000000
 162 #define UARTCTRL_R9T8           0x40000000
 163 #define UARTCTRL_TXDIR          0x20000000
 164 #define UARTCTRL_TXINV          0x10000000
 165 #define UARTCTRL_ORIE           0x08000000
 166 #define UARTCTRL_NEIE           0x04000000
 167 #define UARTCTRL_FEIE           0x02000000
 168 #define UARTCTRL_PEIE           0x01000000
 169 #define UARTCTRL_TIE            0x00800000
 170 #define UARTCTRL_TCIE           0x00400000
 171 #define UARTCTRL_RIE            0x00200000
 172 #define UARTCTRL_ILIE           0x00100000
 173 #define UARTCTRL_TE             0x00080000
 174 #define UARTCTRL_RE             0x00040000
 175 #define UARTCTRL_RWU            0x00020000
 176 #define UARTCTRL_SBK            0x00010000
 177 #define UARTCTRL_MA1IE          0x00008000
 178 #define UARTCTRL_MA2IE          0x00004000
 179 #define UARTCTRL_IDLECFG        0x00000100
 180 #define UARTCTRL_LOOPS          0x00000080
 181 #define UARTCTRL_DOZEEN         0x00000040
 182 #define UARTCTRL_RSRC           0x00000020
 183 #define UARTCTRL_M              0x00000010
 184 #define UARTCTRL_WAKE           0x00000008
 185 #define UARTCTRL_ILT            0x00000004
 186 #define UARTCTRL_PE             0x00000002
 187 #define UARTCTRL_PT             0x00000001
 188
 189 #define UARTDATA_NOISY          0x00008000
 190 #define UARTDATA_PARITYE        0x00004000
 191 #define UARTDATA_FRETSC         0x00002000
 192 #define UARTDATA_RXEMPT         0x00001000
 193 #define UARTDATA_IDLINE         0x00000800
 194 #define UARTDATA_MASK           0x3ff
 195
 196 #define UARTMODIR_IREN          0x00020000
 197 #define UARTMODIR_TXCTSSRC      0x00000020
 198 #define UARTMODIR_TXCTSC        0x00000010
 199 #define UARTMODIR_RXRTSE        0x00000008
 200 #define UARTMODIR_TXRTSPOL      0x00000004
 201 #define UARTMODIR_TXRTSE        0x00000002
 202 #define UARTMODIR_TXCTSE        0x00000001
 203
 204 #define UARTFIFO_TXEMPT         0x00800000
 205 #define UARTFIFO_RXEMPT         0x00400000
 206 #define UARTFIFO_TXOF           0x00020000
 207 #define UARTFIFO_RXUF           0x00010000
 208 #define UARTFIFO_TXFLUSH        0x00008000
 209 #define UARTFIFO_RXFLUSH        0x00004000
 210 #define UARTFIFO_TXOFE          0x00000200
 211 #define UARTFIFO_RXUFE          0x00000100
 212 #define UARTFIFO_TXFE           0x00000080
 213 #define UARTFIFO_FIFOSIZE_MASK  0x7
 214 #define UARTFIFO_TXSIZE_OFF     4
 215 #define UARTFIFO_RXFE           0x00000008
 216 #define UARTFIFO_RXSIZE_OFF     0
 217 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 218
 219 #define UARTWATER_COUNT_MASK    0xff
 220 #define UARTWATER_TXCNT_OFF     8
 221 #define UARTWATER_RXCNT_OFF     24
 222 #define UARTWATER_WATER_MASK    0xff
 223 #define UARTWATER_TXWATER_OFF   0
 224 #define UARTWATER_RXWATER_OFF   16
 225
 226 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 227 #define DMA_RX_TIMEOUT          (10)
 228
 229 #define DRIVER_NAME     "fsl-lpuart"
 230 #define DEV_NAME        "ttyLP"
 231 #define UART_NR         6
 232
 233 /* IMX lpuart has four extra unused regs located at the beginning */
 234 #define IMX_REG_OFF     0x10
 235
 236 static DEFINE_IDA(fsl_lpuart_ida);
 237
 238 enum lpuart_type {
 239         VF610_LPUART,
 240         LS1021A_LPUART,
 241         IMX7ULP_LPUART,
 242         IMX8QXP_LPUART,
 243 };
 244
 245 struct lpuart_port {
 246         struct uart_port        port;
 247         enum lpuart_type        devtype;
 248         struct clk              *ipg_clk;
 249         struct clk              *baud_clk;
 250         unsigned int            txfifo_size;
 251         unsigned int            rxfifo_size;
 252
 253         bool                    lpuart_dma_tx_use;
 254         bool                    lpuart_dma_rx_use;
 255         struct dma_chan         *dma_tx_chan;
 256         struct dma_chan         *dma_rx_chan;
 257         struct dma_async_tx_descriptor  *dma_tx_desc;
 258         struct dma_async_tx_descriptor  *dma_rx_desc;
 259         dma_cookie_t            dma_tx_cookie;
 260         dma_cookie_t            dma_rx_cookie;
 261         unsigned int            dma_tx_bytes;
 262         unsigned int            dma_rx_bytes;
 263         bool                    dma_tx_in_progress;
 264         unsigned int            dma_rx_timeout;
 265         struct timer_list       lpuart_timer;
 266         struct scatterlist      rx_sgl, tx_sgl[2];
 267         struct circ_buf         rx_ring;
 268         int                     rx_dma_rng_buf_len;
 269         unsigned int            dma_tx_nents;
 270         wait_queue_head_t       dma_wait;
 271         bool                    id_allocated;
 272 };
 273
 274 struct lpuart_soc_data {
 275         enum lpuart_type devtype;
 276         char iotype;
 277         u8 reg_off;
 278 };
 279
 280 static const struct lpuart_soc_data vf_data = {
 281         .devtype = VF610_LPUART,
 282         .iotype = UPIO_MEM,
 283 };
 284
 285 static const struct lpuart_soc_data ls_data = {
 286         .devtype = LS1021A_LPUART,
 287         .iotype = UPIO_MEM32BE,
 288 };
 289
 290 static struct lpuart_soc_data imx7ulp_data = {
 291         .devtype = IMX7ULP_LPUART,
 292         .iotype = UPIO_MEM32,
 293         .reg_off = IMX_REG_OFF,
 294 };
 295
 296 static struct lpuart_soc_data imx8qxp_data = {
 297         .devtype = IMX8QXP_LPUART,
 298         .iotype = UPIO_MEM32,
 299         .reg_off = IMX_REG_OFF,
 300 };
 301
 302 static const struct of_device_id lpuart_dt_ids[] = {
 303         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 304         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls_data, },
 305         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 306         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 307         { /* sentinel */ }
 308 };
 309 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 310
 311 /* Forward declare this for the dma callbacks*/
 312 static void lpuart_dma_tx_complete(void *arg);
 313
 314 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 315 {
 316         return sport->devtype == IMX8QXP_LPUART;
 317 }
 318
 319 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 320 {
 321         switch (port->iotype) {
 322         case UPIO_MEM32:
 323                 return readl(port->membase + off);
 324         case UPIO_MEM32BE:
 325                 return ioread32be(port->membase + off);
 326         default:
 327                 return 0;
 328         }
 329 }
 330
 331 static inline void lpuart32_write(struct uart_port *port, u32 val,
 332                                   u32 off)
 333 {
 334         switch (port->iotype) {
 335         case UPIO_MEM32:
 336                 writel(val, port->membase + off);
 337                 break;
 338         case UPIO_MEM32BE:
 339                 iowrite32be(val, port->membase + off);
 340                 break;
 341         }
 342 }
 343
 344 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 345 {
 346         int ret = 0;
 347
 348         if (is_en) {
 349                 ret = clk_prepare_enable(sport->ipg_clk);
 350                 if (ret)
 351                         return ret;
 352
 353                 ret = clk_prepare_enable(sport->baud_clk);
 354                 if (ret) {
 355                         clk_disable_unprepare(sport->ipg_clk);
 356                         return ret;
 357                 }
 358         } else {
 359                 clk_disable_unprepare(sport->baud_clk);
 360                 clk_disable_unprepare(sport->ipg_clk);
 361         }
 362
 363         return 0;
 364 }
 365
 366 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 367 {
 368         if (is_imx8qxp_lpuart(sport))
 369                 return clk_get_rate(sport->baud_clk);
 370
 371         return clk_get_rate(sport->ipg_clk);
 372 }
 373
 374 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 375 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 376
 377 static void lpuart_stop_tx(struct uart_port *port)
 378 {
 379         unsigned char temp;
 380
 381         temp = readb(port->membase + UARTCR2);
 382         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 383         writeb(temp, port->membase + UARTCR2);
 384 }
 385
 386 static void lpuart32_stop_tx(struct uart_port *port)
 387 {
 388         unsigned long temp;
 389
 390         temp = lpuart32_read(port, UARTCTRL);
 391         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 392         lpuart32_write(port, temp, UARTCTRL);
 393 }
 394
 395 static void lpuart_stop_rx(struct uart_port *port)
 396 {
 397         unsigned char temp;
 398
 399         temp = readb(port->membase + UARTCR2);
 400         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 401 }
 402
 403 static void lpuart32_stop_rx(struct uart_port *port)
 404 {
 405         unsigned long temp;
 406
 407         temp = lpuart32_read(port, UARTCTRL);
 408         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 409 }
 410
 411 static void lpuart_dma_tx(struct lpuart_port *sport)
 412 {
 413         struct circ_buf *xmit = &sport->port.state->xmit;
 414         struct scatterlist *sgl = sport->tx_sgl;
 415         struct device *dev = sport->port.dev;
 416         int ret;
 417
 418         if (sport->dma_tx_in_progress)
 419                 return;
 420
 421         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 422
 423         if (xmit->tail < xmit->head || xmit->head == 0) {
 424                 sport->dma_tx_nents = 1;
 425                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 426         } else {
 427                 sport->dma_tx_nents = 2;
 428                 sg_init_table(sgl, 2);
 429                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 430                                 UART_XMIT_SIZE - xmit->tail);
 431                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 432         }
 433
 434         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 435         if (!ret) {
 436                 dev_err(dev, "DMA mapping error for TX.\n");
 437                 return;
 438         }
 439
 440         sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
 441                                         ret, DMA_MEM_TO_DEV,
 442                                         DMA_PREP_INTERRUPT);
 443         if (!sport->dma_tx_desc) {
 444                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 445                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 446                 return;
 447         }
 448
 449         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 450         sport->dma_tx_desc->callback_param = sport;
 451         sport->dma_tx_in_progress = true;
 452         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 453         dma_async_issue_pending(sport->dma_tx_chan);
 454 }
 455
 456 static bool lpuart_stopped_or_empty(struct uart_port *port)
 457 {
 458         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 459 }
 460
 461 static void lpuart_dma_tx_complete(void *arg)
 462 {
 463         struct lpuart_port *sport = arg;
 464         struct scatterlist *sgl = &sport->tx_sgl[0];
 465         struct circ_buf *xmit = &sport->port.state->xmit;
 466         unsigned long flags;
 467
 468         spin_lock_irqsave(&sport->port.lock, flags);
 469
 470         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 471
 472         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 473
 474         sport->port.icount.tx += sport->dma_tx_bytes;
 475         sport->dma_tx_in_progress = false;
 476         spin_unlock_irqrestore(&sport->port.lock, flags);
 477
 478         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 479                 uart_write_wakeup(&sport->port);
 480
 481         if (waitqueue_active(&sport->dma_wait)) {
 482                 wake_up(&sport->dma_wait);
 483                 return;
 484         }
 485
 486         spin_lock_irqsave(&sport->port.lock, flags);
 487
 488         if (!lpuart_stopped_or_empty(&sport->port))
 489                 lpuart_dma_tx(sport);
 490
 491         spin_unlock_irqrestore(&sport->port.lock, flags);
 492 }
 493
 494 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 495 {
 496         switch (sport->port.iotype) {
 497         case UPIO_MEM32:
 498                 return sport->port.mapbase + UARTDATA;
 499         case UPIO_MEM32BE:
 500                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 501         }
 502         return sport->port.mapbase + UARTDR;
 503 }
 504
 505 static int lpuart_dma_tx_request(struct uart_port *port)
 506 {
 507         struct lpuart_port *sport = container_of(port,
 508                                         struct lpuart_port, port);
 509         struct dma_slave_config dma_tx_sconfig = {};
 510         int ret;
 511
 512         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 513         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 514         dma_tx_sconfig.dst_maxburst = 1;
 515         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 516         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 517
 518         if (ret) {
 519                 dev_err(sport->port.dev,
 520                                 "DMA slave config failed, err = %d\n", ret);
 521                 return ret;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static bool lpuart_is_32(struct lpuart_port *sport)
 528 {
 529         return sport->port.iotype == UPIO_MEM32 ||
 530                sport->port.iotype ==  UPIO_MEM32BE;
 531 }
 532
 533 static void lpuart_flush_buffer(struct uart_port *port)
 534 {
 535         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 536         u32 val;
 537
 538         if (sport->lpuart_dma_tx_use) {
 539                 if (sport->dma_tx_in_progress) {
 540                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
 541                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 542                         sport->dma_tx_in_progress = false;
 543                 }
 544                 dmaengine_terminate_all(sport->dma_tx_chan);
 545         }
 546
 547         if (lpuart_is_32(sport)) {
 548                 val = lpuart32_read(&sport->port, UARTFIFO);
 549                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 550                 lpuart32_write(&sport->port, val, UARTFIFO);
 551         } else {
 552                 val = readb(sport->port.membase + UARTCFIFO);
 553                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 554                 writeb(val, sport->port.membase + UARTCFIFO);
 555         }
 556 }
 557
 558 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 559                                 u8 bit)
 560 {
 561         while (!(readb(port->membase + offset) & bit))
 562                 cpu_relax();
 563 }
 564
 565 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 566                                   u32 bit)
 567 {
 568         while (!(lpuart32_read(port, offset) & bit))
 569                 cpu_relax();
 570 }
 571
 572 #if defined(CONFIG_CONSOLE_POLL)
 573
 574 static int lpuart_poll_init(struct uart_port *port)
 575 {
 576         struct lpuart_port *sport = container_of(port,
 577                                         struct lpuart_port, port);
 578         unsigned long flags;
 579         unsigned char temp;
 580
 581         sport->port.fifosize = 0;
 582
 583         spin_lock_irqsave(&sport->port.lock, flags);
 584         /* Disable Rx & Tx */
 585         writeb(0, sport->port.membase + UARTCR2);
 586
 587         temp = readb(sport->port.membase + UARTPFIFO);
 588         /* Enable Rx and Tx FIFO */
 589         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 590                         sport->port.membase + UARTPFIFO);
 591
 592         /* flush Tx and Rx FIFO */
 593         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 594                         sport->port.membase + UARTCFIFO);
 595
 596         /* explicitly clear RDRF */
 597         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 598                 readb(sport->port.membase + UARTDR);
 599                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 600         }
 601
 602         writeb(0, sport->port.membase + UARTTWFIFO);
 603         writeb(1, sport->port.membase + UARTRWFIFO);
 604
 605         /* Enable Rx and Tx */
 606         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 607         spin_unlock_irqrestore(&sport->port.lock, flags);
 608
 609         return 0;
 610 }
 611
 612 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 613 {
 614         /* drain */
 615         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 616         writeb(c, port->membase + UARTDR);
 617 }
 618
 619 static int lpuart_poll_get_char(struct uart_port *port)
 620 {
 621         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 622                 return NO_POLL_CHAR;
 623
 624         return readb(port->membase + UARTDR);
 625 }
 626
 627 static int lpuart32_poll_init(struct uart_port *port)
 628 {
 629         unsigned long flags;
 630         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 631         u32 temp;
 632
 633         sport->port.fifosize = 0;
 634
 635         spin_lock_irqsave(&sport->port.lock, flags);
 636
 637         /* Disable Rx & Tx */
 638         lpuart32_write(&sport->port, UARTCTRL, 0);
 639
 640         temp = lpuart32_read(&sport->port, UARTFIFO);
 641
 642         /* Enable Rx and Tx FIFO */
 643         lpuart32_write(&sport->port, UARTFIFO,
 644                        temp | UARTFIFO_RXFE | UARTFIFO_TXFE);
 645
 646         /* flush Tx and Rx FIFO */
 647         lpuart32_write(&sport->port, UARTFIFO,
 648                        UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH);
 649
 650         /* explicitly clear RDRF */
 651         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 652                 lpuart32_read(&sport->port, UARTDATA);
 653                 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
 654         }
 655
 656         /* Enable Rx and Tx */
 657         lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE);
 658         spin_unlock_irqrestore(&sport->port.lock, flags);
 659
 660         return 0;
 661 }
 662
 663 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 664 {
 665         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 666         lpuart32_write(port, UARTDATA, c);
 667 }
 668
 669 static int lpuart32_poll_get_char(struct uart_port *port)
 670 {
 671         if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF))
 672                 return NO_POLL_CHAR;
 673
 674         return lpuart32_read(port, UARTDATA);
 675 }
 676 #endif
 677
 678 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 679 {
 680         struct circ_buf *xmit = &sport->port.state->xmit;
 681
 682         if (sport->port.x_char) {
 683                 writeb(sport->port.x_char, sport->port.membase + UARTDR);
 684                 sport->port.icount.tx++;
 685                 sport->port.x_char = 0;
 686                 return;
 687         }
 688
 689         if (lpuart_stopped_or_empty(&sport->port)) {
 690                 lpuart_stop_tx(&sport->port);
 691                 return;
 692         }
 693
 694         while (!uart_circ_empty(xmit) &&
 695                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 696                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 697                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 698                 sport->port.icount.tx++;
 699         }
 700
 701         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 702                 uart_write_wakeup(&sport->port);
 703
 704         if (uart_circ_empty(xmit))
 705                 lpuart_stop_tx(&sport->port);
 706 }
 707
 708 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 709 {
 710         struct circ_buf *xmit = &sport->port.state->xmit;
 711         unsigned long txcnt;
 712
 713         if (sport->port.x_char) {
 714                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 715                 sport->port.icount.tx++;
 716                 sport->port.x_char = 0;
 717                 return;
 718         }
 719
 720         if (lpuart_stopped_or_empty(&sport->port)) {
 721                 lpuart32_stop_tx(&sport->port);
 722                 return;
 723         }
 724
 725         txcnt = lpuart32_read(&sport->port, UARTWATER);
 726         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 727         txcnt &= UARTWATER_COUNT_MASK;
 728         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 729                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 730                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 731                 sport->port.icount.tx++;
 732                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 733                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 734                 txcnt &= UARTWATER_COUNT_MASK;
 735         }
 736
 737         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 738                 uart_write_wakeup(&sport->port);
 739
 740         if (uart_circ_empty(xmit))
 741                 lpuart32_stop_tx(&sport->port);
 742 }
 743
 744 static void lpuart_start_tx(struct uart_port *port)
 745 {
 746         struct lpuart_port *sport = container_of(port,
 747                         struct lpuart_port, port);
 748         unsigned char temp;
 749
 750         temp = readb(port->membase + UARTCR2);
 751         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 752
 753         if (sport->lpuart_dma_tx_use) {
 754                 if (!lpuart_stopped_or_empty(port))
 755                         lpuart_dma_tx(sport);
 756         } else {
 757                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 758                         lpuart_transmit_buffer(sport);
 759         }
 760 }
 761
 762 static void lpuart32_start_tx(struct uart_port *port)
 763 {
 764         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 765         unsigned long temp;
 766
 767         if (sport->lpuart_dma_tx_use) {
 768                 if (!lpuart_stopped_or_empty(port))
 769                         lpuart_dma_tx(sport);
 770         } else {
 771                 temp = lpuart32_read(port, UARTCTRL);
 772                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 773
 774                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 775                         lpuart32_transmit_buffer(sport);
 776         }
 777 }
 778
 779 /* return TIOCSER_TEMT when transmitter is not busy */
 780 static unsigned int lpuart_tx_empty(struct uart_port *port)
 781 {
 782         struct lpuart_port *sport = container_of(port,
 783                         struct lpuart_port, port);
 784         unsigned char sr1 = readb(port->membase + UARTSR1);
 785         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 786
 787         if (sport->dma_tx_in_progress)
 788                 return 0;
 789
 790         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 791                 return TIOCSER_TEMT;
 792
 793         return 0;
 794 }
 795
 796 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 797 {
 798         struct lpuart_port *sport = container_of(port,
 799                         struct lpuart_port, port);
 800         unsigned long stat = lpuart32_read(port, UARTSTAT);
 801         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 802
 803         if (sport->dma_tx_in_progress)
 804                 return 0;
 805
 806         if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
 807                 return TIOCSER_TEMT;
 808
 809         return 0;
 810 }
 811
 812 static void lpuart_txint(struct lpuart_port *sport)
 813 {
 814         unsigned long flags;
 815
 816         spin_lock_irqsave(&sport->port.lock, flags);
 817         lpuart_transmit_buffer(sport);
 818         spin_unlock_irqrestore(&sport->port.lock, flags);
 819 }
 820
 821 static void lpuart_rxint(struct lpuart_port *sport)
 822 {
 823         unsigned int flg, ignored = 0, overrun = 0;
 824         struct tty_port *port = &sport->port.state->port;
 825         unsigned long flags;
 826         unsigned char rx, sr;
 827
 828         spin_lock_irqsave(&sport->port.lock, flags);
 829
 830         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 831                 flg = TTY_NORMAL;
 832                 sport->port.icount.rx++;
 833                 /*
 834                  * to clear the FE, OR, NF, FE, PE flags,
 835                  * read SR1 then read DR
 836                  */
 837                 sr = readb(sport->port.membase + UARTSR1);
 838                 rx = readb(sport->port.membase + UARTDR);
 839
 840                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 841                         continue;
 842
 843                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 844                         if (sr & UARTSR1_PE)
 845                                 sport->port.icount.parity++;
 846                         else if (sr & UARTSR1_FE)
 847                                 sport->port.icount.frame++;
 848
 849                         if (sr & UARTSR1_OR)
 850                                 overrun++;
 851
 852                         if (sr & sport->port.ignore_status_mask) {
 853                                 if (++ignored > 100)
 854                                         goto out;
 855                                 continue;
 856                         }
 857
 858                         sr &= sport->port.read_status_mask;
 859
 860                         if (sr & UARTSR1_PE)
 861                                 flg = TTY_PARITY;
 862                         else if (sr & UARTSR1_FE)
 863                                 flg = TTY_FRAME;
 864
 865                         if (sr & UARTSR1_OR)
 866                                 flg = TTY_OVERRUN;
 867
 868 #ifdef SUPPORT_SYSRQ
 869                         sport->port.sysrq = 0;
 870 #endif
 871                 }
 872
 873                 tty_insert_flip_char(port, rx, flg);
 874         }
 875
 876 out:
 877         if (overrun) {
 878                 sport->port.icount.overrun += overrun;
 879
 880                 /*
 881                  * Overruns cause FIFO pointers to become missaligned.
 882                  * Flushing the receive FIFO reinitializes the pointers.
 883                  */
 884                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 885                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 886         }
 887
 888         spin_unlock_irqrestore(&sport->port.lock, flags);
 889
 890         tty_flip_buffer_push(port);
 891 }
 892
 893 static void lpuart32_txint(struct lpuart_port *sport)
 894 {
 895         unsigned long flags;
 896
 897         spin_lock_irqsave(&sport->port.lock, flags);
 898         lpuart32_transmit_buffer(sport);
 899         spin_unlock_irqrestore(&sport->port.lock, flags);
 900 }
 901
 902 static void lpuart32_rxint(struct lpuart_port *sport)
 903 {
 904         unsigned int flg, ignored = 0;
 905         struct tty_port *port = &sport->port.state->port;
 906         unsigned long flags;
 907         unsigned long rx, sr;
 908
 909         spin_lock_irqsave(&sport->port.lock, flags);
 910
 911         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 912                 flg = TTY_NORMAL;
 913                 sport->port.icount.rx++;
 914                 /*
 915                  * to clear the FE, OR, NF, FE, PE flags,
 916                  * read STAT then read DATA reg
 917                  */
 918                 sr = lpuart32_read(&sport->port, UARTSTAT);
 919                 rx = lpuart32_read(&sport->port, UARTDATA);
 920                 rx &= 0x3ff;
 921
 922                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 923                         continue;
 924
 925                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 926                         if (sr & UARTSTAT_PE)
 927                                 sport->port.icount.parity++;
 928                         else if (sr & UARTSTAT_FE)
 929                                 sport->port.icount.frame++;
 930
 931                         if (sr & UARTSTAT_OR)
 932                                 sport->port.icount.overrun++;
 933
 934                         if (sr & sport->port.ignore_status_mask) {
 935                                 if (++ignored > 100)
 936                                         goto out;
 937                                 continue;
 938                         }
 939
 940                         sr &= sport->port.read_status_mask;
 941
 942                         if (sr & UARTSTAT_PE)
 943                                 flg = TTY_PARITY;
 944                         else if (sr & UARTSTAT_FE)
 945                                 flg = TTY_FRAME;
 946
 947                         if (sr & UARTSTAT_OR)
 948                                 flg = TTY_OVERRUN;
 949
 950 #ifdef SUPPORT_SYSRQ
 951                         sport->port.sysrq = 0;
 952 #endif
 953                 }
 954
 955                 tty_insert_flip_char(port, rx, flg);
 956         }
 957
 958 out:
 959         spin_unlock_irqrestore(&sport->port.lock, flags);
 960
 961         tty_flip_buffer_push(port);
 962 }
 963
 964 static irqreturn_t lpuart_int(int irq, void *dev_id)
 965 {
 966         struct lpuart_port *sport = dev_id;
 967         unsigned char sts;
 968
 969         sts = readb(sport->port.membase + UARTSR1);
 970
 971         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
 972                 lpuart_rxint(sport);
 973
 974         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
 975                 lpuart_txint(sport);
 976
 977         return IRQ_HANDLED;
 978 }
 979
 980 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 981 {
 982         struct lpuart_port *sport = dev_id;
 983         unsigned long sts, rxcount;
 984
 985         sts = lpuart32_read(&sport->port, UARTSTAT);
 986         rxcount = lpuart32_read(&sport->port, UARTWATER);
 987         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 988
 989         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
 990                 lpuart32_rxint(sport);
 991
 992         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
 993                 lpuart32_txint(sport);
 994
 995         lpuart32_write(&sport->port, sts, UARTSTAT);
 996         return IRQ_HANDLED;
 997 }
 998
 999 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1000 {
1001         struct tty_port *port = &sport->port.state->port;
1002         struct dma_tx_state state;
1003         enum dma_status dmastat;
1004         struct circ_buf *ring = &sport->rx_ring;
1005         unsigned long flags;
1006         int count = 0;
1007
1008         if (lpuart_is_32(sport)) {
1009                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1010
1011                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1012                         /* Read DR to clear the error flags */
1013                         lpuart32_read(&sport->port, UARTDATA);
1014
1015                         if (sr & UARTSTAT_PE)
1016                                 sport->port.icount.parity++;
1017                         else if (sr & UARTSTAT_FE)
1018                                 sport->port.icount.frame++;
1019                 }
1020         } else {
1021                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1022
1023                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1024                         unsigned char cr2;
1025
1026                         /* Disable receiver during this operation... */
1027                         cr2 = readb(sport->port.membase + UARTCR2);
1028                         cr2 &= ~UARTCR2_RE;
1029                         writeb(cr2, sport->port.membase + UARTCR2);
1030
1031                         /* Read DR to clear the error flags */
1032                         readb(sport->port.membase + UARTDR);
1033
1034                         if (sr & UARTSR1_PE)
1035                                 sport->port.icount.parity++;
1036                         else if (sr & UARTSR1_FE)
1037                                 sport->port.icount.frame++;
1038                         /*
1039                          * At this point parity/framing error is
1040                          * cleared However, since the DMA already read
1041                          * the data register and we had to read it
1042                          * again after reading the status register to
1043                          * properly clear the flags, the FIFO actually
1044                          * underflowed... This requires a clearing of
1045                          * the FIFO...
1046                          */
1047                         if (readb(sport->port.membase + UARTSFIFO) &
1048                             UARTSFIFO_RXUF) {
1049                                 writeb(UARTSFIFO_RXUF,
1050                                        sport->port.membase + UARTSFIFO);
1051                                 writeb(UARTCFIFO_RXFLUSH,
1052                                        sport->port.membase + UARTCFIFO);
1053                         }
1054
1055                         cr2 |= UARTCR2_RE;
1056                         writeb(cr2, sport->port.membase + UARTCR2);
1057                 }
1058         }
1059
1060         async_tx_ack(sport->dma_rx_desc);
1061
1062         spin_lock_irqsave(&sport->port.lock, flags);
1063
1064         dmastat = dmaengine_tx_status(sport->dma_rx_chan,
1065                                 sport->dma_rx_cookie,
1066                                 &state);
1067
1068         if (dmastat == DMA_ERROR) {
1069                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1070                 spin_unlock_irqrestore(&sport->port.lock, flags);
1071                 return;
1072         }
1073
1074         /* CPU claims ownership of RX DMA buffer */
1075         dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1076
1077         /*
1078          * ring->head points to the end of data already written by the DMA.
1079          * ring->tail points to the beginning of data to be read by the
1080          * framework.
1081          * The current transfer size should not be larger than the dma buffer
1082          * length.
1083          */
1084         ring->head = sport->rx_sgl.length - state.residue;
1085         BUG_ON(ring->head > sport->rx_sgl.length);
1086         /*
1087          * At this point ring->head may point to the first byte right after the
1088          * last byte of the dma buffer:
1089          * 0 <= ring->head <= sport->rx_sgl.length
1090          *
1091          * However ring->tail must always points inside the dma buffer:
1092          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1093          *
1094          * Since we use a ring buffer, we have to handle the case
1095          * where head is lower than tail. In such a case, we first read from
1096          * tail to the end of the buffer then reset tail.
1097          */
1098         if (ring->head < ring->tail) {
1099                 count = sport->rx_sgl.length - ring->tail;
1100
1101                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1102                 ring->tail = 0;
1103                 sport->port.icount.rx += count;
1104         }
1105
1106         /* Finally we read data from tail to head */
1107         if (ring->tail < ring->head) {
1108                 count = ring->head - ring->tail;
1109                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1110                 /* Wrap ring->head if needed */
1111                 if (ring->head >= sport->rx_sgl.length)
1112                         ring->head = 0;
1113                 ring->tail = ring->head;
1114                 sport->port.icount.rx += count;
1115         }
1116
1117         dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
1118                                DMA_FROM_DEVICE);
1119
1120         spin_unlock_irqrestore(&sport->port.lock, flags);
1121
1122         tty_flip_buffer_push(port);
1123         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1124 }
1125
1126 static void lpuart_dma_rx_complete(void *arg)
1127 {
1128         struct lpuart_port *sport = arg;
1129
1130         lpuart_copy_rx_to_tty(sport);
1131 }
1132
1133 static void lpuart_timer_func(struct timer_list *t)
1134 {
1135         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1136
1137         lpuart_copy_rx_to_tty(sport);
1138 }
1139
1140 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1141 {
1142         struct dma_slave_config dma_rx_sconfig = {};
1143         struct circ_buf *ring = &sport->rx_ring;
1144         int ret, nent;
1145         int bits, baud;
1146         struct tty_port *port = &sport->port.state->port;
1147         struct tty_struct *tty = port->tty;
1148         struct ktermios *termios = &tty->termios;
1149
1150         baud = tty_get_baud_rate(tty);
1151
1152         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1153         if (termios->c_cflag & PARENB)
1154                 bits++;
1155
1156         /*
1157          * Calculate length of one DMA buffer size to keep latency below
1158          * 10ms at any baud rate.
1159          */
1160         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1161         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1162         if (sport->rx_dma_rng_buf_len < 16)
1163                 sport->rx_dma_rng_buf_len = 16;
1164
1165         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1166         if (!ring->buf)
1167                 return -ENOMEM;
1168
1169         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1170         nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1171
1172         if (!nent) {
1173                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1174                 return -EINVAL;
1175         }
1176
1177         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1178         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1179         dma_rx_sconfig.src_maxburst = 1;
1180         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1181         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1182
1183         if (ret < 0) {
1184                 dev_err(sport->port.dev,
1185                                 "DMA Rx slave config failed, err = %d\n", ret);
1186                 return ret;
1187         }
1188
1189         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1190                                  sg_dma_address(&sport->rx_sgl),
1191                                  sport->rx_sgl.length,
1192                                  sport->rx_sgl.length / 2,
1193                                  DMA_DEV_TO_MEM,
1194                                  DMA_PREP_INTERRUPT);
1195         if (!sport->dma_rx_desc) {
1196                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1197                 return -EFAULT;
1198         }
1199
1200         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1201         sport->dma_rx_desc->callback_param = sport;
1202         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1203         dma_async_issue_pending(sport->dma_rx_chan);
1204
1205         if (lpuart_is_32(sport)) {
1206                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1207
1208                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1209         } else {
1210                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1211                        sport->port.membase + UARTCR5);
1212         }
1213
1214         return 0;
1215 }
1216
1217 static void lpuart_dma_rx_free(struct uart_port *port)
1218 {
1219         struct lpuart_port *sport = container_of(port,
1220                                         struct lpuart_port, port);
1221
1222         if (sport->dma_rx_chan)
1223                 dmaengine_terminate_all(sport->dma_rx_chan);
1224
1225         dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1226         kfree(sport->rx_ring.buf);
1227         sport->rx_ring.tail = 0;
1228         sport->rx_ring.head = 0;
1229         sport->dma_rx_desc = NULL;
1230         sport->dma_rx_cookie = -EINVAL;
1231 }
1232
1233 static int lpuart_config_rs485(struct uart_port *port,
1234                         struct serial_rs485 *rs485)
1235 {
1236         struct lpuart_port *sport = container_of(port,
1237                         struct lpuart_port, port);
1238
1239         u8 modem = readb(sport->port.membase + UARTMODEM) &
1240                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1241         writeb(modem, sport->port.membase + UARTMODEM);
1242
1243         /* clear unsupported configurations */
1244         rs485->delay_rts_before_send = 0;
1245         rs485->delay_rts_after_send = 0;
1246         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1247
1248         if (rs485->flags & SER_RS485_ENABLED) {
1249                 /* Enable auto RS-485 RTS mode */
1250                 modem |= UARTMODEM_TXRTSE;
1251
1252                 /*
1253                  * RTS needs to be logic HIGH either during transer _or_ after
1254                  * transfer, other variants are not supported by the hardware.
1255                  */
1256
1257                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1258                                 SER_RS485_RTS_AFTER_SEND)))
1259                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1260
1261                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1262                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1263                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1264
1265                 /*
1266                  * The hardware defaults to RTS logic HIGH while transfer.
1267                  * Switch polarity in case RTS shall be logic HIGH
1268                  * after transfer.
1269                  * Note: UART is assumed to be active high.
1270                  */
1271                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1272                         modem &= ~UARTMODEM_TXRTSPOL;
1273                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1274                         modem |= UARTMODEM_TXRTSPOL;
1275         }
1276
1277         /* Store the new configuration */
1278         sport->port.rs485 = *rs485;
1279
1280         writeb(modem, sport->port.membase + UARTMODEM);
1281         return 0;
1282 }
1283
1284 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1285 {
1286         unsigned int temp = 0;
1287         unsigned char reg;
1288
1289         reg = readb(port->membase + UARTMODEM);
1290         if (reg & UARTMODEM_TXCTSE)
1291                 temp |= TIOCM_CTS;
1292
1293         if (reg & UARTMODEM_RXRTSE)
1294                 temp |= TIOCM_RTS;
1295
1296         return temp;
1297 }
1298
1299 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1300 {
1301         unsigned int temp = 0;
1302         unsigned long reg;
1303
1304         reg = lpuart32_read(port, UARTMODIR);
1305         if (reg & UARTMODIR_TXCTSE)
1306                 temp |= TIOCM_CTS;
1307
1308         if (reg & UARTMODIR_RXRTSE)
1309                 temp |= TIOCM_RTS;
1310
1311         return temp;
1312 }
1313
1314 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1315 {
1316         unsigned char temp;
1317         struct lpuart_port *sport = container_of(port,
1318                                 struct lpuart_port, port);
1319
1320         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1321         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1322                 temp = readb(sport->port.membase + UARTMODEM) &
1323                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1324
1325                 if (mctrl & TIOCM_RTS)
1326                         temp |= UARTMODEM_RXRTSE;
1327
1328                 if (mctrl & TIOCM_CTS)
1329                         temp |= UARTMODEM_TXCTSE;
1330
1331                 writeb(temp, port->membase + UARTMODEM);
1332         }
1333 }
1334
1335 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1336 {
1337         unsigned long temp;
1338
1339         temp = lpuart32_read(port, UARTMODIR) &
1340                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1341
1342         if (mctrl & TIOCM_RTS)
1343                 temp |= UARTMODIR_RXRTSE;
1344
1345         if (mctrl & TIOCM_CTS)
1346                 temp |= UARTMODIR_TXCTSE;
1347
1348         lpuart32_write(port, temp, UARTMODIR);
1349 }
1350
1351 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1352 {
1353         unsigned char temp;
1354
1355         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1356
1357         if (break_state != 0)
1358                 temp |= UARTCR2_SBK;
1359
1360         writeb(temp, port->membase + UARTCR2);
1361 }
1362
1363 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1364 {
1365         unsigned long temp;
1366
1367         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1368
1369         if (break_state != 0)
1370                 temp |= UARTCTRL_SBK;
1371
1372         lpuart32_write(port, temp, UARTCTRL);
1373 }
1374
1375 static void lpuart_setup_watermark(struct lpuart_port *sport)
1376 {
1377         unsigned char val, cr2;
1378         unsigned char cr2_saved;
1379
1380         cr2 = readb(sport->port.membase + UARTCR2);
1381         cr2_saved = cr2;
1382         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1383                         UARTCR2_RIE | UARTCR2_RE);
1384         writeb(cr2, sport->port.membase + UARTCR2);
1385
1386         val = readb(sport->port.membase + UARTPFIFO);
1387         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1388                         sport->port.membase + UARTPFIFO);
1389
1390         /* flush Tx and Rx FIFO */
1391         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1392                         sport->port.membase + UARTCFIFO);
1393
1394         /* explicitly clear RDRF */
1395         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1396                 readb(sport->port.membase + UARTDR);
1397                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1398         }
1399
1400         writeb(0, sport->port.membase + UARTTWFIFO);
1401         writeb(1, sport->port.membase + UARTRWFIFO);
1402
1403         /* Restore cr2 */
1404         writeb(cr2_saved, sport->port.membase + UARTCR2);
1405 }
1406
1407 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1408 {
1409         unsigned char cr2;
1410
1411         lpuart_setup_watermark(sport);
1412
1413         cr2 = readb(sport->port.membase + UARTCR2);
1414         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1415         writeb(cr2, sport->port.membase + UARTCR2);
1416 }
1417
1418 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1419 {
1420         unsigned long val, ctrl;
1421         unsigned long ctrl_saved;
1422
1423         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1424         ctrl_saved = ctrl;
1425         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1426                         UARTCTRL_RIE | UARTCTRL_RE);
1427         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1428
1429         /* enable FIFO mode */
1430         val = lpuart32_read(&sport->port, UARTFIFO);
1431         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1432         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1433         lpuart32_write(&sport->port, val, UARTFIFO);
1434
1435         /* set the watermark */
1436         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1437         lpuart32_write(&sport->port, val, UARTWATER);
1438
1439         /* Restore cr2 */
1440         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1441 }
1442
1443 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1444 {
1445         u32 temp;
1446
1447         lpuart32_setup_watermark(sport);
1448
1449         temp = lpuart32_read(&sport->port, UARTCTRL);
1450         temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1451         lpuart32_write(&sport->port, temp, UARTCTRL);
1452 }
1453
1454 static void rx_dma_timer_init(struct lpuart_port *sport)
1455 {
1456         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1457         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1458         add_timer(&sport->lpuart_timer);
1459 }
1460
1461 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1462 {
1463         u32 uartbaud;
1464
1465         if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
1466                 init_waitqueue_head(&sport->dma_wait);
1467                 sport->lpuart_dma_tx_use = true;
1468                 if (lpuart_is_32(sport)) {
1469                         uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1470                         lpuart32_write(&sport->port,
1471                                        uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1472                 } else {
1473                         writeb(readb(sport->port.membase + UARTCR5) |
1474                                 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1475                 }
1476         } else {
1477                 sport->lpuart_dma_tx_use = false;
1478         }
1479 }
1480
1481 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1482 {
1483         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1484                 /* set Rx DMA timeout */
1485                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1486                 if (!sport->dma_rx_timeout)
1487                         sport->dma_rx_timeout = 1;
1488
1489                 sport->lpuart_dma_rx_use = true;
1490                 rx_dma_timer_init(sport);
1491         } else {
1492                 sport->lpuart_dma_rx_use = false;
1493         }
1494 }
1495
1496 static int lpuart_startup(struct uart_port *port)
1497 {
1498         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1499         unsigned long flags;
1500         unsigned char temp;
1501
1502         /* determine FIFO size and enable FIFO mode */
1503         temp = readb(sport->port.membase + UARTPFIFO);
1504
1505         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1506                                             UARTPFIFO_FIFOSIZE_MASK);
1507         sport->port.fifosize = sport->txfifo_size;
1508
1509         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1510                                             UARTPFIFO_FIFOSIZE_MASK);
1511
1512         spin_lock_irqsave(&sport->port.lock, flags);
1513
1514         lpuart_setup_watermark_enable(sport);
1515
1516         lpuart_rx_dma_startup(sport);
1517         lpuart_tx_dma_startup(sport);
1518
1519         spin_unlock_irqrestore(&sport->port.lock, flags);
1520
1521         return 0;
1522 }
1523
1524 static void lpuart32_configure(struct lpuart_port *sport)
1525 {
1526         unsigned long temp;
1527
1528         if (sport->lpuart_dma_rx_use) {
1529                 /* RXWATER must be 0 */
1530                 temp = lpuart32_read(&sport->port, UARTWATER);
1531                 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1532                 lpuart32_write(&sport->port, temp, UARTWATER);
1533         }
1534         temp = lpuart32_read(&sport->port, UARTCTRL);
1535         if (!sport->lpuart_dma_rx_use)
1536                 temp |= UARTCTRL_RIE;
1537         if (!sport->lpuart_dma_tx_use)
1538                 temp |= UARTCTRL_TIE;
1539         lpuart32_write(&sport->port, temp, UARTCTRL);
1540 }
1541
1542 static int lpuart32_startup(struct uart_port *port)
1543 {
1544         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1545         unsigned long flags;
1546         unsigned long temp;
1547
1548         /* determine FIFO size */
1549         temp = lpuart32_read(&sport->port, UARTFIFO);
1550
1551         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1552                                             UARTFIFO_FIFOSIZE_MASK);
1553         sport->port.fifosize = sport->txfifo_size;
1554
1555         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1556                                             UARTFIFO_FIFOSIZE_MASK);
1557
1558         spin_lock_irqsave(&sport->port.lock, flags);
1559
1560         lpuart32_setup_watermark_enable(sport);
1561
1562
1563         lpuart_rx_dma_startup(sport);
1564         lpuart_tx_dma_startup(sport);
1565
1566         lpuart32_configure(sport);
1567
1568         spin_unlock_irqrestore(&sport->port.lock, flags);
1569         return 0;
1570 }
1571
1572 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1573 {
1574         if (sport->lpuart_dma_rx_use) {
1575                 del_timer_sync(&sport->lpuart_timer);
1576                 lpuart_dma_rx_free(&sport->port);
1577         }
1578
1579         if (sport->lpuart_dma_tx_use) {
1580                 if (wait_event_interruptible(sport->dma_wait,
1581                         !sport->dma_tx_in_progress) != false) {
1582                         sport->dma_tx_in_progress = false;
1583                         dmaengine_terminate_all(sport->dma_tx_chan);
1584                 }
1585         }
1586 }
1587
1588 static void lpuart_shutdown(struct uart_port *port)
1589 {
1590         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1591         unsigned char temp;
1592         unsigned long flags;
1593
1594         spin_lock_irqsave(&port->lock, flags);
1595
1596         /* disable Rx/Tx and interrupts */
1597         temp = readb(port->membase + UARTCR2);
1598         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1599                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1600         writeb(temp, port->membase + UARTCR2);
1601
1602         spin_unlock_irqrestore(&port->lock, flags);
1603
1604         lpuart_dma_shutdown(sport);
1605 }
1606
1607 static void lpuart32_shutdown(struct uart_port *port)
1608 {
1609         struct lpuart_port *sport =
1610                 container_of(port, struct lpuart_port, port);
1611         unsigned long temp;
1612         unsigned long flags;
1613
1614         spin_lock_irqsave(&port->lock, flags);
1615
1616         /* disable Rx/Tx and interrupts */
1617         temp = lpuart32_read(port, UARTCTRL);
1618         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1619                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1620         lpuart32_write(port, temp, UARTCTRL);
1621
1622         spin_unlock_irqrestore(&port->lock, flags);
1623
1624         lpuart_dma_shutdown(sport);
1625 }
1626
1627 static void
1628 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1629                    struct ktermios *old)
1630 {
1631         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1632         unsigned long flags;
1633         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1634         unsigned int  baud;
1635         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1636         unsigned int sbr, brfa;
1637
1638         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1639         old_cr2 = readb(sport->port.membase + UARTCR2);
1640         cr3 = readb(sport->port.membase + UARTCR3);
1641         cr4 = readb(sport->port.membase + UARTCR4);
1642         bdh = readb(sport->port.membase + UARTBDH);
1643         modem = readb(sport->port.membase + UARTMODEM);
1644         /*
1645          * only support CS8 and CS7, and for CS7 must enable PE.
1646          * supported mode:
1647          *  - (7,e/o,1)
1648          *  - (8,n,1)
1649          *  - (8,m/s,1)
1650          *  - (8,e/o,1)
1651          */
1652         while ((termios->c_cflag & CSIZE) != CS8 &&
1653                 (termios->c_cflag & CSIZE) != CS7) {
1654                 termios->c_cflag &= ~CSIZE;
1655                 termios->c_cflag |= old_csize;
1656                 old_csize = CS8;
1657         }
1658
1659         if ((termios->c_cflag & CSIZE) == CS8 ||
1660                 (termios->c_cflag & CSIZE) == CS7)
1661                 cr1 = old_cr1 & ~UARTCR1_M;
1662
1663         if (termios->c_cflag & CMSPAR) {
1664                 if ((termios->c_cflag & CSIZE) != CS8) {
1665                         termios->c_cflag &= ~CSIZE;
1666                         termios->c_cflag |= CS8;
1667                 }
1668                 cr1 |= UARTCR1_M;
1669         }
1670
1671         /*
1672          * When auto RS-485 RTS mode is enabled,
1673          * hardware flow control need to be disabled.
1674          */
1675         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1676                 termios->c_cflag &= ~CRTSCTS;
1677
1678         if (termios->c_cflag & CRTSCTS)
1679                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1680         else
1681                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1682
1683         termios->c_cflag &= ~CSTOPB;
1684
1685         /* parity must be enabled when CS7 to match 8-bits format */
1686         if ((termios->c_cflag & CSIZE) == CS7)
1687                 termios->c_cflag |= PARENB;
1688
1689         if (termios->c_cflag & PARENB) {
1690                 if (termios->c_cflag & CMSPAR) {
1691                         cr1 &= ~UARTCR1_PE;
1692                         if (termios->c_cflag & PARODD)
1693                                 cr3 |= UARTCR3_T8;
1694                         else
1695                                 cr3 &= ~UARTCR3_T8;
1696                 } else {
1697                         cr1 |= UARTCR1_PE;
1698                         if ((termios->c_cflag & CSIZE) == CS8)
1699                                 cr1 |= UARTCR1_M;
1700                         if (termios->c_cflag & PARODD)
1701                                 cr1 |= UARTCR1_PT;
1702                         else
1703                                 cr1 &= ~UARTCR1_PT;
1704                 }
1705         } else {
1706                 cr1 &= ~UARTCR1_PE;
1707         }
1708
1709         /* ask the core to calculate the divisor */
1710         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1711
1712         /*
1713          * Need to update the Ring buffer length according to the selected
1714          * baud rate and restart Rx DMA path.
1715          *
1716          * Since timer function acqures sport->port.lock, need to stop before
1717          * acquring same lock because otherwise del_timer_sync() can deadlock.
1718          */
1719         if (old && sport->lpuart_dma_rx_use) {
1720                 del_timer_sync(&sport->lpuart_timer);
1721                 lpuart_dma_rx_free(&sport->port);
1722         }
1723
1724         spin_lock_irqsave(&sport->port.lock, flags);
1725
1726         sport->port.read_status_mask = 0;
1727         if (termios->c_iflag & INPCK)
1728                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1729         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1730                 sport->port.read_status_mask |= UARTSR1_FE;
1731
1732         /* characters to ignore */
1733         sport->port.ignore_status_mask = 0;
1734         if (termios->c_iflag & IGNPAR)
1735                 sport->port.ignore_status_mask |= UARTSR1_PE;
1736         if (termios->c_iflag & IGNBRK) {
1737                 sport->port.ignore_status_mask |= UARTSR1_FE;
1738                 /*
1739                  * if we're ignoring parity and break indicators,
1740                  * ignore overruns too (for real raw support).
1741                  */
1742                 if (termios->c_iflag & IGNPAR)
1743                         sport->port.ignore_status_mask |= UARTSR1_OR;
1744         }
1745
1746         /* update the per-port timeout */
1747         uart_update_timeout(port, termios->c_cflag, baud);
1748
1749         /* wait transmit engin complete */
1750         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1751
1752         /* disable transmit and receive */
1753         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1754                         sport->port.membase + UARTCR2);
1755
1756         sbr = sport->port.uartclk / (16 * baud);
1757         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1758         bdh &= ~UARTBDH_SBR_MASK;
1759         bdh |= (sbr >> 8) & 0x1F;
1760         cr4 &= ~UARTCR4_BRFA_MASK;
1761         brfa &= UARTCR4_BRFA_MASK;
1762         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1763         writeb(bdh, sport->port.membase + UARTBDH);
1764         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1765         writeb(cr3, sport->port.membase + UARTCR3);
1766         writeb(cr1, sport->port.membase + UARTCR1);
1767         writeb(modem, sport->port.membase + UARTMODEM);
1768
1769         /* restore control register */
1770         writeb(old_cr2, sport->port.membase + UARTCR2);
1771
1772         if (old && sport->lpuart_dma_rx_use) {
1773                 if (!lpuart_start_rx_dma(sport))
1774                         rx_dma_timer_init(sport);
1775                 else
1776                         sport->lpuart_dma_rx_use = false;
1777         }
1778
1779         spin_unlock_irqrestore(&sport->port.lock, flags);
1780 }
1781
1782 static void
1783 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1784 {
1785         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1786         u32 clk = sport->port.uartclk;
1787
1788         /*
1789          * The idea is to use the best OSR (over-sampling rate) possible.
1790          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1791          * Loop to find the best OSR value possible, one that generates minimum
1792          * baud_diff iterate through the rest of the supported values of OSR.
1793          *
1794          * Calculation Formula:
1795          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1796          */
1797         baud_diff = baudrate;
1798         osr = 0;
1799         sbr = 0;
1800
1801         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1802                 /* calculate the temporary sbr value  */
1803                 tmp_sbr = (clk / (baudrate * tmp_osr));
1804                 if (tmp_sbr == 0)
1805                         tmp_sbr = 1;
1806
1807                 /*
1808                  * calculate the baud rate difference based on the temporary
1809                  * osr and sbr values
1810                  */
1811                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1812
1813                 /* select best values between sbr and sbr+1 */
1814                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1815                 if (tmp_diff > (baudrate - tmp)) {
1816                         tmp_diff = baudrate - tmp;
1817                         tmp_sbr++;
1818                 }
1819
1820                 if (tmp_diff <= baud_diff) {
1821                         baud_diff = tmp_diff;
1822                         osr = tmp_osr;
1823                         sbr = tmp_sbr;
1824
1825                         if (!baud_diff)
1826                                 break;
1827                 }
1828         }
1829
1830         /* handle buadrate outside acceptable rate */
1831         if (baud_diff > ((baudrate / 100) * 3))
1832                 dev_warn(sport->port.dev,
1833                          "unacceptable baud rate difference of more than 3%%\n");
1834
1835         tmp = lpuart32_read(&sport->port, UARTBAUD);
1836
1837         if ((osr > 3) && (osr < 8))
1838                 tmp |= UARTBAUD_BOTHEDGE;
1839
1840         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1841         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
1842
1843         tmp &= ~UARTBAUD_SBR_MASK;
1844         tmp |= sbr & UARTBAUD_SBR_MASK;
1845
1846         if (!sport->lpuart_dma_rx_use)
1847                 tmp &= ~UARTBAUD_RDMAE;
1848         if (!sport->lpuart_dma_tx_use)
1849                 tmp &= ~UARTBAUD_TDMAE;
1850
1851         lpuart32_write(&sport->port, tmp, UARTBAUD);
1852 }
1853
1854 static void
1855 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1856                    struct ktermios *old)
1857 {
1858         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1859         unsigned long flags;
1860         unsigned long ctrl, old_ctrl, modem;
1861         unsigned int  baud;
1862         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1863
1864         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1865         modem = lpuart32_read(&sport->port, UARTMODIR);
1866         /*
1867          * only support CS8 and CS7, and for CS7 must enable PE.
1868          * supported mode:
1869          *  - (7,e/o,1)
1870          *  - (8,n,1)
1871          *  - (8,m/s,1)
1872          *  - (8,e/o,1)
1873          */
1874         while ((termios->c_cflag & CSIZE) != CS8 &&
1875                 (termios->c_cflag & CSIZE) != CS7) {
1876                 termios->c_cflag &= ~CSIZE;
1877                 termios->c_cflag |= old_csize;
1878                 old_csize = CS8;
1879         }
1880
1881         if ((termios->c_cflag & CSIZE) == CS8 ||
1882                 (termios->c_cflag & CSIZE) == CS7)
1883                 ctrl = old_ctrl & ~UARTCTRL_M;
1884
1885         if (termios->c_cflag & CMSPAR) {
1886                 if ((termios->c_cflag & CSIZE) != CS8) {
1887                         termios->c_cflag &= ~CSIZE;
1888                         termios->c_cflag |= CS8;
1889                 }
1890                 ctrl |= UARTCTRL_M;
1891         }
1892
1893         if (termios->c_cflag & CRTSCTS) {
1894                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1895         } else {
1896                 termios->c_cflag &= ~CRTSCTS;
1897                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1898         }
1899
1900         if (termios->c_cflag & CSTOPB)
1901                 termios->c_cflag &= ~CSTOPB;
1902
1903         /* parity must be enabled when CS7 to match 8-bits format */
1904         if ((termios->c_cflag & CSIZE) == CS7)
1905                 termios->c_cflag |= PARENB;
1906
1907         if ((termios->c_cflag & PARENB)) {
1908                 if (termios->c_cflag & CMSPAR) {
1909                         ctrl &= ~UARTCTRL_PE;
1910                         ctrl |= UARTCTRL_M;
1911                 } else {
1912                         ctrl |= UARTCTRL_PE;
1913                         if ((termios->c_cflag & CSIZE) == CS8)
1914                                 ctrl |= UARTCTRL_M;
1915                         if (termios->c_cflag & PARODD)
1916                                 ctrl |= UARTCTRL_PT;
1917                         else
1918                                 ctrl &= ~UARTCTRL_PT;
1919                 }
1920         } else {
1921                 ctrl &= ~UARTCTRL_PE;
1922         }
1923
1924         /* ask the core to calculate the divisor */
1925         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1926
1927         /*
1928          * Need to update the Ring buffer length according to the selected
1929          * baud rate and restart Rx DMA path.
1930          *
1931          * Since timer function acqures sport->port.lock, need to stop before
1932          * acquring same lock because otherwise del_timer_sync() can deadlock.
1933          */
1934         if (old && sport->lpuart_dma_rx_use) {
1935                 del_timer_sync(&sport->lpuart_timer);
1936                 lpuart_dma_rx_free(&sport->port);
1937         }
1938
1939         spin_lock_irqsave(&sport->port.lock, flags);
1940
1941         sport->port.read_status_mask = 0;
1942         if (termios->c_iflag & INPCK)
1943                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
1944         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1945                 sport->port.read_status_mask |= UARTSTAT_FE;
1946
1947         /* characters to ignore */
1948         sport->port.ignore_status_mask = 0;
1949         if (termios->c_iflag & IGNPAR)
1950                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1951         if (termios->c_iflag & IGNBRK) {
1952                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1953                 /*
1954                  * if we're ignoring parity and break indicators,
1955                  * ignore overruns too (for real raw support).
1956                  */
1957                 if (termios->c_iflag & IGNPAR)
1958                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1959         }
1960
1961         /* update the per-port timeout */
1962         uart_update_timeout(port, termios->c_cflag, baud);
1963
1964         /* wait transmit engin complete */
1965         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
1966
1967         /* disable transmit and receive */
1968         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1969                        UARTCTRL);
1970
1971         lpuart32_serial_setbrg(sport, baud);
1972         lpuart32_write(&sport->port, modem, UARTMODIR);
1973         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1974         /* restore control register */
1975
1976         if (old && sport->lpuart_dma_rx_use) {
1977                 if (!lpuart_start_rx_dma(sport))
1978                         rx_dma_timer_init(sport);
1979                 else
1980                         sport->lpuart_dma_rx_use = false;
1981         }
1982
1983         spin_unlock_irqrestore(&sport->port.lock, flags);
1984 }
1985
1986 static const char *lpuart_type(struct uart_port *port)
1987 {
1988         return "FSL_LPUART";
1989 }
1990
1991 static void lpuart_release_port(struct uart_port *port)
1992 {
1993         /* nothing to do */
1994 }
1995
1996 static int lpuart_request_port(struct uart_port *port)
1997 {
1998         return  0;
1999 }
2000
2001 /* configure/autoconfigure the port */
2002 static void lpuart_config_port(struct uart_port *port, int flags)
2003 {
2004         if (flags & UART_CONFIG_TYPE)
2005                 port->type = PORT_LPUART;
2006 }
2007
2008 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2009 {
2010         int ret = 0;
2011
2012         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2013                 ret = -EINVAL;
2014         if (port->irq != ser->irq)
2015                 ret = -EINVAL;
2016         if (ser->io_type != UPIO_MEM)
2017                 ret = -EINVAL;
2018         if (port->uartclk / 16 != ser->baud_base)
2019                 ret = -EINVAL;
2020         if (port->iobase != ser->port)
2021                 ret = -EINVAL;
2022         if (ser->hub6 != 0)
2023                 ret = -EINVAL;
2024         return ret;
2025 }
2026
2027 static const struct uart_ops lpuart_pops = {
2028         .tx_empty       = lpuart_tx_empty,
2029         .set_mctrl      = lpuart_set_mctrl,
2030         .get_mctrl      = lpuart_get_mctrl,
2031         .stop_tx        = lpuart_stop_tx,
2032         .start_tx       = lpuart_start_tx,
2033         .stop_rx        = lpuart_stop_rx,
2034         .break_ctl      = lpuart_break_ctl,
2035         .startup        = lpuart_startup,
2036         .shutdown       = lpuart_shutdown,
2037         .set_termios    = lpuart_set_termios,
2038         .type           = lpuart_type,
2039         .request_port   = lpuart_request_port,
2040         .release_port   = lpuart_release_port,
2041         .config_port    = lpuart_config_port,
2042         .verify_port    = lpuart_verify_port,
2043         .flush_buffer   = lpuart_flush_buffer,
2044 #if defined(CONFIG_CONSOLE_POLL)
2045         .poll_init      = lpuart_poll_init,
2046         .poll_get_char  = lpuart_poll_get_char,
2047         .poll_put_char  = lpuart_poll_put_char,
2048 #endif
2049 };
2050
2051 static const struct uart_ops lpuart32_pops = {
2052         .tx_empty       = lpuart32_tx_empty,
2053         .set_mctrl      = lpuart32_set_mctrl,
2054         .get_mctrl      = lpuart32_get_mctrl,
2055         .stop_tx        = lpuart32_stop_tx,
2056         .start_tx       = lpuart32_start_tx,
2057         .stop_rx        = lpuart32_stop_rx,
2058         .break_ctl      = lpuart32_break_ctl,
2059         .startup        = lpuart32_startup,
2060         .shutdown       = lpuart32_shutdown,
2061         .set_termios    = lpuart32_set_termios,
2062         .type           = lpuart_type,
2063         .request_port   = lpuart_request_port,
2064         .release_port   = lpuart_release_port,
2065         .config_port    = lpuart_config_port,
2066         .verify_port    = lpuart_verify_port,
2067         .flush_buffer   = lpuart_flush_buffer,
2068 #if defined(CONFIG_CONSOLE_POLL)
2069         .poll_init      = lpuart32_poll_init,
2070         .poll_get_char  = lpuart32_poll_get_char,
2071         .poll_put_char  = lpuart32_poll_put_char,
2072 #endif
2073 };
2074
2075 static struct lpuart_port *lpuart_ports[UART_NR];
2076
2077 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2078 static void lpuart_console_putchar(struct uart_port *port, int ch)
2079 {
2080         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2081         writeb(ch, port->membase + UARTDR);
2082 }
2083
2084 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2085 {
2086         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2087         lpuart32_write(port, ch, UARTDATA);
2088 }
2089
2090 static void
2091 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2092 {
2093         struct lpuart_port *sport = lpuart_ports[co->index];
2094         unsigned char  old_cr2, cr2;
2095         unsigned long flags;
2096         int locked = 1;
2097
2098         if (sport->port.sysrq || oops_in_progress)
2099                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2100         else
2101                 spin_lock_irqsave(&sport->port.lock, flags);
2102
2103         /* first save CR2 and then disable interrupts */
2104         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2105         cr2 |= UARTCR2_TE | UARTCR2_RE;
2106         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2107         writeb(cr2, sport->port.membase + UARTCR2);
2108
2109         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2110
2111         /* wait for transmitter finish complete and restore CR2 */
2112         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2113
2114         writeb(old_cr2, sport->port.membase + UARTCR2);
2115
2116         if (locked)
2117                 spin_unlock_irqrestore(&sport->port.lock, flags);
2118 }
2119
2120 static void
2121 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2122 {
2123         struct lpuart_port *sport = lpuart_ports[co->index];
2124         unsigned long  old_cr, cr;
2125         unsigned long flags;
2126         int locked = 1;
2127
2128         if (sport->port.sysrq || oops_in_progress)
2129                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2130         else
2131                 spin_lock_irqsave(&sport->port.lock, flags);
2132
2133         /* first save CR2 and then disable interrupts */
2134         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2135         cr |= UARTCTRL_TE | UARTCTRL_RE;
2136         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2137         lpuart32_write(&sport->port, cr, UARTCTRL);
2138
2139         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2140
2141         /* wait for transmitter finish complete and restore CR2 */
2142         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2143
2144         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2145
2146         if (locked)
2147                 spin_unlock_irqrestore(&sport->port.lock, flags);
2148 }
2149
2150 /*
2151  * if the port was already initialised (eg, by a boot loader),
2152  * try to determine the current setup.
2153  */
2154 static void __init
2155 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2156                            int *parity, int *bits)
2157 {
2158         unsigned char cr, bdh, bdl, brfa;
2159         unsigned int sbr, uartclk, baud_raw;
2160
2161         cr = readb(sport->port.membase + UARTCR2);
2162         cr &= UARTCR2_TE | UARTCR2_RE;
2163         if (!cr)
2164                 return;
2165
2166         /* ok, the port was enabled */
2167
2168         cr = readb(sport->port.membase + UARTCR1);
2169
2170         *parity = 'n';
2171         if (cr & UARTCR1_PE) {
2172                 if (cr & UARTCR1_PT)
2173                         *parity = 'o';
2174                 else
2175                         *parity = 'e';
2176         }
2177
2178         if (cr & UARTCR1_M)
2179                 *bits = 9;
2180         else
2181                 *bits = 8;
2182
2183         bdh = readb(sport->port.membase + UARTBDH);
2184         bdh &= UARTBDH_SBR_MASK;
2185         bdl = readb(sport->port.membase + UARTBDL);
2186         sbr = bdh;
2187         sbr <<= 8;
2188         sbr |= bdl;
2189         brfa = readb(sport->port.membase + UARTCR4);
2190         brfa &= UARTCR4_BRFA_MASK;
2191
2192         uartclk = lpuart_get_baud_clk_rate(sport);
2193         /*
2194          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2195          */
2196         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2197
2198         if (*baud != baud_raw)
2199                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2200                                 "from %d to %d\n", baud_raw, *baud);
2201 }
2202
2203 static void __init
2204 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2205                            int *parity, int *bits)
2206 {
2207         unsigned long cr, bd;
2208         unsigned int sbr, uartclk, baud_raw;
2209
2210         cr = lpuart32_read(&sport->port, UARTCTRL);
2211         cr &= UARTCTRL_TE | UARTCTRL_RE;
2212         if (!cr)
2213                 return;
2214
2215         /* ok, the port was enabled */
2216
2217         cr = lpuart32_read(&sport->port, UARTCTRL);
2218
2219         *parity = 'n';
2220         if (cr & UARTCTRL_PE) {
2221                 if (cr & UARTCTRL_PT)
2222                         *parity = 'o';
2223                 else
2224                         *parity = 'e';
2225         }
2226
2227         if (cr & UARTCTRL_M)
2228                 *bits = 9;
2229         else
2230                 *bits = 8;
2231
2232         bd = lpuart32_read(&sport->port, UARTBAUD);
2233         bd &= UARTBAUD_SBR_MASK;
2234         sbr = bd;
2235         uartclk = lpuart_get_baud_clk_rate(sport);
2236         /*
2237          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2238          */
2239         baud_raw = uartclk / (16 * sbr);
2240
2241         if (*baud != baud_raw)
2242                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2243                                 "from %d to %d\n", baud_raw, *baud);
2244 }
2245
2246 static int __init lpuart_console_setup(struct console *co, char *options)
2247 {
2248         struct lpuart_port *sport;
2249         int baud = 115200;
2250         int bits = 8;
2251         int parity = 'n';
2252         int flow = 'n';
2253
2254         /*
2255          * check whether an invalid uart number has been specified, and
2256          * if so, search for the first available port that does have
2257          * console support.
2258          */
2259         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2260                 co->index = 0;
2261
2262         sport = lpuart_ports[co->index];
2263         if (sport == NULL)
2264                 return -ENODEV;
2265
2266         if (options)
2267                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2268         else
2269                 if (lpuart_is_32(sport))
2270                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2271                 else
2272                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2273
2274         if (lpuart_is_32(sport))
2275                 lpuart32_setup_watermark(sport);
2276         else
2277                 lpuart_setup_watermark(sport);
2278
2279         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2280 }
2281
2282 static struct uart_driver lpuart_reg;
2283 static struct console lpuart_console = {
2284         .name           = DEV_NAME,
2285         .write          = lpuart_console_write,
2286         .device         = uart_console_device,
2287         .setup          = lpuart_console_setup,
2288         .flags          = CON_PRINTBUFFER,
2289         .index          = -1,
2290         .data           = &lpuart_reg,
2291 };
2292
2293 static struct console lpuart32_console = {
2294         .name           = DEV_NAME,
2295         .write          = lpuart32_console_write,
2296         .device         = uart_console_device,
2297         .setup          = lpuart_console_setup,
2298         .flags          = CON_PRINTBUFFER,
2299         .index          = -1,
2300         .data           = &lpuart_reg,
2301 };
2302
2303 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2304 {
2305         struct earlycon_device *dev = con->data;
2306
2307         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2308 }
2309
2310 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2311 {
2312         struct earlycon_device *dev = con->data;
2313
2314         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2315 }
2316
2317 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2318                                           const char *opt)
2319 {
2320         if (!device->port.membase)
2321                 return -ENODEV;
2322
2323         device->con->write = lpuart_early_write;
2324         return 0;
2325 }
2326
2327 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2328                                           const char *opt)
2329 {
2330         if (!device->port.membase)
2331                 return -ENODEV;
2332
2333         device->port.iotype = UPIO_MEM32BE;
2334         device->con->write = lpuart32_early_write;
2335         return 0;
2336 }
2337
2338 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2339                                                    const char *opt)
2340 {
2341         if (!device->port.membase)
2342                 return -ENODEV;
2343
2344         device->port.iotype = UPIO_MEM32;
2345         device->port.membase += IMX_REG_OFF;
2346         device->con->write = lpuart32_early_write;
2347
2348         return 0;
2349 }
2350 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2351 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2352 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2353 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2354 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2355 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2356
2357 #define LPUART_CONSOLE  (&lpuart_console)
2358 #define LPUART32_CONSOLE        (&lpuart32_console)
2359 #else
2360 #define LPUART_CONSOLE  NULL
2361 #define LPUART32_CONSOLE        NULL
2362 #endif
2363
2364 static struct uart_driver lpuart_reg = {
2365         .owner          = THIS_MODULE,
2366         .driver_name    = DRIVER_NAME,
2367         .dev_name       = DEV_NAME,
2368         .nr             = ARRAY_SIZE(lpuart_ports),
2369         .cons           = LPUART_CONSOLE,
2370 };
2371
2372 static int lpuart_probe(struct platform_device *pdev)
2373 {
2374         const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2375                                                            &pdev->dev);
2376         const struct lpuart_soc_data *sdata = of_id->data;
2377         struct device_node *np = pdev->dev.of_node;
2378         struct lpuart_port *sport;
2379         struct resource *res;
2380         int ret;
2381
2382         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2383         if (!sport)
2384                 return -ENOMEM;
2385
2386         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2387         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2388         if (IS_ERR(sport->port.membase))
2389                 return PTR_ERR(sport->port.membase);
2390
2391         sport->port.membase += sdata->reg_off;
2392         sport->port.mapbase = res->start;
2393         sport->port.dev = &pdev->dev;
2394         sport->port.type = PORT_LPUART;
2395         sport->devtype = sdata->devtype;
2396         ret = platform_get_irq(pdev, 0);
2397         if (ret < 0)
2398                 return ret;
2399         sport->port.irq = ret;
2400         sport->port.iotype = sdata->iotype;
2401         if (lpuart_is_32(sport))
2402                 sport->port.ops = &lpuart32_pops;
2403         else
2404                 sport->port.ops = &lpuart_pops;
2405         sport->port.flags = UPF_BOOT_AUTOCONF;
2406
2407         sport->port.rs485_config = lpuart_config_rs485;
2408
2409         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2410         if (IS_ERR(sport->ipg_clk)) {
2411                 ret = PTR_ERR(sport->ipg_clk);
2412                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2413                 return ret;
2414         }
2415
2416         sport->baud_clk = NULL;
2417         if (is_imx8qxp_lpuart(sport)) {
2418                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2419                 if (IS_ERR(sport->baud_clk)) {
2420                         ret = PTR_ERR(sport->baud_clk);
2421                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2422                         return ret;
2423                 }
2424         }
2425
2426         ret = of_alias_get_id(np, "serial");
2427         if (ret < 0) {
2428                 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2429                 if (ret < 0) {
2430                         dev_err(&pdev->dev, "port line is full, add device failed\n");
2431                         return ret;
2432                 }
2433                 sport->id_allocated = true;
2434         }
2435         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2436                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2437                 ret = -EINVAL;
2438                 goto failed_out_of_range;
2439         }
2440         sport->port.line = ret;
2441
2442         ret = lpuart_enable_clks(sport);
2443         if (ret)
2444                 goto failed_clock_enable;
2445         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2446
2447         lpuart_ports[sport->port.line] = sport;
2448
2449         platform_set_drvdata(pdev, &sport->port);
2450
2451         if (lpuart_is_32(sport)) {
2452                 lpuart_reg.cons = LPUART32_CONSOLE;
2453                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2454                                         DRIVER_NAME, sport);
2455         } else {
2456                 lpuart_reg.cons = LPUART_CONSOLE;
2457                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2458                                         DRIVER_NAME, sport);
2459         }
2460
2461         if (ret)
2462                 goto failed_irq_request;
2463
2464         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2465         if (ret)
2466                 goto failed_attach_port;
2467
2468         uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2469
2470         if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2471                 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2472
2473         if (sport->port.rs485.delay_rts_before_send ||
2474             sport->port.rs485.delay_rts_after_send)
2475                 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2476
2477         lpuart_config_rs485(&sport->port, &sport->port.rs485);
2478
2479         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2480         if (!sport->dma_tx_chan)
2481                 dev_info(sport->port.dev, "DMA tx channel request failed, "
2482                                 "operating without tx DMA\n");
2483
2484         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2485         if (!sport->dma_rx_chan)
2486                 dev_info(sport->port.dev, "DMA rx channel request failed, "
2487                                 "operating without rx DMA\n");
2488
2489         return 0;
2490
2491 failed_attach_port:
2492 failed_irq_request:
2493         lpuart_disable_clks(sport);
2494 failed_clock_enable:
2495 failed_out_of_range:
2496         if (sport->id_allocated)
2497                 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2498         return ret;
2499 }
2500
2501 static int lpuart_remove(struct platform_device *pdev)
2502 {
2503         struct lpuart_port *sport = platform_get_drvdata(pdev);
2504
2505         uart_remove_one_port(&lpuart_reg, &sport->port);
2506
2507         if (sport->id_allocated)
2508                 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2509
2510         lpuart_disable_clks(sport);
2511
2512         if (sport->dma_tx_chan)
2513                 dma_release_channel(sport->dma_tx_chan);
2514
2515         if (sport->dma_rx_chan)
2516                 dma_release_channel(sport->dma_rx_chan);
2517
2518         return 0;
2519 }
2520
2521 #ifdef CONFIG_PM_SLEEP
2522 static int lpuart_suspend(struct device *dev)
2523 {
2524         struct lpuart_port *sport = dev_get_drvdata(dev);
2525         unsigned long temp;
2526         bool irq_wake;
2527
2528         if (lpuart_is_32(sport)) {
2529                 /* disable Rx/Tx and interrupts */
2530                 temp = lpuart32_read(&sport->port, UARTCTRL);
2531                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2532                 lpuart32_write(&sport->port, temp, UARTCTRL);
2533         } else {
2534                 /* disable Rx/Tx and interrupts */
2535                 temp = readb(sport->port.membase + UARTCR2);
2536                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2537                 writeb(temp, sport->port.membase + UARTCR2);
2538         }
2539
2540         uart_suspend_port(&lpuart_reg, &sport->port);
2541
2542         /* uart_suspend_port() might set wakeup flag */
2543         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2544
2545         if (sport->lpuart_dma_rx_use) {
2546                 /*
2547                  * EDMA driver during suspend will forcefully release any
2548                  * non-idle DMA channels. If port wakeup is enabled or if port
2549                  * is console port or 'no_console_suspend' is set the Rx DMA
2550                  * cannot resume as as expected, hence gracefully release the
2551                  * Rx DMA path before suspend and start Rx DMA path on resume.
2552                  */
2553                 if (irq_wake) {
2554                         del_timer_sync(&sport->lpuart_timer);
2555                         lpuart_dma_rx_free(&sport->port);
2556                 }
2557
2558                 /* Disable Rx DMA to use UART port as wakeup source */
2559                 if (lpuart_is_32(sport)) {
2560                         temp = lpuart32_read(&sport->port, UARTBAUD);
2561                         lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2562                                        UARTBAUD);
2563                 } else {
2564                         writeb(readb(sport->port.membase + UARTCR5) &
2565                                ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2566                 }
2567         }
2568
2569         if (sport->lpuart_dma_tx_use) {
2570                 sport->dma_tx_in_progress = false;
2571                 dmaengine_terminate_all(sport->dma_tx_chan);
2572         }
2573
2574         if (sport->port.suspended && !irq_wake)
2575                 lpuart_disable_clks(sport);
2576
2577         return 0;
2578 }
2579
2580 static int lpuart_resume(struct device *dev)
2581 {
2582         struct lpuart_port *sport = dev_get_drvdata(dev);
2583         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2584
2585         if (sport->port.suspended && !irq_wake)
2586                 lpuart_enable_clks(sport);
2587
2588         if (lpuart_is_32(sport))
2589                 lpuart32_setup_watermark_enable(sport);
2590         else
2591                 lpuart_setup_watermark_enable(sport);
2592
2593         if (sport->lpuart_dma_rx_use) {
2594                 if (irq_wake) {
2595                         if (!lpuart_start_rx_dma(sport))
2596                                 rx_dma_timer_init(sport);
2597                         else
2598                                 sport->lpuart_dma_rx_use = false;
2599                 }
2600         }
2601
2602         lpuart_tx_dma_startup(sport);
2603
2604         if (lpuart_is_32(sport))
2605                 lpuart32_configure(sport);
2606
2607         uart_resume_port(&lpuart_reg, &sport->port);
2608
2609         return 0;
2610 }
2611 #endif
2612
2613 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2614
2615 static struct platform_driver lpuart_driver = {
2616         .probe          = lpuart_probe,
2617         .remove         = lpuart_remove,
2618         .driver         = {
2619                 .name   = "fsl-lpuart",
2620                 .of_match_table = lpuart_dt_ids,
2621                 .pm     = &lpuart_pm_ops,
2622         },
2623 };
2624
2625 static int __init lpuart_serial_init(void)
2626 {
2627         int ret = uart_register_driver(&lpuart_reg);
2628
2629         if (ret)
2630                 return ret;
2631
2632         ret = platform_driver_register(&lpuart_driver);
2633         if (ret)
2634                 uart_unregister_driver(&lpuart_reg);
2635
2636         return ret;
2637 }
2638
2639 static void __exit lpuart_serial_exit(void)
2640 {
2641         ida_destroy(&fsl_lpuart_ida);
2642         platform_driver_unregister(&lpuart_driver);
2643         uart_unregister_driver(&lpuart_reg);
2644 }
2645
2646 module_init(lpuart_serial_init);
2647 module_exit(lpuart_serial_exit);
2648
2649 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2650 MODULE_LICENSE("GPL v2");