1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type PCI serial ports.
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
22 #include <asm/byteorder.h>
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
33 struct pci_serial_quirk {
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
51 #define PCI_NUM_BAR_RESOURCES 6
53 struct serial_private {
56 struct pci_serial_quirk *quirk;
57 const struct pciserial_board *board;
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
71 static int pci_default_setup(struct serial_private*,
72 const struct pciserial_board*, struct uart_8250_port *, int);
74 static void moan_device(const char *str, struct pci_dev *dev)
78 "Please send the output of lspci -vv, this\n"
79 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
80 "manufacturer and name of serial board or\n"
81 "modem board to <linux-serial@vger.kernel.org>.\n",
82 pci_name(dev), str, dev->vendor, dev->device,
83 dev->subsystem_vendor, dev->subsystem_device);
87 setup_port(struct serial_private *priv, struct uart_8250_port *port,
88 int bar, int offset, int regshift)
90 struct pci_dev *dev = priv->dev;
92 if (bar >= PCI_NUM_BAR_RESOURCES)
95 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
96 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
99 port->port.iotype = UPIO_MEM;
100 port->port.iobase = 0;
101 port->port.mapbase = pci_resource_start(dev, bar) + offset;
102 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
103 port->port.regshift = regshift;
105 port->port.iotype = UPIO_PORT;
106 port->port.iobase = pci_resource_start(dev, bar) + offset;
107 port->port.mapbase = 0;
108 port->port.membase = NULL;
109 port->port.regshift = 0;
115 * ADDI-DATA GmbH communication cards <info@addi-data.com>
117 static int addidata_apci7800_setup(struct serial_private *priv,
118 const struct pciserial_board *board,
119 struct uart_8250_port *port, int idx)
121 unsigned int bar = 0, offset = board->first_offset;
122 bar = FL_GET_BASE(board->flags);
125 offset += idx * board->uart_offset;
126 } else if ((idx >= 2) && (idx < 4)) {
128 offset += ((idx - 2) * board->uart_offset);
129 } else if ((idx >= 4) && (idx < 6)) {
131 offset += ((idx - 4) * board->uart_offset);
132 } else if (idx >= 6) {
134 offset += ((idx - 6) * board->uart_offset);
137 return setup_port(priv, port, bar, offset, board->reg_shift);
141 * AFAVLAB uses a different mixture of BARs and offsets
142 * Not that ugly ;) -- HW
145 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
146 struct uart_8250_port *port, int idx)
148 unsigned int bar, offset = board->first_offset;
150 bar = FL_GET_BASE(board->flags);
155 offset += (idx - 4) * board->uart_offset;
158 return setup_port(priv, port, bar, offset, board->reg_shift);
162 * HP's Remote Management Console. The Diva chip came in several
163 * different versions. N-class, L2000 and A500 have two Diva chips, each
164 * with 3 UARTs (the third UART on the second chip is unused). Superdome
165 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
166 * one Diva chip, but it has been expanded to 5 UARTs.
168 static int pci_hp_diva_init(struct pci_dev *dev)
172 switch (dev->subsystem_device) {
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
174 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
175 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
176 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
182 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
185 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
186 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
195 * HP's Diva chip puts the 4th/5th serial port further out, and
196 * some serial ports are supposed to be hidden on certain models.
199 pci_hp_diva_setup(struct serial_private *priv,
200 const struct pciserial_board *board,
201 struct uart_8250_port *port, int idx)
203 unsigned int offset = board->first_offset;
204 unsigned int bar = FL_GET_BASE(board->flags);
206 switch (priv->dev->subsystem_device) {
207 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
211 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
221 offset += idx * board->uart_offset;
223 return setup_port(priv, port, bar, offset, board->reg_shift);
227 * Added for EKF Intel i960 serial boards
229 static int pci_inteli960ni_init(struct pci_dev *dev)
233 if (!(dev->subsystem_device & 0x1000))
236 /* is firmware started? */
237 pci_read_config_dword(dev, 0x44, &oldval);
238 if (oldval == 0x00001000L) { /* RESET value */
239 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
246 * Some PCI serial cards using the PLX 9050 PCI interface chip require
247 * that the card interrupt be explicitly enabled or disabled. This
248 * seems to be mainly needed on card using the PLX which also use I/O
251 static int pci_plx9050_init(struct pci_dev *dev)
256 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
257 moan_device("no memory in bar 0", dev);
262 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
263 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
266 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
267 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
269 * As the megawolf cards have the int pins active
270 * high, and have 2 UART chips, both ints must be
271 * enabled on the 9050. Also, the UARTS are set in
272 * 16450 mode by default, so we have to enable the
273 * 16C950 'enhanced' mode so that we can use the
278 * enable/disable interrupts
280 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
283 writel(irq_config, p + 0x4c);
286 * Read the register back to ensure that it took effect.
294 static void pci_plx9050_exit(struct pci_dev *dev)
298 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
304 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
309 * Read the register back to ensure that it took effect.
316 #define NI8420_INT_ENABLE_REG 0x38
317 #define NI8420_INT_ENABLE_BIT 0x2000
319 static void pci_ni8420_exit(struct pci_dev *dev)
322 unsigned int bar = 0;
324 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
325 moan_device("no memory in bar", dev);
329 p = pci_ioremap_bar(dev, bar);
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348 static void pci_ni8430_exit(struct pci_dev *dev)
351 unsigned int bar = 0;
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
358 p = pci_ioremap_bar(dev, bar);
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_8250_port *port, int idx)
372 unsigned int bar, offset = board->first_offset;
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return setup_port(priv, port, bar, offset, board->reg_shift);
389 * This does initialization for PMC OCTALPRO cards:
390 * maps the device memory, resets the UARTs (needed, bc
391 * if the module is removed and inserted again, the card
392 * is in the sleep mode) and enables global interrupt.
395 /* global control register offset for SBS PMC-OctalPro */
396 #define OCT_REG_CR_OFF 0x500
398 static int sbs_init(struct pci_dev *dev)
402 p = pci_ioremap_bar(dev, 0);
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
409 writeb(0x0, p + OCT_REG_CR_OFF);
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
419 * Disables the global interrupt of PMC-OctalPro
422 static void sbs_exit(struct pci_dev *dev)
426 p = pci_ioremap_bar(dev, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 writeb(0, p + OCT_REG_CR_OFF);
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equipped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 * Note: some SIIG cards are probed by the parport_serial object.
460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463 static int pci_siig10x_init(struct pci_dev *dev)
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 default: /* 1S1P, 4S */
480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484 writew(readw(p + 0x28) & data, p + 0x28);
490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493 static int pci_siig20x_init(struct pci_dev *dev)
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
510 static int pci_siig_init(struct pci_dev *dev)
512 unsigned int type = dev->device & 0xff00;
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
519 moan_device("Unknown SIIG card", dev);
523 static int pci_siig_setup(struct serial_private *priv,
524 const struct pciserial_board *board,
525 struct uart_8250_port *port, int idx)
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531 offset = (idx - 4) * 8;
534 return setup_port(priv, port, bar, offset, 0);
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
542 static const unsigned short timedia_single_port[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 static const unsigned short timedia_dual_port[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 static const unsigned short timedia_quad_port[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 static const unsigned short timedia_eight_port[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 static const struct timedia_struct {
568 const unsigned short *ids;
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
573 { 8, timedia_eight_port }
577 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
578 * listing them individually, this driver merely grabs them all with
579 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
580 * and should be left free to be claimed by parport_serial instead.
582 static int pci_timedia_probe(struct pci_dev *dev)
585 * Check the third digit of the subdevice ID
586 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 "ignoring Timedia subdevice %04x for parport_serial\n",
591 dev->subsystem_device);
598 static int pci_timedia_init(struct pci_dev *dev)
600 const unsigned short *ids;
603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
604 ids = timedia_data[i].ids;
605 for (j = 0; ids[j]; j++)
606 if (dev->subsystem_device == ids[j])
607 return timedia_data[i].num;
613 * Timedia/SUNIX uses a mixture of BARs and offsets
614 * Ugh, this is ugly as all hell --- TYT
617 pci_timedia_setup(struct serial_private *priv,
618 const struct pciserial_board *board,
619 struct uart_8250_port *port, int idx)
621 unsigned int bar = 0, offset = board->first_offset;
628 offset = board->uart_offset;
635 offset = board->uart_offset;
644 return setup_port(priv, port, bar, offset, board->reg_shift);
648 * Some Titan cards are also a little weird
651 titan_400l_800l_setup(struct serial_private *priv,
652 const struct pciserial_board *board,
653 struct uart_8250_port *port, int idx)
655 unsigned int bar, offset = board->first_offset;
666 offset = (idx - 2) * board->uart_offset;
669 return setup_port(priv, port, bar, offset, board->reg_shift);
672 static int pci_xircom_init(struct pci_dev *dev)
678 static int pci_ni8420_init(struct pci_dev *dev)
681 unsigned int bar = 0;
683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
684 moan_device("no memory in bar", dev);
688 p = pci_ioremap_bar(dev, bar);
692 /* Enable CPU Interrupt */
693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
694 p + NI8420_INT_ENABLE_REG);
700 #define MITE_IOWBSR1_WSIZE 0xa
701 #define MITE_IOWBSR1_WIN_OFFSET 0x800
702 #define MITE_IOWBSR1_WENAB (1 << 7)
703 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
707 static int pci_ni8430_init(struct pci_dev *dev)
710 struct pci_bus_region region;
712 unsigned int bar = 0;
714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
715 moan_device("no memory in bar", dev);
719 p = pci_ioremap_bar(dev, bar);
724 * Set device window address and size in BAR0, while acknowledging that
725 * the resource structure may contain a translated address that differs
726 * from the address the device responds to.
728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
731 writel(device_window, p + MITE_IOWBSR1);
733 /* Set window access to go to RAMSEL IO address space */
734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 /* Enable IO Bus Interrupt 0 */
738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
740 /* Enable CPU Interrupt */
741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
747 /* UART Port Control Register */
748 #define NI8430_PORTCON 0x0f
749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752 pci_ni8430_setup(struct serial_private *priv,
753 const struct pciserial_board *board,
754 struct uart_8250_port *port, int idx)
756 struct pci_dev *dev = priv->dev;
758 unsigned int bar, offset = board->first_offset;
760 if (idx >= board->num_ports)
763 bar = FL_GET_BASE(board->flags);
764 offset += idx * board->uart_offset;
766 p = pci_ioremap_bar(dev, bar);
770 /* enable the transceiver */
771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
772 p + offset + NI8430_PORTCON);
776 return setup_port(priv, port, bar, offset, board->reg_shift);
779 static int pci_netmos_9900_setup(struct serial_private *priv,
780 const struct pciserial_board *board,
781 struct uart_8250_port *port, int idx)
785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
786 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
787 /* netmos apparently orders BARs by datasheet layout, so serial
788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
792 return setup_port(priv, port, bar, 0, board->reg_shift);
794 return pci_default_setup(priv, board, port, idx);
798 /* the 99xx series comes with a range of device IDs and a variety
801 * 9900 has varying capabilities and can cascade to sub-controllers
802 * (cascading should be purely internal)
803 * 9904 is hardwired with 4 serial ports
804 * 9912 and 9922 are hardwired with 2 serial ports
806 static int pci_netmos_9900_numports(struct pci_dev *dev)
808 unsigned int c = dev->class;
810 unsigned short sub_serports;
817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
818 /* two possibilities: 0x30ps encodes number of parallel and
819 * serial ports, or 0x1000 indicates *something*. This is not
820 * immediately obvious, since the 2s1p+4s configuration seems
821 * to offer all functionality on functions 0..2, while still
822 * advertising the same function 3 as the 4s+2s1p config.
824 sub_serports = dev->subsystem_device & 0xf;
825 if (sub_serports > 0)
829 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
833 moan_device("unknown NetMos/Mostech program interface", dev);
837 static int pci_netmos_init(struct pci_dev *dev)
839 /* subdevice 0x00PS means <P> parallel, <S> serial */
840 unsigned int num_serial = dev->subsystem_device & 0xf;
842 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
843 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
847 dev->subsystem_device == 0x0299)
850 switch (dev->device) { /* FALLTHROUGH on all */
851 case PCI_DEVICE_ID_NETMOS_9904:
852 case PCI_DEVICE_ID_NETMOS_9912:
853 case PCI_DEVICE_ID_NETMOS_9922:
854 case PCI_DEVICE_ID_NETMOS_9900:
855 num_serial = pci_netmos_9900_numports(dev);
862 if (num_serial == 0) {
863 moan_device("unknown NetMos/Mostech device", dev);
871 * These chips are available with optionally one parallel port and up to
872 * two serial ports. Unfortunately they all have the same product id.
874 * Basic configuration is done over a region of 32 I/O ports. The base
875 * ioport is called INTA or INTC, depending on docs/other drivers.
877 * The region of the 32 I/O ports is configured in POSIO0R...
881 #define ITE_887x_MISCR 0x9c
882 #define ITE_887x_INTCBAR 0x78
883 #define ITE_887x_UARTBAR 0x7c
884 #define ITE_887x_PS0BAR 0x10
885 #define ITE_887x_POSIO0 0x60
888 #define ITE_887x_IOSIZE 32
889 /* I/O space size (bits 26-24; 8 bytes = 011b) */
890 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
891 /* I/O space size (bits 26-24; 32 bytes = 101b) */
892 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
893 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
894 #define ITE_887x_POSIO_SPEED (3 << 29)
895 /* enable IO_Space bit */
896 #define ITE_887x_POSIO_ENABLE (1 << 31)
898 static int pci_ite887x_init(struct pci_dev *dev)
900 /* inta_addr are the configuration addresses of the ITE */
901 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 struct resource *iobase = NULL;
905 u32 miscr, uartbar, ioport;
907 /* search for the base-ioport */
909 while (inta_addr[i] && iobase == NULL) {
910 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 if (iobase != NULL) {
913 /* write POSIO0R - speed | size | ioport */
914 pci_write_config_dword(dev, ITE_887x_POSIO0,
915 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
916 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
917 /* write INTCBAR - ioport */
918 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 ret = inb(inta_addr[i]);
922 /* ioport connected */
925 release_region(iobase->start, ITE_887x_IOSIZE);
932 dev_err(&dev->dev, "ite887x: could not find iobase\n");
936 /* start of undocumented type checking (see parport_pc.c) */
937 type = inb(iobase->start + 0x18) & 0x0f;
940 case 0x2: /* ITE8871 (1P) */
941 case 0xa: /* ITE8875 (1P) */
944 case 0xe: /* ITE8872 (2S1P) */
947 case 0x6: /* ITE8873 (1S) */
950 case 0x8: /* ITE8874 (2S) */
954 moan_device("Unknown ITE887x", dev);
958 /* configure all serial ports */
959 for (i = 0; i < ret; i++) {
960 /* read the I/O port from the device */
961 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 ioport &= 0x0000FF00; /* the actual base address */
964 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
965 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
966 ITE_887x_POSIO_IOSIZE_8 | ioport);
968 /* write the ioport to the UARTBAR */
969 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
970 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
971 uartbar |= (ioport << (16 * i)); /* set the ioport */
972 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974 /* get current config */
975 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
976 /* disable interrupts (UARTx_Routing[3:0]) */
977 miscr &= ~(0xf << (12 - 4 * i));
978 /* activate the UART (UARTx_En) */
979 miscr |= 1 << (23 - i);
980 /* write new config with activated UART */
981 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
985 /* the device has no UARTs if we get here */
986 release_region(iobase->start, ITE_887x_IOSIZE);
992 static void pci_ite887x_exit(struct pci_dev *dev)
995 /* the ioport is bit 0-15 in POSIO0R */
996 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 release_region(ioport, ITE_887x_IOSIZE);
1002 * EndRun Technologies.
1003 * Determine the number of ports available on the device.
1005 #define PCI_VENDOR_ID_ENDRUN 0x7401
1006 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1008 static int pci_endrun_init(struct pci_dev *dev)
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1014 /* EndRun device is all 0xexxx */
1015 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1016 (dev->device & 0xf000) != 0xe000)
1019 p = pci_iomap(dev, 0, 5);
1023 deviceID = ioread32(p);
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1028 "%d ports detected on EndRun PCI Express device\n",
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1036 * Oxford Semiconductor Inc.
1037 * Check that device is part of the Tornado range of devices, then determine
1038 * the number of ports available on the device.
1040 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1043 unsigned long deviceID;
1044 unsigned int number_uarts = 0;
1046 /* OxSemi Tornado devices are all 0xCxxx */
1047 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1048 (dev->device & 0xF000) != 0xC000)
1051 p = pci_iomap(dev, 0, 5);
1055 deviceID = ioread32(p);
1056 /* Tornado device */
1057 if (deviceID == 0x07000200) {
1058 number_uarts = ioread8(p + 4);
1060 "%d ports detected on Oxford PCI Express device\n",
1063 pci_iounmap(dev, p);
1064 return number_uarts;
1067 static int pci_asix_setup(struct serial_private *priv,
1068 const struct pciserial_board *board,
1069 struct uart_8250_port *port, int idx)
1071 port->bugs |= UART_BUG_PARITY;
1072 return pci_default_setup(priv, board, port, idx);
1075 /* Quatech devices have their own extra interface features */
1077 struct quatech_feature {
1082 #define QPCR_TEST_FOR1 0x3F
1083 #define QPCR_TEST_GET1 0x00
1084 #define QPCR_TEST_FOR2 0x40
1085 #define QPCR_TEST_GET2 0x40
1086 #define QPCR_TEST_FOR3 0x80
1087 #define QPCR_TEST_GET3 0x40
1088 #define QPCR_TEST_FOR4 0xC0
1089 #define QPCR_TEST_GET4 0x80
1091 #define QOPR_CLOCK_X1 0x0000
1092 #define QOPR_CLOCK_X2 0x0001
1093 #define QOPR_CLOCK_X4 0x0002
1094 #define QOPR_CLOCK_X8 0x0003
1095 #define QOPR_CLOCK_RATE_MASK 0x0003
1098 static struct quatech_feature quatech_cards[] = {
1099 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1102 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1104 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1105 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1106 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1107 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1108 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1109 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1110 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1111 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1112 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1113 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1114 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1115 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1116 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1117 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1121 static int pci_quatech_amcc(u16 devid)
1123 struct quatech_feature *qf = &quatech_cards[0];
1125 if (qf->devid == devid)
1129 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1133 static int pci_quatech_rqopr(struct uart_8250_port *port)
1135 unsigned long base = port->port.iobase;
1138 LCR = inb(base + UART_LCR);
1139 outb(0xBF, base + UART_LCR);
1140 val = inb(base + UART_SCR);
1141 outb(LCR, base + UART_LCR);
1145 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1147 unsigned long base = port->port.iobase;
1150 LCR = inb(base + UART_LCR);
1151 outb(0xBF, base + UART_LCR);
1152 inb(base + UART_SCR);
1153 outb(qopr, base + UART_SCR);
1154 outb(LCR, base + UART_LCR);
1157 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1159 unsigned long base = port->port.iobase;
1162 LCR = inb(base + UART_LCR);
1163 outb(0xBF, base + UART_LCR);
1164 val = inb(base + UART_SCR);
1165 outb(val | 0x10, base + UART_SCR);
1166 qmcr = inb(base + UART_MCR);
1167 outb(val, base + UART_SCR);
1168 outb(LCR, base + UART_LCR);
1173 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1175 unsigned long base = port->port.iobase;
1178 LCR = inb(base + UART_LCR);
1179 outb(0xBF, base + UART_LCR);
1180 val = inb(base + UART_SCR);
1181 outb(val | 0x10, base + UART_SCR);
1182 outb(qmcr, base + UART_MCR);
1183 outb(val, base + UART_SCR);
1184 outb(LCR, base + UART_LCR);
1187 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1189 unsigned long base = port->port.iobase;
1192 LCR = inb(base + UART_LCR);
1193 outb(0xBF, base + UART_LCR);
1194 val = inb(base + UART_SCR);
1196 outb(0x80, UART_LCR);
1197 if (!(inb(UART_SCR) & 0x20)) {
1198 outb(LCR, base + UART_LCR);
1205 static int pci_quatech_test(struct uart_8250_port *port)
1209 qopr = pci_quatech_rqopr(port);
1210 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET1)
1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1215 reg = pci_quatech_rqopr(port) & 0xC0;
1216 if (reg != QPCR_TEST_GET2)
1218 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1219 reg = pci_quatech_rqopr(port) & 0xC0;
1220 if (reg != QPCR_TEST_GET3)
1222 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1223 reg = pci_quatech_rqopr(port) & 0xC0;
1224 if (reg != QPCR_TEST_GET4)
1227 pci_quatech_wqopr(port, qopr);
1231 static int pci_quatech_clock(struct uart_8250_port *port)
1234 unsigned long clock;
1236 if (pci_quatech_test(port) < 0)
1239 qopr = pci_quatech_rqopr(port);
1241 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (reg & QOPR_CLOCK_X8) {
1247 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1248 reg = pci_quatech_rqopr(port);
1249 if (!(reg & QOPR_CLOCK_X8)) {
1253 reg &= QOPR_CLOCK_X8;
1254 if (reg == QOPR_CLOCK_X2) {
1256 set = QOPR_CLOCK_X2;
1257 } else if (reg == QOPR_CLOCK_X4) {
1259 set = QOPR_CLOCK_X4;
1260 } else if (reg == QOPR_CLOCK_X8) {
1262 set = QOPR_CLOCK_X8;
1265 set = QOPR_CLOCK_X1;
1267 qopr &= ~QOPR_CLOCK_RATE_MASK;
1271 pci_quatech_wqopr(port, qopr);
1275 static int pci_quatech_rs422(struct uart_8250_port *port)
1280 if (!pci_quatech_has_qmcr(port))
1282 qmcr = pci_quatech_rqmcr(port);
1283 pci_quatech_wqmcr(port, 0xFF);
1284 if (pci_quatech_rqmcr(port))
1286 pci_quatech_wqmcr(port, qmcr);
1290 static int pci_quatech_init(struct pci_dev *dev)
1292 if (pci_quatech_amcc(dev->device)) {
1293 unsigned long base = pci_resource_start(dev, 0);
1297 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1298 tmp = inl(base + 0x3c);
1299 outl(tmp | 0x01000000, base + 0x3c);
1300 outl(tmp &= ~0x01000000, base + 0x3c);
1306 static int pci_quatech_setup(struct serial_private *priv,
1307 const struct pciserial_board *board,
1308 struct uart_8250_port *port, int idx)
1310 /* Needed by pci_quatech calls below */
1311 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1312 /* Set up the clocking */
1313 port->port.uartclk = pci_quatech_clock(port);
1314 /* For now just warn about RS422 */
1315 if (pci_quatech_rs422(port))
1316 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1317 return pci_default_setup(priv, board, port, idx);
1320 static void pci_quatech_exit(struct pci_dev *dev)
1324 static int pci_default_setup(struct serial_private *priv,
1325 const struct pciserial_board *board,
1326 struct uart_8250_port *port, int idx)
1328 unsigned int bar, offset = board->first_offset, maxnr;
1330 bar = FL_GET_BASE(board->flags);
1331 if (board->flags & FL_BASE_BARS)
1334 offset += idx * board->uart_offset;
1336 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1337 (board->reg_shift + 3);
1339 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1342 return setup_port(priv, port, bar, offset, board->reg_shift);
1345 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1346 unsigned int quot, unsigned int quot_frac)
1353 for (scr = 5 ; scr <= 15 ; scr++) {
1354 actual_baud = 921600 * 16 / scr;
1355 tolerance = actual_baud / 50;
1357 if ((baud < actual_baud + tolerance) &&
1358 (baud > actual_baud - tolerance)) {
1360 lcr = serial_port_in(port, UART_LCR);
1361 serial_port_out(port, UART_LCR, lcr | 0x80);
1363 serial_port_out(port, UART_DLL, 1);
1364 serial_port_out(port, UART_DLM, 0);
1365 serial_port_out(port, 2, 16 - scr);
1366 serial_port_out(port, UART_LCR, lcr);
1368 } else if (baud > actual_baud) {
1372 serial8250_do_set_divisor(port, baud, quot, quot_frac);
1374 static int pci_pericom_setup(struct serial_private *priv,
1375 const struct pciserial_board *board,
1376 struct uart_8250_port *port, int idx)
1378 unsigned int bar, offset = board->first_offset, maxnr;
1380 bar = FL_GET_BASE(board->flags);
1381 if (board->flags & FL_BASE_BARS)
1384 offset += idx * board->uart_offset;
1387 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1388 (board->reg_shift + 3);
1390 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1393 port->port.set_divisor = pericom_do_set_divisor;
1395 return setup_port(priv, port, bar, offset, board->reg_shift);
1398 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1399 const struct pciserial_board *board,
1400 struct uart_8250_port *port, int idx)
1402 unsigned int bar, offset = board->first_offset, maxnr;
1404 bar = FL_GET_BASE(board->flags);
1405 if (board->flags & FL_BASE_BARS)
1408 offset += idx * board->uart_offset;
1413 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1414 (board->reg_shift + 3);
1416 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1419 port->port.set_divisor = pericom_do_set_divisor;
1421 return setup_port(priv, port, bar, offset, board->reg_shift);
1425 ce4100_serial_setup(struct serial_private *priv,
1426 const struct pciserial_board *board,
1427 struct uart_8250_port *port, int idx)
1431 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1432 port->port.iotype = UPIO_MEM32;
1433 port->port.type = PORT_XSCALE;
1434 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1435 port->port.regshift = 2;
1441 pci_omegapci_setup(struct serial_private *priv,
1442 const struct pciserial_board *board,
1443 struct uart_8250_port *port, int idx)
1445 return setup_port(priv, port, 2, idx * 8, 0);
1449 pci_brcm_trumanage_setup(struct serial_private *priv,
1450 const struct pciserial_board *board,
1451 struct uart_8250_port *port, int idx)
1453 int ret = pci_default_setup(priv, board, port, idx);
1455 port->port.type = PORT_BRCM_TRUMANAGE;
1456 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1460 /* RTS will control by MCR if this bit is 0 */
1461 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1462 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1463 #define FINTEK_RTS_INVERT BIT(5)
1465 /* We should do proper H/W transceiver setting before change to RS485 mode */
1466 static int pci_fintek_rs485_config(struct uart_port *port,
1467 struct serial_rs485 *rs485)
1469 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1471 u8 *index = (u8 *) port->private_data;
1473 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1476 rs485 = &port->rs485;
1477 else if (rs485->flags & SER_RS485_ENABLED)
1478 memset(rs485->padding, 0, sizeof(rs485->padding));
1480 memset(rs485, 0, sizeof(*rs485));
1482 /* F81504/508/512 not support RTS delay before or after send */
1483 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1485 if (rs485->flags & SER_RS485_ENABLED) {
1486 /* Enable RTS H/W control mode */
1487 setting |= FINTEK_RTS_CONTROL_BY_HW;
1489 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1490 /* RTS driving high on TX */
1491 setting &= ~FINTEK_RTS_INVERT;
1493 /* RTS driving low on TX */
1494 setting |= FINTEK_RTS_INVERT;
1497 rs485->delay_rts_after_send = 0;
1498 rs485->delay_rts_before_send = 0;
1500 /* Disable RTS H/W control mode */
1501 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1504 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1506 if (rs485 != &port->rs485)
1507 port->rs485 = *rs485;
1512 static int pci_fintek_setup(struct serial_private *priv,
1513 const struct pciserial_board *board,
1514 struct uart_8250_port *port, int idx)
1516 struct pci_dev *pdev = priv->dev;
1521 config_base = 0x40 + 0x08 * idx;
1523 /* Get the io address from configuration space */
1524 pci_read_config_word(pdev, config_base + 4, &iobase);
1526 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1528 port->port.iotype = UPIO_PORT;
1529 port->port.iobase = iobase;
1530 port->port.rs485_config = pci_fintek_rs485_config;
1532 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1536 /* preserve index in PCI configuration space */
1538 port->port.private_data = data;
1543 static int pci_fintek_init(struct pci_dev *dev)
1545 unsigned long iobase;
1547 resource_size_t bar_data[3];
1549 struct serial_private *priv = pci_get_drvdata(dev);
1550 struct uart_8250_port *port;
1552 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1553 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1554 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1557 switch (dev->device) {
1558 case 0x1104: /* 4 ports */
1559 case 0x1108: /* 8 ports */
1560 max_port = dev->device & 0xff;
1562 case 0x1112: /* 12 ports */
1569 /* Get the io address dispatch from the BIOS */
1570 bar_data[0] = pci_resource_start(dev, 5);
1571 bar_data[1] = pci_resource_start(dev, 4);
1572 bar_data[2] = pci_resource_start(dev, 3);
1574 for (i = 0; i < max_port; ++i) {
1575 /* UART0 configuration offset start from 0x40 */
1576 config_base = 0x40 + 0x08 * i;
1578 /* Calculate Real IO Port */
1579 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1581 /* Enable UART I/O port */
1582 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1584 /* Select 128-byte FIFO and 8x FIFO threshold */
1585 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1588 pci_write_config_byte(dev, config_base + 0x04,
1589 (u8)(iobase & 0xff));
1592 pci_write_config_byte(dev, config_base + 0x05,
1593 (u8)((iobase & 0xff00) >> 8));
1595 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1598 /* re-apply RS232/485 mode when
1599 * pciserial_resume_ports()
1601 port = serial8250_get_port(priv->line[i]);
1602 pci_fintek_rs485_config(&port->port, NULL);
1604 /* First init without port data
1605 * force init to RS232 Mode
1607 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1614 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1616 struct f815xxa_data *data = p->private_data;
1617 unsigned long flags;
1619 spin_lock_irqsave(&data->lock, flags);
1620 writeb(value, p->membase + offset);
1621 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1622 spin_unlock_irqrestore(&data->lock, flags);
1625 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1626 const struct pciserial_board *board,
1627 struct uart_8250_port *port, int idx)
1629 struct pci_dev *pdev = priv->dev;
1630 struct f815xxa_data *data;
1632 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1637 spin_lock_init(&data->lock);
1639 port->port.private_data = data;
1640 port->port.iotype = UPIO_MEM;
1641 port->port.flags |= UPF_IOREMAP;
1642 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1643 port->port.serial_out = f815xxa_mem_serial_out;
1648 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1653 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1656 switch (dev->device) {
1657 case 0x1204: /* 4 ports */
1658 case 0x1208: /* 8 ports */
1659 max_port = dev->device & 0xff;
1661 case 0x1212: /* 12 ports */
1668 /* Set to mmio decode */
1669 pci_write_config_byte(dev, 0x209, 0x40);
1671 for (i = 0; i < max_port; ++i) {
1672 /* UART0 configuration offset start from 0x2A0 */
1673 config_base = 0x2A0 + 0x08 * i;
1675 /* Select 128-byte FIFO and 8x FIFO threshold */
1676 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1678 /* Enable UART I/O port */
1679 pci_write_config_byte(dev, config_base + 0, 0x01);
1685 static int skip_tx_en_setup(struct serial_private *priv,
1686 const struct pciserial_board *board,
1687 struct uart_8250_port *port, int idx)
1689 port->port.quirks |= UPQ_NO_TXEN_TEST;
1690 dev_dbg(&priv->dev->dev,
1691 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1692 priv->dev->vendor, priv->dev->device,
1693 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1695 return pci_default_setup(priv, board, port, idx);
1698 static void kt_handle_break(struct uart_port *p)
1700 struct uart_8250_port *up = up_to_u8250p(p);
1702 * On receipt of a BI, serial device in Intel ME (Intel
1703 * management engine) needs to have its fifos cleared for sane
1704 * SOL (Serial Over Lan) output.
1706 serial8250_clear_and_reinit_fifos(up);
1709 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1711 struct uart_8250_port *up = up_to_u8250p(p);
1715 * When the Intel ME (management engine) gets reset its serial
1716 * port registers could return 0 momentarily. Functions like
1717 * serial8250_console_write, read and save the IER, perform
1718 * some operation and then restore it. In order to avoid
1719 * setting IER register inadvertently to 0, if the value read
1720 * is 0, double check with ier value in uart_8250_port and use
1721 * that instead. up->ier should be the same value as what is
1722 * currently configured.
1724 val = inb(p->iobase + offset);
1725 if (offset == UART_IER) {
1732 static int kt_serial_setup(struct serial_private *priv,
1733 const struct pciserial_board *board,
1734 struct uart_8250_port *port, int idx)
1736 port->port.flags |= UPF_BUG_THRE;
1737 port->port.serial_in = kt_serial_in;
1738 port->port.handle_break = kt_handle_break;
1739 return skip_tx_en_setup(priv, board, port, idx);
1742 static int pci_eg20t_init(struct pci_dev *dev)
1744 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1752 pci_wch_ch353_setup(struct serial_private *priv,
1753 const struct pciserial_board *board,
1754 struct uart_8250_port *port, int idx)
1756 port->port.flags |= UPF_FIXED_TYPE;
1757 port->port.type = PORT_16550A;
1758 return pci_default_setup(priv, board, port, idx);
1762 pci_wch_ch355_setup(struct serial_private *priv,
1763 const struct pciserial_board *board,
1764 struct uart_8250_port *port, int idx)
1766 port->port.flags |= UPF_FIXED_TYPE;
1767 port->port.type = PORT_16550A;
1768 return pci_default_setup(priv, board, port, idx);
1772 pci_wch_ch38x_setup(struct serial_private *priv,
1773 const struct pciserial_board *board,
1774 struct uart_8250_port *port, int idx)
1776 port->port.flags |= UPF_FIXED_TYPE;
1777 port->port.type = PORT_16850;
1778 return pci_default_setup(priv, board, port, idx);
1782 pci_sunix_setup(struct serial_private *priv,
1783 const struct pciserial_board *board,
1784 struct uart_8250_port *port, int idx)
1789 port->port.flags |= UPF_FIXED_TYPE;
1790 port->port.type = PORT_SUNIX;
1794 offset = idx * board->uart_offset;
1798 idx = div_s64_rem(idx, 4, &offset);
1799 offset = idx * 64 + offset * board->uart_offset;
1802 return setup_port(priv, port, bar, offset, 0);
1806 pci_moxa_setup(struct serial_private *priv,
1807 const struct pciserial_board *board,
1808 struct uart_8250_port *port, int idx)
1810 unsigned int bar = FL_GET_BASE(board->flags);
1813 if (board->num_ports == 4 && idx == 3)
1814 offset = 7 * board->uart_offset;
1816 offset = idx * board->uart_offset;
1818 return setup_port(priv, port, bar, offset, 0);
1821 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1822 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1823 #define PCI_DEVICE_ID_OCTPRO 0x0001
1824 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1825 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1826 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1827 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1828 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1829 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1830 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1831 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1832 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1833 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1834 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1835 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1836 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1837 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1838 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1839 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1840 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1841 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1842 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1843 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1844 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1845 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1846 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1847 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1848 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1849 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1850 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1851 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1852 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1853 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1854 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1855 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1856 #define PCI_VENDOR_ID_WCH 0x4348
1857 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1858 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1859 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1860 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1861 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1862 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1863 #define PCI_VENDOR_ID_AGESTAR 0x5372
1864 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1865 #define PCI_VENDOR_ID_ASIX 0x9710
1866 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1867 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1869 #define PCIE_VENDOR_ID_WCH 0x1c00
1870 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1871 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1872 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1874 #define PCI_VENDOR_ID_ACCESIO 0x494f
1875 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1876 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1877 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1878 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1879 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1880 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1881 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1882 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1883 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1884 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1885 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1886 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1887 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1888 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1889 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1890 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1892 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1893 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1894 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1898 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1899 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1900 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1901 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1902 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1903 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1904 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1906 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1910 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1911 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1912 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1913 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1914 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1915 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1916 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1917 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1918 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1919 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1920 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1921 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1923 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1924 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1925 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1928 * Master list of serial port init/setup/exit quirks.
1929 * This does not describe the general nature of the port.
1930 * (ie, baud base, number and location of ports, etc)
1932 * This list is ordered alphabetically by vendor then device.
1933 * Specific entries must come before more generic entries.
1935 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1937 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1940 .vendor = PCI_VENDOR_ID_AMCC,
1941 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1942 .subvendor = PCI_ANY_ID,
1943 .subdevice = PCI_ANY_ID,
1944 .setup = addidata_apci7800_setup,
1947 * AFAVLAB cards - these may be called via parport_serial
1948 * It is not clear whether this applies to all products.
1951 .vendor = PCI_VENDOR_ID_AFAVLAB,
1952 .device = PCI_ANY_ID,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .setup = afavlab_setup,
1961 .vendor = PCI_VENDOR_ID_HP,
1962 .device = PCI_DEVICE_ID_HP_DIVA,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .init = pci_hp_diva_init,
1966 .setup = pci_hp_diva_setup,
1972 .vendor = PCI_VENDOR_ID_INTEL,
1973 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1974 .subvendor = 0xe4bf,
1975 .subdevice = PCI_ANY_ID,
1976 .init = pci_inteli960ni_init,
1977 .setup = pci_default_setup,
1980 .vendor = PCI_VENDOR_ID_INTEL,
1981 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1982 .subvendor = PCI_ANY_ID,
1983 .subdevice = PCI_ANY_ID,
1984 .setup = skip_tx_en_setup,
1987 .vendor = PCI_VENDOR_ID_INTEL,
1988 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1989 .subvendor = PCI_ANY_ID,
1990 .subdevice = PCI_ANY_ID,
1991 .setup = skip_tx_en_setup,
1994 .vendor = PCI_VENDOR_ID_INTEL,
1995 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = skip_tx_en_setup,
2001 .vendor = PCI_VENDOR_ID_INTEL,
2002 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .setup = ce4100_serial_setup,
2008 .vendor = PCI_VENDOR_ID_INTEL,
2009 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = kt_serial_setup,
2018 .vendor = PCI_VENDOR_ID_ITE,
2019 .device = PCI_DEVICE_ID_ITE_8872,
2020 .subvendor = PCI_ANY_ID,
2021 .subdevice = PCI_ANY_ID,
2022 .init = pci_ite887x_init,
2023 .setup = pci_default_setup,
2024 .exit = pci_ite887x_exit,
2027 * National Instruments
2030 .vendor = PCI_VENDOR_ID_NI,
2031 .device = PCI_DEVICE_ID_NI_PCI23216,
2032 .subvendor = PCI_ANY_ID,
2033 .subdevice = PCI_ANY_ID,
2034 .init = pci_ni8420_init,
2035 .setup = pci_default_setup,
2036 .exit = pci_ni8420_exit,
2039 .vendor = PCI_VENDOR_ID_NI,
2040 .device = PCI_DEVICE_ID_NI_PCI2328,
2041 .subvendor = PCI_ANY_ID,
2042 .subdevice = PCI_ANY_ID,
2043 .init = pci_ni8420_init,
2044 .setup = pci_default_setup,
2045 .exit = pci_ni8420_exit,
2048 .vendor = PCI_VENDOR_ID_NI,
2049 .device = PCI_DEVICE_ID_NI_PCI2324,
2050 .subvendor = PCI_ANY_ID,
2051 .subdevice = PCI_ANY_ID,
2052 .init = pci_ni8420_init,
2053 .setup = pci_default_setup,
2054 .exit = pci_ni8420_exit,
2057 .vendor = PCI_VENDOR_ID_NI,
2058 .device = PCI_DEVICE_ID_NI_PCI2322,
2059 .subvendor = PCI_ANY_ID,
2060 .subdevice = PCI_ANY_ID,
2061 .init = pci_ni8420_init,
2062 .setup = pci_default_setup,
2063 .exit = pci_ni8420_exit,
2066 .vendor = PCI_VENDOR_ID_NI,
2067 .device = PCI_DEVICE_ID_NI_PCI2324I,
2068 .subvendor = PCI_ANY_ID,
2069 .subdevice = PCI_ANY_ID,
2070 .init = pci_ni8420_init,
2071 .setup = pci_default_setup,
2072 .exit = pci_ni8420_exit,
2075 .vendor = PCI_VENDOR_ID_NI,
2076 .device = PCI_DEVICE_ID_NI_PCI2322I,
2077 .subvendor = PCI_ANY_ID,
2078 .subdevice = PCI_ANY_ID,
2079 .init = pci_ni8420_init,
2080 .setup = pci_default_setup,
2081 .exit = pci_ni8420_exit,
2084 .vendor = PCI_VENDOR_ID_NI,
2085 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2086 .subvendor = PCI_ANY_ID,
2087 .subdevice = PCI_ANY_ID,
2088 .init = pci_ni8420_init,
2089 .setup = pci_default_setup,
2090 .exit = pci_ni8420_exit,
2093 .vendor = PCI_VENDOR_ID_NI,
2094 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .init = pci_ni8420_init,
2098 .setup = pci_default_setup,
2099 .exit = pci_ni8420_exit,
2102 .vendor = PCI_VENDOR_ID_NI,
2103 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2104 .subvendor = PCI_ANY_ID,
2105 .subdevice = PCI_ANY_ID,
2106 .init = pci_ni8420_init,
2107 .setup = pci_default_setup,
2108 .exit = pci_ni8420_exit,
2111 .vendor = PCI_VENDOR_ID_NI,
2112 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2113 .subvendor = PCI_ANY_ID,
2114 .subdevice = PCI_ANY_ID,
2115 .init = pci_ni8420_init,
2116 .setup = pci_default_setup,
2117 .exit = pci_ni8420_exit,
2120 .vendor = PCI_VENDOR_ID_NI,
2121 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2122 .subvendor = PCI_ANY_ID,
2123 .subdevice = PCI_ANY_ID,
2124 .init = pci_ni8420_init,
2125 .setup = pci_default_setup,
2126 .exit = pci_ni8420_exit,
2129 .vendor = PCI_VENDOR_ID_NI,
2130 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .init = pci_ni8420_init,
2134 .setup = pci_default_setup,
2135 .exit = pci_ni8420_exit,
2138 .vendor = PCI_VENDOR_ID_NI,
2139 .device = PCI_ANY_ID,
2140 .subvendor = PCI_ANY_ID,
2141 .subdevice = PCI_ANY_ID,
2142 .init = pci_ni8430_init,
2143 .setup = pci_ni8430_setup,
2144 .exit = pci_ni8430_exit,
2148 .vendor = PCI_VENDOR_ID_QUATECH,
2149 .device = PCI_ANY_ID,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .init = pci_quatech_init,
2153 .setup = pci_quatech_setup,
2154 .exit = pci_quatech_exit,
2160 .vendor = PCI_VENDOR_ID_PANACOM,
2161 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2162 .subvendor = PCI_ANY_ID,
2163 .subdevice = PCI_ANY_ID,
2164 .init = pci_plx9050_init,
2165 .setup = pci_default_setup,
2166 .exit = pci_plx9050_exit,
2169 .vendor = PCI_VENDOR_ID_PANACOM,
2170 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .init = pci_plx9050_init,
2174 .setup = pci_default_setup,
2175 .exit = pci_plx9050_exit,
2178 * Pericom (Only 7954 - It have a offset jump for port 4)
2181 .vendor = PCI_VENDOR_ID_PERICOM,
2182 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .setup = pci_pericom_setup_four_at_eight,
2191 .vendor = PCI_VENDOR_ID_PLX,
2192 .device = PCI_DEVICE_ID_PLX_9050,
2193 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2194 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2195 .init = pci_plx9050_init,
2196 .setup = pci_default_setup,
2197 .exit = pci_plx9050_exit,
2200 .vendor = PCI_VENDOR_ID_PLX,
2201 .device = PCI_DEVICE_ID_PLX_9050,
2202 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2203 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2204 .init = pci_plx9050_init,
2205 .setup = pci_default_setup,
2206 .exit = pci_plx9050_exit,
2209 .vendor = PCI_VENDOR_ID_PLX,
2210 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2211 .subvendor = PCI_VENDOR_ID_PLX,
2212 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2213 .init = pci_plx9050_init,
2214 .setup = pci_default_setup,
2215 .exit = pci_plx9050_exit,
2218 .vendor = PCI_VENDOR_ID_ACCESIO,
2219 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .setup = pci_pericom_setup_four_at_eight,
2225 .vendor = PCI_VENDOR_ID_ACCESIO,
2226 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2227 .subvendor = PCI_ANY_ID,
2228 .subdevice = PCI_ANY_ID,
2229 .setup = pci_pericom_setup_four_at_eight,
2232 .vendor = PCI_VENDOR_ID_ACCESIO,
2233 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .setup = pci_pericom_setup_four_at_eight,
2239 .vendor = PCI_VENDOR_ID_ACCESIO,
2240 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2241 .subvendor = PCI_ANY_ID,
2242 .subdevice = PCI_ANY_ID,
2243 .setup = pci_pericom_setup_four_at_eight,
2246 .vendor = PCI_VENDOR_ID_ACCESIO,
2247 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2248 .subvendor = PCI_ANY_ID,
2249 .subdevice = PCI_ANY_ID,
2250 .setup = pci_pericom_setup_four_at_eight,
2253 .vendor = PCI_VENDOR_ID_ACCESIO,
2254 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .setup = pci_pericom_setup_four_at_eight,
2260 .vendor = PCI_VENDOR_ID_ACCESIO,
2261 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2262 .subvendor = PCI_ANY_ID,
2263 .subdevice = PCI_ANY_ID,
2264 .setup = pci_pericom_setup_four_at_eight,
2267 .vendor = PCI_VENDOR_ID_ACCESIO,
2268 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .setup = pci_pericom_setup_four_at_eight,
2274 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2275 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2276 .subvendor = PCI_ANY_ID,
2277 .subdevice = PCI_ANY_ID,
2278 .setup = pci_pericom_setup_four_at_eight,
2281 .vendor = PCI_VENDOR_ID_ACCESIO,
2282 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2283 .subvendor = PCI_ANY_ID,
2284 .subdevice = PCI_ANY_ID,
2285 .setup = pci_pericom_setup_four_at_eight,
2288 .vendor = PCI_VENDOR_ID_ACCESIO,
2289 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2290 .subvendor = PCI_ANY_ID,
2291 .subdevice = PCI_ANY_ID,
2292 .setup = pci_pericom_setup_four_at_eight,
2295 .vendor = PCI_VENDOR_ID_ACCESIO,
2296 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2297 .subvendor = PCI_ANY_ID,
2298 .subdevice = PCI_ANY_ID,
2299 .setup = pci_pericom_setup_four_at_eight,
2302 .vendor = PCI_VENDOR_ID_ACCESIO,
2303 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .setup = pci_pericom_setup_four_at_eight,
2309 .vendor = PCI_VENDOR_ID_ACCESIO,
2310 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2311 .subvendor = PCI_ANY_ID,
2312 .subdevice = PCI_ANY_ID,
2313 .setup = pci_pericom_setup_four_at_eight,
2316 .vendor = PCI_VENDOR_ID_ACCESIO,
2317 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .setup = pci_pericom_setup_four_at_eight,
2323 .vendor = PCI_VENDOR_ID_ACCESIO,
2324 .device = PCI_ANY_ID,
2325 .subvendor = PCI_ANY_ID,
2326 .subdevice = PCI_ANY_ID,
2327 .setup = pci_pericom_setup,
2329 * SBS Technologies, Inc., PMC-OCTALPRO 232
2332 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2333 .device = PCI_DEVICE_ID_OCTPRO,
2334 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2335 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2341 * SBS Technologies, Inc., PMC-OCTALPRO 422
2344 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2345 .device = PCI_DEVICE_ID_OCTPRO,
2346 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2347 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2353 * SBS Technologies, Inc., P-Octal 232
2356 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2357 .device = PCI_DEVICE_ID_OCTPRO,
2358 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2359 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2365 * SBS Technologies, Inc., P-Octal 422
2368 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2369 .device = PCI_DEVICE_ID_OCTPRO,
2370 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2371 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2377 * SIIG cards - these may be called via parport_serial
2380 .vendor = PCI_VENDOR_ID_SIIG,
2381 .device = PCI_ANY_ID,
2382 .subvendor = PCI_ANY_ID,
2383 .subdevice = PCI_ANY_ID,
2384 .init = pci_siig_init,
2385 .setup = pci_siig_setup,
2391 .vendor = PCI_VENDOR_ID_TITAN,
2392 .device = PCI_DEVICE_ID_TITAN_400L,
2393 .subvendor = PCI_ANY_ID,
2394 .subdevice = PCI_ANY_ID,
2395 .setup = titan_400l_800l_setup,
2398 .vendor = PCI_VENDOR_ID_TITAN,
2399 .device = PCI_DEVICE_ID_TITAN_800L,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .setup = titan_400l_800l_setup,
2408 .vendor = PCI_VENDOR_ID_TIMEDIA,
2409 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2410 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2411 .subdevice = PCI_ANY_ID,
2412 .probe = pci_timedia_probe,
2413 .init = pci_timedia_init,
2414 .setup = pci_timedia_setup,
2417 .vendor = PCI_VENDOR_ID_TIMEDIA,
2418 .device = PCI_ANY_ID,
2419 .subvendor = PCI_ANY_ID,
2420 .subdevice = PCI_ANY_ID,
2421 .setup = pci_timedia_setup,
2424 * Sunix PCI serial boards
2427 .vendor = PCI_VENDOR_ID_SUNIX,
2428 .device = PCI_DEVICE_ID_SUNIX_1999,
2429 .subvendor = PCI_VENDOR_ID_SUNIX,
2430 .subdevice = PCI_ANY_ID,
2431 .setup = pci_sunix_setup,
2437 .vendor = PCI_VENDOR_ID_XIRCOM,
2438 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .init = pci_xircom_init,
2442 .setup = pci_default_setup,
2445 * Netmos cards - these may be called via parport_serial
2448 .vendor = PCI_VENDOR_ID_NETMOS,
2449 .device = PCI_ANY_ID,
2450 .subvendor = PCI_ANY_ID,
2451 .subdevice = PCI_ANY_ID,
2452 .init = pci_netmos_init,
2453 .setup = pci_netmos_9900_setup,
2456 * EndRun Technologies
2459 .vendor = PCI_VENDOR_ID_ENDRUN,
2460 .device = PCI_ANY_ID,
2461 .subvendor = PCI_ANY_ID,
2462 .subdevice = PCI_ANY_ID,
2463 .init = pci_endrun_init,
2464 .setup = pci_default_setup,
2467 * For Oxford Semiconductor Tornado based devices
2470 .vendor = PCI_VENDOR_ID_OXSEMI,
2471 .device = PCI_ANY_ID,
2472 .subvendor = PCI_ANY_ID,
2473 .subdevice = PCI_ANY_ID,
2474 .init = pci_oxsemi_tornado_init,
2475 .setup = pci_default_setup,
2478 .vendor = PCI_VENDOR_ID_MAINPINE,
2479 .device = PCI_ANY_ID,
2480 .subvendor = PCI_ANY_ID,
2481 .subdevice = PCI_ANY_ID,
2482 .init = pci_oxsemi_tornado_init,
2483 .setup = pci_default_setup,
2486 .vendor = PCI_VENDOR_ID_DIGI,
2487 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2488 .subvendor = PCI_SUBVENDOR_ID_IBM,
2489 .subdevice = PCI_ANY_ID,
2490 .init = pci_oxsemi_tornado_init,
2491 .setup = pci_default_setup,
2494 .vendor = PCI_VENDOR_ID_INTEL,
2496 .subvendor = PCI_ANY_ID,
2497 .subdevice = PCI_ANY_ID,
2498 .init = pci_eg20t_init,
2499 .setup = pci_default_setup,
2502 .vendor = PCI_VENDOR_ID_INTEL,
2504 .subvendor = PCI_ANY_ID,
2505 .subdevice = PCI_ANY_ID,
2506 .init = pci_eg20t_init,
2507 .setup = pci_default_setup,
2510 .vendor = PCI_VENDOR_ID_INTEL,
2512 .subvendor = PCI_ANY_ID,
2513 .subdevice = PCI_ANY_ID,
2514 .init = pci_eg20t_init,
2515 .setup = pci_default_setup,
2518 .vendor = PCI_VENDOR_ID_INTEL,
2520 .subvendor = PCI_ANY_ID,
2521 .subdevice = PCI_ANY_ID,
2522 .init = pci_eg20t_init,
2523 .setup = pci_default_setup,
2528 .subvendor = PCI_ANY_ID,
2529 .subdevice = PCI_ANY_ID,
2530 .init = pci_eg20t_init,
2531 .setup = pci_default_setup,
2536 .subvendor = PCI_ANY_ID,
2537 .subdevice = PCI_ANY_ID,
2538 .init = pci_eg20t_init,
2539 .setup = pci_default_setup,
2544 .subvendor = PCI_ANY_ID,
2545 .subdevice = PCI_ANY_ID,
2546 .init = pci_eg20t_init,
2547 .setup = pci_default_setup,
2552 .subvendor = PCI_ANY_ID,
2553 .subdevice = PCI_ANY_ID,
2554 .init = pci_eg20t_init,
2555 .setup = pci_default_setup,
2560 .subvendor = PCI_ANY_ID,
2561 .subdevice = PCI_ANY_ID,
2562 .init = pci_eg20t_init,
2563 .setup = pci_default_setup,
2566 * Cronyx Omega PCI (PLX-chip based)
2569 .vendor = PCI_VENDOR_ID_PLX,
2570 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2571 .subvendor = PCI_ANY_ID,
2572 .subdevice = PCI_ANY_ID,
2573 .setup = pci_omegapci_setup,
2575 /* WCH CH353 1S1P card (16550 clone) */
2577 .vendor = PCI_VENDOR_ID_WCH,
2578 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2579 .subvendor = PCI_ANY_ID,
2580 .subdevice = PCI_ANY_ID,
2581 .setup = pci_wch_ch353_setup,
2583 /* WCH CH353 2S1P card (16550 clone) */
2585 .vendor = PCI_VENDOR_ID_WCH,
2586 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2587 .subvendor = PCI_ANY_ID,
2588 .subdevice = PCI_ANY_ID,
2589 .setup = pci_wch_ch353_setup,
2591 /* WCH CH353 4S card (16550 clone) */
2593 .vendor = PCI_VENDOR_ID_WCH,
2594 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2595 .subvendor = PCI_ANY_ID,
2596 .subdevice = PCI_ANY_ID,
2597 .setup = pci_wch_ch353_setup,
2599 /* WCH CH353 2S1PF card (16550 clone) */
2601 .vendor = PCI_VENDOR_ID_WCH,
2602 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
2605 .setup = pci_wch_ch353_setup,
2607 /* WCH CH352 2S card (16550 clone) */
2609 .vendor = PCI_VENDOR_ID_WCH,
2610 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2611 .subvendor = PCI_ANY_ID,
2612 .subdevice = PCI_ANY_ID,
2613 .setup = pci_wch_ch353_setup,
2615 /* WCH CH355 4S card (16550 clone) */
2617 .vendor = PCI_VENDOR_ID_WCH,
2618 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2619 .subvendor = PCI_ANY_ID,
2620 .subdevice = PCI_ANY_ID,
2621 .setup = pci_wch_ch355_setup,
2623 /* WCH CH382 2S card (16850 clone) */
2625 .vendor = PCIE_VENDOR_ID_WCH,
2626 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2627 .subvendor = PCI_ANY_ID,
2628 .subdevice = PCI_ANY_ID,
2629 .setup = pci_wch_ch38x_setup,
2631 /* WCH CH382 2S1P card (16850 clone) */
2633 .vendor = PCIE_VENDOR_ID_WCH,
2634 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2635 .subvendor = PCI_ANY_ID,
2636 .subdevice = PCI_ANY_ID,
2637 .setup = pci_wch_ch38x_setup,
2639 /* WCH CH384 4S card (16850 clone) */
2641 .vendor = PCIE_VENDOR_ID_WCH,
2642 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .setup = pci_wch_ch38x_setup,
2648 * ASIX devices with FIFO bug
2651 .vendor = PCI_VENDOR_ID_ASIX,
2652 .device = PCI_ANY_ID,
2653 .subvendor = PCI_ANY_ID,
2654 .subdevice = PCI_ANY_ID,
2655 .setup = pci_asix_setup,
2658 * Broadcom TruManage (NetXtreme)
2661 .vendor = PCI_VENDOR_ID_BROADCOM,
2662 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2663 .subvendor = PCI_ANY_ID,
2664 .subdevice = PCI_ANY_ID,
2665 .setup = pci_brcm_trumanage_setup,
2670 .subvendor = PCI_ANY_ID,
2671 .subdevice = PCI_ANY_ID,
2672 .setup = pci_fintek_setup,
2673 .init = pci_fintek_init,
2678 .subvendor = PCI_ANY_ID,
2679 .subdevice = PCI_ANY_ID,
2680 .setup = pci_fintek_setup,
2681 .init = pci_fintek_init,
2686 .subvendor = PCI_ANY_ID,
2687 .subdevice = PCI_ANY_ID,
2688 .setup = pci_fintek_setup,
2689 .init = pci_fintek_init,
2695 .vendor = PCI_VENDOR_ID_MOXA,
2696 .device = PCI_ANY_ID,
2697 .subvendor = PCI_ANY_ID,
2698 .subdevice = PCI_ANY_ID,
2699 .setup = pci_moxa_setup,
2704 .subvendor = PCI_ANY_ID,
2705 .subdevice = PCI_ANY_ID,
2706 .setup = pci_fintek_f815xxa_setup,
2707 .init = pci_fintek_f815xxa_init,
2712 .subvendor = PCI_ANY_ID,
2713 .subdevice = PCI_ANY_ID,
2714 .setup = pci_fintek_f815xxa_setup,
2715 .init = pci_fintek_f815xxa_init,
2720 .subvendor = PCI_ANY_ID,
2721 .subdevice = PCI_ANY_ID,
2722 .setup = pci_fintek_f815xxa_setup,
2723 .init = pci_fintek_f815xxa_init,
2727 * Default "match everything" terminator entry
2730 .vendor = PCI_ANY_ID,
2731 .device = PCI_ANY_ID,
2732 .subvendor = PCI_ANY_ID,
2733 .subdevice = PCI_ANY_ID,
2734 .setup = pci_default_setup,
2738 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2740 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2743 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2745 struct pci_serial_quirk *quirk;
2747 for (quirk = pci_serial_quirks; ; quirk++)
2748 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2749 quirk_id_matches(quirk->device, dev->device) &&
2750 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2751 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2756 static inline int get_pci_irq(struct pci_dev *dev,
2757 const struct pciserial_board *board)
2759 if (board->flags & FL_NOIRQ)
2766 * This is the configuration table for all of the PCI serial boards
2767 * which we support. It is directly indexed by the pci_board_num_t enum
2768 * value, which is encoded in the pci_device_id PCI probe table's
2769 * driver_data member.
2771 * The makeup of these names are:
2772 * pbn_bn{_bt}_n_baud{_offsetinhex}
2774 * bn = PCI BAR number
2775 * bt = Index using PCI BARs
2776 * n = number of serial ports
2778 * offsetinhex = offset for each sequential port (in hex)
2780 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2782 * Please note: in theory if n = 1, _bt infix should make no difference.
2783 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2785 enum pci_board_num_t {
2879 * Board-specific versions.
2885 pbn_endrun_2_4000000,
2887 pbn_oxsemi_1_4000000,
2888 pbn_oxsemi_2_4000000,
2889 pbn_oxsemi_4_4000000,
2890 pbn_oxsemi_8_4000000,
2902 pbn_ADDIDATA_PCIe_1_3906250,
2903 pbn_ADDIDATA_PCIe_2_3906250,
2904 pbn_ADDIDATA_PCIe_4_3906250,
2905 pbn_ADDIDATA_PCIe_8_3906250,
2906 pbn_ce4100_1_115200,
2908 pbn_NETMOS9900_2s_115200,
2918 pbn_pericom_PI7C9X7951,
2919 pbn_pericom_PI7C9X7952,
2920 pbn_pericom_PI7C9X7954,
2921 pbn_pericom_PI7C9X7958,
2933 * uart_offset - the space between channels
2934 * reg_shift - describes how the UART registers are mapped
2935 * to PCI memory by the card.
2936 * For example IER register on SBS, Inc. PMC-OctPro is located at
2937 * offset 0x10 from the UART base, while UART_IER is defined as 1
2938 * in include/linux/serial_reg.h,
2939 * see first lines of serial_in() and serial_out() in 8250.c
2942 static struct pciserial_board pci_boards[] = {
2946 .base_baud = 115200,
2949 [pbn_b0_1_115200] = {
2952 .base_baud = 115200,
2955 [pbn_b0_2_115200] = {
2958 .base_baud = 115200,
2961 [pbn_b0_4_115200] = {
2964 .base_baud = 115200,
2967 [pbn_b0_5_115200] = {
2970 .base_baud = 115200,
2973 [pbn_b0_8_115200] = {
2976 .base_baud = 115200,
2979 [pbn_b0_1_921600] = {
2982 .base_baud = 921600,
2985 [pbn_b0_2_921600] = {
2988 .base_baud = 921600,
2991 [pbn_b0_4_921600] = {
2994 .base_baud = 921600,
2998 [pbn_b0_2_1130000] = {
3001 .base_baud = 1130000,
3005 [pbn_b0_4_1152000] = {
3008 .base_baud = 1152000,
3012 [pbn_b0_4_1250000] = {
3015 .base_baud = 1250000,
3019 [pbn_b0_2_1843200] = {
3022 .base_baud = 1843200,
3025 [pbn_b0_4_1843200] = {
3028 .base_baud = 1843200,
3032 [pbn_b0_1_4000000] = {
3035 .base_baud = 4000000,
3039 [pbn_b0_bt_1_115200] = {
3040 .flags = FL_BASE0|FL_BASE_BARS,
3042 .base_baud = 115200,
3045 [pbn_b0_bt_2_115200] = {
3046 .flags = FL_BASE0|FL_BASE_BARS,
3048 .base_baud = 115200,
3051 [pbn_b0_bt_4_115200] = {
3052 .flags = FL_BASE0|FL_BASE_BARS,
3054 .base_baud = 115200,
3057 [pbn_b0_bt_8_115200] = {
3058 .flags = FL_BASE0|FL_BASE_BARS,
3060 .base_baud = 115200,
3064 [pbn_b0_bt_1_460800] = {
3065 .flags = FL_BASE0|FL_BASE_BARS,
3067 .base_baud = 460800,
3070 [pbn_b0_bt_2_460800] = {
3071 .flags = FL_BASE0|FL_BASE_BARS,
3073 .base_baud = 460800,
3076 [pbn_b0_bt_4_460800] = {
3077 .flags = FL_BASE0|FL_BASE_BARS,
3079 .base_baud = 460800,
3083 [pbn_b0_bt_1_921600] = {
3084 .flags = FL_BASE0|FL_BASE_BARS,
3086 .base_baud = 921600,
3089 [pbn_b0_bt_2_921600] = {
3090 .flags = FL_BASE0|FL_BASE_BARS,
3092 .base_baud = 921600,
3095 [pbn_b0_bt_4_921600] = {
3096 .flags = FL_BASE0|FL_BASE_BARS,
3098 .base_baud = 921600,
3101 [pbn_b0_bt_8_921600] = {
3102 .flags = FL_BASE0|FL_BASE_BARS,
3104 .base_baud = 921600,
3108 [pbn_b1_1_115200] = {
3111 .base_baud = 115200,
3114 [pbn_b1_2_115200] = {
3117 .base_baud = 115200,
3120 [pbn_b1_4_115200] = {
3123 .base_baud = 115200,
3126 [pbn_b1_8_115200] = {
3129 .base_baud = 115200,
3132 [pbn_b1_16_115200] = {
3135 .base_baud = 115200,
3139 [pbn_b1_1_921600] = {
3142 .base_baud = 921600,
3145 [pbn_b1_2_921600] = {
3148 .base_baud = 921600,
3151 [pbn_b1_4_921600] = {
3154 .base_baud = 921600,
3157 [pbn_b1_8_921600] = {
3160 .base_baud = 921600,
3163 [pbn_b1_2_1250000] = {
3166 .base_baud = 1250000,
3170 [pbn_b1_bt_1_115200] = {
3171 .flags = FL_BASE1|FL_BASE_BARS,
3173 .base_baud = 115200,
3176 [pbn_b1_bt_2_115200] = {
3177 .flags = FL_BASE1|FL_BASE_BARS,
3179 .base_baud = 115200,
3182 [pbn_b1_bt_4_115200] = {
3183 .flags = FL_BASE1|FL_BASE_BARS,
3185 .base_baud = 115200,
3189 [pbn_b1_bt_2_921600] = {
3190 .flags = FL_BASE1|FL_BASE_BARS,
3192 .base_baud = 921600,
3196 [pbn_b1_1_1382400] = {
3199 .base_baud = 1382400,
3202 [pbn_b1_2_1382400] = {
3205 .base_baud = 1382400,
3208 [pbn_b1_4_1382400] = {
3211 .base_baud = 1382400,
3214 [pbn_b1_8_1382400] = {
3217 .base_baud = 1382400,
3221 [pbn_b2_1_115200] = {
3224 .base_baud = 115200,
3227 [pbn_b2_2_115200] = {
3230 .base_baud = 115200,
3233 [pbn_b2_4_115200] = {
3236 .base_baud = 115200,
3239 [pbn_b2_8_115200] = {
3242 .base_baud = 115200,
3246 [pbn_b2_1_460800] = {
3249 .base_baud = 460800,
3252 [pbn_b2_4_460800] = {
3255 .base_baud = 460800,
3258 [pbn_b2_8_460800] = {
3261 .base_baud = 460800,
3264 [pbn_b2_16_460800] = {
3267 .base_baud = 460800,
3271 [pbn_b2_1_921600] = {
3274 .base_baud = 921600,
3277 [pbn_b2_4_921600] = {
3280 .base_baud = 921600,
3283 [pbn_b2_8_921600] = {
3286 .base_baud = 921600,
3290 [pbn_b2_8_1152000] = {
3293 .base_baud = 1152000,
3297 [pbn_b2_bt_1_115200] = {
3298 .flags = FL_BASE2|FL_BASE_BARS,
3300 .base_baud = 115200,
3303 [pbn_b2_bt_2_115200] = {
3304 .flags = FL_BASE2|FL_BASE_BARS,
3306 .base_baud = 115200,
3309 [pbn_b2_bt_4_115200] = {
3310 .flags = FL_BASE2|FL_BASE_BARS,
3312 .base_baud = 115200,
3316 [pbn_b2_bt_2_921600] = {
3317 .flags = FL_BASE2|FL_BASE_BARS,
3319 .base_baud = 921600,
3322 [pbn_b2_bt_4_921600] = {
3323 .flags = FL_BASE2|FL_BASE_BARS,
3325 .base_baud = 921600,
3329 [pbn_b3_2_115200] = {
3332 .base_baud = 115200,
3335 [pbn_b3_4_115200] = {
3338 .base_baud = 115200,
3341 [pbn_b3_8_115200] = {
3344 .base_baud = 115200,
3348 [pbn_b4_bt_2_921600] = {
3351 .base_baud = 921600,
3354 [pbn_b4_bt_4_921600] = {
3357 .base_baud = 921600,
3360 [pbn_b4_bt_8_921600] = {
3363 .base_baud = 921600,
3368 * Entries following this are board-specific.
3377 .base_baud = 921600,
3378 .uart_offset = 0x400,
3382 .flags = FL_BASE2|FL_BASE_BARS,
3384 .base_baud = 921600,
3385 .uart_offset = 0x400,
3389 .flags = FL_BASE2|FL_BASE_BARS,
3391 .base_baud = 921600,
3392 .uart_offset = 0x400,
3396 /* I think this entry is broken - the first_offset looks wrong --rmk */
3397 [pbn_plx_romulus] = {
3400 .base_baud = 921600,
3401 .uart_offset = 8 << 2,
3403 .first_offset = 0x03,
3407 * EndRun Technologies
3408 * Uses the size of PCI Base region 0 to
3409 * signal now many ports are available
3410 * 2 port 952 Uart support
3412 [pbn_endrun_2_4000000] = {
3415 .base_baud = 4000000,
3416 .uart_offset = 0x200,
3417 .first_offset = 0x1000,
3421 * This board uses the size of PCI Base region 0 to
3422 * signal now many ports are available
3425 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3427 .base_baud = 115200,
3430 [pbn_oxsemi_1_4000000] = {
3433 .base_baud = 4000000,
3434 .uart_offset = 0x200,
3435 .first_offset = 0x1000,
3437 [pbn_oxsemi_2_4000000] = {
3440 .base_baud = 4000000,
3441 .uart_offset = 0x200,
3442 .first_offset = 0x1000,
3444 [pbn_oxsemi_4_4000000] = {
3447 .base_baud = 4000000,
3448 .uart_offset = 0x200,
3449 .first_offset = 0x1000,
3451 [pbn_oxsemi_8_4000000] = {
3454 .base_baud = 4000000,
3455 .uart_offset = 0x200,
3456 .first_offset = 0x1000,
3461 * EKF addition for i960 Boards form EKF with serial port.
3464 [pbn_intel_i960] = {
3467 .base_baud = 921600,
3468 .uart_offset = 8 << 2,
3470 .first_offset = 0x10000,
3473 .flags = FL_BASE0|FL_NOIRQ,
3475 .base_baud = 458333,
3478 .first_offset = 0x20178,
3482 * Computone - uses IOMEM.
3484 [pbn_computone_4] = {
3487 .base_baud = 921600,
3488 .uart_offset = 0x40,
3490 .first_offset = 0x200,
3492 [pbn_computone_6] = {
3495 .base_baud = 921600,
3496 .uart_offset = 0x40,
3498 .first_offset = 0x200,
3500 [pbn_computone_8] = {
3503 .base_baud = 921600,
3504 .uart_offset = 0x40,
3506 .first_offset = 0x200,
3511 .base_baud = 460800,
3516 * PA Semi PWRficient PA6T-1682M on-chip UART
3518 [pbn_pasemi_1682M] = {
3521 .base_baud = 8333333,
3524 * National Instruments 843x
3529 .base_baud = 3686400,
3530 .uart_offset = 0x10,
3531 .first_offset = 0x800,
3536 .base_baud = 3686400,
3537 .uart_offset = 0x10,
3538 .first_offset = 0x800,
3543 .base_baud = 3686400,
3544 .uart_offset = 0x10,
3545 .first_offset = 0x800,
3550 .base_baud = 3686400,
3551 .uart_offset = 0x10,
3552 .first_offset = 0x800,
3555 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3557 [pbn_ADDIDATA_PCIe_1_3906250] = {
3560 .base_baud = 3906250,
3561 .uart_offset = 0x200,
3562 .first_offset = 0x1000,
3564 [pbn_ADDIDATA_PCIe_2_3906250] = {
3567 .base_baud = 3906250,
3568 .uart_offset = 0x200,
3569 .first_offset = 0x1000,
3571 [pbn_ADDIDATA_PCIe_4_3906250] = {
3574 .base_baud = 3906250,
3575 .uart_offset = 0x200,
3576 .first_offset = 0x1000,
3578 [pbn_ADDIDATA_PCIe_8_3906250] = {
3581 .base_baud = 3906250,
3582 .uart_offset = 0x200,
3583 .first_offset = 0x1000,
3585 [pbn_ce4100_1_115200] = {
3586 .flags = FL_BASE_BARS,
3588 .base_baud = 921600,
3594 .base_baud = 115200,
3595 .uart_offset = 0x200,
3597 [pbn_NETMOS9900_2s_115200] = {
3600 .base_baud = 115200,
3602 [pbn_brcm_trumanage] = {
3606 .base_baud = 115200,
3611 .base_baud = 115200,
3612 .first_offset = 0x40,
3617 .base_baud = 115200,
3618 .first_offset = 0x40,
3623 .base_baud = 115200,
3624 .first_offset = 0x40,
3626 [pbn_fintek_F81504A] = {
3629 .base_baud = 115200,
3631 [pbn_fintek_F81508A] = {
3634 .base_baud = 115200,
3636 [pbn_fintek_F81512A] = {
3639 .base_baud = 115200,
3644 .base_baud = 115200,
3646 .first_offset = 0xC0,
3651 .base_baud = 115200,
3653 .first_offset = 0xC0,
3656 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3658 [pbn_pericom_PI7C9X7951] = {
3661 .base_baud = 921600,
3664 [pbn_pericom_PI7C9X7952] = {
3667 .base_baud = 921600,
3670 [pbn_pericom_PI7C9X7954] = {
3673 .base_baud = 921600,
3676 [pbn_pericom_PI7C9X7958] = {
3679 .base_baud = 921600,
3682 [pbn_sunix_pci_1s] = {
3684 .base_baud = 921600,
3687 [pbn_sunix_pci_2s] = {
3689 .base_baud = 921600,
3692 [pbn_sunix_pci_4s] = {
3694 .base_baud = 921600,
3697 [pbn_sunix_pci_8s] = {
3699 .base_baud = 921600,
3702 [pbn_sunix_pci_16s] = {
3704 .base_baud = 921600,
3707 [pbn_moxa8250_2p] = {
3710 .base_baud = 921600,
3711 .uart_offset = 0x200,
3713 [pbn_moxa8250_4p] = {
3716 .base_baud = 921600,
3717 .uart_offset = 0x200,
3719 [pbn_moxa8250_8p] = {
3722 .base_baud = 921600,
3723 .uart_offset = 0x200,
3727 static const struct pci_device_id blacklist[] = {
3729 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3730 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3731 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3733 /* multi-io cards handled by parport_serial */
3734 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3735 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3736 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3738 /* Intel platforms with MID UART */
3739 { PCI_VDEVICE(INTEL, 0x081b), },
3740 { PCI_VDEVICE(INTEL, 0x081c), },
3741 { PCI_VDEVICE(INTEL, 0x081d), },
3742 { PCI_VDEVICE(INTEL, 0x1191), },
3743 { PCI_VDEVICE(INTEL, 0x18d8), },
3744 { PCI_VDEVICE(INTEL, 0x19d8), },
3746 /* Intel platforms with DesignWare UART */
3747 { PCI_VDEVICE(INTEL, 0x0936), },
3748 { PCI_VDEVICE(INTEL, 0x0f0a), },
3749 { PCI_VDEVICE(INTEL, 0x0f0c), },
3750 { PCI_VDEVICE(INTEL, 0x228a), },
3751 { PCI_VDEVICE(INTEL, 0x228c), },
3752 { PCI_VDEVICE(INTEL, 0x9ce3), },
3753 { PCI_VDEVICE(INTEL, 0x9ce4), },
3756 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3757 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3759 /* End of the black list */
3763 static int serial_pci_is_class_communication(struct pci_dev *dev)
3766 * If it is not a communications device or the programming
3767 * interface is greater than 6, give up.
3769 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3770 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3771 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3772 (dev->class & 0xff) > 6)
3779 * Given a complete unknown PCI device, try to use some heuristics to
3780 * guess what the configuration might be, based on the pitiful PCI
3781 * serial specs. Returns 0 on success, -ENODEV on failure.
3784 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3786 int num_iomem, num_port, first_port = -1, i;
3789 rc = serial_pci_is_class_communication(dev);
3794 * Should we try to make guesses for multiport serial devices later?
3796 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3799 num_iomem = num_port = 0;
3800 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3801 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3803 if (first_port == -1)
3806 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3811 * If there is 1 or 0 iomem regions, and exactly one port,
3812 * use it. We guess the number of ports based on the IO
3815 if (num_iomem <= 1 && num_port == 1) {
3816 board->flags = first_port;
3817 board->num_ports = pci_resource_len(dev, first_port) / 8;
3822 * Now guess if we've got a board which indexes by BARs.
3823 * Each IO BAR should be 8 bytes, and they should follow
3828 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3829 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3830 pci_resource_len(dev, i) == 8 &&
3831 (first_port == -1 || (first_port + num_port) == i)) {
3833 if (first_port == -1)
3839 board->flags = first_port | FL_BASE_BARS;
3840 board->num_ports = num_port;
3848 serial_pci_matches(const struct pciserial_board *board,
3849 const struct pciserial_board *guessed)
3852 board->num_ports == guessed->num_ports &&
3853 board->base_baud == guessed->base_baud &&
3854 board->uart_offset == guessed->uart_offset &&
3855 board->reg_shift == guessed->reg_shift &&
3856 board->first_offset == guessed->first_offset;
3859 struct serial_private *
3860 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3862 struct uart_8250_port uart;
3863 struct serial_private *priv;
3864 struct pci_serial_quirk *quirk;
3865 int rc, nr_ports, i;
3867 nr_ports = board->num_ports;
3870 * Find an init and setup quirks.
3872 quirk = find_quirk(dev);
3875 * Run the new-style initialization function.
3876 * The initialization function returns:
3878 * 0 - use board->num_ports
3879 * >0 - number of ports
3882 rc = quirk->init(dev);
3891 priv = kzalloc(sizeof(struct serial_private) +
3892 sizeof(unsigned int) * nr_ports,
3895 priv = ERR_PTR(-ENOMEM);
3900 priv->quirk = quirk;
3902 memset(&uart, 0, sizeof(uart));
3903 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3904 uart.port.uartclk = board->base_baud * 16;
3906 if (pci_match_id(pci_use_msi, dev)) {
3907 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
3908 pci_set_master(dev);
3909 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3911 dev_dbg(&dev->dev, "Using legacy interrupts\n");
3912 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3920 uart.port.irq = pci_irq_vector(dev, 0);
3921 uart.port.dev = &dev->dev;
3923 for (i = 0; i < nr_ports; i++) {
3924 if (quirk->setup(priv, board, &uart, i))
3927 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3928 uart.port.iobase, uart.port.irq, uart.port.iotype);
3930 priv->line[i] = serial8250_register_8250_port(&uart);
3931 if (priv->line[i] < 0) {
3933 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3934 uart.port.iobase, uart.port.irq,
3935 uart.port.iotype, priv->line[i]);
3940 priv->board = board;
3949 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3951 static void pciserial_detach_ports(struct serial_private *priv)
3953 struct pci_serial_quirk *quirk;
3956 for (i = 0; i < priv->nr; i++)
3957 serial8250_unregister_port(priv->line[i]);
3960 * Find the exit quirks.
3962 quirk = find_quirk(priv->dev);
3964 quirk->exit(priv->dev);
3967 void pciserial_remove_ports(struct serial_private *priv)
3969 pciserial_detach_ports(priv);
3972 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3974 void pciserial_suspend_ports(struct serial_private *priv)
3978 for (i = 0; i < priv->nr; i++)
3979 if (priv->line[i] >= 0)
3980 serial8250_suspend_port(priv->line[i]);
3983 * Ensure that every init quirk is properly torn down
3985 if (priv->quirk->exit)
3986 priv->quirk->exit(priv->dev);
3988 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3990 void pciserial_resume_ports(struct serial_private *priv)
3995 * Ensure that the board is correctly configured.
3997 if (priv->quirk->init)
3998 priv->quirk->init(priv->dev);
4000 for (i = 0; i < priv->nr; i++)
4001 if (priv->line[i] >= 0)
4002 serial8250_resume_port(priv->line[i]);
4004 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4007 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4008 * to the arrangement of serial ports on a PCI card.
4011 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4013 struct pci_serial_quirk *quirk;
4014 struct serial_private *priv;
4015 const struct pciserial_board *board;
4016 const struct pci_device_id *exclude;
4017 struct pciserial_board tmp;
4020 quirk = find_quirk(dev);
4022 rc = quirk->probe(dev);
4027 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4028 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4033 board = &pci_boards[ent->driver_data];
4035 exclude = pci_match_id(blacklist, dev);
4039 rc = pcim_enable_device(dev);
4040 pci_save_state(dev);
4044 if (ent->driver_data == pbn_default) {
4046 * Use a copy of the pci_board entry for this;
4047 * avoid changing entries in the table.
4049 memcpy(&tmp, board, sizeof(struct pciserial_board));
4053 * We matched one of our class entries. Try to
4054 * determine the parameters of this board.
4056 rc = serial_pci_guess_board(dev, &tmp);
4061 * We matched an explicit entry. If we are able to
4062 * detect this boards settings with our heuristic,
4063 * then we no longer need this entry.
4065 memcpy(&tmp, &pci_boards[pbn_default],
4066 sizeof(struct pciserial_board));
4067 rc = serial_pci_guess_board(dev, &tmp);
4068 if (rc == 0 && serial_pci_matches(board, &tmp))
4069 moan_device("Redundant entry in serial pci_table.",
4073 priv = pciserial_init_ports(dev, board);
4075 return PTR_ERR(priv);
4077 pci_set_drvdata(dev, priv);
4081 static void pciserial_remove_one(struct pci_dev *dev)
4083 struct serial_private *priv = pci_get_drvdata(dev);
4085 pciserial_remove_ports(priv);
4088 #ifdef CONFIG_PM_SLEEP
4089 static int pciserial_suspend_one(struct device *dev)
4091 struct serial_private *priv = dev_get_drvdata(dev);
4094 pciserial_suspend_ports(priv);
4099 static int pciserial_resume_one(struct device *dev)
4101 struct pci_dev *pdev = to_pci_dev(dev);
4102 struct serial_private *priv = pci_get_drvdata(pdev);
4107 * The device may have been disabled. Re-enable it.
4109 err = pci_enable_device(pdev);
4110 /* FIXME: We cannot simply error out here */
4112 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4113 pciserial_resume_ports(priv);
4119 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4120 pciserial_resume_one);
4122 static const struct pci_device_id serial_pci_tbl[] = {
4123 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4124 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4125 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4127 /* Advantech also use 0x3618 and 0xf618 */
4128 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4129 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4131 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4132 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4134 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4135 PCI_SUBVENDOR_ID_CONNECT_TECH,
4136 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4138 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4139 PCI_SUBVENDOR_ID_CONNECT_TECH,
4140 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4142 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4143 PCI_SUBVENDOR_ID_CONNECT_TECH,
4144 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4146 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4147 PCI_SUBVENDOR_ID_CONNECT_TECH,
4148 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4150 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4151 PCI_SUBVENDOR_ID_CONNECT_TECH,
4152 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4154 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4155 PCI_SUBVENDOR_ID_CONNECT_TECH,
4156 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4158 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4159 PCI_SUBVENDOR_ID_CONNECT_TECH,
4160 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4162 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4163 PCI_SUBVENDOR_ID_CONNECT_TECH,
4164 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4166 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4167 PCI_SUBVENDOR_ID_CONNECT_TECH,
4168 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4170 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4171 PCI_SUBVENDOR_ID_CONNECT_TECH,
4172 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4174 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4175 PCI_SUBVENDOR_ID_CONNECT_TECH,
4176 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4178 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4179 PCI_SUBVENDOR_ID_CONNECT_TECH,
4180 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4182 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4183 PCI_SUBVENDOR_ID_CONNECT_TECH,
4184 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4186 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4187 PCI_SUBVENDOR_ID_CONNECT_TECH,
4188 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4190 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4191 PCI_SUBVENDOR_ID_CONNECT_TECH,
4192 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4194 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4195 PCI_SUBVENDOR_ID_CONNECT_TECH,
4196 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4198 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4199 PCI_SUBVENDOR_ID_CONNECT_TECH,
4200 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4202 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4203 PCI_VENDOR_ID_AFAVLAB,
4204 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4206 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208 pbn_b2_bt_1_115200 },
4209 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211 pbn_b2_bt_2_115200 },
4212 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214 pbn_b2_bt_4_115200 },
4215 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4217 pbn_b2_bt_2_115200 },
4218 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4220 pbn_b2_bt_4_115200 },
4221 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233 pbn_b2_bt_2_115200 },
4234 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 pbn_b2_bt_2_921600 },
4238 * VScom SPCOM800, from sl@s.pl
4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 /* Unknown card - subdevice 0x1584 */
4247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4249 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4251 /* Unknown card - subdevice 0x1588 */
4252 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4254 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4256 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4257 PCI_SUBVENDOR_ID_KEYSPAN,
4258 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4260 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4267 PCI_VENDOR_ID_ESDGMBH,
4268 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4270 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4271 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4272 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4274 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4275 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4276 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4278 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4279 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4280 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4282 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4283 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4284 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4286 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4287 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4288 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4290 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4291 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4292 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4294 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4295 PCI_SUBVENDOR_ID_EXSYS,
4296 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4299 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4302 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4303 0x10b5, 0x106a, 0, 0,
4306 * EndRun Technologies. PCI express device range.
4307 * EndRun PTP/1588 has 2 Native UARTs.
4309 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 pbn_endrun_2_4000000 },
4313 * Quatech cards. These actually have configurable clocks but for
4314 * now we just use the default.
4316 * 100 series are RS232, 200 series RS422,
4318 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4377 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4380 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4381 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4384 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4386 pbn_b0_bt_2_921600 },
4389 * The below card is a little controversial since it is the
4390 * subject of a PCI vendor/device ID clash. (See
4391 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4392 * For now just used the hex ID 0x950a.
4394 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4395 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4396 0, 0, pbn_b0_2_115200 },
4397 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4398 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4399 0, 0, pbn_b0_2_115200 },
4400 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4404 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4406 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411 pbn_b0_bt_2_921600 },
4412 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417 * Oxford Semiconductor Inc. Tornado PCI express device range.
4419 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_oxsemi_1_4000000 },
4428 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_oxsemi_1_4000000 },
4431 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_oxsemi_1_4000000 },
4440 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_oxsemi_1_4000000 },
4443 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_oxsemi_2_4000000 },
4458 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_oxsemi_2_4000000 },
4461 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_oxsemi_4_4000000 },
4464 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_oxsemi_4_4000000 },
4467 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_oxsemi_8_4000000 },
4470 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_oxsemi_8_4000000 },
4473 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_oxsemi_1_4000000 },
4476 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_oxsemi_1_4000000 },
4479 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_oxsemi_1_4000000 },
4482 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_oxsemi_1_4000000 },
4485 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_oxsemi_1_4000000 },
4488 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_oxsemi_1_4000000 },
4491 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_oxsemi_1_4000000 },
4494 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_oxsemi_1_4000000 },
4497 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_oxsemi_1_4000000 },
4500 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_oxsemi_1_4000000 },
4503 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_oxsemi_1_4000000 },
4506 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_oxsemi_1_4000000 },
4509 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_oxsemi_1_4000000 },
4512 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_oxsemi_1_4000000 },
4515 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_oxsemi_1_4000000 },
4518 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_oxsemi_1_4000000 },
4521 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_oxsemi_1_4000000 },
4524 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_oxsemi_1_4000000 },
4527 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_oxsemi_1_4000000 },
4530 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_oxsemi_1_4000000 },
4533 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_oxsemi_1_4000000 },
4536 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_oxsemi_1_4000000 },
4539 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_oxsemi_1_4000000 },
4542 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_oxsemi_1_4000000 },
4545 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_oxsemi_1_4000000 },
4548 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_oxsemi_1_4000000 },
4552 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4554 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4555 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4556 pbn_oxsemi_1_4000000 },
4557 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4558 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4559 pbn_oxsemi_2_4000000 },
4560 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4561 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4562 pbn_oxsemi_4_4000000 },
4563 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4564 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4565 pbn_oxsemi_8_4000000 },
4568 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4570 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4571 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4572 pbn_oxsemi_2_4000000 },
4575 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4576 * from skokodyn@yahoo.com
4578 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4579 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4581 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4582 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4584 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4585 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4587 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4588 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4592 * Digitan DS560-558, from jimd@esoft.com
4594 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 * Titan Electronic cards
4600 * The 400L and 800L have a custom setup quirk.
4602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b1_bt_2_921600 },
4620 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b0_bt_4_921600 },
4623 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_b0_bt_8_921600 },
4626 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_b4_bt_2_921600 },
4629 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_b4_bt_4_921600 },
4632 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_b4_bt_8_921600 },
4635 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_oxsemi_1_4000000 },
4647 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_oxsemi_2_4000000 },
4650 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_oxsemi_4_4000000 },
4653 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_oxsemi_8_4000000 },
4656 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_oxsemi_2_4000000 },
4659 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_oxsemi_2_4000000 },
4662 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_b0_bt_2_921600 },
4665 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_b2_bt_2_921600 },
4690 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_b2_bt_2_921600 },
4693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_b2_bt_2_921600 },
4696 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_b2_bt_4_921600 },
4699 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_b2_bt_4_921600 },
4702 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_b2_bt_4_921600 },
4705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_b0_bt_2_921600 },
4717 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_b0_bt_2_921600 },
4720 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_b0_bt_2_921600 },
4723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_b0_bt_4_921600 },
4726 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_bt_4_921600 },
4729 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_b0_bt_4_921600 },
4732 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b0_bt_8_921600 },
4735 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_b0_bt_8_921600 },
4738 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_b0_bt_8_921600 },
4743 * Computone devices submitted by Doug McNash dmcnash@computone.com
4745 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4746 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4747 0, 0, pbn_computone_4 },
4748 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4749 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4750 0, 0, pbn_computone_8 },
4751 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4752 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4753 0, 0, pbn_computone_6 },
4755 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4759 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4760 pbn_b0_bt_1_921600 },
4763 * Sunix PCI serial boards
4765 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4766 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4768 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4769 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4771 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4772 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4774 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4775 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4777 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4778 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4780 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4781 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4783 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4784 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4785 pbn_sunix_pci_16s },
4788 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4790 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_b0_bt_8_115200 },
4793 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_b0_bt_8_115200 },
4797 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_b0_bt_2_115200 },
4800 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_b0_bt_2_115200 },
4803 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_b0_bt_2_115200 },
4806 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_b0_bt_2_115200 },
4809 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_b0_bt_2_115200 },
4812 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_b0_bt_4_460800 },
4815 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_b0_bt_4_460800 },
4818 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_b0_bt_2_460800 },
4821 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_b0_bt_2_460800 },
4824 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_b0_bt_2_460800 },
4827 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 pbn_b0_bt_1_115200 },
4830 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_b0_bt_1_460800 },
4835 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4836 * Cards are identified by their subsystem vendor IDs, which
4837 * (in hex) match the model number.
4839 * Note that JC140x are RS422/485 cards which require ox950
4840 * ACR = 0x10, and as such are not currently fully supported.
4842 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4843 0x1204, 0x0004, 0, 0,
4845 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4846 0x1208, 0x0004, 0, 0,
4848 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4849 0x1402, 0x0002, 0, 0,
4850 pbn_b0_2_921600 }, */
4851 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4852 0x1404, 0x0004, 0, 0,
4853 pbn_b0_4_921600 }, */
4854 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4855 0x1208, 0x0004, 0, 0,
4858 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4859 0x1204, 0x0004, 0, 0,
4861 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4862 0x1208, 0x0004, 0, 0,
4864 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4865 0x1208, 0x0004, 0, 0,
4868 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4870 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4877 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 * RAStel 2 port modem, gerg@moreton.com.au
4884 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_b2_bt_2_115200 },
4889 * EKF addition for i960 Boards form EKF with serial port
4891 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4892 0xE4BF, PCI_ANY_ID, 0, 0,
4896 * Xircom Cardbus/Ethernet combos
4898 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4904 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 * Untested PCI modems, sent in from various folks...
4913 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4915 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4916 0x1048, 0x1500, 0, 0,
4919 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4926 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4927 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4929 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4948 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4949 PCI_ANY_ID, PCI_ANY_ID,
4951 0, pbn_pericom_PI7C9X7951 },
4952 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4953 PCI_ANY_ID, PCI_ANY_ID,
4955 0, pbn_pericom_PI7C9X7952 },
4956 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4957 PCI_ANY_ID, PCI_ANY_ID,
4959 0, pbn_pericom_PI7C9X7954 },
4960 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4961 PCI_ANY_ID, PCI_ANY_ID,
4963 0, pbn_pericom_PI7C9X7958 },
4965 * ACCES I/O Products quad
4967 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_pericom_PI7C9X7952 },
4970 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_pericom_PI7C9X7952 },
4973 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_pericom_PI7C9X7954 },
4976 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_pericom_PI7C9X7954 },
4979 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_pericom_PI7C9X7952 },
4982 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_pericom_PI7C9X7952 },
4985 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 pbn_pericom_PI7C9X7954 },
4988 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_pericom_PI7C9X7954 },
4991 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_pericom_PI7C9X7952 },
4994 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_pericom_PI7C9X7952 },
4997 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_pericom_PI7C9X7954 },
5000 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_pericom_PI7C9X7954 },
5003 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 pbn_pericom_PI7C9X7951 },
5006 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_pericom_PI7C9X7952 },
5009 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 pbn_pericom_PI7C9X7952 },
5012 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_pericom_PI7C9X7954 },
5015 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 pbn_pericom_PI7C9X7954 },
5018 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_pericom_PI7C9X7952 },
5021 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_pericom_PI7C9X7954 },
5024 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026 pbn_pericom_PI7C9X7952 },
5027 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5029 pbn_pericom_PI7C9X7952 },
5030 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032 pbn_pericom_PI7C9X7954 },
5033 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 pbn_pericom_PI7C9X7954 },
5036 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_pericom_PI7C9X7952 },
5039 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_pericom_PI7C9X7954 },
5042 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_pericom_PI7C9X7954 },
5045 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047 pbn_pericom_PI7C9X7958 },
5048 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_pericom_PI7C9X7958 },
5051 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_pericom_PI7C9X7954 },
5054 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 pbn_pericom_PI7C9X7958 },
5057 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059 pbn_pericom_PI7C9X7954 },
5060 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_pericom_PI7C9X7958 },
5063 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_pericom_PI7C9X7954 },
5067 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5069 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5076 PCI_ANY_ID, PCI_ANY_ID,
5078 pbn_b1_bt_1_115200 },
5083 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5089 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5095 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5096 PCI_ANY_ID, PCI_ANY_ID,
5097 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5099 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5100 PCI_ANY_ID, PCI_ANY_ID,
5101 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5104 * Perle PCI-RAS cards
5106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5107 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5108 0, 0, pbn_b2_4_921600 },
5109 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5110 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5111 0, 0, pbn_b2_8_921600 },
5114 * Mainpine series cards: Fairly standard layout but fools
5115 * parts of the autodetect in some cases and uses otherwise
5116 * unmatched communications subclasses in the PCI Express case
5119 { /* RockForceDUO */
5120 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5121 PCI_VENDOR_ID_MAINPINE, 0x0200,
5122 0, 0, pbn_b0_2_115200 },
5123 { /* RockForceQUATRO */
5124 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5125 PCI_VENDOR_ID_MAINPINE, 0x0300,
5126 0, 0, pbn_b0_4_115200 },
5127 { /* RockForceDUO+ */
5128 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5129 PCI_VENDOR_ID_MAINPINE, 0x0400,
5130 0, 0, pbn_b0_2_115200 },
5131 { /* RockForceQUATRO+ */
5132 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5133 PCI_VENDOR_ID_MAINPINE, 0x0500,
5134 0, 0, pbn_b0_4_115200 },
5136 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5137 PCI_VENDOR_ID_MAINPINE, 0x0600,
5138 0, 0, pbn_b0_2_115200 },
5140 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5141 PCI_VENDOR_ID_MAINPINE, 0x0700,
5142 0, 0, pbn_b0_4_115200 },
5143 { /* RockForceOCTO+ */
5144 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5145 PCI_VENDOR_ID_MAINPINE, 0x0800,
5146 0, 0, pbn_b0_8_115200 },
5147 { /* RockForceDUO+ */
5148 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5149 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5150 0, 0, pbn_b0_2_115200 },
5151 { /* RockForceQUARTRO+ */
5152 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5153 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5154 0, 0, pbn_b0_4_115200 },
5155 { /* RockForceOCTO+ */
5156 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5157 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5158 0, 0, pbn_b0_8_115200 },
5160 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5161 PCI_VENDOR_ID_MAINPINE, 0x2000,
5162 0, 0, pbn_b0_1_115200 },
5164 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5165 PCI_VENDOR_ID_MAINPINE, 0x2100,
5166 0, 0, pbn_b0_1_115200 },
5168 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5169 PCI_VENDOR_ID_MAINPINE, 0x2200,
5170 0, 0, pbn_b0_2_115200 },
5172 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5173 PCI_VENDOR_ID_MAINPINE, 0x2300,
5174 0, 0, pbn_b0_2_115200 },
5176 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5177 PCI_VENDOR_ID_MAINPINE, 0x2400,
5178 0, 0, pbn_b0_4_115200 },
5180 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5181 PCI_VENDOR_ID_MAINPINE, 0x2500,
5182 0, 0, pbn_b0_4_115200 },
5184 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5185 PCI_VENDOR_ID_MAINPINE, 0x2600,
5186 0, 0, pbn_b0_8_115200 },
5188 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5189 PCI_VENDOR_ID_MAINPINE, 0x2700,
5190 0, 0, pbn_b0_8_115200 },
5191 { /* IQ Express D1 */
5192 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5193 PCI_VENDOR_ID_MAINPINE, 0x3000,
5194 0, 0, pbn_b0_1_115200 },
5195 { /* IQ Express F1 */
5196 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5197 PCI_VENDOR_ID_MAINPINE, 0x3100,
5198 0, 0, pbn_b0_1_115200 },
5199 { /* IQ Express D2 */
5200 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5201 PCI_VENDOR_ID_MAINPINE, 0x3200,
5202 0, 0, pbn_b0_2_115200 },
5203 { /* IQ Express F2 */
5204 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5205 PCI_VENDOR_ID_MAINPINE, 0x3300,
5206 0, 0, pbn_b0_2_115200 },
5207 { /* IQ Express D4 */
5208 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5209 PCI_VENDOR_ID_MAINPINE, 0x3400,
5210 0, 0, pbn_b0_4_115200 },
5211 { /* IQ Express F4 */
5212 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5213 PCI_VENDOR_ID_MAINPINE, 0x3500,
5214 0, 0, pbn_b0_4_115200 },
5215 { /* IQ Express D8 */
5216 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5217 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5218 0, 0, pbn_b0_8_115200 },
5219 { /* IQ Express F8 */
5220 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5221 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5222 0, 0, pbn_b0_8_115200 },
5226 * PA Semi PA6T-1682M on-chip UART
5228 { PCI_VENDOR_ID_PASEMI, 0xa004,
5229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5233 * National Instruments
5235 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5238 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5241 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5243 pbn_b1_bt_4_115200 },
5244 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5246 pbn_b1_bt_2_115200 },
5247 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5249 pbn_b1_bt_4_115200 },
5250 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5252 pbn_b1_bt_2_115200 },
5253 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5256 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5259 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261 pbn_b1_bt_4_115200 },
5262 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264 pbn_b1_bt_2_115200 },
5265 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267 pbn_b1_bt_4_115200 },
5268 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270 pbn_b1_bt_2_115200 },
5271 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5274 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5277 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5283 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5286 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5289 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5292 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5295 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5298 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5301 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5304 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5317 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5320 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5329 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5332 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5335 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5338 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5341 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5344 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5349 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5351 { PCI_VENDOR_ID_ADDIDATA,
5352 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5359 { PCI_VENDOR_ID_ADDIDATA,
5360 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5367 { PCI_VENDOR_ID_ADDIDATA,
5368 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5375 { PCI_VENDOR_ID_AMCC,
5376 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5383 { PCI_VENDOR_ID_ADDIDATA,
5384 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5391 { PCI_VENDOR_ID_ADDIDATA,
5392 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5399 { PCI_VENDOR_ID_ADDIDATA,
5400 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5407 { PCI_VENDOR_ID_ADDIDATA,
5408 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5415 { PCI_VENDOR_ID_ADDIDATA,
5416 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5423 { PCI_VENDOR_ID_ADDIDATA,
5424 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5431 { PCI_VENDOR_ID_ADDIDATA,
5432 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5439 { PCI_VENDOR_ID_ADDIDATA,
5440 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5445 pbn_ADDIDATA_PCIe_4_3906250 },
5447 { PCI_VENDOR_ID_ADDIDATA,
5448 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5453 pbn_ADDIDATA_PCIe_2_3906250 },
5455 { PCI_VENDOR_ID_ADDIDATA,
5456 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5461 pbn_ADDIDATA_PCIe_1_3906250 },
5463 { PCI_VENDOR_ID_ADDIDATA,
5464 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5469 pbn_ADDIDATA_PCIe_8_3906250 },
5471 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5472 PCI_VENDOR_ID_IBM, 0x0299,
5473 0, 0, pbn_b0_bt_2_115200 },
5476 * other NetMos 9835 devices are most likely handled by the
5477 * parport_serial driver, check drivers/parport/parport_serial.c
5478 * before adding them here.
5481 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5483 0, 0, pbn_b0_1_115200 },
5485 /* the 9901 is a rebranded 9912 */
5486 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5488 0, 0, pbn_b0_1_115200 },
5490 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5492 0, 0, pbn_b0_1_115200 },
5494 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5496 0, 0, pbn_b0_1_115200 },
5498 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5500 0, 0, pbn_b0_1_115200 },
5502 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5504 0, 0, pbn_NETMOS9900_2s_115200 },
5507 * Best Connectivity and Rosewill PCI Multi I/O cards
5510 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5512 0, 0, pbn_b0_1_115200 },
5514 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5516 0, 0, pbn_b0_bt_2_115200 },
5518 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5520 0, 0, pbn_b0_bt_4_115200 },
5522 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5524 pbn_ce4100_1_115200 },
5529 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5534 * Broadcom TruManage
5536 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5538 pbn_brcm_trumanage },
5541 * AgeStar as-prs2-009
5543 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5544 PCI_ANY_ID, PCI_ANY_ID,
5545 0, 0, pbn_b0_bt_2_115200 },
5548 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5549 * so not listed here.
5551 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5552 PCI_ANY_ID, PCI_ANY_ID,
5553 0, 0, pbn_b0_bt_4_115200 },
5555 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5556 PCI_ANY_ID, PCI_ANY_ID,
5557 0, 0, pbn_b0_bt_2_115200 },
5559 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5560 PCI_ANY_ID, PCI_ANY_ID,
5561 0, 0, pbn_b0_bt_4_115200 },
5563 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5564 PCI_ANY_ID, PCI_ANY_ID,
5565 0, 0, pbn_wch382_2 },
5567 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5568 PCI_ANY_ID, PCI_ANY_ID,
5569 0, 0, pbn_wch384_4 },
5571 /* Fintek PCI serial cards */
5572 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5573 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5574 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5575 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5576 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5577 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5579 /* MKS Tenta SCOM-080x serial cards */
5580 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5581 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5583 /* Amazon PCI serial device */
5584 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5587 * These entries match devices with class COMMUNICATION_SERIAL,
5588 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5590 { PCI_ANY_ID, PCI_ANY_ID,
5591 PCI_ANY_ID, PCI_ANY_ID,
5592 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5593 0xffff00, pbn_default },
5594 { PCI_ANY_ID, PCI_ANY_ID,
5595 PCI_ANY_ID, PCI_ANY_ID,
5596 PCI_CLASS_COMMUNICATION_MODEM << 8,
5597 0xffff00, pbn_default },
5598 { PCI_ANY_ID, PCI_ANY_ID,
5599 PCI_ANY_ID, PCI_ANY_ID,
5600 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5601 0xffff00, pbn_default },
5605 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5606 pci_channel_state_t state)
5608 struct serial_private *priv = pci_get_drvdata(dev);
5610 if (state == pci_channel_io_perm_failure)
5611 return PCI_ERS_RESULT_DISCONNECT;
5614 pciserial_detach_ports(priv);
5616 pci_disable_device(dev);
5618 return PCI_ERS_RESULT_NEED_RESET;
5621 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5625 rc = pci_enable_device(dev);
5628 return PCI_ERS_RESULT_DISCONNECT;
5630 pci_restore_state(dev);
5631 pci_save_state(dev);
5633 return PCI_ERS_RESULT_RECOVERED;
5636 static void serial8250_io_resume(struct pci_dev *dev)
5638 struct serial_private *priv = pci_get_drvdata(dev);
5639 struct serial_private *new;
5644 new = pciserial_init_ports(dev, priv->board);
5646 pci_set_drvdata(dev, new);
5651 static const struct pci_error_handlers serial8250_err_handler = {
5652 .error_detected = serial8250_io_error_detected,
5653 .slot_reset = serial8250_io_slot_reset,
5654 .resume = serial8250_io_resume,
5657 static struct pci_driver serial_pci_driver = {
5659 .probe = pciserial_init_one,
5660 .remove = pciserial_remove_one,
5662 .pm = &pciserial_pm_ops,
5664 .id_table = serial_pci_tbl,
5665 .err_handler = &serial8250_err_handler,
5668 module_pci_driver(serial_pci_driver);
5670 MODULE_LICENSE("GPL");
5671 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5672 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);