drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24 #include <linux/rational.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_data/dma-dw.h>
  31
  32 #include "8250.h"
  33
  34 /*
  35  * init function returns:
  36  *  > 0 - number of ports
  37  *  = 0 - use board->num_ports
  38  *  < 0 - error
  39  */
  40 struct pci_serial_quirk {
  41         u32     vendor;
  42         u32     device;
  43         u32     subvendor;
  44         u32     subdevice;
  45         int     (*probe)(struct pci_dev *dev);
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *,
  48                          const struct pciserial_board *,
  49                          struct uart_8250_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         const struct pciserial_board *board;
  61         int                     line[0];
  62 };
  63
  64 static int pci_default_setup(struct serial_private*,
  65           const struct pciserial_board*, struct uart_8250_port *, int);
  66
  67 static void moan_device(const char *str, struct pci_dev *dev)
  68 {
  69         dev_err(&dev->dev,
  70                "%s: %s\n"
  71                "Please send the output of lspci -vv, this\n"
  72                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  73                "manufacturer and name of serial board or\n"
  74                "modem board to <linux-serial@vger.kernel.org>.\n",
  75                pci_name(dev), str, dev->vendor, dev->device,
  76                dev->subsystem_vendor, dev->subsystem_device);
  77 }
  78
  79 static int
  80 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  81            int bar, int offset, int regshift)
  82 {
  83         struct pci_dev *dev = priv->dev;
  84
  85         if (bar >= PCI_NUM_BAR_RESOURCES)
  86                 return -EINVAL;
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->port.iotype = UPIO_MEM;
  95                 port->port.iobase = 0;
  96                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
  97                 port->port.membase = priv->remapped_bar[bar] + offset;
  98                 port->port.regshift = regshift;
  99         } else {
 100                 port->port.iotype = UPIO_PORT;
 101                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 102                 port->port.mapbase = 0;
 103                 port->port.membase = NULL;
 104                 port->port.regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 111  */
 112 static int addidata_apci7800_setup(struct serial_private *priv,
 113                                 const struct pciserial_board *board,
 114                                 struct uart_8250_port *port, int idx)
 115 {
 116         unsigned int bar = 0, offset = board->first_offset;
 117         bar = FL_GET_BASE(board->flags);
 118
 119         if (idx < 2) {
 120                 offset += idx * board->uart_offset;
 121         } else if ((idx >= 2) && (idx < 4)) {
 122                 bar += 1;
 123                 offset += ((idx - 2) * board->uart_offset);
 124         } else if ((idx >= 4) && (idx < 6)) {
 125                 bar += 2;
 126                 offset += ((idx - 4) * board->uart_offset);
 127         } else if (idx >= 6) {
 128                 bar += 3;
 129                 offset += ((idx - 6) * board->uart_offset);
 130         }
 131
 132         return setup_port(priv, port, bar, offset, board->reg_shift);
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 141               struct uart_8250_port *port, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(priv, port, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct serial_private *priv,
 195                 const struct pciserial_board *board,
 196                 struct uart_8250_port *port, int idx)
 197 {
 198         unsigned int offset = board->first_offset;
 199         unsigned int bar = FL_GET_BASE(board->flags);
 200
 201         switch (priv->dev->subsystem_device) {
 202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 203                 if (idx == 3)
 204                         idx++;
 205                 break;
 206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 207                 if (idx > 0)
 208                         idx++;
 209                 if (idx > 2)
 210                         idx++;
 211                 break;
 212         }
 213         if (idx > 2)
 214                 offset = 0x18;
 215
 216         offset += idx * board->uart_offset;
 217
 218         return setup_port(priv, port, bar, offset, board->reg_shift);
 219 }
 220
 221 /*
 222  * Added for EKF Intel i960 serial boards
 223  */
 224 static int pci_inteli960ni_init(struct pci_dev *dev)
 225 {
 226         u32 oldval;
 227
 228         if (!(dev->subsystem_device & 0x1000))
 229                 return -ENODEV;
 230
 231         /* is firmware started? */
 232         pci_read_config_dword(dev, 0x44, &oldval);
 233         if (oldval == 0x00001000L) { /* RESET value */
 234                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 235                 return -ENODEV;
 236         }
 237         return 0;
 238 }
 239
 240 /*
 241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 242  * that the card interrupt be explicitly enabled or disabled.  This
 243  * seems to be mainly needed on card using the PLX which also use I/O
 244  * mapped memory.
 245  */
 246 static int pci_plx9050_init(struct pci_dev *dev)
 247 {
 248         u8 irq_config;
 249         void __iomem *p;
 250
 251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 252                 moan_device("no memory in bar 0", dev);
 253                 return 0;
 254         }
 255
 256         irq_config = 0x41;
 257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 259                 irq_config = 0x43;
 260
 261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 263                 /*
 264                  * As the megawolf cards have the int pins active
 265                  * high, and have 2 UART chips, both ints must be
 266                  * enabled on the 9050. Also, the UARTS are set in
 267                  * 16450 mode by default, so we have to enable the
 268                  * 16C950 'enhanced' mode so that we can use the
 269                  * deep FIFOs
 270                  */
 271                 irq_config = 0x5b;
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 #define NI8420_INT_ENABLE_REG   0x38
 312 #define NI8420_INT_ENABLE_BIT   0x2000
 313
 314 static void pci_ni8420_exit(struct pci_dev *dev)
 315 {
 316         void __iomem *p;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         p = pci_ioremap_bar(dev, bar);
 325         if (p == NULL)
 326                 return;
 327
 328         /* Disable the CPU Interrupt */
 329         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 330                p + NI8420_INT_ENABLE_REG);
 331         iounmap(p);
 332 }
 333
 334
 335 /* MITE registers */
 336 #define MITE_IOWBSR1    0xc4
 337 #define MITE_IOWCR1     0xf4
 338 #define MITE_LCIMR1     0x08
 339 #define MITE_LCIMR2     0x10
 340
 341 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 342
 343 static void pci_ni8430_exit(struct pci_dev *dev)
 344 {
 345         void __iomem *p;
 346         unsigned int bar = 0;
 347
 348         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 349                 moan_device("no memory in bar", dev);
 350                 return;
 351         }
 352
 353         p = pci_ioremap_bar(dev, bar);
 354         if (p == NULL)
 355                 return;
 356
 357         /* Disable the CPU Interrupt */
 358         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 359         iounmap(p);
 360 }
 361
 362 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 363 static int
 364 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 365                 struct uart_8250_port *port, int idx)
 366 {
 367         unsigned int bar, offset = board->first_offset;
 368
 369         bar = 0;
 370
 371         if (idx < 4) {
 372                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 373                 offset += idx * board->uart_offset;
 374         } else if (idx < 8) {
 375                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 376                 offset += idx * board->uart_offset + 0xC00;
 377         } else /* we have only 8 ports on PMC-OCTALPRO */
 378                 return 1;
 379
 380         return setup_port(priv, port, bar, offset, board->reg_shift);
 381 }
 382
 383 /*
 384 * This does initialization for PMC OCTALPRO cards:
 385 * maps the device memory, resets the UARTs (needed, bc
 386 * if the module is removed and inserted again, the card
 387 * is in the sleep mode) and enables global interrupt.
 388 */
 389
 390 /* global control register offset for SBS PMC-OctalPro */
 391 #define OCT_REG_CR_OFF          0x500
 392
 393 static int sbs_init(struct pci_dev *dev)
 394 {
 395         u8 __iomem *p;
 396
 397         p = pci_ioremap_bar(dev, 0);
 398
 399         if (p == NULL)
 400                 return -ENOMEM;
 401         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 402         writeb(0x10, p + OCT_REG_CR_OFF);
 403         udelay(50);
 404         writeb(0x0, p + OCT_REG_CR_OFF);
 405
 406         /* Set bit-2 (INTENABLE) of Control Register */
 407         writeb(0x4, p + OCT_REG_CR_OFF);
 408         iounmap(p);
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * Disables the global interrupt of PMC-OctalPro
 415  */
 416
 417 static void sbs_exit(struct pci_dev *dev)
 418 {
 419         u8 __iomem *p;
 420
 421         p = pci_ioremap_bar(dev, 0);
 422         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 423         if (p != NULL)
 424                 writeb(0, p + OCT_REG_CR_OFF);
 425         iounmap(p);
 426 }
 427
 428 /*
 429  * SIIG serial cards have an PCI interface chip which also controls
 430  * the UART clocking frequency. Each UART can be clocked independently
 431  * (except cards equipped with 4 UARTs) and initial clocking settings
 432  * are stored in the EEPROM chip. It can cause problems because this
 433  * version of serial driver doesn't support differently clocked UART's
 434  * on single PCI card. To prevent this, initialization functions set
 435  * high frequency clocking for all UART's on given card. It is safe (I
 436  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 437  * with other OSes (like M$ DOS).
 438  *
 439  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 440  *
 441  * There is two family of SIIG serial cards with different PCI
 442  * interface chip and different configuration methods:
 443  *     - 10x cards have control registers in IO and/or memory space;
 444  *     - 20x cards have control registers in standard PCI configuration space.
 445  *
 446  * Note: all 10x cards have PCI device ids 0x10..
 447  *       all 20x cards have PCI device ids 0x20..
 448  *
 449  * There are also Quartet Serial cards which use Oxford Semiconductor
 450  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 451  *
 452  * Note: some SIIG cards are probed by the parport_serial object.
 453  */
 454
 455 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 456 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 457
 458 static int pci_siig10x_init(struct pci_dev *dev)
 459 {
 460         u16 data;
 461         void __iomem *p;
 462
 463         switch (dev->device & 0xfff8) {
 464         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 465                 data = 0xffdf;
 466                 break;
 467         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 468                 data = 0xf7ff;
 469                 break;
 470         default:                        /* 1S1P, 4S */
 471                 data = 0xfffb;
 472                 break;
 473         }
 474
 475         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 476         if (p == NULL)
 477                 return -ENOMEM;
 478
 479         writew(readw(p + 0x28) & data, p + 0x28);
 480         readw(p + 0x28);
 481         iounmap(p);
 482         return 0;
 483 }
 484
 485 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 486 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 487
 488 static int pci_siig20x_init(struct pci_dev *dev)
 489 {
 490         u8 data;
 491
 492         /* Change clock frequency for the first UART. */
 493         pci_read_config_byte(dev, 0x6f, &data);
 494         pci_write_config_byte(dev, 0x6f, data & 0xef);
 495
 496         /* If this card has 2 UART, we have to do the same with second UART. */
 497         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 498             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 499                 pci_read_config_byte(dev, 0x73, &data);
 500                 pci_write_config_byte(dev, 0x73, data & 0xef);
 501         }
 502         return 0;
 503 }
 504
 505 static int pci_siig_init(struct pci_dev *dev)
 506 {
 507         unsigned int type = dev->device & 0xff00;
 508
 509         if (type == 0x1000)
 510                 return pci_siig10x_init(dev);
 511         else if (type == 0x2000)
 512                 return pci_siig20x_init(dev);
 513
 514         moan_device("Unknown SIIG card", dev);
 515         return -ENODEV;
 516 }
 517
 518 static int pci_siig_setup(struct serial_private *priv,
 519                           const struct pciserial_board *board,
 520                           struct uart_8250_port *port, int idx)
 521 {
 522         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 523
 524         if (idx > 3) {
 525                 bar = 4;
 526                 offset = (idx - 4) * 8;
 527         }
 528
 529         return setup_port(priv, port, bar, offset, 0);
 530 }
 531
 532 /*
 533  * Timedia has an explosion of boards, and to avoid the PCI table from
 534  * growing *huge*, we use this function to collapse some 70 entries
 535  * in the PCI table into one, for sanity's and compactness's sake.
 536  */
 537 static const unsigned short timedia_single_port[] = {
 538         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 539 };
 540
 541 static const unsigned short timedia_dual_port[] = {
 542         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 543         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 544         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 545         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 546         0xD079, 0
 547 };
 548
 549 static const unsigned short timedia_quad_port[] = {
 550         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 551         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 552         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 553         0xB157, 0
 554 };
 555
 556 static const unsigned short timedia_eight_port[] = {
 557         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 558         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 559 };
 560
 561 static const struct timedia_struct {
 562         int num;
 563         const unsigned short *ids;
 564 } timedia_data[] = {
 565         { 1, timedia_single_port },
 566         { 2, timedia_dual_port },
 567         { 4, timedia_quad_port },
 568         { 8, timedia_eight_port }
 569 };
 570
 571 /*
 572  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 573  * listing them individually, this driver merely grabs them all with
 574  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 575  * and should be left free to be claimed by parport_serial instead.
 576  */
 577 static int pci_timedia_probe(struct pci_dev *dev)
 578 {
 579         /*
 580          * Check the third digit of the subdevice ID
 581          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 582          */
 583         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 584                 dev_info(&dev->dev,
 585                         "ignoring Timedia subdevice %04x for parport_serial\n",
 586                         dev->subsystem_device);
 587                 return -ENODEV;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int pci_timedia_init(struct pci_dev *dev)
 594 {
 595         const unsigned short *ids;
 596         int i, j;
 597
 598         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 599                 ids = timedia_data[i].ids;
 600                 for (j = 0; ids[j]; j++)
 601                         if (dev->subsystem_device == ids[j])
 602                                 return timedia_data[i].num;
 603         }
 604         return 0;
 605 }
 606
 607 /*
 608  * Timedia/SUNIX uses a mixture of BARs and offsets
 609  * Ugh, this is ugly as all hell --- TYT
 610  */
 611 static int
 612 pci_timedia_setup(struct serial_private *priv,
 613                   const struct pciserial_board *board,
 614                   struct uart_8250_port *port, int idx)
 615 {
 616         unsigned int bar = 0, offset = board->first_offset;
 617
 618         switch (idx) {
 619         case 0:
 620                 bar = 0;
 621                 break;
 622         case 1:
 623                 offset = board->uart_offset;
 624                 bar = 0;
 625                 break;
 626         case 2:
 627                 bar = 1;
 628                 break;
 629         case 3:
 630                 offset = board->uart_offset;
 631                 /* FALLTHROUGH */
 632         case 4: /* BAR 2 */
 633         case 5: /* BAR 3 */
 634         case 6: /* BAR 4 */
 635         case 7: /* BAR 5 */
 636                 bar = idx - 2;
 637         }
 638
 639         return setup_port(priv, port, bar, offset, board->reg_shift);
 640 }
 641
 642 /*
 643  * Some Titan cards are also a little weird
 644  */
 645 static int
 646 titan_400l_800l_setup(struct serial_private *priv,
 647                       const struct pciserial_board *board,
 648                       struct uart_8250_port *port, int idx)
 649 {
 650         unsigned int bar, offset = board->first_offset;
 651
 652         switch (idx) {
 653         case 0:
 654                 bar = 1;
 655                 break;
 656         case 1:
 657                 bar = 2;
 658                 break;
 659         default:
 660                 bar = 4;
 661                 offset = (idx - 2) * board->uart_offset;
 662         }
 663
 664         return setup_port(priv, port, bar, offset, board->reg_shift);
 665 }
 666
 667 static int pci_xircom_init(struct pci_dev *dev)
 668 {
 669         msleep(100);
 670         return 0;
 671 }
 672
 673 static int pci_ni8420_init(struct pci_dev *dev)
 674 {
 675         void __iomem *p;
 676         unsigned int bar = 0;
 677
 678         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 679                 moan_device("no memory in bar", dev);
 680                 return 0;
 681         }
 682
 683         p = pci_ioremap_bar(dev, bar);
 684         if (p == NULL)
 685                 return -ENOMEM;
 686
 687         /* Enable CPU Interrupt */
 688         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 689                p + NI8420_INT_ENABLE_REG);
 690
 691         iounmap(p);
 692         return 0;
 693 }
 694
 695 #define MITE_IOWBSR1_WSIZE      0xa
 696 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 697 #define MITE_IOWBSR1_WENAB      (1 << 7)
 698 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 699 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 700 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 701
 702 static int pci_ni8430_init(struct pci_dev *dev)
 703 {
 704         void __iomem *p;
 705         struct pci_bus_region region;
 706         u32 device_window;
 707         unsigned int bar = 0;
 708
 709         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 710                 moan_device("no memory in bar", dev);
 711                 return 0;
 712         }
 713
 714         p = pci_ioremap_bar(dev, bar);
 715         if (p == NULL)
 716                 return -ENOMEM;
 717
 718         /*
 719          * Set device window address and size in BAR0, while acknowledging that
 720          * the resource structure may contain a translated address that differs
 721          * from the address the device responds to.
 722          */
 723         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 724         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 725                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 726         writel(device_window, p + MITE_IOWBSR1);
 727
 728         /* Set window access to go to RAMSEL IO address space */
 729         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 730                p + MITE_IOWCR1);
 731
 732         /* Enable IO Bus Interrupt 0 */
 733         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 734
 735         /* Enable CPU Interrupt */
 736         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 737
 738         iounmap(p);
 739         return 0;
 740 }
 741
 742 /* UART Port Control Register */
 743 #define NI8430_PORTCON  0x0f
 744 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 745
 746 static int
 747 pci_ni8430_setup(struct serial_private *priv,
 748                  const struct pciserial_board *board,
 749                  struct uart_8250_port *port, int idx)
 750 {
 751         struct pci_dev *dev = priv->dev;
 752         void __iomem *p;
 753         unsigned int bar, offset = board->first_offset;
 754
 755         if (idx >= board->num_ports)
 756                 return 1;
 757
 758         bar = FL_GET_BASE(board->flags);
 759         offset += idx * board->uart_offset;
 760
 761         p = pci_ioremap_bar(dev, bar);
 762         if (!p)
 763                 return -ENOMEM;
 764
 765         /* enable the transceiver */
 766         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 767                p + offset + NI8430_PORTCON);
 768
 769         iounmap(p);
 770
 771         return setup_port(priv, port, bar, offset, board->reg_shift);
 772 }
 773
 774 static int pci_netmos_9900_setup(struct serial_private *priv,
 775                                 const struct pciserial_board *board,
 776                                 struct uart_8250_port *port, int idx)
 777 {
 778         unsigned int bar;
 779
 780         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 781             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 782                 /* netmos apparently orders BARs by datasheet layout, so serial
 783                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 784                  */
 785                 bar = 3 * idx;
 786
 787                 return setup_port(priv, port, bar, 0, board->reg_shift);
 788         } else {
 789                 return pci_default_setup(priv, board, port, idx);
 790         }
 791 }
 792
 793 /* the 99xx series comes with a range of device IDs and a variety
 794  * of capabilities:
 795  *
 796  * 9900 has varying capabilities and can cascade to sub-controllers
 797  *   (cascading should be purely internal)
 798  * 9904 is hardwired with 4 serial ports
 799  * 9912 and 9922 are hardwired with 2 serial ports
 800  */
 801 static int pci_netmos_9900_numports(struct pci_dev *dev)
 802 {
 803         unsigned int c = dev->class;
 804         unsigned int pi;
 805         unsigned short sub_serports;
 806
 807         pi = (c & 0xff);
 808
 809         if (pi == 2) {
 810                 return 1;
 811         } else if ((pi == 0) &&
 812                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 813                 /* two possibilities: 0x30ps encodes number of parallel and
 814                  * serial ports, or 0x1000 indicates *something*. This is not
 815                  * immediately obvious, since the 2s1p+4s configuration seems
 816                  * to offer all functionality on functions 0..2, while still
 817                  * advertising the same function 3 as the 4s+2s1p config.
 818                  */
 819                 sub_serports = dev->subsystem_device & 0xf;
 820                 if (sub_serports > 0) {
 821                         return sub_serports;
 822                 } else {
 823                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 824                         return 0;
 825                 }
 826         }
 827
 828         moan_device("unknown NetMos/Mostech program interface", dev);
 829         return 0;
 830 }
 831
 832 static int pci_netmos_init(struct pci_dev *dev)
 833 {
 834         /* subdevice 0x00PS means <P> parallel, <S> serial */
 835         unsigned int num_serial = dev->subsystem_device & 0xf;
 836
 837         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 838                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 839                 return 0;
 840
 841         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 842                         dev->subsystem_device == 0x0299)
 843                 return 0;
 844
 845         switch (dev->device) { /* FALLTHROUGH on all */
 846                 case PCI_DEVICE_ID_NETMOS_9904:
 847                 case PCI_DEVICE_ID_NETMOS_9912:
 848                 case PCI_DEVICE_ID_NETMOS_9922:
 849                 case PCI_DEVICE_ID_NETMOS_9900:
 850                         num_serial = pci_netmos_9900_numports(dev);
 851                         break;
 852
 853                 default:
 854                         if (num_serial == 0 ) {
 855                                 moan_device("unknown NetMos/Mostech device", dev);
 856                         }
 857         }
 858
 859         if (num_serial == 0)
 860                 return -ENODEV;
 861
 862         return num_serial;
 863 }
 864
 865 /*
 866  * These chips are available with optionally one parallel port and up to
 867  * two serial ports. Unfortunately they all have the same product id.
 868  *
 869  * Basic configuration is done over a region of 32 I/O ports. The base
 870  * ioport is called INTA or INTC, depending on docs/other drivers.
 871  *
 872  * The region of the 32 I/O ports is configured in POSIO0R...
 873  */
 874
 875 /* registers */
 876 #define ITE_887x_MISCR          0x9c
 877 #define ITE_887x_INTCBAR        0x78
 878 #define ITE_887x_UARTBAR        0x7c
 879 #define ITE_887x_PS0BAR         0x10
 880 #define ITE_887x_POSIO0         0x60
 881
 882 /* I/O space size */
 883 #define ITE_887x_IOSIZE         32
 884 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 885 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 886 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 887 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 888 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 889 #define ITE_887x_POSIO_SPEED            (3 << 29)
 890 /* enable IO_Space bit */
 891 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 892
 893 static int pci_ite887x_init(struct pci_dev *dev)
 894 {
 895         /* inta_addr are the configuration addresses of the ITE */
 896         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 897                                                         0x200, 0x280, 0 };
 898         int ret, i, type;
 899         struct resource *iobase = NULL;
 900         u32 miscr, uartbar, ioport;
 901
 902         /* search for the base-ioport */
 903         i = 0;
 904         while (inta_addr[i] && iobase == NULL) {
 905                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 906                                                                 "ite887x");
 907                 if (iobase != NULL) {
 908                         /* write POSIO0R - speed | size | ioport */
 909                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 910                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 911                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 912                         /* write INTCBAR - ioport */
 913                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 914                                                                 inta_addr[i]);
 915                         ret = inb(inta_addr[i]);
 916                         if (ret != 0xff) {
 917                                 /* ioport connected */
 918                                 break;
 919                         }
 920                         release_region(iobase->start, ITE_887x_IOSIZE);
 921                         iobase = NULL;
 922                 }
 923                 i++;
 924         }
 925
 926         if (!inta_addr[i]) {
 927                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 928                 return -ENODEV;
 929         }
 930
 931         /* start of undocumented type checking (see parport_pc.c) */
 932         type = inb(iobase->start + 0x18) & 0x0f;
 933
 934         switch (type) {
 935         case 0x2:       /* ITE8871 (1P) */
 936         case 0xa:       /* ITE8875 (1P) */
 937                 ret = 0;
 938                 break;
 939         case 0xe:       /* ITE8872 (2S1P) */
 940                 ret = 2;
 941                 break;
 942         case 0x6:       /* ITE8873 (1S) */
 943                 ret = 1;
 944                 break;
 945         case 0x8:       /* ITE8874 (2S) */
 946                 ret = 2;
 947                 break;
 948         default:
 949                 moan_device("Unknown ITE887x", dev);
 950                 ret = -ENODEV;
 951         }
 952
 953         /* configure all serial ports */
 954         for (i = 0; i < ret; i++) {
 955                 /* read the I/O port from the device */
 956                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 957                                                                 &ioport);
 958                 ioport &= 0x0000FF00;   /* the actual base address */
 959                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 960                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 961                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 962
 963                 /* write the ioport to the UARTBAR */
 964                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 965                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 966                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 967                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 968
 969                 /* get current config */
 970                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 971                 /* disable interrupts (UARTx_Routing[3:0]) */
 972                 miscr &= ~(0xf << (12 - 4 * i));
 973                 /* activate the UART (UARTx_En) */
 974                 miscr |= 1 << (23 - i);
 975                 /* write new config with activated UART */
 976                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 977         }
 978
 979         if (ret <= 0) {
 980                 /* the device has no UARTs if we get here */
 981                 release_region(iobase->start, ITE_887x_IOSIZE);
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void pci_ite887x_exit(struct pci_dev *dev)
 988 {
 989         u32 ioport;
 990         /* the ioport is bit 0-15 in POSIO0R */
 991         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 992         ioport &= 0xffff;
 993         release_region(ioport, ITE_887x_IOSIZE);
 994 }
 995
 996 /*
 997  * EndRun Technologies.
 998  * Determine the number of ports available on the device.
 999  */
1000 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1002
1003 static int pci_endrun_init(struct pci_dev *dev)
1004 {
1005         u8 __iomem *p;
1006         unsigned long deviceID;
1007         unsigned int  number_uarts = 0;
1008
1009         /* EndRun device is all 0xexxx */
1010         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011                 (dev->device & 0xf000) != 0xe000)
1012                 return 0;
1013
1014         p = pci_iomap(dev, 0, 5);
1015         if (p == NULL)
1016                 return -ENOMEM;
1017
1018         deviceID = ioread32(p);
1019         /* EndRun device */
1020         if (deviceID == 0x07000200) {
1021                 number_uarts = ioread8(p + 4);
1022                 dev_dbg(&dev->dev,
1023                         "%d ports detected on EndRun PCI Express device\n",
1024                         number_uarts);
1025         }
1026         pci_iounmap(dev, p);
1027         return number_uarts;
1028 }
1029
1030 /*
1031  * Oxford Semiconductor Inc.
1032  * Check that device is part of the Tornado range of devices, then determine
1033  * the number of ports available on the device.
1034  */
1035 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 {
1037         u8 __iomem *p;
1038         unsigned long deviceID;
1039         unsigned int  number_uarts = 0;
1040
1041         /* OxSemi Tornado devices are all 0xCxxx */
1042         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043             (dev->device & 0xF000) != 0xC000)
1044                 return 0;
1045
1046         p = pci_iomap(dev, 0, 5);
1047         if (p == NULL)
1048                 return -ENOMEM;
1049
1050         deviceID = ioread32(p);
1051         /* Tornado device */
1052         if (deviceID == 0x07000200) {
1053                 number_uarts = ioread8(p + 4);
1054                 dev_dbg(&dev->dev,
1055                         "%d ports detected on Oxford PCI Express device\n",
1056                         number_uarts);
1057         }
1058         pci_iounmap(dev, p);
1059         return number_uarts;
1060 }
1061
1062 static int pci_asix_setup(struct serial_private *priv,
1063                   const struct pciserial_board *board,
1064                   struct uart_8250_port *port, int idx)
1065 {
1066         port->bugs |= UART_BUG_PARITY;
1067         return pci_default_setup(priv, board, port, idx);
1068 }
1069
1070 /* Quatech devices have their own extra interface features */
1071
1072 struct quatech_feature {
1073         u16 devid;
1074         bool amcc;
1075 };
1076
1077 #define QPCR_TEST_FOR1          0x3F
1078 #define QPCR_TEST_GET1          0x00
1079 #define QPCR_TEST_FOR2          0x40
1080 #define QPCR_TEST_GET2          0x40
1081 #define QPCR_TEST_FOR3          0x80
1082 #define QPCR_TEST_GET3          0x40
1083 #define QPCR_TEST_FOR4          0xC0
1084 #define QPCR_TEST_GET4          0x80
1085
1086 #define QOPR_CLOCK_X1           0x0000
1087 #define QOPR_CLOCK_X2           0x0001
1088 #define QOPR_CLOCK_X4           0x0002
1089 #define QOPR_CLOCK_X8           0x0003
1090 #define QOPR_CLOCK_RATE_MASK    0x0003
1091
1092
1093 static struct quatech_feature quatech_cards[] = {
1094         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1096         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1098         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1100         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1101         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1103         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1105         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113         { 0, }
1114 };
1115
1116 static int pci_quatech_amcc(u16 devid)
1117 {
1118         struct quatech_feature *qf = &quatech_cards[0];
1119         while (qf->devid) {
1120                 if (qf->devid == devid)
1121                         return qf->amcc;
1122                 qf++;
1123         }
1124         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125         return 0;
1126 };
1127
1128 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 {
1130         unsigned long base = port->port.iobase;
1131         u8 LCR, val;
1132
1133         LCR = inb(base + UART_LCR);
1134         outb(0xBF, base + UART_LCR);
1135         val = inb(base + UART_SCR);
1136         outb(LCR, base + UART_LCR);
1137         return val;
1138 }
1139
1140 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(qopr, base + UART_SCR);
1149         outb(LCR, base + UART_LCR);
1150 }
1151
1152 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 {
1154         unsigned long base = port->port.iobase;
1155         u8 LCR, val, qmcr;
1156
1157         LCR = inb(base + UART_LCR);
1158         outb(0xBF, base + UART_LCR);
1159         val = inb(base + UART_SCR);
1160         outb(val | 0x10, base + UART_SCR);
1161         qmcr = inb(base + UART_MCR);
1162         outb(val, base + UART_SCR);
1163         outb(LCR, base + UART_LCR);
1164
1165         return qmcr;
1166 }
1167
1168 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 {
1170         unsigned long base = port->port.iobase;
1171         u8 LCR, val;
1172
1173         LCR = inb(base + UART_LCR);
1174         outb(0xBF, base + UART_LCR);
1175         val = inb(base + UART_SCR);
1176         outb(val | 0x10, base + UART_SCR);
1177         outb(qmcr, base + UART_MCR);
1178         outb(val, base + UART_SCR);
1179         outb(LCR, base + UART_LCR);
1180 }
1181
1182 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 {
1184         unsigned long base = port->port.iobase;
1185         u8 LCR, val;
1186
1187         LCR = inb(base + UART_LCR);
1188         outb(0xBF, base + UART_LCR);
1189         val = inb(base + UART_SCR);
1190         if (val & 0x20) {
1191                 outb(0x80, UART_LCR);
1192                 if (!(inb(UART_SCR) & 0x20)) {
1193                         outb(LCR, base + UART_LCR);
1194                         return 1;
1195                 }
1196         }
1197         return 0;
1198 }
1199
1200 static int pci_quatech_test(struct uart_8250_port *port)
1201 {
1202         u8 reg;
1203         u8 qopr = pci_quatech_rqopr(port);
1204         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205         reg = pci_quatech_rqopr(port) & 0xC0;
1206         if (reg != QPCR_TEST_GET1)
1207                 return -EINVAL;
1208         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209         reg = pci_quatech_rqopr(port) & 0xC0;
1210         if (reg != QPCR_TEST_GET2)
1211                 return -EINVAL;
1212         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213         reg = pci_quatech_rqopr(port) & 0xC0;
1214         if (reg != QPCR_TEST_GET3)
1215                 return -EINVAL;
1216         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217         reg = pci_quatech_rqopr(port) & 0xC0;
1218         if (reg != QPCR_TEST_GET4)
1219                 return -EINVAL;
1220
1221         pci_quatech_wqopr(port, qopr);
1222         return 0;
1223 }
1224
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227         u8 qopr, reg, set;
1228         unsigned long clock;
1229
1230         if (pci_quatech_test(port) < 0)
1231                 return 1843200;
1232
1233         qopr = pci_quatech_rqopr(port);
1234
1235         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236         reg = pci_quatech_rqopr(port);
1237         if (reg & QOPR_CLOCK_X8) {
1238                 clock = 1843200;
1239                 goto out;
1240         }
1241         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (!(reg & QOPR_CLOCK_X8)) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         reg &= QOPR_CLOCK_X8;
1248         if (reg == QOPR_CLOCK_X2) {
1249                 clock =  3685400;
1250                 set = QOPR_CLOCK_X2;
1251         } else if (reg == QOPR_CLOCK_X4) {
1252                 clock = 7372800;
1253                 set = QOPR_CLOCK_X4;
1254         } else if (reg == QOPR_CLOCK_X8) {
1255                 clock = 14745600;
1256                 set = QOPR_CLOCK_X8;
1257         } else {
1258                 clock = 1843200;
1259                 set = QOPR_CLOCK_X1;
1260         }
1261         qopr &= ~QOPR_CLOCK_RATE_MASK;
1262         qopr |= set;
1263
1264 out:
1265         pci_quatech_wqopr(port, qopr);
1266         return clock;
1267 }
1268
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271         u8 qmcr;
1272         int rs422 = 0;
1273
1274         if (!pci_quatech_has_qmcr(port))
1275                 return 0;
1276         qmcr = pci_quatech_rqmcr(port);
1277         pci_quatech_wqmcr(port, 0xFF);
1278         if (pci_quatech_rqmcr(port))
1279                 rs422 = 1;
1280         pci_quatech_wqmcr(port, qmcr);
1281         return rs422;
1282 }
1283
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286         if (pci_quatech_amcc(dev->device)) {
1287                 unsigned long base = pci_resource_start(dev, 0);
1288                 if (base) {
1289                         u32 tmp;
1290                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1291                         tmp = inl(base + 0x3c);
1292                         outl(tmp | 0x01000000, base + 0x3c);
1293                         outl(tmp &= ~0x01000000, base + 0x3c);
1294                 }
1295         }
1296         return 0;
1297 }
1298
1299 static int pci_quatech_setup(struct serial_private *priv,
1300                   const struct pciserial_board *board,
1301                   struct uart_8250_port *port, int idx)
1302 {
1303         /* Needed by pci_quatech calls below */
1304         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305         /* Set up the clocking */
1306         port->port.uartclk = pci_quatech_clock(port);
1307         /* For now just warn about RS422 */
1308         if (pci_quatech_rs422(port))
1309                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310         return pci_default_setup(priv, board, port, idx);
1311 }
1312
1313 static void pci_quatech_exit(struct pci_dev *dev)
1314 {
1315 }
1316
1317 static int pci_default_setup(struct serial_private *priv,
1318                   const struct pciserial_board *board,
1319                   struct uart_8250_port *port, int idx)
1320 {
1321         unsigned int bar, offset = board->first_offset, maxnr;
1322
1323         bar = FL_GET_BASE(board->flags);
1324         if (board->flags & FL_BASE_BARS)
1325                 bar += idx;
1326         else
1327                 offset += idx * board->uart_offset;
1328
1329         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330                 (board->reg_shift + 3);
1331
1332         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333                 return 1;
1334
1335         return setup_port(priv, port, bar, offset, board->reg_shift);
1336 }
1337
1338 static int pci_pericom_setup(struct serial_private *priv,
1339                   const struct pciserial_board *board,
1340                   struct uart_8250_port *port, int idx)
1341 {
1342         unsigned int bar, offset = board->first_offset, maxnr;
1343
1344         bar = FL_GET_BASE(board->flags);
1345         if (board->flags & FL_BASE_BARS)
1346                 bar += idx;
1347         else
1348                 offset += idx * board->uart_offset;
1349
1350         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351                 (board->reg_shift + 3);
1352
1353         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354                 return 1;
1355
1356         port->port.uartclk = 14745600;
1357
1358         return setup_port(priv, port, bar, offset, board->reg_shift);
1359 }
1360
1361 static int
1362 ce4100_serial_setup(struct serial_private *priv,
1363                   const struct pciserial_board *board,
1364                   struct uart_8250_port *port, int idx)
1365 {
1366         int ret;
1367
1368         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1369         port->port.iotype = UPIO_MEM32;
1370         port->port.type = PORT_XSCALE;
1371         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372         port->port.regshift = 2;
1373
1374         return ret;
1375 }
1376
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1378 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1379
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1381 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1382
1383 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1384 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1385
1386 #define BYT_PRV_CLK                     0x800
1387 #define BYT_PRV_CLK_EN                  (1 << 0)
1388 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1389 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1390 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1391
1392 #define BYT_TX_OVF_INT                  0x820
1393 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1394
1395 static void
1396 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1397                 struct ktermios *old)
1398 {
1399         unsigned int baud = tty_termios_baud_rate(termios);
1400         unsigned long fref = 100000000, fuart = baud * 16;
1401         unsigned long w = BIT(15) - 1;
1402         unsigned long m, n;
1403         u32 reg;
1404
1405         /* Gracefully handle the B0 case: fall back to B9600 */
1406         fuart = fuart ? fuart : 9600 * 16;
1407
1408         /* Get Fuart closer to Fref */
1409         fuart *= rounddown_pow_of_two(fref / fuart);
1410
1411         /*
1412          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1413          * dividers must be adjusted.
1414          *
1415          * uartclk = (m / n) * 100 MHz, where m <= n
1416          */
1417         rational_best_approximation(fuart, fref, w, w, &m, &n);
1418         p->uartclk = fuart;
1419
1420         /* Reset the clock */
1421         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1422         writel(reg, p->membase + BYT_PRV_CLK);
1423         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1424         writel(reg, p->membase + BYT_PRV_CLK);
1425
1426         p->status &= ~UPSTAT_AUTOCTS;
1427         if (termios->c_cflag & CRTSCTS)
1428                 p->status |= UPSTAT_AUTOCTS;
1429
1430         serial8250_do_set_termios(p, termios, old);
1431 }
1432
1433 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1434 {
1435         struct dw_dma_slave *dws = param;
1436
1437         if (dws->dma_dev != chan->device->dev)
1438                 return false;
1439
1440         chan->private = dws;
1441         return true;
1442 }
1443
1444 static int
1445 byt_serial_setup(struct serial_private *priv,
1446                  const struct pciserial_board *board,
1447                  struct uart_8250_port *port, int idx)
1448 {
1449         struct pci_dev *pdev = priv->dev;
1450         struct device *dev = port->port.dev;
1451         struct uart_8250_dma *dma;
1452         struct dw_dma_slave *tx_param, *rx_param;
1453         struct pci_dev *dma_dev;
1454         int ret;
1455
1456         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1457         if (!dma)
1458                 return -ENOMEM;
1459
1460         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1461         if (!tx_param)
1462                 return -ENOMEM;
1463
1464         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1465         if (!rx_param)
1466                 return -ENOMEM;
1467
1468         switch (pdev->device) {
1469         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1470         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1471         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1472                 rx_param->src_id = 3;
1473                 tx_param->dst_id = 2;
1474                 break;
1475         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1476         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1477         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1478                 rx_param->src_id = 5;
1479                 tx_param->dst_id = 4;
1480                 break;
1481         default:
1482                 return -EINVAL;
1483         }
1484
1485         rx_param->src_master = 1;
1486         rx_param->dst_master = 0;
1487
1488         dma->rxconf.src_maxburst = 16;
1489
1490         tx_param->src_master = 1;
1491         tx_param->dst_master = 0;
1492
1493         dma->txconf.dst_maxburst = 16;
1494
1495         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1496         rx_param->dma_dev = &dma_dev->dev;
1497         tx_param->dma_dev = &dma_dev->dev;
1498
1499         dma->fn = byt_dma_filter;
1500         dma->rx_param = rx_param;
1501         dma->tx_param = tx_param;
1502
1503         ret = pci_default_setup(priv, board, port, idx);
1504         port->port.iotype = UPIO_MEM;
1505         port->port.type = PORT_16550A;
1506         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1507         port->port.set_termios = byt_set_termios;
1508         port->port.fifosize = 64;
1509         port->tx_loadsz = 64;
1510         port->dma = dma;
1511         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1512
1513         /* Disable Tx counter interrupts */
1514         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1515
1516         return ret;
1517 }
1518
1519 static int
1520 pci_omegapci_setup(struct serial_private *priv,
1521                       const struct pciserial_board *board,
1522                       struct uart_8250_port *port, int idx)
1523 {
1524         return setup_port(priv, port, 2, idx * 8, 0);
1525 }
1526
1527 static int
1528 pci_brcm_trumanage_setup(struct serial_private *priv,
1529                          const struct pciserial_board *board,
1530                          struct uart_8250_port *port, int idx)
1531 {
1532         int ret = pci_default_setup(priv, board, port, idx);
1533
1534         port->port.type = PORT_BRCM_TRUMANAGE;
1535         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1536         return ret;
1537 }
1538
1539 /* RTS will control by MCR if this bit is 0 */
1540 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1541 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1542 #define FINTEK_RTS_INVERT               BIT(5)
1543
1544 /* We should do proper H/W transceiver setting before change to RS485 mode */
1545 static int pci_fintek_rs485_config(struct uart_port *port,
1546                                struct serial_rs485 *rs485)
1547 {
1548         u8 setting;
1549         u8 *index = (u8 *) port->private_data;
1550         struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1551                                                 dev);
1552
1553         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1554
1555         if (!rs485)
1556                 rs485 = &port->rs485;
1557         else if (rs485->flags & SER_RS485_ENABLED)
1558                 memset(rs485->padding, 0, sizeof(rs485->padding));
1559         else
1560                 memset(rs485, 0, sizeof(*rs485));
1561
1562         /* F81504/508/512 not support RTS delay before or after send */
1563         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1564
1565         if (rs485->flags & SER_RS485_ENABLED) {
1566                 /* Enable RTS H/W control mode */
1567                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1568
1569                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1570                         /* RTS driving high on TX */
1571                         setting &= ~FINTEK_RTS_INVERT;
1572                 } else {
1573                         /* RTS driving low on TX */
1574                         setting |= FINTEK_RTS_INVERT;
1575                 }
1576
1577                 rs485->delay_rts_after_send = 0;
1578                 rs485->delay_rts_before_send = 0;
1579         } else {
1580                 /* Disable RTS H/W control mode */
1581                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1582         }
1583
1584         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1585
1586         if (rs485 != &port->rs485)
1587                 port->rs485 = *rs485;
1588
1589         return 0;
1590 }
1591
1592 static int pci_fintek_setup(struct serial_private *priv,
1593                             const struct pciserial_board *board,
1594                             struct uart_8250_port *port, int idx)
1595 {
1596         struct pci_dev *pdev = priv->dev;
1597         u8 *data;
1598         u8 config_base;
1599         u16 iobase;
1600
1601         config_base = 0x40 + 0x08 * idx;
1602
1603         /* Get the io address from configuration space */
1604         pci_read_config_word(pdev, config_base + 4, &iobase);
1605
1606         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1607
1608         port->port.iotype = UPIO_PORT;
1609         port->port.iobase = iobase;
1610         port->port.rs485_config = pci_fintek_rs485_config;
1611
1612         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1613         if (!data)
1614                 return -ENOMEM;
1615
1616         /* preserve index in PCI configuration space */
1617         *data = idx;
1618         port->port.private_data = data;
1619
1620         return 0;
1621 }
1622
1623 static int pci_fintek_init(struct pci_dev *dev)
1624 {
1625         unsigned long iobase;
1626         u32 max_port, i;
1627         u32 bar_data[3];
1628         u8 config_base;
1629         struct serial_private *priv = pci_get_drvdata(dev);
1630         struct uart_8250_port *port;
1631
1632         switch (dev->device) {
1633         case 0x1104: /* 4 ports */
1634         case 0x1108: /* 8 ports */
1635                 max_port = dev->device & 0xff;
1636                 break;
1637         case 0x1112: /* 12 ports */
1638                 max_port = 12;
1639                 break;
1640         default:
1641                 return -EINVAL;
1642         }
1643
1644         /* Get the io address dispatch from the BIOS */
1645         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1646         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1647         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1648
1649         for (i = 0; i < max_port; ++i) {
1650                 /* UART0 configuration offset start from 0x40 */
1651                 config_base = 0x40 + 0x08 * i;
1652
1653                 /* Calculate Real IO Port */
1654                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1655
1656                 /* Enable UART I/O port */
1657                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1658
1659                 /* Select 128-byte FIFO and 8x FIFO threshold */
1660                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1661
1662                 /* LSB UART */
1663                 pci_write_config_byte(dev, config_base + 0x04,
1664                                 (u8)(iobase & 0xff));
1665
1666                 /* MSB UART */
1667                 pci_write_config_byte(dev, config_base + 0x05,
1668                                 (u8)((iobase & 0xff00) >> 8));
1669
1670                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1671
1672                 if (priv) {
1673                         /* re-apply RS232/485 mode when
1674                          * pciserial_resume_ports()
1675                          */
1676                         port = serial8250_get_port(priv->line[i]);
1677                         pci_fintek_rs485_config(&port->port, NULL);
1678                 } else {
1679                         /* First init without port data
1680                          * force init to RS232 Mode
1681                          */
1682                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1683                 }
1684         }
1685
1686         return max_port;
1687 }
1688
1689 static int skip_tx_en_setup(struct serial_private *priv,
1690                         const struct pciserial_board *board,
1691                         struct uart_8250_port *port, int idx)
1692 {
1693         port->port.flags |= UPF_NO_TXEN_TEST;
1694         dev_dbg(&priv->dev->dev,
1695                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1696                 priv->dev->vendor, priv->dev->device,
1697                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1698
1699         return pci_default_setup(priv, board, port, idx);
1700 }
1701
1702 static void kt_handle_break(struct uart_port *p)
1703 {
1704         struct uart_8250_port *up = up_to_u8250p(p);
1705         /*
1706          * On receipt of a BI, serial device in Intel ME (Intel
1707          * management engine) needs to have its fifos cleared for sane
1708          * SOL (Serial Over Lan) output.
1709          */
1710         serial8250_clear_and_reinit_fifos(up);
1711 }
1712
1713 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1714 {
1715         struct uart_8250_port *up = up_to_u8250p(p);
1716         unsigned int val;
1717
1718         /*
1719          * When the Intel ME (management engine) gets reset its serial
1720          * port registers could return 0 momentarily.  Functions like
1721          * serial8250_console_write, read and save the IER, perform
1722          * some operation and then restore it.  In order to avoid
1723          * setting IER register inadvertently to 0, if the value read
1724          * is 0, double check with ier value in uart_8250_port and use
1725          * that instead.  up->ier should be the same value as what is
1726          * currently configured.
1727          */
1728         val = inb(p->iobase + offset);
1729         if (offset == UART_IER) {
1730                 if (val == 0)
1731                         val = up->ier;
1732         }
1733         return val;
1734 }
1735
1736 static int kt_serial_setup(struct serial_private *priv,
1737                            const struct pciserial_board *board,
1738                            struct uart_8250_port *port, int idx)
1739 {
1740         port->port.flags |= UPF_BUG_THRE;
1741         port->port.serial_in = kt_serial_in;
1742         port->port.handle_break = kt_handle_break;
1743         return skip_tx_en_setup(priv, board, port, idx);
1744 }
1745
1746 static int pci_eg20t_init(struct pci_dev *dev)
1747 {
1748 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1749         return -ENODEV;
1750 #else
1751         return 0;
1752 #endif
1753 }
1754
1755 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1756 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1757
1758 static int
1759 pci_xr17c154_setup(struct serial_private *priv,
1760                   const struct pciserial_board *board,
1761                   struct uart_8250_port *port, int idx)
1762 {
1763         port->port.flags |= UPF_EXAR_EFR;
1764         return pci_default_setup(priv, board, port, idx);
1765 }
1766
1767 static inline int
1768 xr17v35x_has_slave(struct serial_private *priv)
1769 {
1770         const int dev_id = priv->dev->device;
1771
1772         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1773                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1774 }
1775
1776 static int
1777 pci_xr17v35x_setup(struct serial_private *priv,
1778                   const struct pciserial_board *board,
1779                   struct uart_8250_port *port, int idx)
1780 {
1781         u8 __iomem *p;
1782
1783         p = pci_ioremap_bar(priv->dev, 0);
1784         if (p == NULL)
1785                 return -ENOMEM;
1786
1787         port->port.flags |= UPF_EXAR_EFR;
1788
1789         /*
1790          * Setup the uart clock for the devices on expansion slot to
1791          * half the clock speed of the main chip (which is 125MHz)
1792          */
1793         if (xr17v35x_has_slave(priv) && idx >= 8)
1794                 port->port.uartclk = (7812500 * 16 / 2);
1795
1796         /*
1797          * Setup Multipurpose Input/Output pins.
1798          */
1799         if (idx == 0) {
1800                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1801                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1802                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1803                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1804                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1805                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1806                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1807                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1808                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1809                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1810                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1811                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1812         }
1813         writeb(0x00, p + UART_EXAR_8XMODE);
1814         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1815         writeb(128, p + UART_EXAR_TXTRG);
1816         writeb(128, p + UART_EXAR_RXTRG);
1817         iounmap(p);
1818
1819         return pci_default_setup(priv, board, port, idx);
1820 }
1821
1822 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1823 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1824 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1825 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1826
1827 static int
1828 pci_fastcom335_setup(struct serial_private *priv,
1829                   const struct pciserial_board *board,
1830                   struct uart_8250_port *port, int idx)
1831 {
1832         u8 __iomem *p;
1833
1834         p = pci_ioremap_bar(priv->dev, 0);
1835         if (p == NULL)
1836                 return -ENOMEM;
1837
1838         port->port.flags |= UPF_EXAR_EFR;
1839
1840         /*
1841          * Setup Multipurpose Input/Output pins.
1842          */
1843         if (idx == 0) {
1844                 switch (priv->dev->device) {
1845                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1846                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1847                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1848                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1849                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1850                         break;
1851                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1852                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1853                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1854                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1855                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1856                         break;
1857                 }
1858                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1859                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1860                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1861         }
1862         writeb(0x00, p + UART_EXAR_8XMODE);
1863         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1864         writeb(32, p + UART_EXAR_TXTRG);
1865         writeb(32, p + UART_EXAR_RXTRG);
1866         iounmap(p);
1867
1868         return pci_default_setup(priv, board, port, idx);
1869 }
1870
1871 static int
1872 pci_wch_ch353_setup(struct serial_private *priv,
1873                     const struct pciserial_board *board,
1874                     struct uart_8250_port *port, int idx)
1875 {
1876         port->port.flags |= UPF_FIXED_TYPE;
1877         port->port.type = PORT_16550A;
1878         return pci_default_setup(priv, board, port, idx);
1879 }
1880
1881 static int
1882 pci_wch_ch38x_setup(struct serial_private *priv,
1883                     const struct pciserial_board *board,
1884                     struct uart_8250_port *port, int idx)
1885 {
1886         port->port.flags |= UPF_FIXED_TYPE;
1887         port->port.type = PORT_16850;
1888         return pci_default_setup(priv, board, port, idx);
1889 }
1890
1891 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1892 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1893 #define PCI_DEVICE_ID_OCTPRO            0x0001
1894 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1895 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1896 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1897 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1898 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1899 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1900 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1901 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1902 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1903 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1904 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1905 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1906 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1907 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1908 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1909 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1910 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1911 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1912 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1913 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1914 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1915 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1916 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1917 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1918 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1919 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1920 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1921 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1922 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1923 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1924 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1925 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1926 #define PCI_VENDOR_ID_WCH               0x4348
1927 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1928 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1929 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1930 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1931 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1932 #define PCI_VENDOR_ID_AGESTAR           0x5372
1933 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1934 #define PCI_VENDOR_ID_ASIX              0x9710
1935 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1936 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1937 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1938 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1939 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1940 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1941
1942 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1943 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1944
1945 #define PCIE_VENDOR_ID_WCH              0x1c00
1946 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1947 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1948 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1949
1950 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1951 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1952 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1953 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1954 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1955
1956 #define PCI_VENDOR_ID_ACCESIO                   0x494f
1957 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB     0x1051
1958 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S      0x1053
1959 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB     0x105C
1960 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S      0x105E
1961 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB   0x1091
1962 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2    0x1093
1963 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB   0x1099
1964 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4    0x109B
1965 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB    0x10D1
1966 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM     0x10D3
1967 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB    0x10DA
1968 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM     0x10DC
1969 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1    0x1108
1970 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2    0x1110
1971 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2    0x1111
1972 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4    0x1118
1973 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4    0x1119
1974 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S       0x1152
1975 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S       0x115A
1976 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2     0x1190
1977 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2    0x1191
1978 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4     0x1198
1979 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4    0x1199
1980 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM      0x11D0
1981 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4     0x105A
1982 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4     0x105B
1983 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8     0x106A
1984 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8     0x106B
1985 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4     0x1098
1986 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8     0x10A9
1987 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM      0x10D9
1988 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM      0x10E9
1989 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM      0x11D8
1990
1991
1992
1993 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1994 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1995 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1996
1997 /*
1998  * Master list of serial port init/setup/exit quirks.
1999  * This does not describe the general nature of the port.
2000  * (ie, baud base, number and location of ports, etc)
2001  *
2002  * This list is ordered alphabetically by vendor then device.
2003  * Specific entries must come before more generic entries.
2004  */
2005 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2006         /*
2007         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2008         */
2009         {
2010                 .vendor         = PCI_VENDOR_ID_AMCC,
2011                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2012                 .subvendor      = PCI_ANY_ID,
2013                 .subdevice      = PCI_ANY_ID,
2014                 .setup          = addidata_apci7800_setup,
2015         },
2016         /*
2017          * AFAVLAB cards - these may be called via parport_serial
2018          *  It is not clear whether this applies to all products.
2019          */
2020         {
2021                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
2022                 .device         = PCI_ANY_ID,
2023                 .subvendor      = PCI_ANY_ID,
2024                 .subdevice      = PCI_ANY_ID,
2025                 .setup          = afavlab_setup,
2026         },
2027         /*
2028          * HP Diva
2029          */
2030         {
2031                 .vendor         = PCI_VENDOR_ID_HP,
2032                 .device         = PCI_DEVICE_ID_HP_DIVA,
2033                 .subvendor      = PCI_ANY_ID,
2034                 .subdevice      = PCI_ANY_ID,
2035                 .init           = pci_hp_diva_init,
2036                 .setup          = pci_hp_diva_setup,
2037         },
2038         /*
2039          * Intel
2040          */
2041         {
2042                 .vendor         = PCI_VENDOR_ID_INTEL,
2043                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2044                 .subvendor      = 0xe4bf,
2045                 .subdevice      = PCI_ANY_ID,
2046                 .init           = pci_inteli960ni_init,
2047                 .setup          = pci_default_setup,
2048         },
2049         {
2050                 .vendor         = PCI_VENDOR_ID_INTEL,
2051                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2052                 .subvendor      = PCI_ANY_ID,
2053                 .subdevice      = PCI_ANY_ID,
2054                 .setup          = skip_tx_en_setup,
2055         },
2056         {
2057                 .vendor         = PCI_VENDOR_ID_INTEL,
2058                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2059                 .subvendor      = PCI_ANY_ID,
2060                 .subdevice      = PCI_ANY_ID,
2061                 .setup          = skip_tx_en_setup,
2062         },
2063         {
2064                 .vendor         = PCI_VENDOR_ID_INTEL,
2065                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2066                 .subvendor      = PCI_ANY_ID,
2067                 .subdevice      = PCI_ANY_ID,
2068                 .setup          = skip_tx_en_setup,
2069         },
2070         {
2071                 .vendor         = PCI_VENDOR_ID_INTEL,
2072                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2073                 .subvendor      = PCI_ANY_ID,
2074                 .subdevice      = PCI_ANY_ID,
2075                 .setup          = ce4100_serial_setup,
2076         },
2077         {
2078                 .vendor         = PCI_VENDOR_ID_INTEL,
2079                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2080                 .subvendor      = PCI_ANY_ID,
2081                 .subdevice      = PCI_ANY_ID,
2082                 .setup          = kt_serial_setup,
2083         },
2084         {
2085                 .vendor         = PCI_VENDOR_ID_INTEL,
2086                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2087                 .subvendor      = PCI_ANY_ID,
2088                 .subdevice      = PCI_ANY_ID,
2089                 .setup          = byt_serial_setup,
2090         },
2091         {
2092                 .vendor         = PCI_VENDOR_ID_INTEL,
2093                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2094                 .subvendor      = PCI_ANY_ID,
2095                 .subdevice      = PCI_ANY_ID,
2096                 .setup          = byt_serial_setup,
2097         },
2098         {
2099                 .vendor         = PCI_VENDOR_ID_INTEL,
2100                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2101                 .subvendor      = PCI_ANY_ID,
2102                 .subdevice      = PCI_ANY_ID,
2103                 .setup          = byt_serial_setup,
2104         },
2105         {
2106                 .vendor         = PCI_VENDOR_ID_INTEL,
2107                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2108                 .subvendor      = PCI_ANY_ID,
2109                 .subdevice      = PCI_ANY_ID,
2110                 .setup          = byt_serial_setup,
2111         },
2112         {
2113                 .vendor         = PCI_VENDOR_ID_INTEL,
2114                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2115                 .subvendor      = PCI_ANY_ID,
2116                 .subdevice      = PCI_ANY_ID,
2117                 .setup          = byt_serial_setup,
2118         },
2119         {
2120                 .vendor         = PCI_VENDOR_ID_INTEL,
2121                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2122                 .subvendor      = PCI_ANY_ID,
2123                 .subdevice      = PCI_ANY_ID,
2124                 .setup          = byt_serial_setup,
2125         },
2126         /*
2127          * ITE
2128          */
2129         {
2130                 .vendor         = PCI_VENDOR_ID_ITE,
2131                 .device         = PCI_DEVICE_ID_ITE_8872,
2132                 .subvendor      = PCI_ANY_ID,
2133                 .subdevice      = PCI_ANY_ID,
2134                 .init           = pci_ite887x_init,
2135                 .setup          = pci_default_setup,
2136                 .exit           = pci_ite887x_exit,
2137         },
2138         /*
2139          * National Instruments
2140          */
2141         {
2142                 .vendor         = PCI_VENDOR_ID_NI,
2143                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2144                 .subvendor      = PCI_ANY_ID,
2145                 .subdevice      = PCI_ANY_ID,
2146                 .init           = pci_ni8420_init,
2147                 .setup          = pci_default_setup,
2148                 .exit           = pci_ni8420_exit,
2149         },
2150         {
2151                 .vendor         = PCI_VENDOR_ID_NI,
2152                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2153                 .subvendor      = PCI_ANY_ID,
2154                 .subdevice      = PCI_ANY_ID,
2155                 .init           = pci_ni8420_init,
2156                 .setup          = pci_default_setup,
2157                 .exit           = pci_ni8420_exit,
2158         },
2159         {
2160                 .vendor         = PCI_VENDOR_ID_NI,
2161                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2162                 .subvendor      = PCI_ANY_ID,
2163                 .subdevice      = PCI_ANY_ID,
2164                 .init           = pci_ni8420_init,
2165                 .setup          = pci_default_setup,
2166                 .exit           = pci_ni8420_exit,
2167         },
2168         {
2169                 .vendor         = PCI_VENDOR_ID_NI,
2170                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2171                 .subvendor      = PCI_ANY_ID,
2172                 .subdevice      = PCI_ANY_ID,
2173                 .init           = pci_ni8420_init,
2174                 .setup          = pci_default_setup,
2175                 .exit           = pci_ni8420_exit,
2176         },
2177         {
2178                 .vendor         = PCI_VENDOR_ID_NI,
2179                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2180                 .subvendor      = PCI_ANY_ID,
2181                 .subdevice      = PCI_ANY_ID,
2182                 .init           = pci_ni8420_init,
2183                 .setup          = pci_default_setup,
2184                 .exit           = pci_ni8420_exit,
2185         },
2186         {
2187                 .vendor         = PCI_VENDOR_ID_NI,
2188                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2189                 .subvendor      = PCI_ANY_ID,
2190                 .subdevice      = PCI_ANY_ID,
2191                 .init           = pci_ni8420_init,
2192                 .setup          = pci_default_setup,
2193                 .exit           = pci_ni8420_exit,
2194         },
2195         {
2196                 .vendor         = PCI_VENDOR_ID_NI,
2197                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2198                 .subvendor      = PCI_ANY_ID,
2199                 .subdevice      = PCI_ANY_ID,
2200                 .init           = pci_ni8420_init,
2201                 .setup          = pci_default_setup,
2202                 .exit           = pci_ni8420_exit,
2203         },
2204         {
2205                 .vendor         = PCI_VENDOR_ID_NI,
2206                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2207                 .subvendor      = PCI_ANY_ID,
2208                 .subdevice      = PCI_ANY_ID,
2209                 .init           = pci_ni8420_init,
2210                 .setup          = pci_default_setup,
2211                 .exit           = pci_ni8420_exit,
2212         },
2213         {
2214                 .vendor         = PCI_VENDOR_ID_NI,
2215                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2216                 .subvendor      = PCI_ANY_ID,
2217                 .subdevice      = PCI_ANY_ID,
2218                 .init           = pci_ni8420_init,
2219                 .setup          = pci_default_setup,
2220                 .exit           = pci_ni8420_exit,
2221         },
2222         {
2223                 .vendor         = PCI_VENDOR_ID_NI,
2224                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2225                 .subvendor      = PCI_ANY_ID,
2226                 .subdevice      = PCI_ANY_ID,
2227                 .init           = pci_ni8420_init,
2228                 .setup          = pci_default_setup,
2229                 .exit           = pci_ni8420_exit,
2230         },
2231         {
2232                 .vendor         = PCI_VENDOR_ID_NI,
2233                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2234                 .subvendor      = PCI_ANY_ID,
2235                 .subdevice      = PCI_ANY_ID,
2236                 .init           = pci_ni8420_init,
2237                 .setup          = pci_default_setup,
2238                 .exit           = pci_ni8420_exit,
2239         },
2240         {
2241                 .vendor         = PCI_VENDOR_ID_NI,
2242                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2243                 .subvendor      = PCI_ANY_ID,
2244                 .subdevice      = PCI_ANY_ID,
2245                 .init           = pci_ni8420_init,
2246                 .setup          = pci_default_setup,
2247                 .exit           = pci_ni8420_exit,
2248         },
2249         {
2250                 .vendor         = PCI_VENDOR_ID_NI,
2251                 .device         = PCI_ANY_ID,
2252                 .subvendor      = PCI_ANY_ID,
2253                 .subdevice      = PCI_ANY_ID,
2254                 .init           = pci_ni8430_init,
2255                 .setup          = pci_ni8430_setup,
2256                 .exit           = pci_ni8430_exit,
2257         },
2258         /* Quatech */
2259         {
2260                 .vendor         = PCI_VENDOR_ID_QUATECH,
2261                 .device         = PCI_ANY_ID,
2262                 .subvendor      = PCI_ANY_ID,
2263                 .subdevice      = PCI_ANY_ID,
2264                 .init           = pci_quatech_init,
2265                 .setup          = pci_quatech_setup,
2266                 .exit           = pci_quatech_exit,
2267         },
2268         /*
2269          * Panacom
2270          */
2271         {
2272                 .vendor         = PCI_VENDOR_ID_PANACOM,
2273                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2274                 .subvendor      = PCI_ANY_ID,
2275                 .subdevice      = PCI_ANY_ID,
2276                 .init           = pci_plx9050_init,
2277                 .setup          = pci_default_setup,
2278                 .exit           = pci_plx9050_exit,
2279         },
2280         {
2281                 .vendor         = PCI_VENDOR_ID_PANACOM,
2282                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2283                 .subvendor      = PCI_ANY_ID,
2284                 .subdevice      = PCI_ANY_ID,
2285                 .init           = pci_plx9050_init,
2286                 .setup          = pci_default_setup,
2287                 .exit           = pci_plx9050_exit,
2288         },
2289         /*
2290          * Pericom
2291          */
2292         {
2293                 .vendor         = PCI_VENDOR_ID_PERICOM,
2294                 .device         = PCI_ANY_ID,
2295                 .subvendor      = PCI_ANY_ID,
2296                 .subdevice      = PCI_ANY_ID,
2297                 .setup          = pci_pericom_setup,
2298         },
2299         /*
2300          * PLX
2301          */
2302         {
2303                 .vendor         = PCI_VENDOR_ID_PLX,
2304                 .device         = PCI_DEVICE_ID_PLX_9050,
2305                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2306                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2307                 .init           = pci_plx9050_init,
2308                 .setup          = pci_default_setup,
2309                 .exit           = pci_plx9050_exit,
2310         },
2311         {
2312                 .vendor         = PCI_VENDOR_ID_PLX,
2313                 .device         = PCI_DEVICE_ID_PLX_9050,
2314                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2315                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2316                 .init           = pci_plx9050_init,
2317                 .setup          = pci_default_setup,
2318                 .exit           = pci_plx9050_exit,
2319         },
2320         {
2321                 .vendor         = PCI_VENDOR_ID_PLX,
2322                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2323                 .subvendor      = PCI_VENDOR_ID_PLX,
2324                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2325                 .init           = pci_plx9050_init,
2326                 .setup          = pci_default_setup,
2327                 .exit           = pci_plx9050_exit,
2328         },
2329         /*
2330          * SBS Technologies, Inc., PMC-OCTALPRO 232
2331          */
2332         {
2333                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2334                 .device         = PCI_DEVICE_ID_OCTPRO,
2335                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2336                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2337                 .init           = sbs_init,
2338                 .setup          = sbs_setup,
2339                 .exit           = sbs_exit,
2340         },
2341         /*
2342          * SBS Technologies, Inc., PMC-OCTALPRO 422
2343          */
2344         {
2345                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2346                 .device         = PCI_DEVICE_ID_OCTPRO,
2347                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2348                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2349                 .init           = sbs_init,
2350                 .setup          = sbs_setup,
2351                 .exit           = sbs_exit,
2352         },
2353         /*
2354          * SBS Technologies, Inc., P-Octal 232
2355          */
2356         {
2357                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2358                 .device         = PCI_DEVICE_ID_OCTPRO,
2359                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2360                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2361                 .init           = sbs_init,
2362                 .setup          = sbs_setup,
2363                 .exit           = sbs_exit,
2364         },
2365         /*
2366          * SBS Technologies, Inc., P-Octal 422
2367          */
2368         {
2369                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2370                 .device         = PCI_DEVICE_ID_OCTPRO,
2371                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2372                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2373                 .init           = sbs_init,
2374                 .setup          = sbs_setup,
2375                 .exit           = sbs_exit,
2376         },
2377         /*
2378          * SIIG cards - these may be called via parport_serial
2379          */
2380         {
2381                 .vendor         = PCI_VENDOR_ID_SIIG,
2382                 .device         = PCI_ANY_ID,
2383                 .subvendor      = PCI_ANY_ID,
2384                 .subdevice      = PCI_ANY_ID,
2385                 .init           = pci_siig_init,
2386                 .setup          = pci_siig_setup,
2387         },
2388         /*
2389          * Titan cards
2390          */
2391         {
2392                 .vendor         = PCI_VENDOR_ID_TITAN,
2393                 .device         = PCI_DEVICE_ID_TITAN_400L,
2394                 .subvendor      = PCI_ANY_ID,
2395                 .subdevice      = PCI_ANY_ID,
2396                 .setup          = titan_400l_800l_setup,
2397         },
2398         {
2399                 .vendor         = PCI_VENDOR_ID_TITAN,
2400                 .device         = PCI_DEVICE_ID_TITAN_800L,
2401                 .subvendor      = PCI_ANY_ID,
2402                 .subdevice      = PCI_ANY_ID,
2403                 .setup          = titan_400l_800l_setup,
2404         },
2405         /*
2406          * Timedia cards
2407          */
2408         {
2409                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2410                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2411                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2412                 .subdevice      = PCI_ANY_ID,
2413                 .probe          = pci_timedia_probe,
2414                 .init           = pci_timedia_init,
2415                 .setup          = pci_timedia_setup,
2416         },
2417         {
2418                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2419                 .device         = PCI_ANY_ID,
2420                 .subvendor      = PCI_ANY_ID,
2421                 .subdevice      = PCI_ANY_ID,
2422                 .setup          = pci_timedia_setup,
2423         },
2424         /*
2425          * SUNIX (Timedia) cards
2426          * Do not "probe" for these cards as there is at least one combination
2427          * card that should be handled by parport_pc that doesn't match the
2428          * rule in pci_timedia_probe.
2429          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2430          * There are some boards with part number SER5037AL that report
2431          * subdevice ID 0x0002.
2432          */
2433         {
2434                 .vendor         = PCI_VENDOR_ID_SUNIX,
2435                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2436                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2437                 .subdevice      = PCI_ANY_ID,
2438                 .init           = pci_timedia_init,
2439                 .setup          = pci_timedia_setup,
2440         },
2441         /*
2442          * Exar cards
2443          */
2444         {
2445                 .vendor = PCI_VENDOR_ID_EXAR,
2446                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2447                 .subvendor      = PCI_ANY_ID,
2448                 .subdevice      = PCI_ANY_ID,
2449                 .setup          = pci_xr17c154_setup,
2450         },
2451         {
2452                 .vendor = PCI_VENDOR_ID_EXAR,
2453                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2454                 .subvendor      = PCI_ANY_ID,
2455                 .subdevice      = PCI_ANY_ID,
2456                 .setup          = pci_xr17c154_setup,
2457         },
2458         {
2459                 .vendor = PCI_VENDOR_ID_EXAR,
2460                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2461                 .subvendor      = PCI_ANY_ID,
2462                 .subdevice      = PCI_ANY_ID,
2463                 .setup          = pci_xr17c154_setup,
2464         },
2465         {
2466                 .vendor = PCI_VENDOR_ID_EXAR,
2467                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2468                 .subvendor      = PCI_ANY_ID,
2469                 .subdevice      = PCI_ANY_ID,
2470                 .setup          = pci_xr17v35x_setup,
2471         },
2472         {
2473                 .vendor = PCI_VENDOR_ID_EXAR,
2474                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2475                 .subvendor      = PCI_ANY_ID,
2476                 .subdevice      = PCI_ANY_ID,
2477                 .setup          = pci_xr17v35x_setup,
2478         },
2479         {
2480                 .vendor = PCI_VENDOR_ID_EXAR,
2481                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2482                 .subvendor      = PCI_ANY_ID,
2483                 .subdevice      = PCI_ANY_ID,
2484                 .setup          = pci_xr17v35x_setup,
2485         },
2486         {
2487                 .vendor = PCI_VENDOR_ID_EXAR,
2488                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2489                 .subvendor      = PCI_ANY_ID,
2490                 .subdevice      = PCI_ANY_ID,
2491                 .setup          = pci_xr17v35x_setup,
2492         },
2493         {
2494                 .vendor = PCI_VENDOR_ID_EXAR,
2495                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2496                 .subvendor      = PCI_ANY_ID,
2497                 .subdevice      = PCI_ANY_ID,
2498                 .setup          = pci_xr17v35x_setup,
2499         },
2500         /*
2501          * Xircom cards
2502          */
2503         {
2504                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2505                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2506                 .subvendor      = PCI_ANY_ID,
2507                 .subdevice      = PCI_ANY_ID,
2508                 .init           = pci_xircom_init,
2509                 .setup          = pci_default_setup,
2510         },
2511         /*
2512          * Netmos cards - these may be called via parport_serial
2513          */
2514         {
2515                 .vendor         = PCI_VENDOR_ID_NETMOS,
2516                 .device         = PCI_ANY_ID,
2517                 .subvendor      = PCI_ANY_ID,
2518                 .subdevice      = PCI_ANY_ID,
2519                 .init           = pci_netmos_init,
2520                 .setup          = pci_netmos_9900_setup,
2521         },
2522         /*
2523          * EndRun Technologies
2524         */
2525         {
2526                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2527                 .device         = PCI_ANY_ID,
2528                 .subvendor      = PCI_ANY_ID,
2529                 .subdevice      = PCI_ANY_ID,
2530                 .init           = pci_endrun_init,
2531                 .setup          = pci_default_setup,
2532         },
2533         /*
2534          * For Oxford Semiconductor Tornado based devices
2535          */
2536         {
2537                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2538                 .device         = PCI_ANY_ID,
2539                 .subvendor      = PCI_ANY_ID,
2540                 .subdevice      = PCI_ANY_ID,
2541                 .init           = pci_oxsemi_tornado_init,
2542                 .setup          = pci_default_setup,
2543         },
2544         {
2545                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2546                 .device         = PCI_ANY_ID,
2547                 .subvendor      = PCI_ANY_ID,
2548                 .subdevice      = PCI_ANY_ID,
2549                 .init           = pci_oxsemi_tornado_init,
2550                 .setup          = pci_default_setup,
2551         },
2552         {
2553                 .vendor         = PCI_VENDOR_ID_DIGI,
2554                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2555                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2556                 .subdevice              = PCI_ANY_ID,
2557                 .init                   = pci_oxsemi_tornado_init,
2558                 .setup          = pci_default_setup,
2559         },
2560         {
2561                 .vendor         = PCI_VENDOR_ID_INTEL,
2562                 .device         = 0x8811,
2563                 .subvendor      = PCI_ANY_ID,
2564                 .subdevice      = PCI_ANY_ID,
2565                 .init           = pci_eg20t_init,
2566                 .setup          = pci_default_setup,
2567         },
2568         {
2569                 .vendor         = PCI_VENDOR_ID_INTEL,
2570                 .device         = 0x8812,
2571                 .subvendor      = PCI_ANY_ID,
2572                 .subdevice      = PCI_ANY_ID,
2573                 .init           = pci_eg20t_init,
2574                 .setup          = pci_default_setup,
2575         },
2576         {
2577                 .vendor         = PCI_VENDOR_ID_INTEL,
2578                 .device         = 0x8813,
2579                 .subvendor      = PCI_ANY_ID,
2580                 .subdevice      = PCI_ANY_ID,
2581                 .init           = pci_eg20t_init,
2582                 .setup          = pci_default_setup,
2583         },
2584         {
2585                 .vendor         = PCI_VENDOR_ID_INTEL,
2586                 .device         = 0x8814,
2587                 .subvendor      = PCI_ANY_ID,
2588                 .subdevice      = PCI_ANY_ID,
2589                 .init           = pci_eg20t_init,
2590                 .setup          = pci_default_setup,
2591         },
2592         {
2593                 .vendor         = 0x10DB,
2594                 .device         = 0x8027,
2595                 .subvendor      = PCI_ANY_ID,
2596                 .subdevice      = PCI_ANY_ID,
2597                 .init           = pci_eg20t_init,
2598                 .setup          = pci_default_setup,
2599         },
2600         {
2601                 .vendor         = 0x10DB,
2602                 .device         = 0x8028,
2603                 .subvendor      = PCI_ANY_ID,
2604                 .subdevice      = PCI_ANY_ID,
2605                 .init           = pci_eg20t_init,
2606                 .setup          = pci_default_setup,
2607         },
2608         {
2609                 .vendor         = 0x10DB,
2610                 .device         = 0x8029,
2611                 .subvendor      = PCI_ANY_ID,
2612                 .subdevice      = PCI_ANY_ID,
2613                 .init           = pci_eg20t_init,
2614                 .setup          = pci_default_setup,
2615         },
2616         {
2617                 .vendor         = 0x10DB,
2618                 .device         = 0x800C,
2619                 .subvendor      = PCI_ANY_ID,
2620                 .subdevice      = PCI_ANY_ID,
2621                 .init           = pci_eg20t_init,
2622                 .setup          = pci_default_setup,
2623         },
2624         {
2625                 .vendor         = 0x10DB,
2626                 .device         = 0x800D,
2627                 .subvendor      = PCI_ANY_ID,
2628                 .subdevice      = PCI_ANY_ID,
2629                 .init           = pci_eg20t_init,
2630                 .setup          = pci_default_setup,
2631         },
2632         /*
2633          * Cronyx Omega PCI (PLX-chip based)
2634          */
2635         {
2636                 .vendor         = PCI_VENDOR_ID_PLX,
2637                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2638                 .subvendor      = PCI_ANY_ID,
2639                 .subdevice      = PCI_ANY_ID,
2640                 .setup          = pci_omegapci_setup,
2641         },
2642         /* WCH CH353 1S1P card (16550 clone) */
2643         {
2644                 .vendor         = PCI_VENDOR_ID_WCH,
2645                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2646                 .subvendor      = PCI_ANY_ID,
2647                 .subdevice      = PCI_ANY_ID,
2648                 .setup          = pci_wch_ch353_setup,
2649         },
2650         /* WCH CH353 2S1P card (16550 clone) */
2651         {
2652                 .vendor         = PCI_VENDOR_ID_WCH,
2653                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2654                 .subvendor      = PCI_ANY_ID,
2655                 .subdevice      = PCI_ANY_ID,
2656                 .setup          = pci_wch_ch353_setup,
2657         },
2658         /* WCH CH353 4S card (16550 clone) */
2659         {
2660                 .vendor         = PCI_VENDOR_ID_WCH,
2661                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2662                 .subvendor      = PCI_ANY_ID,
2663                 .subdevice      = PCI_ANY_ID,
2664                 .setup          = pci_wch_ch353_setup,
2665         },
2666         /* WCH CH353 2S1PF card (16550 clone) */
2667         {
2668                 .vendor         = PCI_VENDOR_ID_WCH,
2669                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2670                 .subvendor      = PCI_ANY_ID,
2671                 .subdevice      = PCI_ANY_ID,
2672                 .setup          = pci_wch_ch353_setup,
2673         },
2674         /* WCH CH352 2S card (16550 clone) */
2675         {
2676                 .vendor         = PCI_VENDOR_ID_WCH,
2677                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2678                 .subvendor      = PCI_ANY_ID,
2679                 .subdevice      = PCI_ANY_ID,
2680                 .setup          = pci_wch_ch353_setup,
2681         },
2682         /* WCH CH382 2S card (16850 clone) */
2683         {
2684                 .vendor         = PCIE_VENDOR_ID_WCH,
2685                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2686                 .subvendor      = PCI_ANY_ID,
2687                 .subdevice      = PCI_ANY_ID,
2688                 .setup          = pci_wch_ch38x_setup,
2689         },
2690         /* WCH CH382 2S1P card (16850 clone) */
2691         {
2692                 .vendor         = PCIE_VENDOR_ID_WCH,
2693                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2694                 .subvendor      = PCI_ANY_ID,
2695                 .subdevice      = PCI_ANY_ID,
2696                 .setup          = pci_wch_ch38x_setup,
2697         },
2698         /* WCH CH384 4S card (16850 clone) */
2699         {
2700                 .vendor         = PCIE_VENDOR_ID_WCH,
2701                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2702                 .subvendor      = PCI_ANY_ID,
2703                 .subdevice      = PCI_ANY_ID,
2704                 .setup          = pci_wch_ch38x_setup,
2705         },
2706         /*
2707          * ASIX devices with FIFO bug
2708          */
2709         {
2710                 .vendor         = PCI_VENDOR_ID_ASIX,
2711                 .device         = PCI_ANY_ID,
2712                 .subvendor      = PCI_ANY_ID,
2713                 .subdevice      = PCI_ANY_ID,
2714                 .setup          = pci_asix_setup,
2715         },
2716         /*
2717          * Commtech, Inc. Fastcom adapters
2718          *
2719          */
2720         {
2721                 .vendor = PCI_VENDOR_ID_COMMTECH,
2722                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2723                 .subvendor      = PCI_ANY_ID,
2724                 .subdevice      = PCI_ANY_ID,
2725                 .setup          = pci_fastcom335_setup,
2726         },
2727         {
2728                 .vendor = PCI_VENDOR_ID_COMMTECH,
2729                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2730                 .subvendor      = PCI_ANY_ID,
2731                 .subdevice      = PCI_ANY_ID,
2732                 .setup          = pci_fastcom335_setup,
2733         },
2734         {
2735                 .vendor = PCI_VENDOR_ID_COMMTECH,
2736                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2737                 .subvendor      = PCI_ANY_ID,
2738                 .subdevice      = PCI_ANY_ID,
2739                 .setup          = pci_fastcom335_setup,
2740         },
2741         {
2742                 .vendor = PCI_VENDOR_ID_COMMTECH,
2743                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2744                 .subvendor      = PCI_ANY_ID,
2745                 .subdevice      = PCI_ANY_ID,
2746                 .setup          = pci_fastcom335_setup,
2747         },
2748         {
2749                 .vendor = PCI_VENDOR_ID_COMMTECH,
2750                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2751                 .subvendor      = PCI_ANY_ID,
2752                 .subdevice      = PCI_ANY_ID,
2753                 .setup          = pci_xr17v35x_setup,
2754         },
2755         {
2756                 .vendor = PCI_VENDOR_ID_COMMTECH,
2757                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2758                 .subvendor      = PCI_ANY_ID,
2759                 .subdevice      = PCI_ANY_ID,
2760                 .setup          = pci_xr17v35x_setup,
2761         },
2762         {
2763                 .vendor = PCI_VENDOR_ID_COMMTECH,
2764                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2765                 .subvendor      = PCI_ANY_ID,
2766                 .subdevice      = PCI_ANY_ID,
2767                 .setup          = pci_xr17v35x_setup,
2768         },
2769         /*
2770          * Broadcom TruManage (NetXtreme)
2771          */
2772         {
2773                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2774                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2775                 .subvendor      = PCI_ANY_ID,
2776                 .subdevice      = PCI_ANY_ID,
2777                 .setup          = pci_brcm_trumanage_setup,
2778         },
2779         {
2780                 .vendor         = 0x1c29,
2781                 .device         = 0x1104,
2782                 .subvendor      = PCI_ANY_ID,
2783                 .subdevice      = PCI_ANY_ID,
2784                 .setup          = pci_fintek_setup,
2785                 .init           = pci_fintek_init,
2786         },
2787         {
2788                 .vendor         = 0x1c29,
2789                 .device         = 0x1108,
2790                 .subvendor      = PCI_ANY_ID,
2791                 .subdevice      = PCI_ANY_ID,
2792                 .setup          = pci_fintek_setup,
2793                 .init           = pci_fintek_init,
2794         },
2795         {
2796                 .vendor         = 0x1c29,
2797                 .device         = 0x1112,
2798                 .subvendor      = PCI_ANY_ID,
2799                 .subdevice      = PCI_ANY_ID,
2800                 .setup          = pci_fintek_setup,
2801                 .init           = pci_fintek_init,
2802         },
2803
2804         /*
2805          * Default "match everything" terminator entry
2806          */
2807         {
2808                 .vendor         = PCI_ANY_ID,
2809                 .device         = PCI_ANY_ID,
2810                 .subvendor      = PCI_ANY_ID,
2811                 .subdevice      = PCI_ANY_ID,
2812                 .setup          = pci_default_setup,
2813         }
2814 };
2815
2816 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2817 {
2818         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2819 }
2820
2821 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2822 {
2823         struct pci_serial_quirk *quirk;
2824
2825         for (quirk = pci_serial_quirks; ; quirk++)
2826                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2827                     quirk_id_matches(quirk->device, dev->device) &&
2828                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2829                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2830                         break;
2831         return quirk;
2832 }
2833
2834 static inline int get_pci_irq(struct pci_dev *dev,
2835                                 const struct pciserial_board *board)
2836 {
2837         if (board->flags & FL_NOIRQ)
2838                 return 0;
2839         else
2840                 return dev->irq;
2841 }
2842
2843 /*
2844  * This is the configuration table for all of the PCI serial boards
2845  * which we support.  It is directly indexed by the pci_board_num_t enum
2846  * value, which is encoded in the pci_device_id PCI probe table's
2847  * driver_data member.
2848  *
2849  * The makeup of these names are:
2850  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2851  *
2852  *  bn          = PCI BAR number
2853  *  bt          = Index using PCI BARs
2854  *  n           = number of serial ports
2855  *  baud        = baud rate
2856  *  offsetinhex = offset for each sequential port (in hex)
2857  *
2858  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2859  *
2860  * Please note: in theory if n = 1, _bt infix should make no difference.
2861  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2862  */
2863 enum pci_board_num_t {
2864         pbn_default = 0,
2865
2866         pbn_b0_1_115200,
2867         pbn_b0_2_115200,
2868         pbn_b0_4_115200,
2869         pbn_b0_5_115200,
2870         pbn_b0_8_115200,
2871
2872         pbn_b0_1_921600,
2873         pbn_b0_2_921600,
2874         pbn_b0_4_921600,
2875
2876         pbn_b0_2_1130000,
2877
2878         pbn_b0_4_1152000,
2879
2880         pbn_b0_2_1152000_200,
2881         pbn_b0_4_1152000_200,
2882         pbn_b0_8_1152000_200,
2883
2884         pbn_b0_4_1250000,
2885
2886         pbn_b0_2_1843200,
2887         pbn_b0_4_1843200,
2888
2889         pbn_b0_2_1843200_200,
2890         pbn_b0_4_1843200_200,
2891         pbn_b0_8_1843200_200,
2892
2893         pbn_b0_1_4000000,
2894
2895         pbn_b0_bt_1_115200,
2896         pbn_b0_bt_2_115200,
2897         pbn_b0_bt_4_115200,
2898         pbn_b0_bt_8_115200,
2899
2900         pbn_b0_bt_1_460800,
2901         pbn_b0_bt_2_460800,
2902         pbn_b0_bt_4_460800,
2903
2904         pbn_b0_bt_1_921600,
2905         pbn_b0_bt_2_921600,
2906         pbn_b0_bt_4_921600,
2907         pbn_b0_bt_8_921600,
2908
2909         pbn_b1_1_115200,
2910         pbn_b1_2_115200,
2911         pbn_b1_4_115200,
2912         pbn_b1_8_115200,
2913         pbn_b1_16_115200,
2914
2915         pbn_b1_1_921600,
2916         pbn_b1_2_921600,
2917         pbn_b1_4_921600,
2918         pbn_b1_8_921600,
2919
2920         pbn_b1_2_1250000,
2921
2922         pbn_b1_bt_1_115200,
2923         pbn_b1_bt_2_115200,
2924         pbn_b1_bt_4_115200,
2925
2926         pbn_b1_bt_2_921600,
2927
2928         pbn_b1_1_1382400,
2929         pbn_b1_2_1382400,
2930         pbn_b1_4_1382400,
2931         pbn_b1_8_1382400,
2932
2933         pbn_b2_1_115200,
2934         pbn_b2_2_115200,
2935         pbn_b2_4_115200,
2936         pbn_b2_8_115200,
2937
2938         pbn_b2_1_460800,
2939         pbn_b2_4_460800,
2940         pbn_b2_8_460800,
2941         pbn_b2_16_460800,
2942
2943         pbn_b2_1_921600,
2944         pbn_b2_4_921600,
2945         pbn_b2_8_921600,
2946
2947         pbn_b2_8_1152000,
2948
2949         pbn_b2_bt_1_115200,
2950         pbn_b2_bt_2_115200,
2951         pbn_b2_bt_4_115200,
2952
2953         pbn_b2_bt_2_921600,
2954         pbn_b2_bt_4_921600,
2955
2956         pbn_b3_2_115200,
2957         pbn_b3_4_115200,
2958         pbn_b3_8_115200,
2959
2960         pbn_b4_bt_2_921600,
2961         pbn_b4_bt_4_921600,
2962         pbn_b4_bt_8_921600,
2963
2964         /*
2965          * Board-specific versions.
2966          */
2967         pbn_panacom,
2968         pbn_panacom2,
2969         pbn_panacom4,
2970         pbn_plx_romulus,
2971         pbn_endrun_2_4000000,
2972         pbn_oxsemi,
2973         pbn_oxsemi_1_4000000,
2974         pbn_oxsemi_2_4000000,
2975         pbn_oxsemi_4_4000000,
2976         pbn_oxsemi_8_4000000,
2977         pbn_intel_i960,
2978         pbn_sgi_ioc3,
2979         pbn_computone_4,
2980         pbn_computone_6,
2981         pbn_computone_8,
2982         pbn_sbsxrsio,
2983         pbn_exar_XR17C152,
2984         pbn_exar_XR17C154,
2985         pbn_exar_XR17C158,
2986         pbn_exar_XR17V352,
2987         pbn_exar_XR17V354,
2988         pbn_exar_XR17V358,
2989         pbn_exar_XR17V4358,
2990         pbn_exar_XR17V8358,
2991         pbn_exar_ibm_saturn,
2992         pbn_pasemi_1682M,
2993         pbn_ni8430_2,
2994         pbn_ni8430_4,
2995         pbn_ni8430_8,
2996         pbn_ni8430_16,
2997         pbn_ADDIDATA_PCIe_1_3906250,
2998         pbn_ADDIDATA_PCIe_2_3906250,
2999         pbn_ADDIDATA_PCIe_4_3906250,
3000         pbn_ADDIDATA_PCIe_8_3906250,
3001         pbn_ce4100_1_115200,
3002         pbn_byt,
3003         pbn_qrk,
3004         pbn_omegapci,
3005         pbn_NETMOS9900_2s_115200,
3006         pbn_brcm_trumanage,
3007         pbn_fintek_4,
3008         pbn_fintek_8,
3009         pbn_fintek_12,
3010         pbn_wch382_2,
3011         pbn_wch384_4,
3012         pbn_pericom_PI7C9X7951,
3013         pbn_pericom_PI7C9X7952,
3014         pbn_pericom_PI7C9X7954,
3015         pbn_pericom_PI7C9X7958,
3016 };
3017
3018 /*
3019  * uart_offset - the space between channels
3020  * reg_shift   - describes how the UART registers are mapped
3021  *               to PCI memory by the card.
3022  * For example IER register on SBS, Inc. PMC-OctPro is located at
3023  * offset 0x10 from the UART base, while UART_IER is defined as 1
3024  * in include/linux/serial_reg.h,
3025  * see first lines of serial_in() and serial_out() in 8250.c
3026 */
3027
3028 static struct pciserial_board pci_boards[] = {
3029         [pbn_default] = {
3030                 .flags          = FL_BASE0,
3031                 .num_ports      = 1,
3032                 .base_baud      = 115200,
3033                 .uart_offset    = 8,
3034         },
3035         [pbn_b0_1_115200] = {
3036                 .flags          = FL_BASE0,
3037                 .num_ports      = 1,
3038                 .base_baud      = 115200,
3039                 .uart_offset    = 8,
3040         },
3041         [pbn_b0_2_115200] = {
3042                 .flags          = FL_BASE0,
3043                 .num_ports      = 2,
3044                 .base_baud      = 115200,
3045                 .uart_offset    = 8,
3046         },
3047         [pbn_b0_4_115200] = {
3048                 .flags          = FL_BASE0,
3049                 .num_ports      = 4,
3050                 .base_baud      = 115200,
3051                 .uart_offset    = 8,
3052         },
3053         [pbn_b0_5_115200] = {
3054                 .flags          = FL_BASE0,
3055                 .num_ports      = 5,
3056                 .base_baud      = 115200,
3057                 .uart_offset    = 8,
3058         },
3059         [pbn_b0_8_115200] = {
3060                 .flags          = FL_BASE0,
3061                 .num_ports      = 8,
3062                 .base_baud      = 115200,
3063                 .uart_offset    = 8,
3064         },
3065         [pbn_b0_1_921600] = {
3066                 .flags          = FL_BASE0,
3067                 .num_ports      = 1,
3068                 .base_baud      = 921600,
3069                 .uart_offset    = 8,
3070         },
3071         [pbn_b0_2_921600] = {
3072                 .flags          = FL_BASE0,
3073                 .num_ports      = 2,
3074                 .base_baud      = 921600,
3075                 .uart_offset    = 8,
3076         },
3077         [pbn_b0_4_921600] = {
3078                 .flags          = FL_BASE0,
3079                 .num_ports      = 4,
3080                 .base_baud      = 921600,
3081                 .uart_offset    = 8,
3082         },
3083
3084         [pbn_b0_2_1130000] = {
3085                 .flags          = FL_BASE0,
3086                 .num_ports      = 2,
3087                 .base_baud      = 1130000,
3088                 .uart_offset    = 8,
3089         },
3090
3091         [pbn_b0_4_1152000] = {
3092                 .flags          = FL_BASE0,
3093                 .num_ports      = 4,
3094                 .base_baud      = 1152000,
3095                 .uart_offset    = 8,
3096         },
3097
3098         [pbn_b0_2_1152000_200] = {
3099                 .flags          = FL_BASE0,
3100                 .num_ports      = 2,
3101                 .base_baud      = 1152000,
3102                 .uart_offset    = 0x200,
3103         },
3104
3105         [pbn_b0_4_1152000_200] = {
3106                 .flags          = FL_BASE0,
3107                 .num_ports      = 4,
3108                 .base_baud      = 1152000,
3109                 .uart_offset    = 0x200,
3110         },
3111
3112         [pbn_b0_8_1152000_200] = {
3113                 .flags          = FL_BASE0,
3114                 .num_ports      = 8,
3115                 .base_baud      = 1152000,
3116                 .uart_offset    = 0x200,
3117         },
3118
3119         [pbn_b0_4_1250000] = {
3120                 .flags          = FL_BASE0,
3121                 .num_ports      = 4,
3122                 .base_baud      = 1250000,
3123                 .uart_offset    = 8,
3124         },
3125
3126         [pbn_b0_2_1843200] = {
3127                 .flags          = FL_BASE0,
3128                 .num_ports      = 2,
3129                 .base_baud      = 1843200,
3130                 .uart_offset    = 8,
3131         },
3132         [pbn_b0_4_1843200] = {
3133                 .flags          = FL_BASE0,
3134                 .num_ports      = 4,
3135                 .base_baud      = 1843200,
3136                 .uart_offset    = 8,
3137         },
3138
3139         [pbn_b0_2_1843200_200] = {
3140                 .flags          = FL_BASE0,
3141                 .num_ports      = 2,
3142                 .base_baud      = 1843200,
3143                 .uart_offset    = 0x200,
3144         },
3145         [pbn_b0_4_1843200_200] = {
3146                 .flags          = FL_BASE0,
3147                 .num_ports      = 4,
3148                 .base_baud      = 1843200,
3149                 .uart_offset    = 0x200,
3150         },
3151         [pbn_b0_8_1843200_200] = {
3152                 .flags          = FL_BASE0,
3153                 .num_ports      = 8,
3154                 .base_baud      = 1843200,
3155                 .uart_offset    = 0x200,
3156         },
3157         [pbn_b0_1_4000000] = {
3158                 .flags          = FL_BASE0,
3159                 .num_ports      = 1,
3160                 .base_baud      = 4000000,
3161                 .uart_offset    = 8,
3162         },
3163
3164         [pbn_b0_bt_1_115200] = {
3165                 .flags          = FL_BASE0|FL_BASE_BARS,
3166                 .num_ports      = 1,
3167                 .base_baud      = 115200,
3168                 .uart_offset    = 8,
3169         },
3170         [pbn_b0_bt_2_115200] = {
3171                 .flags          = FL_BASE0|FL_BASE_BARS,
3172                 .num_ports      = 2,
3173                 .base_baud      = 115200,
3174                 .uart_offset    = 8,
3175         },
3176         [pbn_b0_bt_4_115200] = {
3177                 .flags          = FL_BASE0|FL_BASE_BARS,
3178                 .num_ports      = 4,
3179                 .base_baud      = 115200,
3180                 .uart_offset    = 8,
3181         },
3182         [pbn_b0_bt_8_115200] = {
3183                 .flags          = FL_BASE0|FL_BASE_BARS,
3184                 .num_ports      = 8,
3185                 .base_baud      = 115200,
3186                 .uart_offset    = 8,
3187         },
3188
3189         [pbn_b0_bt_1_460800] = {
3190                 .flags          = FL_BASE0|FL_BASE_BARS,
3191                 .num_ports      = 1,
3192                 .base_baud      = 460800,
3193                 .uart_offset    = 8,
3194         },
3195         [pbn_b0_bt_2_460800] = {
3196                 .flags          = FL_BASE0|FL_BASE_BARS,
3197                 .num_ports      = 2,
3198                 .base_baud      = 460800,
3199                 .uart_offset    = 8,
3200         },
3201         [pbn_b0_bt_4_460800] = {
3202                 .flags          = FL_BASE0|FL_BASE_BARS,
3203                 .num_ports      = 4,
3204                 .base_baud      = 460800,
3205                 .uart_offset    = 8,
3206         },
3207
3208         [pbn_b0_bt_1_921600] = {
3209                 .flags          = FL_BASE0|FL_BASE_BARS,
3210                 .num_ports      = 1,
3211                 .base_baud      = 921600,
3212                 .uart_offset    = 8,
3213         },
3214         [pbn_b0_bt_2_921600] = {
3215                 .flags          = FL_BASE0|FL_BASE_BARS,
3216                 .num_ports      = 2,
3217                 .base_baud      = 921600,
3218                 .uart_offset    = 8,
3219         },
3220         [pbn_b0_bt_4_921600] = {
3221                 .flags          = FL_BASE0|FL_BASE_BARS,
3222                 .num_ports      = 4,
3223                 .base_baud      = 921600,
3224                 .uart_offset    = 8,
3225         },
3226         [pbn_b0_bt_8_921600] = {
3227                 .flags          = FL_BASE0|FL_BASE_BARS,
3228                 .num_ports      = 8,
3229                 .base_baud      = 921600,
3230                 .uart_offset    = 8,
3231         },
3232
3233         [pbn_b1_1_115200] = {
3234                 .flags          = FL_BASE1,
3235                 .num_ports      = 1,
3236                 .base_baud      = 115200,
3237                 .uart_offset    = 8,
3238         },
3239         [pbn_b1_2_115200] = {
3240                 .flags          = FL_BASE1,
3241                 .num_ports      = 2,
3242                 .base_baud      = 115200,
3243                 .uart_offset    = 8,
3244         },
3245         [pbn_b1_4_115200] = {
3246                 .flags          = FL_BASE1,
3247                 .num_ports      = 4,
3248                 .base_baud      = 115200,
3249                 .uart_offset    = 8,
3250         },
3251         [pbn_b1_8_115200] = {
3252                 .flags          = FL_BASE1,
3253                 .num_ports      = 8,
3254                 .base_baud      = 115200,
3255                 .uart_offset    = 8,
3256         },
3257         [pbn_b1_16_115200] = {
3258                 .flags          = FL_BASE1,
3259                 .num_ports      = 16,
3260                 .base_baud      = 115200,
3261                 .uart_offset    = 8,
3262         },
3263
3264         [pbn_b1_1_921600] = {
3265                 .flags          = FL_BASE1,
3266                 .num_ports      = 1,
3267                 .base_baud      = 921600,
3268                 .uart_offset    = 8,
3269         },
3270         [pbn_b1_2_921600] = {
3271                 .flags          = FL_BASE1,
3272                 .num_ports      = 2,
3273                 .base_baud      = 921600,
3274                 .uart_offset    = 8,
3275         },
3276         [pbn_b1_4_921600] = {
3277                 .flags          = FL_BASE1,
3278                 .num_ports      = 4,
3279                 .base_baud      = 921600,
3280                 .uart_offset    = 8,
3281         },
3282         [pbn_b1_8_921600] = {
3283                 .flags          = FL_BASE1,
3284                 .num_ports      = 8,
3285                 .base_baud      = 921600,
3286                 .uart_offset    = 8,
3287         },
3288         [pbn_b1_2_1250000] = {
3289                 .flags          = FL_BASE1,
3290                 .num_ports      = 2,
3291                 .base_baud      = 1250000,
3292                 .uart_offset    = 8,
3293         },
3294
3295         [pbn_b1_bt_1_115200] = {
3296                 .flags          = FL_BASE1|FL_BASE_BARS,
3297                 .num_ports      = 1,
3298                 .base_baud      = 115200,
3299                 .uart_offset    = 8,
3300         },
3301         [pbn_b1_bt_2_115200] = {
3302                 .flags          = FL_BASE1|FL_BASE_BARS,
3303                 .num_ports      = 2,
3304                 .base_baud      = 115200,
3305                 .uart_offset    = 8,
3306         },
3307         [pbn_b1_bt_4_115200] = {
3308                 .flags          = FL_BASE1|FL_BASE_BARS,
3309                 .num_ports      = 4,
3310                 .base_baud      = 115200,
3311                 .uart_offset    = 8,
3312         },
3313
3314         [pbn_b1_bt_2_921600] = {
3315                 .flags          = FL_BASE1|FL_BASE_BARS,
3316                 .num_ports      = 2,
3317                 .base_baud      = 921600,
3318                 .uart_offset    = 8,
3319         },
3320
3321         [pbn_b1_1_1382400] = {
3322                 .flags          = FL_BASE1,
3323                 .num_ports      = 1,
3324                 .base_baud      = 1382400,
3325                 .uart_offset    = 8,
3326         },
3327         [pbn_b1_2_1382400] = {
3328                 .flags          = FL_BASE1,
3329                 .num_ports      = 2,
3330                 .base_baud      = 1382400,
3331                 .uart_offset    = 8,
3332         },
3333         [pbn_b1_4_1382400] = {
3334                 .flags          = FL_BASE1,
3335                 .num_ports      = 4,
3336                 .base_baud      = 1382400,
3337                 .uart_offset    = 8,
3338         },
3339         [pbn_b1_8_1382400] = {
3340                 .flags          = FL_BASE1,
3341                 .num_ports      = 8,
3342                 .base_baud      = 1382400,
3343                 .uart_offset    = 8,
3344         },
3345
3346         [pbn_b2_1_115200] = {
3347                 .flags          = FL_BASE2,
3348                 .num_ports      = 1,
3349                 .base_baud      = 115200,
3350                 .uart_offset    = 8,
3351         },
3352         [pbn_b2_2_115200] = {
3353                 .flags          = FL_BASE2,
3354                 .num_ports      = 2,
3355                 .base_baud      = 115200,
3356                 .uart_offset    = 8,
3357         },
3358         [pbn_b2_4_115200] = {
3359                 .flags          = FL_BASE2,
3360                 .num_ports      = 4,
3361                 .base_baud      = 115200,
3362                 .uart_offset    = 8,
3363         },
3364         [pbn_b2_8_115200] = {
3365                 .flags          = FL_BASE2,
3366                 .num_ports      = 8,
3367                 .base_baud      = 115200,
3368                 .uart_offset    = 8,
3369         },
3370
3371         [pbn_b2_1_460800] = {
3372                 .flags          = FL_BASE2,
3373                 .num_ports      = 1,
3374                 .base_baud      = 460800,
3375                 .uart_offset    = 8,
3376         },
3377         [pbn_b2_4_460800] = {
3378                 .flags          = FL_BASE2,
3379                 .num_ports      = 4,
3380                 .base_baud      = 460800,
3381                 .uart_offset    = 8,
3382         },
3383         [pbn_b2_8_460800] = {
3384                 .flags          = FL_BASE2,
3385                 .num_ports      = 8,
3386                 .base_baud      = 460800,
3387                 .uart_offset    = 8,
3388         },
3389         [pbn_b2_16_460800] = {
3390                 .flags          = FL_BASE2,
3391                 .num_ports      = 16,
3392                 .base_baud      = 460800,
3393                 .uart_offset    = 8,
3394          },
3395
3396         [pbn_b2_1_921600] = {
3397                 .flags          = FL_BASE2,
3398                 .num_ports      = 1,
3399                 .base_baud      = 921600,
3400                 .uart_offset    = 8,
3401         },
3402         [pbn_b2_4_921600] = {
3403                 .flags          = FL_BASE2,
3404                 .num_ports      = 4,
3405                 .base_baud      = 921600,
3406                 .uart_offset    = 8,
3407         },
3408         [pbn_b2_8_921600] = {
3409                 .flags          = FL_BASE2,
3410                 .num_ports      = 8,
3411                 .base_baud      = 921600,
3412                 .uart_offset    = 8,
3413         },
3414
3415         [pbn_b2_8_1152000] = {
3416                 .flags          = FL_BASE2,
3417                 .num_ports      = 8,
3418                 .base_baud      = 1152000,
3419                 .uart_offset    = 8,
3420         },
3421
3422         [pbn_b2_bt_1_115200] = {
3423                 .flags          = FL_BASE2|FL_BASE_BARS,
3424                 .num_ports      = 1,
3425                 .base_baud      = 115200,
3426                 .uart_offset    = 8,
3427         },
3428         [pbn_b2_bt_2_115200] = {
3429                 .flags          = FL_BASE2|FL_BASE_BARS,
3430                 .num_ports      = 2,
3431                 .base_baud      = 115200,
3432                 .uart_offset    = 8,
3433         },
3434         [pbn_b2_bt_4_115200] = {
3435                 .flags          = FL_BASE2|FL_BASE_BARS,
3436                 .num_ports      = 4,
3437                 .base_baud      = 115200,
3438                 .uart_offset    = 8,
3439         },
3440
3441         [pbn_b2_bt_2_921600] = {
3442                 .flags          = FL_BASE2|FL_BASE_BARS,
3443                 .num_ports      = 2,
3444                 .base_baud      = 921600,
3445                 .uart_offset    = 8,
3446         },
3447         [pbn_b2_bt_4_921600] = {
3448                 .flags          = FL_BASE2|FL_BASE_BARS,
3449                 .num_ports      = 4,
3450                 .base_baud      = 921600,
3451                 .uart_offset    = 8,
3452         },
3453
3454         [pbn_b3_2_115200] = {
3455                 .flags          = FL_BASE3,
3456                 .num_ports      = 2,
3457                 .base_baud      = 115200,
3458                 .uart_offset    = 8,
3459         },
3460         [pbn_b3_4_115200] = {
3461                 .flags          = FL_BASE3,
3462                 .num_ports      = 4,
3463                 .base_baud      = 115200,
3464                 .uart_offset    = 8,
3465         },
3466         [pbn_b3_8_115200] = {
3467                 .flags          = FL_BASE3,
3468                 .num_ports      = 8,
3469                 .base_baud      = 115200,
3470                 .uart_offset    = 8,
3471         },
3472
3473         [pbn_b4_bt_2_921600] = {
3474                 .flags          = FL_BASE4,
3475                 .num_ports      = 2,
3476                 .base_baud      = 921600,
3477                 .uart_offset    = 8,
3478         },
3479         [pbn_b4_bt_4_921600] = {
3480                 .flags          = FL_BASE4,
3481                 .num_ports      = 4,
3482                 .base_baud      = 921600,
3483                 .uart_offset    = 8,
3484         },
3485         [pbn_b4_bt_8_921600] = {
3486                 .flags          = FL_BASE4,
3487                 .num_ports      = 8,
3488                 .base_baud      = 921600,
3489                 .uart_offset    = 8,
3490         },
3491
3492         /*
3493          * Entries following this are board-specific.
3494          */
3495
3496         /*
3497          * Panacom - IOMEM
3498          */
3499         [pbn_panacom] = {
3500                 .flags          = FL_BASE2,
3501                 .num_ports      = 2,
3502                 .base_baud      = 921600,
3503                 .uart_offset    = 0x400,
3504                 .reg_shift      = 7,
3505         },
3506         [pbn_panacom2] = {
3507                 .flags          = FL_BASE2|FL_BASE_BARS,
3508                 .num_ports      = 2,
3509                 .base_baud      = 921600,
3510                 .uart_offset    = 0x400,
3511                 .reg_shift      = 7,
3512         },
3513         [pbn_panacom4] = {
3514                 .flags          = FL_BASE2|FL_BASE_BARS,
3515                 .num_ports      = 4,
3516                 .base_baud      = 921600,
3517                 .uart_offset    = 0x400,
3518                 .reg_shift      = 7,
3519         },
3520
3521         /* I think this entry is broken - the first_offset looks wrong --rmk */
3522         [pbn_plx_romulus] = {
3523                 .flags          = FL_BASE2,
3524                 .num_ports      = 4,
3525                 .base_baud      = 921600,
3526                 .uart_offset    = 8 << 2,
3527                 .reg_shift      = 2,
3528                 .first_offset   = 0x03,
3529         },
3530
3531         /*
3532          * EndRun Technologies
3533         * Uses the size of PCI Base region 0 to
3534         * signal now many ports are available
3535         * 2 port 952 Uart support
3536         */
3537         [pbn_endrun_2_4000000] = {
3538                 .flags          = FL_BASE0,
3539                 .num_ports      = 2,
3540                 .base_baud      = 4000000,
3541                 .uart_offset    = 0x200,
3542                 .first_offset   = 0x1000,
3543         },
3544
3545         /*
3546          * This board uses the size of PCI Base region 0 to
3547          * signal now many ports are available
3548          */
3549         [pbn_oxsemi] = {
3550                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3551                 .num_ports      = 32,
3552                 .base_baud      = 115200,
3553                 .uart_offset    = 8,
3554         },
3555         [pbn_oxsemi_1_4000000] = {
3556                 .flags          = FL_BASE0,
3557                 .num_ports      = 1,
3558                 .base_baud      = 4000000,
3559                 .uart_offset    = 0x200,
3560                 .first_offset   = 0x1000,
3561         },
3562         [pbn_oxsemi_2_4000000] = {
3563                 .flags          = FL_BASE0,
3564                 .num_ports      = 2,
3565                 .base_baud      = 4000000,
3566                 .uart_offset    = 0x200,
3567                 .first_offset   = 0x1000,
3568         },
3569         [pbn_oxsemi_4_4000000] = {
3570                 .flags          = FL_BASE0,
3571                 .num_ports      = 4,
3572                 .base_baud      = 4000000,
3573                 .uart_offset    = 0x200,
3574                 .first_offset   = 0x1000,
3575         },
3576         [pbn_oxsemi_8_4000000] = {
3577                 .flags          = FL_BASE0,
3578                 .num_ports      = 8,
3579                 .base_baud      = 4000000,
3580                 .uart_offset    = 0x200,
3581                 .first_offset   = 0x1000,
3582         },
3583
3584
3585         /*
3586          * EKF addition for i960 Boards form EKF with serial port.
3587          * Max 256 ports.
3588          */
3589         [pbn_intel_i960] = {
3590                 .flags          = FL_BASE0,
3591                 .num_ports      = 32,
3592                 .base_baud      = 921600,
3593                 .uart_offset    = 8 << 2,
3594                 .reg_shift      = 2,
3595                 .first_offset   = 0x10000,
3596         },
3597         [pbn_sgi_ioc3] = {
3598                 .flags          = FL_BASE0|FL_NOIRQ,
3599                 .num_ports      = 1,
3600                 .base_baud      = 458333,
3601                 .uart_offset    = 8,
3602                 .reg_shift      = 0,
3603                 .first_offset   = 0x20178,
3604         },
3605
3606         /*
3607          * Computone - uses IOMEM.
3608          */
3609         [pbn_computone_4] = {
3610                 .flags          = FL_BASE0,
3611                 .num_ports      = 4,
3612                 .base_baud      = 921600,
3613                 .uart_offset    = 0x40,
3614                 .reg_shift      = 2,
3615                 .first_offset   = 0x200,
3616         },
3617         [pbn_computone_6] = {
3618                 .flags          = FL_BASE0,
3619                 .num_ports      = 6,
3620                 .base_baud      = 921600,
3621                 .uart_offset    = 0x40,
3622                 .reg_shift      = 2,
3623                 .first_offset   = 0x200,
3624         },
3625         [pbn_computone_8] = {
3626                 .flags          = FL_BASE0,
3627                 .num_ports      = 8,
3628                 .base_baud      = 921600,
3629                 .uart_offset    = 0x40,
3630                 .reg_shift      = 2,
3631                 .first_offset   = 0x200,
3632         },
3633         [pbn_sbsxrsio] = {
3634                 .flags          = FL_BASE0,
3635                 .num_ports      = 8,
3636                 .base_baud      = 460800,
3637                 .uart_offset    = 256,
3638                 .reg_shift      = 4,
3639         },
3640         /*
3641          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3642          *  Only basic 16550A support.
3643          *  XR17C15[24] are not tested, but they should work.
3644          */
3645         [pbn_exar_XR17C152] = {
3646                 .flags          = FL_BASE0,
3647                 .num_ports      = 2,
3648                 .base_baud      = 921600,
3649                 .uart_offset    = 0x200,
3650         },
3651         [pbn_exar_XR17C154] = {
3652                 .flags          = FL_BASE0,
3653                 .num_ports      = 4,
3654                 .base_baud      = 921600,
3655                 .uart_offset    = 0x200,
3656         },
3657         [pbn_exar_XR17C158] = {
3658                 .flags          = FL_BASE0,
3659                 .num_ports      = 8,
3660                 .base_baud      = 921600,
3661                 .uart_offset    = 0x200,
3662         },
3663         [pbn_exar_XR17V352] = {
3664                 .flags          = FL_BASE0,
3665                 .num_ports      = 2,
3666                 .base_baud      = 7812500,
3667                 .uart_offset    = 0x400,
3668                 .reg_shift      = 0,
3669                 .first_offset   = 0,
3670         },
3671         [pbn_exar_XR17V354] = {
3672                 .flags          = FL_BASE0,
3673                 .num_ports      = 4,
3674                 .base_baud      = 7812500,
3675                 .uart_offset    = 0x400,
3676                 .reg_shift      = 0,
3677                 .first_offset   = 0,
3678         },
3679         [pbn_exar_XR17V358] = {
3680                 .flags          = FL_BASE0,
3681                 .num_ports      = 8,
3682                 .base_baud      = 7812500,
3683                 .uart_offset    = 0x400,
3684                 .reg_shift      = 0,
3685                 .first_offset   = 0,
3686         },
3687         [pbn_exar_XR17V4358] = {
3688                 .flags          = FL_BASE0,
3689                 .num_ports      = 12,
3690                 .base_baud      = 7812500,
3691                 .uart_offset    = 0x400,
3692                 .reg_shift      = 0,
3693                 .first_offset   = 0,
3694         },
3695         [pbn_exar_XR17V8358] = {
3696                 .flags          = FL_BASE0,
3697                 .num_ports      = 16,
3698                 .base_baud      = 7812500,
3699                 .uart_offset    = 0x400,
3700                 .reg_shift      = 0,
3701                 .first_offset   = 0,
3702         },
3703         [pbn_exar_ibm_saturn] = {
3704                 .flags          = FL_BASE0,
3705                 .num_ports      = 1,
3706                 .base_baud      = 921600,
3707                 .uart_offset    = 0x200,
3708         },
3709
3710         /*
3711          * PA Semi PWRficient PA6T-1682M on-chip UART
3712          */
3713         [pbn_pasemi_1682M] = {
3714                 .flags          = FL_BASE0,
3715                 .num_ports      = 1,
3716                 .base_baud      = 8333333,
3717         },
3718         /*
3719          * National Instruments 843x
3720          */
3721         [pbn_ni8430_16] = {
3722                 .flags          = FL_BASE0,
3723                 .num_ports      = 16,
3724                 .base_baud      = 3686400,
3725                 .uart_offset    = 0x10,
3726                 .first_offset   = 0x800,
3727         },
3728         [pbn_ni8430_8] = {
3729                 .flags          = FL_BASE0,
3730                 .num_ports      = 8,
3731                 .base_baud      = 3686400,
3732                 .uart_offset    = 0x10,
3733                 .first_offset   = 0x800,
3734         },
3735         [pbn_ni8430_4] = {
3736                 .flags          = FL_BASE0,
3737                 .num_ports      = 4,
3738                 .base_baud      = 3686400,
3739                 .uart_offset    = 0x10,
3740                 .first_offset   = 0x800,
3741         },
3742         [pbn_ni8430_2] = {
3743                 .flags          = FL_BASE0,
3744                 .num_ports      = 2,
3745                 .base_baud      = 3686400,
3746                 .uart_offset    = 0x10,
3747                 .first_offset   = 0x800,
3748         },
3749         /*
3750          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3751          */
3752         [pbn_ADDIDATA_PCIe_1_3906250] = {
3753                 .flags          = FL_BASE0,
3754                 .num_ports      = 1,
3755                 .base_baud      = 3906250,
3756                 .uart_offset    = 0x200,
3757                 .first_offset   = 0x1000,
3758         },
3759         [pbn_ADDIDATA_PCIe_2_3906250] = {
3760                 .flags          = FL_BASE0,
3761                 .num_ports      = 2,
3762                 .base_baud      = 3906250,
3763                 .uart_offset    = 0x200,
3764                 .first_offset   = 0x1000,
3765         },
3766         [pbn_ADDIDATA_PCIe_4_3906250] = {
3767                 .flags          = FL_BASE0,
3768                 .num_ports      = 4,
3769                 .base_baud      = 3906250,
3770                 .uart_offset    = 0x200,
3771                 .first_offset   = 0x1000,
3772         },
3773         [pbn_ADDIDATA_PCIe_8_3906250] = {
3774                 .flags          = FL_BASE0,
3775                 .num_ports      = 8,
3776                 .base_baud      = 3906250,
3777                 .uart_offset    = 0x200,
3778                 .first_offset   = 0x1000,
3779         },
3780         [pbn_ce4100_1_115200] = {
3781                 .flags          = FL_BASE_BARS,
3782                 .num_ports      = 2,
3783                 .base_baud      = 921600,
3784                 .reg_shift      = 2,
3785         },
3786         /*
3787          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3788          * but is overridden by byt_set_termios.
3789          */
3790         [pbn_byt] = {
3791                 .flags          = FL_BASE0,
3792                 .num_ports      = 1,
3793                 .base_baud      = 2764800,
3794                 .uart_offset    = 0x80,
3795                 .reg_shift      = 2,
3796         },
3797         [pbn_qrk] = {
3798                 .flags          = FL_BASE0,
3799                 .num_ports      = 1,
3800                 .base_baud      = 2764800,
3801                 .reg_shift      = 2,
3802         },
3803         [pbn_omegapci] = {
3804                 .flags          = FL_BASE0,
3805                 .num_ports      = 8,
3806                 .base_baud      = 115200,
3807                 .uart_offset    = 0x200,
3808         },
3809         [pbn_NETMOS9900_2s_115200] = {
3810                 .flags          = FL_BASE0,
3811                 .num_ports      = 2,
3812                 .base_baud      = 115200,
3813         },
3814         [pbn_brcm_trumanage] = {
3815                 .flags          = FL_BASE0,
3816                 .num_ports      = 1,
3817                 .reg_shift      = 2,
3818                 .base_baud      = 115200,
3819         },
3820         [pbn_fintek_4] = {
3821                 .num_ports      = 4,
3822                 .uart_offset    = 8,
3823                 .base_baud      = 115200,
3824                 .first_offset   = 0x40,
3825         },
3826         [pbn_fintek_8] = {
3827                 .num_ports      = 8,
3828                 .uart_offset    = 8,
3829                 .base_baud      = 115200,
3830                 .first_offset   = 0x40,
3831         },
3832         [pbn_fintek_12] = {
3833                 .num_ports      = 12,
3834                 .uart_offset    = 8,
3835                 .base_baud      = 115200,
3836                 .first_offset   = 0x40,
3837         },
3838         [pbn_wch382_2] = {
3839                 .flags          = FL_BASE0,
3840                 .num_ports      = 2,
3841                 .base_baud      = 115200,
3842                 .uart_offset    = 8,
3843                 .first_offset   = 0xC0,
3844         },
3845         [pbn_wch384_4] = {
3846                 .flags          = FL_BASE0,
3847                 .num_ports      = 4,
3848                 .base_baud      = 115200,
3849                 .uart_offset    = 8,
3850                 .first_offset   = 0xC0,
3851         },
3852         /*
3853          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3854          */
3855         [pbn_pericom_PI7C9X7951] = {
3856                 .flags          = FL_BASE0,
3857                 .num_ports      = 1,
3858                 .base_baud      = 921600,
3859                 .uart_offset    = 0x8,
3860         },
3861         [pbn_pericom_PI7C9X7952] = {
3862                 .flags          = FL_BASE0,
3863                 .num_ports      = 2,
3864                 .base_baud      = 921600,
3865                 .uart_offset    = 0x8,
3866         },
3867         [pbn_pericom_PI7C9X7954] = {
3868                 .flags          = FL_BASE0,
3869                 .num_ports      = 4,
3870                 .base_baud      = 921600,
3871                 .uart_offset    = 0x8,
3872         },
3873         [pbn_pericom_PI7C9X7958] = {
3874                 .flags          = FL_BASE0,
3875                 .num_ports      = 8,
3876                 .base_baud      = 921600,
3877                 .uart_offset    = 0x8,
3878         },
3879 };
3880
3881 static const struct pci_device_id blacklist[] = {
3882         /* softmodems */
3883         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3884         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3885         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3886
3887         /* multi-io cards handled by parport_serial */
3888         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3889         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3890         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3891         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3892
3893         /* Intel platforms with MID UART */
3894         { PCI_VDEVICE(INTEL, 0x081b), },
3895         { PCI_VDEVICE(INTEL, 0x081c), },
3896         { PCI_VDEVICE(INTEL, 0x081d), },
3897         { PCI_VDEVICE(INTEL, 0x1191), },
3898         { PCI_VDEVICE(INTEL, 0x19d8), },
3899 };
3900
3901 /*
3902  * Given a complete unknown PCI device, try to use some heuristics to
3903  * guess what the configuration might be, based on the pitiful PCI
3904  * serial specs.  Returns 0 on success, 1 on failure.
3905  */
3906 static int
3907 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3908 {
3909         const struct pci_device_id *bldev;
3910         int num_iomem, num_port, first_port = -1, i;
3911
3912         /*
3913          * If it is not a communications device or the programming
3914          * interface is greater than 6, give up.
3915          *
3916          * (Should we try to make guesses for multiport serial devices
3917          * later?)
3918          */
3919         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3920              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3921             (dev->class & 0xff) > 6)
3922                 return -ENODEV;
3923
3924         /*
3925          * Do not access blacklisted devices that are known not to
3926          * feature serial ports or are handled by other modules.
3927          */
3928         for (bldev = blacklist;
3929              bldev < blacklist + ARRAY_SIZE(blacklist);
3930              bldev++) {
3931                 if (dev->vendor == bldev->vendor &&
3932                     dev->device == bldev->device)
3933                         return -ENODEV;
3934         }
3935
3936         num_iomem = num_port = 0;
3937         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3938                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3939                         num_port++;
3940                         if (first_port == -1)
3941                                 first_port = i;
3942                 }
3943                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3944                         num_iomem++;
3945         }
3946
3947         /*
3948          * If there is 1 or 0 iomem regions, and exactly one port,
3949          * use it.  We guess the number of ports based on the IO
3950          * region size.
3951          */
3952         if (num_iomem <= 1 && num_port == 1) {
3953                 board->flags = first_port;
3954                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3955                 return 0;
3956         }
3957
3958         /*
3959          * Now guess if we've got a board which indexes by BARs.
3960          * Each IO BAR should be 8 bytes, and they should follow
3961          * consecutively.
3962          */
3963         first_port = -1;
3964         num_port = 0;
3965         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3966                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3967                     pci_resource_len(dev, i) == 8 &&
3968                     (first_port == -1 || (first_port + num_port) == i)) {
3969                         num_port++;
3970                         if (first_port == -1)
3971                                 first_port = i;
3972                 }
3973         }
3974
3975         if (num_port > 1) {
3976                 board->flags = first_port | FL_BASE_BARS;
3977                 board->num_ports = num_port;
3978                 return 0;
3979         }
3980
3981         return -ENODEV;
3982 }
3983
3984 static inline int
3985 serial_pci_matches(const struct pciserial_board *board,
3986                    const struct pciserial_board *guessed)
3987 {
3988         return
3989             board->num_ports == guessed->num_ports &&
3990             board->base_baud == guessed->base_baud &&
3991             board->uart_offset == guessed->uart_offset &&
3992             board->reg_shift == guessed->reg_shift &&
3993             board->first_offset == guessed->first_offset;
3994 }
3995
3996 struct serial_private *
3997 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3998 {
3999         struct uart_8250_port uart;
4000         struct serial_private *priv;
4001         struct pci_serial_quirk *quirk;
4002         int rc, nr_ports, i;
4003
4004         nr_ports = board->num_ports;
4005
4006         /*
4007          * Find an init and setup quirks.
4008          */
4009         quirk = find_quirk(dev);
4010
4011         /*
4012          * Run the new-style initialization function.
4013          * The initialization function returns:
4014          *  <0  - error
4015          *   0  - use board->num_ports
4016          *  >0  - number of ports
4017          */
4018         if (quirk->init) {
4019                 rc = quirk->init(dev);
4020                 if (rc < 0) {
4021                         priv = ERR_PTR(rc);
4022                         goto err_out;
4023                 }
4024                 if (rc)
4025                         nr_ports = rc;
4026         }
4027
4028         priv = kzalloc(sizeof(struct serial_private) +
4029                        sizeof(unsigned int) * nr_ports,
4030                        GFP_KERNEL);
4031         if (!priv) {
4032                 priv = ERR_PTR(-ENOMEM);
4033                 goto err_deinit;
4034         }
4035
4036         priv->dev = dev;
4037         priv->quirk = quirk;
4038
4039         memset(&uart, 0, sizeof(uart));
4040         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4041         uart.port.uartclk = board->base_baud * 16;
4042         uart.port.irq = get_pci_irq(dev, board);
4043         uart.port.dev = &dev->dev;
4044
4045         for (i = 0; i < nr_ports; i++) {
4046                 if (quirk->setup(priv, board, &uart, i))
4047                         break;
4048
4049                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4050                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4051
4052                 priv->line[i] = serial8250_register_8250_port(&uart);
4053                 if (priv->line[i] < 0) {
4054                         dev_err(&dev->dev,
4055                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4056                                 uart.port.iobase, uart.port.irq,
4057                                 uart.port.iotype, priv->line[i]);
4058                         break;
4059                 }
4060         }
4061         priv->nr = i;
4062         priv->board = board;
4063         return priv;
4064
4065 err_deinit:
4066         if (quirk->exit)
4067                 quirk->exit(dev);
4068 err_out:
4069         return priv;
4070 }
4071 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4072
4073 void pciserial_detach_ports(struct serial_private *priv)
4074 {
4075         struct pci_serial_quirk *quirk;
4076         int i;
4077
4078         for (i = 0; i < priv->nr; i++)
4079                 serial8250_unregister_port(priv->line[i]);
4080
4081         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4082                 if (priv->remapped_bar[i])
4083                         iounmap(priv->remapped_bar[i]);
4084                 priv->remapped_bar[i] = NULL;
4085         }
4086
4087         /*
4088          * Find the exit quirks.
4089          */
4090         quirk = find_quirk(priv->dev);
4091         if (quirk->exit)
4092                 quirk->exit(priv->dev);
4093 }
4094
4095 void pciserial_remove_ports(struct serial_private *priv)
4096 {
4097         pciserial_detach_ports(priv);
4098         kfree(priv);
4099 }
4100 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4101
4102 void pciserial_suspend_ports(struct serial_private *priv)
4103 {
4104         int i;
4105
4106         for (i = 0; i < priv->nr; i++)
4107                 if (priv->line[i] >= 0)
4108                         serial8250_suspend_port(priv->line[i]);
4109
4110         /*
4111          * Ensure that every init quirk is properly torn down
4112          */
4113         if (priv->quirk->exit)
4114                 priv->quirk->exit(priv->dev);
4115 }
4116 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4117
4118 void pciserial_resume_ports(struct serial_private *priv)
4119 {
4120         int i;
4121
4122         /*
4123          * Ensure that the board is correctly configured.
4124          */
4125         if (priv->quirk->init)
4126                 priv->quirk->init(priv->dev);
4127
4128         for (i = 0; i < priv->nr; i++)
4129                 if (priv->line[i] >= 0)
4130                         serial8250_resume_port(priv->line[i]);
4131 }
4132 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4133
4134 /*
4135  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4136  * to the arrangement of serial ports on a PCI card.
4137  */
4138 static int
4139 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4140 {
4141         struct pci_serial_quirk *quirk;
4142         struct serial_private *priv;
4143         const struct pciserial_board *board;
4144         struct pciserial_board tmp;
4145         int rc;
4146
4147         quirk = find_quirk(dev);
4148         if (quirk->probe) {
4149                 rc = quirk->probe(dev);
4150                 if (rc)
4151                         return rc;
4152         }
4153
4154         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4155                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4156                         ent->driver_data);
4157                 return -EINVAL;
4158         }
4159
4160         board = &pci_boards[ent->driver_data];
4161
4162         rc = pci_enable_device(dev);
4163         pci_save_state(dev);
4164         if (rc)
4165                 return rc;
4166
4167         if (ent->driver_data == pbn_default) {
4168                 /*
4169                  * Use a copy of the pci_board entry for this;
4170                  * avoid changing entries in the table.
4171                  */
4172                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4173                 board = &tmp;
4174
4175                 /*
4176                  * We matched one of our class entries.  Try to
4177                  * determine the parameters of this board.
4178                  */
4179                 rc = serial_pci_guess_board(dev, &tmp);
4180                 if (rc)
4181                         goto disable;
4182         } else {
4183                 /*
4184                  * We matched an explicit entry.  If we are able to
4185                  * detect this boards settings with our heuristic,
4186                  * then we no longer need this entry.
4187                  */
4188                 memcpy(&tmp, &pci_boards[pbn_default],
4189                        sizeof(struct pciserial_board));
4190                 rc = serial_pci_guess_board(dev, &tmp);
4191                 if (rc == 0 && serial_pci_matches(board, &tmp))
4192                         moan_device("Redundant entry in serial pci_table.",
4193                                     dev);
4194         }
4195
4196         priv = pciserial_init_ports(dev, board);
4197         if (!IS_ERR(priv)) {
4198                 pci_set_drvdata(dev, priv);
4199                 return 0;
4200         }
4201
4202         rc = PTR_ERR(priv);
4203
4204  disable:
4205         pci_disable_device(dev);
4206         return rc;
4207 }
4208
4209 static void pciserial_remove_one(struct pci_dev *dev)
4210 {
4211         struct serial_private *priv = pci_get_drvdata(dev);
4212
4213         pciserial_remove_ports(priv);
4214
4215         pci_disable_device(dev);
4216 }
4217
4218 #ifdef CONFIG_PM_SLEEP
4219 static int pciserial_suspend_one(struct device *dev)
4220 {
4221         struct pci_dev *pdev = to_pci_dev(dev);
4222         struct serial_private *priv = pci_get_drvdata(pdev);
4223
4224         if (priv)
4225                 pciserial_suspend_ports(priv);
4226
4227         return 0;
4228 }
4229
4230 static int pciserial_resume_one(struct device *dev)
4231 {
4232         struct pci_dev *pdev = to_pci_dev(dev);
4233         struct serial_private *priv = pci_get_drvdata(pdev);
4234         int err;
4235
4236         if (priv) {
4237                 /*
4238                  * The device may have been disabled.  Re-enable it.
4239                  */
4240                 err = pci_enable_device(pdev);
4241                 /* FIXME: We cannot simply error out here */
4242                 if (err)
4243                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4244                 pciserial_resume_ports(priv);
4245         }
4246         return 0;
4247 }
4248 #endif
4249
4250 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4251                          pciserial_resume_one);
4252
4253 static struct pci_device_id serial_pci_tbl[] = {
4254         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4255         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4256                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4257                 pbn_b2_8_921600 },
4258         /* Advantech also use 0x3618 and 0xf618 */
4259         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4260                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4261                 pbn_b0_4_921600 },
4262         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4263                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4264                 pbn_b0_4_921600 },
4265         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4266                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4267                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4268                 pbn_b1_8_1382400 },
4269         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4270                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4272                 pbn_b1_4_1382400 },
4273         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4274                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4276                 pbn_b1_2_1382400 },
4277         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4278                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4280                 pbn_b1_8_1382400 },
4281         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4282                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4283                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4284                 pbn_b1_4_1382400 },
4285         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4286                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4287                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4288                 pbn_b1_2_1382400 },
4289         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4290                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4291                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4292                 pbn_b1_8_921600 },
4293         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4294                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4295                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4296                 pbn_b1_8_921600 },
4297         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4298                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4299                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4300                 pbn_b1_4_921600 },
4301         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4302                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4303                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4304                 pbn_b1_4_921600 },
4305         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4306                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4307                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4308                 pbn_b1_2_921600 },
4309         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4310                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4311                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4312                 pbn_b1_8_921600 },
4313         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4314                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4315                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4316                 pbn_b1_8_921600 },
4317         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4318                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4319                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4320                 pbn_b1_4_921600 },
4321         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4322                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4323                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4324                 pbn_b1_2_1250000 },
4325         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4326                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4327                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4328                 pbn_b0_2_1843200 },
4329         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4330                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4331                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4332                 pbn_b0_4_1843200 },
4333         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4334                 PCI_VENDOR_ID_AFAVLAB,
4335                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4336                 pbn_b0_4_1152000 },
4337         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4338                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4339                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4340                 pbn_b0_2_1843200_200 },
4341         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4342                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4343                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4344                 pbn_b0_4_1843200_200 },
4345         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4346                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4347                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4348                 pbn_b0_8_1843200_200 },
4349         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4350                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4351                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4352                 pbn_b0_2_1843200_200 },
4353         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4354                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4355                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4356                 pbn_b0_4_1843200_200 },
4357         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4358                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4359                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4360                 pbn_b0_8_1843200_200 },
4361         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4362                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4363                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4364                 pbn_b0_2_1843200_200 },
4365         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4366                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4367                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4368                 pbn_b0_4_1843200_200 },
4369         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4370                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4371                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4372                 pbn_b0_8_1843200_200 },
4373         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4374                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4375                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4376                 pbn_b0_2_1843200_200 },
4377         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4378                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4379                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4380                 pbn_b0_4_1843200_200 },
4381         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4382                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4383                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4384                 pbn_b0_8_1843200_200 },
4385         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4386                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4387                 0, 0, pbn_exar_ibm_saturn },
4388
4389         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391                 pbn_b2_bt_1_115200 },
4392         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394                 pbn_b2_bt_2_115200 },
4395         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397                 pbn_b2_bt_4_115200 },
4398         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400                 pbn_b2_bt_2_115200 },
4401         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403                 pbn_b2_bt_4_115200 },
4404         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406                 pbn_b2_8_115200 },
4407         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409                 pbn_b2_8_460800 },
4410         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412                 pbn_b2_8_115200 },
4413
4414         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416                 pbn_b2_bt_2_115200 },
4417         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4418                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419                 pbn_b2_bt_2_921600 },
4420         /*
4421          * VScom SPCOM800, from sl@s.pl
4422          */
4423         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4424                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425                 pbn_b2_8_921600 },
4426         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4427                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428                 pbn_b2_4_921600 },
4429         /* Unknown card - subdevice 0x1584 */
4430         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4431                 PCI_VENDOR_ID_PLX,
4432                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4433                 pbn_b2_4_115200 },
4434         /* Unknown card - subdevice 0x1588 */
4435         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4436                 PCI_VENDOR_ID_PLX,
4437                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4438                 pbn_b2_8_115200 },
4439         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4440                 PCI_SUBVENDOR_ID_KEYSPAN,
4441                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4442                 pbn_panacom },
4443         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445                 pbn_panacom4 },
4446         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448                 pbn_panacom2 },
4449         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4450                 PCI_VENDOR_ID_ESDGMBH,
4451                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4452                 pbn_b2_4_115200 },
4453         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4454                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4455                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4456                 pbn_b2_4_460800 },
4457         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4458                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4459                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4460                 pbn_b2_8_460800 },
4461         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4462                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4463                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4464                 pbn_b2_16_460800 },
4465         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4466                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4467                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4468                 pbn_b2_16_460800 },
4469         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4470                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4471                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4472                 pbn_b2_4_460800 },
4473         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4474                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4475                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4476                 pbn_b2_8_460800 },
4477         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4478                 PCI_SUBVENDOR_ID_EXSYS,
4479                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4480                 pbn_b2_4_115200 },
4481         /*
4482          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4483          * (Exoray@isys.ca)
4484          */
4485         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4486                 0x10b5, 0x106a, 0, 0,
4487                 pbn_plx_romulus },
4488         /*
4489         * EndRun Technologies. PCI express device range.
4490         *    EndRun PTP/1588 has 2 Native UARTs.
4491         */
4492         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4493                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494                 pbn_endrun_2_4000000 },
4495         /*
4496          * Quatech cards. These actually have configurable clocks but for
4497          * now we just use the default.
4498          *
4499          * 100 series are RS232, 200 series RS422,
4500          */
4501         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4502                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503                 pbn_b1_4_115200 },
4504         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4505                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506                 pbn_b1_2_115200 },
4507         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4508                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509                 pbn_b2_2_115200 },
4510         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4511                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512                 pbn_b1_2_115200 },
4513         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4514                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515                 pbn_b2_2_115200 },
4516         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4517                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518                 pbn_b1_4_115200 },
4519         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4520                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521                 pbn_b1_8_115200 },
4522         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524                 pbn_b1_8_115200 },
4525         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4526                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527                 pbn_b1_4_115200 },
4528         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4529                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530                 pbn_b1_2_115200 },
4531         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4532                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533                 pbn_b1_4_115200 },
4534         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4535                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536                 pbn_b1_2_115200 },
4537         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4538                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539                 pbn_b2_4_115200 },
4540         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542                 pbn_b2_2_115200 },
4543         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4544                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545                 pbn_b2_1_115200 },
4546         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548                 pbn_b2_4_115200 },
4549         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4550                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551                 pbn_b2_2_115200 },
4552         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4553                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554                 pbn_b2_1_115200 },
4555         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557                 pbn_b0_8_115200 },
4558
4559         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4560                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4561                 0, 0,
4562                 pbn_b0_4_921600 },
4563         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4564                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4565                 0, 0,
4566                 pbn_b0_4_1152000 },
4567         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569                 pbn_b0_bt_2_921600 },
4570
4571                 /*
4572                  * The below card is a little controversial since it is the
4573                  * subject of a PCI vendor/device ID clash.  (See
4574                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4575                  * For now just used the hex ID 0x950a.
4576                  */
4577         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4578                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4579                 0, 0, pbn_b0_2_115200 },
4580         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4581                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4582                 0, 0, pbn_b0_2_115200 },
4583         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585                 pbn_b0_2_1130000 },
4586         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4587                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4588                 pbn_b0_1_921600 },
4589         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4590                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591                 pbn_b0_4_115200 },
4592         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594                 pbn_b0_bt_2_921600 },
4595         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4596                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4597                 pbn_b2_8_1152000 },
4598
4599         /*
4600          * Oxford Semiconductor Inc. Tornado PCI express device range.
4601          */
4602         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4603                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604                 pbn_b0_1_4000000 },
4605         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4606                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607                 pbn_b0_1_4000000 },
4608         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610                 pbn_oxsemi_1_4000000 },
4611         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613                 pbn_oxsemi_1_4000000 },
4614         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616                 pbn_b0_1_4000000 },
4617         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619                 pbn_b0_1_4000000 },
4620         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622                 pbn_oxsemi_1_4000000 },
4623         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625                 pbn_oxsemi_1_4000000 },
4626         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4627                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628                 pbn_b0_1_4000000 },
4629         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4630                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631                 pbn_b0_1_4000000 },
4632         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4633                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634                 pbn_b0_1_4000000 },
4635         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4636                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637                 pbn_b0_1_4000000 },
4638         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4639                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640                 pbn_oxsemi_2_4000000 },
4641         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4642                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643                 pbn_oxsemi_2_4000000 },
4644         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646                 pbn_oxsemi_4_4000000 },
4647         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649                 pbn_oxsemi_4_4000000 },
4650         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652                 pbn_oxsemi_8_4000000 },
4653         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655                 pbn_oxsemi_8_4000000 },
4656         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658                 pbn_oxsemi_1_4000000 },
4659         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661                 pbn_oxsemi_1_4000000 },
4662         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4663                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664                 pbn_oxsemi_1_4000000 },
4665         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4666                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667                 pbn_oxsemi_1_4000000 },
4668         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4669                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670                 pbn_oxsemi_1_4000000 },
4671         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4672                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673                 pbn_oxsemi_1_4000000 },
4674         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4675                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676                 pbn_oxsemi_1_4000000 },
4677         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4678                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679                 pbn_oxsemi_1_4000000 },
4680         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4681                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682                 pbn_oxsemi_1_4000000 },
4683         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4684                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685                 pbn_oxsemi_1_4000000 },
4686         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4687                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688                 pbn_oxsemi_1_4000000 },
4689         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4690                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691                 pbn_oxsemi_1_4000000 },
4692         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4693                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694                 pbn_oxsemi_1_4000000 },
4695         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4696                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697                 pbn_oxsemi_1_4000000 },
4698         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4699                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700                 pbn_oxsemi_1_4000000 },
4701         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4702                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703                 pbn_oxsemi_1_4000000 },
4704         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4705                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706                 pbn_oxsemi_1_4000000 },
4707         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4708                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709                 pbn_oxsemi_1_4000000 },
4710         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4711                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712                 pbn_oxsemi_1_4000000 },
4713         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4714                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715                 pbn_oxsemi_1_4000000 },
4716         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4717                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718                 pbn_oxsemi_1_4000000 },
4719         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4720                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721                 pbn_oxsemi_1_4000000 },
4722         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4723                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724                 pbn_oxsemi_1_4000000 },
4725         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4726                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727                 pbn_oxsemi_1_4000000 },
4728         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4729                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730                 pbn_oxsemi_1_4000000 },
4731         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733                 pbn_oxsemi_1_4000000 },
4734         /*
4735          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4736          */
4737         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4738                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4739                 pbn_oxsemi_1_4000000 },
4740         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4741                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4742                 pbn_oxsemi_2_4000000 },
4743         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4744                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4745                 pbn_oxsemi_4_4000000 },
4746         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4747                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4748                 pbn_oxsemi_8_4000000 },
4749
4750         /*
4751          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4752          */
4753         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4754                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4755                 pbn_oxsemi_2_4000000 },
4756
4757         /*
4758          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4759          * from skokodyn@yahoo.com
4760          */
4761         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4762                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4763                 pbn_sbsxrsio },
4764         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4765                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4766                 pbn_sbsxrsio },
4767         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4768                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4769                 pbn_sbsxrsio },
4770         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4771                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4772                 pbn_sbsxrsio },
4773
4774         /*
4775          * Digitan DS560-558, from jimd@esoft.com
4776          */
4777         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4778                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779                 pbn_b1_1_115200 },
4780
4781         /*
4782          * Titan Electronic cards
4783          *  The 400L and 800L have a custom setup quirk.
4784          */
4785         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787                 pbn_b0_1_921600 },
4788         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4789                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790                 pbn_b0_2_921600 },
4791         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793                 pbn_b0_4_921600 },
4794         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4795                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796                 pbn_b0_4_921600 },
4797         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4798                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799                 pbn_b1_1_921600 },
4800         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4801                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802                 pbn_b1_bt_2_921600 },
4803         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4804                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805                 pbn_b0_bt_4_921600 },
4806         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808                 pbn_b0_bt_8_921600 },
4809         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811                 pbn_b4_bt_2_921600 },
4812         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814                 pbn_b4_bt_4_921600 },
4815         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4816                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817                 pbn_b4_bt_8_921600 },
4818         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820                 pbn_b0_4_921600 },
4821         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823                 pbn_b0_4_921600 },
4824         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826                 pbn_b0_4_921600 },
4827         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_oxsemi_1_4000000 },
4830         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832                 pbn_oxsemi_2_4000000 },
4833         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835                 pbn_oxsemi_4_4000000 },
4836         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4837                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838                 pbn_oxsemi_8_4000000 },
4839         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4840                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841                 pbn_oxsemi_2_4000000 },
4842         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4843                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844                 pbn_oxsemi_2_4000000 },
4845         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4846                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847                 pbn_b0_bt_2_921600 },
4848         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4849                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850                 pbn_b0_4_921600 },
4851         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4852                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853                 pbn_b0_4_921600 },
4854         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4855                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856                 pbn_b0_4_921600 },
4857         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4858                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859                 pbn_b0_4_921600 },
4860
4861         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4862                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4863                 pbn_b2_1_460800 },
4864         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4865                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866                 pbn_b2_1_460800 },
4867         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869                 pbn_b2_1_460800 },
4870         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4871                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872                 pbn_b2_bt_2_921600 },
4873         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4874                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875                 pbn_b2_bt_2_921600 },
4876         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4877                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878                 pbn_b2_bt_2_921600 },
4879         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4880                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881                 pbn_b2_bt_4_921600 },
4882         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884                 pbn_b2_bt_4_921600 },
4885         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4886                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887                 pbn_b2_bt_4_921600 },
4888         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4889                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890                 pbn_b0_1_921600 },
4891         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4892                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893                 pbn_b0_1_921600 },
4894         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4895                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896                 pbn_b0_1_921600 },
4897         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4898                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899                 pbn_b0_bt_2_921600 },
4900         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4901                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902                 pbn_b0_bt_2_921600 },
4903         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4904                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905                 pbn_b0_bt_2_921600 },
4906         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908                 pbn_b0_bt_4_921600 },
4909         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911                 pbn_b0_bt_4_921600 },
4912         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4913                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914                 pbn_b0_bt_4_921600 },
4915         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917                 pbn_b0_bt_8_921600 },
4918         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920                 pbn_b0_bt_8_921600 },
4921         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923                 pbn_b0_bt_8_921600 },
4924
4925         /*
4926          * Computone devices submitted by Doug McNash dmcnash@computone.com
4927          */
4928         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4929                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4930                 0, 0, pbn_computone_4 },
4931         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4932                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4933                 0, 0, pbn_computone_8 },
4934         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4935                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4936                 0, 0, pbn_computone_6 },
4937
4938         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4939                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940                 pbn_oxsemi },
4941         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4942                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4943                 pbn_b0_bt_1_921600 },
4944
4945         /*
4946          * SUNIX (TIMEDIA)
4947          */
4948         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4949                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4950                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4951                 pbn_b0_bt_1_921600 },
4952
4953         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4954                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4955                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4956                 pbn_b0_bt_1_921600 },
4957
4958         /*
4959          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4960          */
4961         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963                 pbn_b0_bt_8_115200 },
4964         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4965                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966                 pbn_b0_bt_8_115200 },
4967
4968         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970                 pbn_b0_bt_2_115200 },
4971         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973                 pbn_b0_bt_2_115200 },
4974         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976                 pbn_b0_bt_2_115200 },
4977         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979                 pbn_b0_bt_2_115200 },
4980         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982                 pbn_b0_bt_2_115200 },
4983         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985                 pbn_b0_bt_4_460800 },
4986         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988                 pbn_b0_bt_4_460800 },
4989         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4991                 pbn_b0_bt_2_460800 },
4992         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4994                 pbn_b0_bt_2_460800 },
4995         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4997                 pbn_b0_bt_2_460800 },
4998         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000                 pbn_b0_bt_1_115200 },
5001         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5002                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003                 pbn_b0_bt_1_460800 },
5004
5005         /*
5006          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5007          * Cards are identified by their subsystem vendor IDs, which
5008          * (in hex) match the model number.
5009          *
5010          * Note that JC140x are RS422/485 cards which require ox950
5011          * ACR = 0x10, and as such are not currently fully supported.
5012          */
5013         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5014                 0x1204, 0x0004, 0, 0,
5015                 pbn_b0_4_921600 },
5016         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5017                 0x1208, 0x0004, 0, 0,
5018                 pbn_b0_4_921600 },
5019 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5020                 0x1402, 0x0002, 0, 0,
5021                 pbn_b0_2_921600 }, */
5022 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5023                 0x1404, 0x0004, 0, 0,
5024                 pbn_b0_4_921600 }, */
5025         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5026                 0x1208, 0x0004, 0, 0,
5027                 pbn_b0_4_921600 },
5028
5029         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5030                 0x1204, 0x0004, 0, 0,
5031                 pbn_b0_4_921600 },
5032         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5033                 0x1208, 0x0004, 0, 0,
5034                 pbn_b0_4_921600 },
5035         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5036                 0x1208, 0x0004, 0, 0,
5037                 pbn_b0_4_921600 },
5038         /*
5039          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5040          */
5041         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043                 pbn_b1_1_1382400 },
5044
5045         /*
5046          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5047          */
5048         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050                 pbn_b1_1_1382400 },
5051
5052         /*
5053          * RAStel 2 port modem, gerg@moreton.com.au
5054          */
5055         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5056                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057                 pbn_b2_bt_2_115200 },
5058
5059         /*
5060          * EKF addition for i960 Boards form EKF with serial port
5061          */
5062         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5063                 0xE4BF, PCI_ANY_ID, 0, 0,
5064                 pbn_intel_i960 },
5065
5066         /*
5067          * Xircom Cardbus/Ethernet combos
5068          */
5069         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071                 pbn_b0_1_115200 },
5072         /*
5073          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5074          */
5075         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077                 pbn_b0_1_115200 },
5078
5079         /*
5080          * Untested PCI modems, sent in from various folks...
5081          */
5082
5083         /*
5084          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5085          */
5086         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5087                 0x1048, 0x1500, 0, 0,
5088                 pbn_b1_1_115200 },
5089
5090         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5091                 0xFF00, 0, 0, 0,
5092                 pbn_sgi_ioc3 },
5093
5094         /*
5095          * HP Diva card
5096          */
5097         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5098                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5099                 pbn_b1_1_115200 },
5100         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102                 pbn_b0_5_115200 },
5103         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5104                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105                 pbn_b2_1_115200 },
5106
5107         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5108                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109                 pbn_b3_2_115200 },
5110         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112                 pbn_b3_4_115200 },
5113         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5115                 pbn_b3_8_115200 },
5116
5117         /*
5118          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5119          */
5120         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5121                 PCI_ANY_ID, PCI_ANY_ID,
5122                 0,
5123                 0, pbn_exar_XR17C152 },
5124         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5125                 PCI_ANY_ID, PCI_ANY_ID,
5126                 0,
5127                 0, pbn_exar_XR17C154 },
5128         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5129                 PCI_ANY_ID, PCI_ANY_ID,
5130                 0,
5131                 0, pbn_exar_XR17C158 },
5132         /*
5133          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5134          */
5135         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5136                 PCI_ANY_ID, PCI_ANY_ID,
5137                 0,
5138                 0, pbn_exar_XR17V352 },
5139         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5140                 PCI_ANY_ID, PCI_ANY_ID,
5141                 0,
5142                 0, pbn_exar_XR17V354 },
5143         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5144                 PCI_ANY_ID, PCI_ANY_ID,
5145                 0,
5146                 0, pbn_exar_XR17V358 },
5147         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5148                 PCI_ANY_ID, PCI_ANY_ID,
5149                 0,
5150                 0, pbn_exar_XR17V4358 },
5151         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5152                 PCI_ANY_ID, PCI_ANY_ID,
5153                 0,
5154                 0, pbn_exar_XR17V8358 },
5155         /*
5156          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5157          */
5158         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5159                 PCI_ANY_ID, PCI_ANY_ID,
5160                 0,
5161                 0, pbn_pericom_PI7C9X7951 },
5162         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5163                 PCI_ANY_ID, PCI_ANY_ID,
5164                 0,
5165                 0, pbn_pericom_PI7C9X7952 },
5166         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5167                 PCI_ANY_ID, PCI_ANY_ID,
5168                 0,
5169                 0, pbn_pericom_PI7C9X7954 },
5170         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5171                 PCI_ANY_ID, PCI_ANY_ID,
5172                 0,
5173                 0, pbn_pericom_PI7C9X7958 },
5174         /*
5175          * ACCES I/O Products quad
5176          */
5177         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5179                 pbn_pericom_PI7C9X7954 },
5180         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5182                 pbn_pericom_PI7C9X7954 },
5183         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5185                 pbn_pericom_PI7C9X7954 },
5186         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5187                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5188                 pbn_pericom_PI7C9X7954 },
5189         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5190                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5191                 pbn_pericom_PI7C9X7954 },
5192         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5194                 pbn_pericom_PI7C9X7954 },
5195         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5197                 pbn_pericom_PI7C9X7954 },
5198         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5200                 pbn_pericom_PI7C9X7954 },
5201         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5203                 pbn_pericom_PI7C9X7954 },
5204         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206                 pbn_pericom_PI7C9X7954 },
5207         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209                 pbn_pericom_PI7C9X7954 },
5210         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5212                 pbn_pericom_PI7C9X7954 },
5213         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5215                 pbn_pericom_PI7C9X7954 },
5216         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5217                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5218                 pbn_pericom_PI7C9X7954 },
5219         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5220                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5221                 pbn_pericom_PI7C9X7954 },
5222         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5223                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5224                 pbn_pericom_PI7C9X7954 },
5225         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5227                 pbn_pericom_PI7C9X7954 },
5228         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5230                 pbn_pericom_PI7C9X7954 },
5231         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5233                 pbn_pericom_PI7C9X7954 },
5234         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5236                 pbn_pericom_PI7C9X7954 },
5237         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5239                 pbn_pericom_PI7C9X7954 },
5240         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5242                 pbn_pericom_PI7C9X7954 },
5243         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5245                 pbn_pericom_PI7C9X7954 },
5246         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5248                 pbn_pericom_PI7C9X7954 },
5249         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5251                 pbn_pericom_PI7C9X7958 },
5252         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5254                 pbn_pericom_PI7C9X7958 },
5255         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5257                 pbn_pericom_PI7C9X7958 },
5258         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5260                 pbn_pericom_PI7C9X7958 },
5261         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5263                 pbn_pericom_PI7C9X7958 },
5264         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5266                 pbn_pericom_PI7C9X7958 },
5267         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5269                 pbn_pericom_PI7C9X7958 },
5270         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5272                 pbn_pericom_PI7C9X7958 },
5273         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5275                 pbn_pericom_PI7C9X7958 },
5276         /*
5277          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5278          */
5279         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5281                 pbn_b0_1_115200 },
5282         /*
5283          * ITE
5284          */
5285         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5286                 PCI_ANY_ID, PCI_ANY_ID,
5287                 0, 0,
5288                 pbn_b1_bt_1_115200 },
5289
5290         /*
5291          * IntaShield IS-200
5292          */
5293         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5295                 pbn_b2_2_115200 },
5296         /*
5297          * IntaShield IS-400
5298          */
5299         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5301                 pbn_b2_4_115200 },
5302         /*
5303          * BrainBoxes UC-260
5304          */
5305         {       PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5306                 PCI_ANY_ID, PCI_ANY_ID,
5307                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5308                 pbn_b2_4_115200 },
5309         {       PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5310                 PCI_ANY_ID, PCI_ANY_ID,
5311                  PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5312                 pbn_b2_4_115200 },
5313         /*
5314          * Perle PCI-RAS cards
5315          */
5316         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5317                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5318                 0, 0, pbn_b2_4_921600 },
5319         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5320                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5321                 0, 0, pbn_b2_8_921600 },
5322
5323         /*
5324          * Mainpine series cards: Fairly standard layout but fools
5325          * parts of the autodetect in some cases and uses otherwise
5326          * unmatched communications subclasses in the PCI Express case
5327          */
5328
5329         {       /* RockForceDUO */
5330                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5331                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5332                 0, 0, pbn_b0_2_115200 },
5333         {       /* RockForceQUATRO */
5334                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5335                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5336                 0, 0, pbn_b0_4_115200 },
5337         {       /* RockForceDUO+ */
5338                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5339                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5340                 0, 0, pbn_b0_2_115200 },
5341         {       /* RockForceQUATRO+ */
5342                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5343                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5344                 0, 0, pbn_b0_4_115200 },
5345         {       /* RockForce+ */
5346                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5347                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5348                 0, 0, pbn_b0_2_115200 },
5349         {       /* RockForce+ */
5350                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5351                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5352                 0, 0, pbn_b0_4_115200 },
5353         {       /* RockForceOCTO+ */
5354                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5355                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5356                 0, 0, pbn_b0_8_115200 },
5357         {       /* RockForceDUO+ */
5358                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5359                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5360                 0, 0, pbn_b0_2_115200 },
5361         {       /* RockForceQUARTRO+ */
5362                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5363                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5364                 0, 0, pbn_b0_4_115200 },
5365         {       /* RockForceOCTO+ */
5366                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5367                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5368                 0, 0, pbn_b0_8_115200 },
5369         {       /* RockForceD1 */
5370                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5371                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5372                 0, 0, pbn_b0_1_115200 },
5373         {       /* RockForceF1 */
5374                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5375                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5376                 0, 0, pbn_b0_1_115200 },
5377         {       /* RockForceD2 */
5378                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5379                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5380                 0, 0, pbn_b0_2_115200 },
5381         {       /* RockForceF2 */
5382                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5383                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5384                 0, 0, pbn_b0_2_115200 },
5385         {       /* RockForceD4 */
5386                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5387                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5388                 0, 0, pbn_b0_4_115200 },
5389         {       /* RockForceF4 */
5390                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5391                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5392                 0, 0, pbn_b0_4_115200 },
5393         {       /* RockForceD8 */
5394                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5395                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5396                 0, 0, pbn_b0_8_115200 },
5397         {       /* RockForceF8 */
5398                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5399                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5400                 0, 0, pbn_b0_8_115200 },
5401         {       /* IQ Express D1 */
5402                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5403                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5404                 0, 0, pbn_b0_1_115200 },
5405         {       /* IQ Express F1 */
5406                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5407                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5408                 0, 0, pbn_b0_1_115200 },
5409         {       /* IQ Express D2 */
5410                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5411                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5412                 0, 0, pbn_b0_2_115200 },
5413         {       /* IQ Express F2 */
5414                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5415                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5416                 0, 0, pbn_b0_2_115200 },
5417         {       /* IQ Express D4 */
5418                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5419                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5420                 0, 0, pbn_b0_4_115200 },
5421         {       /* IQ Express F4 */
5422                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5423                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5424                 0, 0, pbn_b0_4_115200 },
5425         {       /* IQ Express D8 */
5426                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5427                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5428                 0, 0, pbn_b0_8_115200 },
5429         {       /* IQ Express F8 */
5430                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5431                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5432                 0, 0, pbn_b0_8_115200 },
5433
5434
5435         /*
5436          * PA Semi PA6T-1682M on-chip UART
5437          */
5438         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5439                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5440                 pbn_pasemi_1682M },
5441
5442         /*
5443          * National Instruments
5444          */
5445         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5446                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5447                 pbn_b1_16_115200 },
5448         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5449                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5450                 pbn_b1_8_115200 },
5451         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5453                 pbn_b1_bt_4_115200 },
5454         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5456                 pbn_b1_bt_2_115200 },
5457         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5458                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5459                 pbn_b1_bt_4_115200 },
5460         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5462                 pbn_b1_bt_2_115200 },
5463         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5465                 pbn_b1_16_115200 },
5466         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5468                 pbn_b1_8_115200 },
5469         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5471                 pbn_b1_bt_4_115200 },
5472         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5474                 pbn_b1_bt_2_115200 },
5475         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5477                 pbn_b1_bt_4_115200 },
5478         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5480                 pbn_b1_bt_2_115200 },
5481         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5483                 pbn_ni8430_2 },
5484         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5486                 pbn_ni8430_2 },
5487         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5489                 pbn_ni8430_4 },
5490         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5492                 pbn_ni8430_4 },
5493         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5495                 pbn_ni8430_8 },
5496         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5498                 pbn_ni8430_8 },
5499         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5501                 pbn_ni8430_16 },
5502         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5504                 pbn_ni8430_16 },
5505         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5507                 pbn_ni8430_2 },
5508         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5510                 pbn_ni8430_2 },
5511         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5513                 pbn_ni8430_4 },
5514         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5516                 pbn_ni8430_4 },
5517
5518         /*
5519         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5520         */
5521         {       PCI_VENDOR_ID_ADDIDATA,
5522                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5523                 PCI_ANY_ID,
5524                 PCI_ANY_ID,
5525                 0,
5526                 0,
5527                 pbn_b0_4_115200 },
5528
5529         {       PCI_VENDOR_ID_ADDIDATA,
5530                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5531                 PCI_ANY_ID,
5532                 PCI_ANY_ID,
5533                 0,
5534                 0,
5535                 pbn_b0_2_115200 },
5536
5537         {       PCI_VENDOR_ID_ADDIDATA,
5538                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5539                 PCI_ANY_ID,
5540                 PCI_ANY_ID,
5541                 0,
5542                 0,
5543                 pbn_b0_1_115200 },
5544
5545         {       PCI_VENDOR_ID_AMCC,
5546                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5547                 PCI_ANY_ID,
5548                 PCI_ANY_ID,
5549                 0,
5550                 0,
5551                 pbn_b1_8_115200 },
5552
5553         {       PCI_VENDOR_ID_ADDIDATA,
5554                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5555                 PCI_ANY_ID,
5556                 PCI_ANY_ID,
5557                 0,
5558                 0,
5559                 pbn_b0_4_115200 },
5560
5561         {       PCI_VENDOR_ID_ADDIDATA,
5562                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5563                 PCI_ANY_ID,
5564                 PCI_ANY_ID,
5565                 0,
5566                 0,
5567                 pbn_b0_2_115200 },
5568
5569         {       PCI_VENDOR_ID_ADDIDATA,
5570                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5571                 PCI_ANY_ID,
5572                 PCI_ANY_ID,
5573                 0,
5574                 0,
5575                 pbn_b0_1_115200 },
5576
5577         {       PCI_VENDOR_ID_ADDIDATA,
5578                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5579                 PCI_ANY_ID,
5580                 PCI_ANY_ID,
5581                 0,
5582                 0,
5583                 pbn_b0_4_115200 },
5584
5585         {       PCI_VENDOR_ID_ADDIDATA,
5586                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5587                 PCI_ANY_ID,
5588                 PCI_ANY_ID,
5589                 0,
5590                 0,
5591                 pbn_b0_2_115200 },
5592
5593         {       PCI_VENDOR_ID_ADDIDATA,
5594                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5595                 PCI_ANY_ID,
5596                 PCI_ANY_ID,
5597                 0,
5598                 0,
5599                 pbn_b0_1_115200 },
5600
5601         {       PCI_VENDOR_ID_ADDIDATA,
5602                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5603                 PCI_ANY_ID,
5604                 PCI_ANY_ID,
5605                 0,
5606                 0,
5607                 pbn_b0_8_115200 },
5608
5609         {       PCI_VENDOR_ID_ADDIDATA,
5610                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5611                 PCI_ANY_ID,
5612                 PCI_ANY_ID,
5613                 0,
5614                 0,
5615                 pbn_ADDIDATA_PCIe_4_3906250 },
5616
5617         {       PCI_VENDOR_ID_ADDIDATA,
5618                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5619                 PCI_ANY_ID,
5620                 PCI_ANY_ID,
5621                 0,
5622                 0,
5623                 pbn_ADDIDATA_PCIe_2_3906250 },
5624
5625         {       PCI_VENDOR_ID_ADDIDATA,
5626                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5627                 PCI_ANY_ID,
5628                 PCI_ANY_ID,
5629                 0,
5630                 0,
5631                 pbn_ADDIDATA_PCIe_1_3906250 },
5632
5633         {       PCI_VENDOR_ID_ADDIDATA,
5634                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5635                 PCI_ANY_ID,
5636                 PCI_ANY_ID,
5637                 0,
5638                 0,
5639                 pbn_ADDIDATA_PCIe_8_3906250 },
5640
5641         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5642                 PCI_VENDOR_ID_IBM, 0x0299,
5643                 0, 0, pbn_b0_bt_2_115200 },
5644
5645         /*
5646          * other NetMos 9835 devices are most likely handled by the
5647          * parport_serial driver, check drivers/parport/parport_serial.c
5648          * before adding them here.
5649          */
5650
5651         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5652                 0xA000, 0x1000,
5653                 0, 0, pbn_b0_1_115200 },
5654
5655         /* the 9901 is a rebranded 9912 */
5656         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5657                 0xA000, 0x1000,
5658                 0, 0, pbn_b0_1_115200 },
5659
5660         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5661                 0xA000, 0x1000,
5662                 0, 0, pbn_b0_1_115200 },
5663
5664         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5665                 0xA000, 0x1000,
5666                 0, 0, pbn_b0_1_115200 },
5667
5668         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5669                 0xA000, 0x1000,
5670                 0, 0, pbn_b0_1_115200 },
5671
5672         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5673                 0xA000, 0x3002,
5674                 0, 0, pbn_NETMOS9900_2s_115200 },
5675
5676         /*
5677          * Best Connectivity and Rosewill PCI Multi I/O cards
5678          */
5679
5680         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5681                 0xA000, 0x1000,
5682                 0, 0, pbn_b0_1_115200 },
5683
5684         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5685                 0xA000, 0x3002,
5686                 0, 0, pbn_b0_bt_2_115200 },
5687
5688         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5689                 0xA000, 0x3004,
5690                 0, 0, pbn_b0_bt_4_115200 },
5691         /* Intel CE4100 */
5692         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5693                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5694                 pbn_ce4100_1_115200 },
5695         /* Intel BayTrail */
5696         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5697                 PCI_ANY_ID,  PCI_ANY_ID,
5698                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5699                 pbn_byt },
5700         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5701                 PCI_ANY_ID,  PCI_ANY_ID,
5702                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5703                 pbn_byt },
5704         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5705                 PCI_ANY_ID,  PCI_ANY_ID,
5706                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5707                 pbn_byt },
5708         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5709                 PCI_ANY_ID,  PCI_ANY_ID,
5710                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5711                 pbn_byt },
5712
5713         /* Intel Broadwell */
5714         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5715                 PCI_ANY_ID,  PCI_ANY_ID,
5716                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5717                 pbn_byt },
5718         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5719                 PCI_ANY_ID,  PCI_ANY_ID,
5720                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5721                 pbn_byt },
5722
5723         /*
5724          * Intel Quark x1000
5725          */
5726         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5727                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5728                 pbn_qrk },
5729         /*
5730          * Cronyx Omega PCI
5731          */
5732         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5733                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5734                 pbn_omegapci },
5735
5736         /*
5737          * Broadcom TruManage
5738          */
5739         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5741                 pbn_brcm_trumanage },
5742
5743         /*
5744          * AgeStar as-prs2-009
5745          */
5746         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5747                 PCI_ANY_ID, PCI_ANY_ID,
5748                 0, 0, pbn_b0_bt_2_115200 },
5749
5750         /*
5751          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5752          * so not listed here.
5753          */
5754         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5755                 PCI_ANY_ID, PCI_ANY_ID,
5756                 0, 0, pbn_b0_bt_4_115200 },
5757
5758         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5759                 PCI_ANY_ID, PCI_ANY_ID,
5760                 0, 0, pbn_b0_bt_2_115200 },
5761
5762         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5763                 PCI_ANY_ID, PCI_ANY_ID,
5764                 0, 0, pbn_wch382_2 },
5765
5766         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5767                 PCI_ANY_ID, PCI_ANY_ID,
5768                 0, 0, pbn_wch384_4 },
5769
5770         /*
5771          * Commtech, Inc. Fastcom adapters
5772          */
5773         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5774                 PCI_ANY_ID, PCI_ANY_ID,
5775                 0,
5776                 0, pbn_b0_2_1152000_200 },
5777         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5778                 PCI_ANY_ID, PCI_ANY_ID,
5779                 0,
5780                 0, pbn_b0_4_1152000_200 },
5781         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5782                 PCI_ANY_ID, PCI_ANY_ID,
5783                 0,
5784                 0, pbn_b0_4_1152000_200 },
5785         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5786                 PCI_ANY_ID, PCI_ANY_ID,
5787                 0,
5788                 0, pbn_b0_8_1152000_200 },
5789         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5790                 PCI_ANY_ID, PCI_ANY_ID,
5791                 0,
5792                 0, pbn_exar_XR17V352 },
5793         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5794                 PCI_ANY_ID, PCI_ANY_ID,
5795                 0,
5796                 0, pbn_exar_XR17V354 },
5797         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5798                 PCI_ANY_ID, PCI_ANY_ID,
5799                 0,
5800                 0, pbn_exar_XR17V358 },
5801
5802         /* Fintek PCI serial cards */
5803         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5804         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5805         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5806
5807         /* MKS Tenta SCOM-080x serial cards */
5808         { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5809         { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5810
5811         /* Amazon PCI serial device */
5812         { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5813
5814         /*
5815          * These entries match devices with class COMMUNICATION_SERIAL,
5816          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5817          */
5818         {       PCI_ANY_ID, PCI_ANY_ID,
5819                 PCI_ANY_ID, PCI_ANY_ID,
5820                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5821                 0xffff00, pbn_default },
5822         {       PCI_ANY_ID, PCI_ANY_ID,
5823                 PCI_ANY_ID, PCI_ANY_ID,
5824                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5825                 0xffff00, pbn_default },
5826         {       PCI_ANY_ID, PCI_ANY_ID,
5827                 PCI_ANY_ID, PCI_ANY_ID,
5828                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5829                 0xffff00, pbn_default },
5830         { 0, }
5831 };
5832
5833 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5834                                                 pci_channel_state_t state)
5835 {
5836         struct serial_private *priv = pci_get_drvdata(dev);
5837
5838         if (state == pci_channel_io_perm_failure)
5839                 return PCI_ERS_RESULT_DISCONNECT;
5840
5841         if (priv)
5842                 pciserial_detach_ports(priv);
5843
5844         pci_disable_device(dev);
5845
5846         return PCI_ERS_RESULT_NEED_RESET;
5847 }
5848
5849 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5850 {
5851         int rc;
5852
5853         rc = pci_enable_device(dev);
5854
5855         if (rc)
5856                 return PCI_ERS_RESULT_DISCONNECT;
5857
5858         pci_restore_state(dev);
5859         pci_save_state(dev);
5860
5861         return PCI_ERS_RESULT_RECOVERED;
5862 }
5863
5864 static void serial8250_io_resume(struct pci_dev *dev)
5865 {
5866         struct serial_private *priv = pci_get_drvdata(dev);
5867         struct serial_private *new;
5868
5869         if (!priv)
5870                 return;
5871
5872         new = pciserial_init_ports(dev, priv->board);
5873         if (!IS_ERR(new)) {
5874                 pci_set_drvdata(dev, new);
5875                 kfree(priv);
5876         }
5877 }
5878
5879 static const struct pci_error_handlers serial8250_err_handler = {
5880         .error_detected = serial8250_io_error_detected,
5881         .slot_reset = serial8250_io_slot_reset,
5882         .resume = serial8250_io_resume,
5883 };
5884
5885 static struct pci_driver serial_pci_driver = {
5886         .name           = "serial",
5887         .probe          = pciserial_init_one,
5888         .remove         = pciserial_remove_one,
5889         .driver         = {
5890                 .pm     = &pciserial_pm_ops,
5891         },
5892         .id_table       = serial_pci_tbl,
5893         .err_handler    = &serial8250_err_handler,
5894 };
5895
5896 module_pci_driver(serial_pci_driver);
5897
5898 MODULE_LICENSE("GPL");
5899 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5900 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);