drivers/thermal/tegra/tegra132-soctherm.c

   1 /*
   2  * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17
  18 #include <dt-bindings/thermal/tegra124-soctherm.h>
  19
  20 #include "soctherm.h"
  21
  22 #define TEGRA132_THERMTRIP_ANY_EN_MASK          (0x1 << 28)
  23 #define TEGRA132_THERMTRIP_MEM_EN_MASK          (0x1 << 27)
  24 #define TEGRA132_THERMTRIP_GPU_EN_MASK          (0x1 << 26)
  25 #define TEGRA132_THERMTRIP_CPU_EN_MASK          (0x1 << 25)
  26 #define TEGRA132_THERMTRIP_TSENSE_EN_MASK       (0x1 << 24)
  27 #define TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK   (0xff << 16)
  28 #define TEGRA132_THERMTRIP_CPU_THRESH_MASK      (0xff << 8)
  29 #define TEGRA132_THERMTRIP_TSENSE_THRESH_MASK   0xff
  30
  31 #define TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK   (0xff << 17)
  32 #define TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK   (0xff << 9)
  33
  34 #define TEGRA132_THRESH_GRAIN                   1000
  35 #define TEGRA132_BPTT                           8
  36
  37 static const struct tegra_tsensor_configuration tegra132_tsensor_config = {
  38         .tall = 16300,
  39         .tiddq_en = 1,
  40         .ten_count = 1,
  41         .tsample = 120,
  42         .tsample_ate = 480,
  43 };
  44
  45 static const struct tegra_tsensor_group tegra132_tsensor_group_cpu = {
  46         .id = TEGRA124_SOCTHERM_SENSOR_CPU,
  47         .name = "cpu",
  48         .sensor_temp_offset = SENSOR_TEMP1,
  49         .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
  50         .pdiv = 8,
  51         .pdiv_ate = 8,
  52         .pdiv_mask = SENSOR_PDIV_CPU_MASK,
  53         .pllx_hotspot_diff = 10,
  54         .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
  55         .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  56         .thermtrip_enable_mask = TEGRA132_THERMTRIP_CPU_EN_MASK,
  57         .thermtrip_threshold_mask = TEGRA132_THERMTRIP_CPU_THRESH_MASK,
  58         .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
  59         .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  60         .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  61 };
  62
  63 static const struct tegra_tsensor_group tegra132_tsensor_group_gpu = {
  64         .id = TEGRA124_SOCTHERM_SENSOR_GPU,
  65         .name = "gpu",
  66         .sensor_temp_offset = SENSOR_TEMP1,
  67         .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
  68         .pdiv = 8,
  69         .pdiv_ate = 8,
  70         .pdiv_mask = SENSOR_PDIV_GPU_MASK,
  71         .pllx_hotspot_diff = 5,
  72         .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
  73         .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  74         .thermtrip_enable_mask = TEGRA132_THERMTRIP_GPU_EN_MASK,
  75         .thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
  76         .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
  77         .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  78         .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  79 };
  80
  81 static const struct tegra_tsensor_group tegra132_tsensor_group_pll = {
  82         .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
  83         .name = "pll",
  84         .sensor_temp_offset = SENSOR_TEMP2,
  85         .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
  86         .pdiv = 8,
  87         .pdiv_ate = 8,
  88         .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
  89         .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  90         .thermtrip_enable_mask = TEGRA132_THERMTRIP_TSENSE_EN_MASK,
  91         .thermtrip_threshold_mask = TEGRA132_THERMTRIP_TSENSE_THRESH_MASK,
  92         .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
  93         .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  94         .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  95 };
  96
  97 static const struct tegra_tsensor_group tegra132_tsensor_group_mem = {
  98         .id = TEGRA124_SOCTHERM_SENSOR_MEM,
  99         .name = "mem",
 100         .sensor_temp_offset = SENSOR_TEMP2,
 101         .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
 102         .pdiv = 8,
 103         .pdiv_ate = 8,
 104         .pdiv_mask = SENSOR_PDIV_MEM_MASK,
 105         .pllx_hotspot_diff = 0,
 106         .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
 107         .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
 108         .thermtrip_enable_mask = TEGRA132_THERMTRIP_MEM_EN_MASK,
 109         .thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
 110         .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
 111         .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
 112         .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
 113 };
 114
 115 static const struct tegra_tsensor_group *tegra132_tsensor_groups[] = {
 116         &tegra132_tsensor_group_cpu,
 117         &tegra132_tsensor_group_gpu,
 118         &tegra132_tsensor_group_pll,
 119         &tegra132_tsensor_group_mem,
 120 };
 121
 122 static struct tegra_tsensor tegra132_tsensors[] = {
 123         {
 124                 .name = "cpu0",
 125                 .base = 0xc0,
 126                 .config = &tegra132_tsensor_config,
 127                 .calib_fuse_offset = 0x098,
 128                 .fuse_corr_alpha = 1126600,
 129                 .fuse_corr_beta = -9433500,
 130                 .group = &tegra132_tsensor_group_cpu,
 131         }, {
 132                 .name = "cpu1",
 133                 .base = 0xe0,
 134                 .config = &tegra132_tsensor_config,
 135                 .calib_fuse_offset = 0x084,
 136                 .fuse_corr_alpha = 1110800,
 137                 .fuse_corr_beta = -7383000,
 138                 .group = &tegra132_tsensor_group_cpu,
 139         }, {
 140                 .name = "cpu2",
 141                 .base = 0x100,
 142                 .config = &tegra132_tsensor_config,
 143                 .calib_fuse_offset = 0x088,
 144                 .fuse_corr_alpha = 1113800,
 145                 .fuse_corr_beta = -6215200,
 146                 .group = &tegra132_tsensor_group_cpu,
 147         }, {
 148                 .name = "cpu3",
 149                 .base = 0x120,
 150                 .config = &tegra132_tsensor_config,
 151                 .calib_fuse_offset = 0x12c,
 152                 .fuse_corr_alpha = 1129600,
 153                 .fuse_corr_beta = -8196100,
 154                 .group = &tegra132_tsensor_group_cpu,
 155         }, {
 156                 .name = "mem0",
 157                 .base = 0x140,
 158                 .config = &tegra132_tsensor_config,
 159                 .calib_fuse_offset = 0x158,
 160                 .fuse_corr_alpha = 1132900,
 161                 .fuse_corr_beta = -6755300,
 162                 .group = &tegra132_tsensor_group_mem,
 163         }, {
 164                 .name = "mem1",
 165                 .base = 0x160,
 166                 .config = &tegra132_tsensor_config,
 167                 .calib_fuse_offset = 0x15c,
 168                 .fuse_corr_alpha = 1142300,
 169                 .fuse_corr_beta = -7374200,
 170                 .group = &tegra132_tsensor_group_mem,
 171         }, {
 172                 .name = "gpu",
 173                 .base = 0x180,
 174                 .config = &tegra132_tsensor_config,
 175                 .calib_fuse_offset = 0x154,
 176                 .fuse_corr_alpha = 1125100,
 177                 .fuse_corr_beta = -6350400,
 178                 .group = &tegra132_tsensor_group_gpu,
 179         }, {
 180                 .name = "pllx",
 181                 .base = 0x1a0,
 182                 .config = &tegra132_tsensor_config,
 183                 .calib_fuse_offset = 0x160,
 184                 .fuse_corr_alpha = 1118100,
 185                 .fuse_corr_beta = -8208800,
 186                 .group = &tegra132_tsensor_group_pll,
 187         },
 188 };
 189
 190 /*
 191  * Mask/shift bits in FUSE_TSENSOR_COMMON and
 192  * FUSE_TSENSOR_COMMON, which are described in
 193  * tegra_soctherm_fuse.c
 194  */
 195 static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
 196         .fuse_base_cp_mask = 0x3ff,
 197         .fuse_base_cp_shift = 0,
 198         .fuse_base_ft_mask = 0x7ff << 10,
 199         .fuse_base_ft_shift = 10,
 200         .fuse_shift_ft_mask = 0x1f << 21,
 201         .fuse_shift_ft_shift = 21,
 202         .fuse_spare_realignment = 0x1fc,
 203 };
 204
 205 const struct tegra_soctherm_soc tegra132_soctherm = {
 206         .tsensors = tegra132_tsensors,
 207         .num_tsensors = ARRAY_SIZE(tegra132_tsensors),
 208         .ttgs = tegra132_tsensor_groups,
 209         .num_ttgs = ARRAY_SIZE(tegra132_tsensor_groups),
 210         .tfuse = &tegra132_soctherm_fuse,
 211         .thresh_grain = TEGRA132_THRESH_GRAIN,
 212         .bptt = TEGRA132_BPTT,
 213         .use_ccroc = true,
 214 };