1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
8 * Purpose: Implement functions to access baseband
15 * BBuGetFrameTime - Calculate data frame transmitting time
16 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal
17 * parameter for baseband Tx
18 * BBbReadEmbedded - Embedded read baseband register via MAC
19 * BBbWriteEmbedded - Embedded write baseband register via MAC
20 * BBbVT3253Init - VIA VT3253 baseband chip init code
23 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
24 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
25 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
26 * BBvCalculateParameter().
27 * cancel the setting of MAC_REG_SOFTPWRCTL on
30 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
31 * Modified BBvLoopbackOn & BBvLoopbackOff().
42 /*--------------------- Static Classes ----------------------------*/
44 /*--------------------- Static Variables --------------------------*/
46 /*--------------------- Static Functions --------------------------*/
48 /*--------------------- Export Variables --------------------------*/
50 /*--------------------- Static Definitions -------------------------*/
52 /*--------------------- Static Classes ----------------------------*/
54 /*--------------------- Static Variables --------------------------*/
56 #define CB_VT3253_INIT_FOR_RFMD 446
57 static const unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
506 #define CB_VT3253B0_INIT_FOR_RFMD 256
507 static const unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
766 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
769 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
967 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
970 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1079 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1229 #define CB_VT3253B0_INIT_FOR_UW2451 256
1231 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1340 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1490 #define CB_VT3253B0_AGC 193
1492 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1688 static const unsigned short awcFrameTime[MAX_RATE] = {
1689 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1692 /*--------------------- Export Variables --------------------------*/
1694 * Description: Calculate data frame transmitting time
1698 * byPreambleType - Preamble Type
1699 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1700 * cbFrameLength - Baseband Type
1704 * Return Value: FrameTime
1709 unsigned char byPreambleType,
1710 unsigned char byPktType,
1711 unsigned int cbFrameLength,
1712 unsigned short wRate
1715 unsigned int uFrameTime;
1716 unsigned int uPreamble;
1718 unsigned int uRateIdx = (unsigned int)wRate;
1719 unsigned int uRate = 0;
1721 if (uRateIdx > RATE_54M)
1724 uRate = (unsigned int)awcFrameTime[uRateIdx];
1726 if (uRateIdx <= 3) { /* CCK mode */
1727 if (byPreambleType == 1) /* Short */
1732 uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */
1733 uTmp = (uFrameTime * uRate) / 80;
1734 if (cbFrameLength != uTmp)
1737 return uPreamble + uFrameTime;
1739 uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */
1740 uTmp = ((uFrameTime * uRate) - 22) / 8;
1741 if (cbFrameLength != uTmp)
1744 uFrameTime = uFrameTime * 4; /* ??????? */
1745 if (byPktType != PK_TYPE_11A)
1746 uFrameTime += 6; /* ?????? */
1748 return 20 + uFrameTime; /* ?????? */
1752 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1756 * priv - Device Structure
1757 * frame_length - Tx Frame Length
1760 * struct vnt_phy_field *phy
1761 * - pointer to Phy Length field
1762 * - pointer to Phy Service field
1763 * - pointer to Phy Signal field
1765 * Return Value: none
1768 void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length,
1769 u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy)
1775 u8 preamble_type = priv->byPreambleType;
1777 bit_count = frame_length * 8;
1788 count = bit_count / 2;
1790 if (preamble_type == 1)
1797 count = (bit_count * 10) / 55;
1798 tmp = (count * 55) / 10;
1800 if (tmp != bit_count)
1803 if (preamble_type == 1)
1810 count = bit_count / 11;
1813 if (tmp != bit_count) {
1816 if ((bit_count - tmp) <= 3)
1820 if (preamble_type == 1)
1827 if (pkt_type == PK_TYPE_11A)
1834 if (pkt_type == PK_TYPE_11A)
1841 if (pkt_type == PK_TYPE_11A)
1848 if (pkt_type == PK_TYPE_11A)
1855 if (pkt_type == PK_TYPE_11A)
1862 if (pkt_type == PK_TYPE_11A)
1869 if (pkt_type == PK_TYPE_11A)
1876 if (pkt_type == PK_TYPE_11A)
1882 if (pkt_type == PK_TYPE_11A)
1889 if (pkt_type == PK_TYPE_11B) {
1890 phy->service = 0x00;
1892 phy->service |= 0x80;
1893 phy->len = cpu_to_le16((u16)count);
1895 phy->service = 0x00;
1896 phy->len = cpu_to_le16((u16)frame_length);
1901 * Description: Read a byte from BASEBAND, by embedded programming
1905 * iobase - I/O base address
1906 * byBBAddr - address of register in Baseband
1908 * pbyData - data read
1910 * Return Value: true if succeeded; false if failed.
1913 bool BBbReadEmbedded(struct vnt_private *priv,
1914 unsigned char byBBAddr, unsigned char *pbyData)
1916 void __iomem *iobase = priv->PortOffset;
1918 unsigned char byValue;
1921 VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr);
1924 MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1925 /* W_MAX_TIMEOUT is the timeout period */
1926 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1927 VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue);
1928 if (byValue & BBREGCTL_DONE)
1933 VNSvInPortB(iobase + MAC_REG_BBREGDATA, pbyData);
1935 if (ww == W_MAX_TIMEOUT) {
1936 pr_debug(" DBG_PORT80(0x30)\n");
1943 * Description: Write a Byte to BASEBAND, by embedded programming
1947 * iobase - I/O base address
1948 * byBBAddr - address of register in Baseband
1949 * byData - data to write
1953 * Return Value: true if succeeded; false if failed.
1956 bool BBbWriteEmbedded(struct vnt_private *priv,
1957 unsigned char byBBAddr, unsigned char byData)
1959 void __iomem *iobase = priv->PortOffset;
1961 unsigned char byValue;
1964 VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr);
1966 VNSvOutPortB(iobase + MAC_REG_BBREGDATA, byData);
1968 /* turn on BBREGCTL_REGW */
1969 MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
1970 /* W_MAX_TIMEOUT is the timeout period */
1971 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1972 VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue);
1973 if (byValue & BBREGCTL_DONE)
1977 if (ww == W_MAX_TIMEOUT) {
1978 pr_debug(" DBG_PORT80(0x31)\n");
1985 * Description: VIA VT3253 Baseband chip init function
1989 * iobase - I/O base address
1990 * byRevId - Revision ID
1991 * byRFType - RF type
1995 * Return Value: true if succeeded; false if failed.
1999 bool BBbVT3253Init(struct vnt_private *priv)
2001 bool bResult = true;
2003 void __iomem *iobase = priv->PortOffset;
2004 unsigned char byRFType = priv->byRFType;
2005 unsigned char byLocalID = priv->byLocalID;
2007 if (byRFType == RF_RFMD2959) {
2008 if (byLocalID <= REV_ID_VT3253_A1) {
2009 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2010 bResult &= BBbWriteEmbedded(priv,
2011 byVT3253InitTab_RFMD[ii][0],
2012 byVT3253InitTab_RFMD[ii][1]);
2015 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2016 bResult &= BBbWriteEmbedded(priv,
2017 byVT3253B0_RFMD[ii][0],
2018 byVT3253B0_RFMD[ii][1]);
2020 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2021 bResult &= BBbWriteEmbedded(priv,
2022 byVT3253B0_AGC4_RFMD2959[ii][0],
2023 byVT3253B0_AGC4_RFMD2959[ii][1]);
2025 VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);
2026 MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
2028 priv->abyBBVGA[0] = 0x18;
2029 priv->abyBBVGA[1] = 0x0A;
2030 priv->abyBBVGA[2] = 0x0;
2031 priv->abyBBVGA[3] = 0x0;
2032 priv->ldBmThreshold[0] = -70;
2033 priv->ldBmThreshold[1] = -50;
2034 priv->ldBmThreshold[2] = 0;
2035 priv->ldBmThreshold[3] = 0;
2036 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2037 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2038 bResult &= BBbWriteEmbedded(priv,
2039 byVT3253B0_AIROHA2230[ii][0],
2040 byVT3253B0_AIROHA2230[ii][1]);
2042 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2043 bResult &= BBbWriteEmbedded(priv,
2044 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2046 priv->abyBBVGA[0] = 0x1C;
2047 priv->abyBBVGA[1] = 0x10;
2048 priv->abyBBVGA[2] = 0x0;
2049 priv->abyBBVGA[3] = 0x0;
2050 priv->ldBmThreshold[0] = -70;
2051 priv->ldBmThreshold[1] = -48;
2052 priv->ldBmThreshold[2] = 0;
2053 priv->ldBmThreshold[3] = 0;
2054 } else if (byRFType == RF_UW2451) {
2055 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2056 bResult &= BBbWriteEmbedded(priv,
2057 byVT3253B0_UW2451[ii][0],
2058 byVT3253B0_UW2451[ii][1]);
2060 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2061 bResult &= BBbWriteEmbedded(priv,
2062 byVT3253B0_AGC[ii][0],
2063 byVT3253B0_AGC[ii][1]);
2065 VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23);
2066 MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
2068 priv->abyBBVGA[0] = 0x14;
2069 priv->abyBBVGA[1] = 0x0A;
2070 priv->abyBBVGA[2] = 0x0;
2071 priv->abyBBVGA[3] = 0x0;
2072 priv->ldBmThreshold[0] = -60;
2073 priv->ldBmThreshold[1] = -50;
2074 priv->ldBmThreshold[2] = 0;
2075 priv->ldBmThreshold[3] = 0;
2076 } else if (byRFType == RF_UW2452) {
2077 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2078 bResult &= BBbWriteEmbedded(priv,
2079 byVT3253B0_UW2451[ii][0],
2080 byVT3253B0_UW2451[ii][1]);
2082 /* Init ANT B select,
2083 * TX Config CR09 = 0x61->0x45,
2084 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2087 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2089 /* Init ANT B select,
2090 * RX Config CR10 = 0x28->0x2A,
2091 * 0x2A->0x28(VC1/VC2 define,
2092 * make the ANT_A, ANT_B inverted)
2095 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2096 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2097 bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2099 /* {{RobertYu:20050125, request by Jack */
2100 bResult &= BBbWriteEmbedded(priv, 0x90, 0x20);
2101 bResult &= BBbWriteEmbedded(priv, 0x97, 0xeb);
2104 /* {{RobertYu:20050221, request by Jack */
2105 bResult &= BBbWriteEmbedded(priv, 0xa6, 0x00);
2106 bResult &= BBbWriteEmbedded(priv, 0xa8, 0x30);
2108 bResult &= BBbWriteEmbedded(priv, 0xb0, 0x58);
2110 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2111 bResult &= BBbWriteEmbedded(priv,
2112 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2114 priv->abyBBVGA[0] = 0x14;
2115 priv->abyBBVGA[1] = 0x0A;
2116 priv->abyBBVGA[2] = 0x0;
2117 priv->abyBBVGA[3] = 0x0;
2118 priv->ldBmThreshold[0] = -60;
2119 priv->ldBmThreshold[1] = -50;
2120 priv->ldBmThreshold[2] = 0;
2121 priv->ldBmThreshold[3] = 0;
2124 } else if (byRFType == RF_VT3226) {
2125 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2126 bResult &= BBbWriteEmbedded(priv,
2127 byVT3253B0_AIROHA2230[ii][0],
2128 byVT3253B0_AIROHA2230[ii][1]);
2130 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2131 bResult &= BBbWriteEmbedded(priv,
2132 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2134 priv->abyBBVGA[0] = 0x1C;
2135 priv->abyBBVGA[1] = 0x10;
2136 priv->abyBBVGA[2] = 0x0;
2137 priv->abyBBVGA[3] = 0x0;
2138 priv->ldBmThreshold[0] = -70;
2139 priv->ldBmThreshold[1] = -48;
2140 priv->ldBmThreshold[2] = 0;
2141 priv->ldBmThreshold[3] = 0;
2142 /* Fix VT3226 DFC system timing issue */
2143 MACvSetRFLE_LatchBase(iobase);
2144 /* {{ RobertYu: 20050104 */
2145 } else if (byRFType == RF_AIROHA7230) {
2146 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2147 bResult &= BBbWriteEmbedded(priv,
2148 byVT3253B0_AIROHA2230[ii][0],
2149 byVT3253B0_AIROHA2230[ii][1]);
2151 /* {{ RobertYu:20050223, request by JerryChung */
2152 /* Init ANT B select,TX Config CR09 = 0x61->0x45,
2153 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2155 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2156 /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
2157 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2159 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2160 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2161 bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2164 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2165 bResult &= BBbWriteEmbedded(priv,
2166 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2168 priv->abyBBVGA[0] = 0x1C;
2169 priv->abyBBVGA[1] = 0x10;
2170 priv->abyBBVGA[2] = 0x0;
2171 priv->abyBBVGA[3] = 0x0;
2172 priv->ldBmThreshold[0] = -70;
2173 priv->ldBmThreshold[1] = -48;
2174 priv->ldBmThreshold[2] = 0;
2175 priv->ldBmThreshold[3] = 0;
2178 /* No VGA Table now */
2179 priv->bUpdateBBVGA = false;
2180 priv->abyBBVGA[0] = 0x1C;
2183 if (byLocalID > REV_ID_VT3253_A1) {
2184 BBbWriteEmbedded(priv, 0x04, 0x7F);
2185 BBbWriteEmbedded(priv, 0x0D, 0x01);
2192 * Description: Set ShortSlotTime mode
2196 * priv - Device Structure
2200 * Return Value: none
2204 BBvSetShortSlotTime(struct vnt_private *priv)
2206 unsigned char byBBRxConf = 0;
2207 unsigned char byBBVGA = 0;
2209 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2211 if (priv->bShortSlotTime)
2212 byBBRxConf &= 0xDF; /* 1101 1111 */
2214 byBBRxConf |= 0x20; /* 0010 0000 */
2216 /* patch for 3253B0 Baseband with Cardbus module */
2217 BBbReadEmbedded(priv, 0xE7, &byBBVGA);
2218 if (byBBVGA == priv->abyBBVGA[0])
2219 byBBRxConf |= 0x20; /* 0010 0000 */
2221 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2224 void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData)
2226 unsigned char byBBRxConf = 0;
2228 BBbWriteEmbedded(priv, 0xE7, byData);
2230 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2231 /* patch for 3253B0 Baseband with Cardbus module */
2232 if (byData == priv->abyBBVGA[0])
2233 byBBRxConf |= 0x20; /* 0010 0000 */
2234 else if (priv->bShortSlotTime)
2235 byBBRxConf &= 0xDF; /* 1101 1111 */
2237 byBBRxConf |= 0x20; /* 0010 0000 */
2238 priv->byBBVGACurrent = byData;
2239 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2243 * Description: Baseband SoftwareReset
2247 * iobase - I/O base address
2251 * Return Value: none
2255 BBvSoftwareReset(struct vnt_private *priv)
2257 BBbWriteEmbedded(priv, 0x50, 0x40);
2258 BBbWriteEmbedded(priv, 0x50, 0);
2259 BBbWriteEmbedded(priv, 0x9C, 0x01);
2260 BBbWriteEmbedded(priv, 0x9C, 0);
2264 * Description: Baseband Power Save Mode ON
2268 * iobase - I/O base address
2272 * Return Value: none
2276 BBvPowerSaveModeON(struct vnt_private *priv)
2278 unsigned char byOrgData;
2280 BBbReadEmbedded(priv, 0x0D, &byOrgData);
2281 byOrgData |= BIT(0);
2282 BBbWriteEmbedded(priv, 0x0D, byOrgData);
2286 * Description: Baseband Power Save Mode OFF
2290 * iobase - I/O base address
2294 * Return Value: none
2298 BBvPowerSaveModeOFF(struct vnt_private *priv)
2300 unsigned char byOrgData;
2302 BBbReadEmbedded(priv, 0x0D, &byOrgData);
2303 byOrgData &= ~(BIT(0));
2304 BBbWriteEmbedded(priv, 0x0D, byOrgData);
2308 * Description: Set Tx Antenna mode
2312 * priv - Device Structure
2313 * byAntennaMode - Antenna Mode
2317 * Return Value: none
2322 BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2324 unsigned char byBBTxConf;
2326 BBbReadEmbedded(priv, 0x09, &byBBTxConf); /* CR09 */
2327 if (byAntennaMode == ANT_DIVERSITY) {
2328 /* bit 1 is diversity */
2330 } else if (byAntennaMode == ANT_A) {
2331 /* bit 2 is ANTSEL */
2332 byBBTxConf &= 0xF9; /* 1111 1001 */
2333 } else if (byAntennaMode == ANT_B) {
2334 byBBTxConf &= 0xFD; /* 1111 1101 */
2337 BBbWriteEmbedded(priv, 0x09, byBBTxConf); /* CR09 */
2341 * Description: Set Rx Antenna mode
2345 * priv - Device Structure
2346 * byAntennaMode - Antenna Mode
2350 * Return Value: none
2355 BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2357 unsigned char byBBRxConf;
2359 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2360 if (byAntennaMode == ANT_DIVERSITY) {
2363 } else if (byAntennaMode == ANT_A) {
2364 byBBRxConf &= 0xFC; /* 1111 1100 */
2365 } else if (byAntennaMode == ANT_B) {
2366 byBBRxConf &= 0xFE; /* 1111 1110 */
2369 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2373 * Description: BBvSetDeepSleep
2377 * priv - Device Structure
2381 * Return Value: none
2385 BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2387 BBbWriteEmbedded(priv, 0x0C, 0x17); /* CR12 */
2388 BBbWriteEmbedded(priv, 0x0D, 0xB9); /* CR13 */
2392 BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2394 BBbWriteEmbedded(priv, 0x0C, 0x00); /* CR12 */
2395 BBbWriteEmbedded(priv, 0x0D, 0x01); /* CR13 */