4 * Support for the Tundra TSI148 VME Bridge chip
6 * Author: Tom Armistead
7 * Updated and maintained by Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
19 #ifndef PCI_VENDOR_ID_TUNDRA
20 #define PCI_VENDOR_ID_TUNDRA 0x10e3
23 #ifndef PCI_DEVICE_ID_TUNDRA_TSI148
24 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x148
28 * Define the number of each that the Tsi148 supports.
30 #define TSI148_MAX_MASTER 8 /* Max Master Windows */
31 #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
32 #define TSI148_MAX_DMA 2 /* Max DMA Controllers */
33 #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */
34 #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
37 * Layout of a DMAC Linked-List Descriptor
39 * Note: This structure is accessed via the chip and therefore must be
40 * correctly laid out - It must also be aligned on 64-bit boundaries.
42 struct tsi148_dma_descriptor {
43 u32 dsau; /* Source Address */
45 u32 ddau; /* Destination Address */
47 u32 dsat; /* Source attributes */
48 u32 ddat; /* Destination attributes */
49 u32 dnlau; /* Next link address */
51 u32 dcnt; /* Byte count */
52 u32 ddbs; /* 2eSST Broadcast select */
55 struct tsi148_dma_entry {
57 * The descriptor needs to be aligned on a 64-bit boundary, we increase
58 * the chance of this by putting it first in the structure.
60 struct tsi148_dma_descriptor descriptor;
61 struct list_head list;
65 * TSI148 ASIC register structure overlays and bit field definitions.
67 * Note: Tsi148 Register Group (CRG) consists of the following
68 * combination of registers:
69 * PCFS - PCI Configuration Space Registers
70 * LCSR - Local Control and Status Registers
71 * GCSR - Global Control and Status Registers
72 * CR/CSR - Subset of Configuration ROM /
73 * Control and Status Registers
78 * Command/Status Registers (CRG + $004)
80 #define TSI148_PCFS_ID 0x0
81 #define TSI148_PCFS_CSR 0x4
82 #define TSI148_PCFS_CLASS 0x8
83 #define TSI148_PCFS_MISC0 0xC
84 #define TSI148_PCFS_MBARL 0x10
85 #define TSI148_PCFS_MBARU 0x14
87 #define TSI148_PCFS_SUBID 0x28
89 #define TSI148_PCFS_CAPP 0x34
91 #define TSI148_PCFS_MISC1 0x3C
93 #define TSI148_PCFS_XCAPP 0x40
94 #define TSI148_PCFS_XSTAT 0x44
101 * Outbound Translations
103 #define TSI148_LCSR_OT0_OTSAU 0x100
104 #define TSI148_LCSR_OT0_OTSAL 0x104
105 #define TSI148_LCSR_OT0_OTEAU 0x108
106 #define TSI148_LCSR_OT0_OTEAL 0x10C
107 #define TSI148_LCSR_OT0_OTOFU 0x110
108 #define TSI148_LCSR_OT0_OTOFL 0x114
109 #define TSI148_LCSR_OT0_OTBS 0x118
110 #define TSI148_LCSR_OT0_OTAT 0x11C
112 #define TSI148_LCSR_OT1_OTSAU 0x120
113 #define TSI148_LCSR_OT1_OTSAL 0x124
114 #define TSI148_LCSR_OT1_OTEAU 0x128
115 #define TSI148_LCSR_OT1_OTEAL 0x12C
116 #define TSI148_LCSR_OT1_OTOFU 0x130
117 #define TSI148_LCSR_OT1_OTOFL 0x134
118 #define TSI148_LCSR_OT1_OTBS 0x138
119 #define TSI148_LCSR_OT1_OTAT 0x13C
121 #define TSI148_LCSR_OT2_OTSAU 0x140
122 #define TSI148_LCSR_OT2_OTSAL 0x144
123 #define TSI148_LCSR_OT2_OTEAU 0x148
124 #define TSI148_LCSR_OT2_OTEAL 0x14C
125 #define TSI148_LCSR_OT2_OTOFU 0x150
126 #define TSI148_LCSR_OT2_OTOFL 0x154
127 #define TSI148_LCSR_OT2_OTBS 0x158
128 #define TSI148_LCSR_OT2_OTAT 0x15C
130 #define TSI148_LCSR_OT3_OTSAU 0x160
131 #define TSI148_LCSR_OT3_OTSAL 0x164
132 #define TSI148_LCSR_OT3_OTEAU 0x168
133 #define TSI148_LCSR_OT3_OTEAL 0x16C
134 #define TSI148_LCSR_OT3_OTOFU 0x170
135 #define TSI148_LCSR_OT3_OTOFL 0x174
136 #define TSI148_LCSR_OT3_OTBS 0x178
137 #define TSI148_LCSR_OT3_OTAT 0x17C
139 #define TSI148_LCSR_OT4_OTSAU 0x180
140 #define TSI148_LCSR_OT4_OTSAL 0x184
141 #define TSI148_LCSR_OT4_OTEAU 0x188
142 #define TSI148_LCSR_OT4_OTEAL 0x18C
143 #define TSI148_LCSR_OT4_OTOFU 0x190
144 #define TSI148_LCSR_OT4_OTOFL 0x194
145 #define TSI148_LCSR_OT4_OTBS 0x198
146 #define TSI148_LCSR_OT4_OTAT 0x19C
148 #define TSI148_LCSR_OT5_OTSAU 0x1A0
149 #define TSI148_LCSR_OT5_OTSAL 0x1A4
150 #define TSI148_LCSR_OT5_OTEAU 0x1A8
151 #define TSI148_LCSR_OT5_OTEAL 0x1AC
152 #define TSI148_LCSR_OT5_OTOFU 0x1B0
153 #define TSI148_LCSR_OT5_OTOFL 0x1B4
154 #define TSI148_LCSR_OT5_OTBS 0x1B8
155 #define TSI148_LCSR_OT5_OTAT 0x1BC
157 #define TSI148_LCSR_OT6_OTSAU 0x1C0
158 #define TSI148_LCSR_OT6_OTSAL 0x1C4
159 #define TSI148_LCSR_OT6_OTEAU 0x1C8
160 #define TSI148_LCSR_OT6_OTEAL 0x1CC
161 #define TSI148_LCSR_OT6_OTOFU 0x1D0
162 #define TSI148_LCSR_OT6_OTOFL 0x1D4
163 #define TSI148_LCSR_OT6_OTBS 0x1D8
164 #define TSI148_LCSR_OT6_OTAT 0x1DC
166 #define TSI148_LCSR_OT7_OTSAU 0x1E0
167 #define TSI148_LCSR_OT7_OTSAL 0x1E4
168 #define TSI148_LCSR_OT7_OTEAU 0x1E8
169 #define TSI148_LCSR_OT7_OTEAL 0x1EC
170 #define TSI148_LCSR_OT7_OTOFU 0x1F0
171 #define TSI148_LCSR_OT7_OTOFL 0x1F4
172 #define TSI148_LCSR_OT7_OTBS 0x1F8
173 #define TSI148_LCSR_OT7_OTAT 0x1FC
175 #define TSI148_LCSR_OT0 0x100
176 #define TSI148_LCSR_OT1 0x120
177 #define TSI148_LCSR_OT2 0x140
178 #define TSI148_LCSR_OT3 0x160
179 #define TSI148_LCSR_OT4 0x180
180 #define TSI148_LCSR_OT5 0x1A0
181 #define TSI148_LCSR_OT6 0x1C0
182 #define TSI148_LCSR_OT7 0x1E0
184 static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
185 TSI148_LCSR_OT2, TSI148_LCSR_OT3,
186 TSI148_LCSR_OT4, TSI148_LCSR_OT5,
187 TSI148_LCSR_OT6, TSI148_LCSR_OT7 };
189 #define TSI148_LCSR_OFFSET_OTSAU 0x0
190 #define TSI148_LCSR_OFFSET_OTSAL 0x4
191 #define TSI148_LCSR_OFFSET_OTEAU 0x8
192 #define TSI148_LCSR_OFFSET_OTEAL 0xC
193 #define TSI148_LCSR_OFFSET_OTOFU 0x10
194 #define TSI148_LCSR_OFFSET_OTOFL 0x14
195 #define TSI148_LCSR_OFFSET_OTBS 0x18
196 #define TSI148_LCSR_OFFSET_OTAT 0x1C
199 * VMEbus interupt ack
202 #define TSI148_LCSR_VIACK1 0x204
203 #define TSI148_LCSR_VIACK2 0x208
204 #define TSI148_LCSR_VIACK3 0x20C
205 #define TSI148_LCSR_VIACK4 0x210
206 #define TSI148_LCSR_VIACK5 0x214
207 #define TSI148_LCSR_VIACK6 0x218
208 #define TSI148_LCSR_VIACK7 0x21C
210 static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
211 TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3,
212 TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5,
213 TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 };
219 #define TSI148_LCSR_RMWAU 0x220
220 #define TSI148_LCSR_RMWAL 0x224
221 #define TSI148_LCSR_RMWEN 0x228
222 #define TSI148_LCSR_RMWC 0x22C
223 #define TSI148_LCSR_RMWS 0x230
229 #define TSI148_LCSR_VMCTRL 0x234
230 #define TSI148_LCSR_VCTRL 0x238
231 #define TSI148_LCSR_VSTAT 0x23C
237 #define TSI148_LCSR_PSTAT 0x240
243 #define TSI148_LCSR_VMEFL 0x250
249 #define TSI148_LCSR_VEAU 0x260
250 #define TSI148_LCSR_VEAL 0x264
251 #define TSI148_LCSR_VEAT 0x268
257 #define TSI148_LCSR_EDPAU 0x270
258 #define TSI148_LCSR_EDPAL 0x274
259 #define TSI148_LCSR_EDPXA 0x278
260 #define TSI148_LCSR_EDPXS 0x27C
261 #define TSI148_LCSR_EDPAT 0x280
264 * Inbound Translations
267 #define TSI148_LCSR_IT0_ITSAU 0x300
268 #define TSI148_LCSR_IT0_ITSAL 0x304
269 #define TSI148_LCSR_IT0_ITEAU 0x308
270 #define TSI148_LCSR_IT0_ITEAL 0x30C
271 #define TSI148_LCSR_IT0_ITOFU 0x310
272 #define TSI148_LCSR_IT0_ITOFL 0x314
273 #define TSI148_LCSR_IT0_ITAT 0x318
275 #define TSI148_LCSR_IT1_ITSAU 0x320
276 #define TSI148_LCSR_IT1_ITSAL 0x324
277 #define TSI148_LCSR_IT1_ITEAU 0x328
278 #define TSI148_LCSR_IT1_ITEAL 0x32C
279 #define TSI148_LCSR_IT1_ITOFU 0x330
280 #define TSI148_LCSR_IT1_ITOFL 0x334
281 #define TSI148_LCSR_IT1_ITAT 0x338
283 #define TSI148_LCSR_IT2_ITSAU 0x340
284 #define TSI148_LCSR_IT2_ITSAL 0x344
285 #define TSI148_LCSR_IT2_ITEAU 0x348
286 #define TSI148_LCSR_IT2_ITEAL 0x34C
287 #define TSI148_LCSR_IT2_ITOFU 0x350
288 #define TSI148_LCSR_IT2_ITOFL 0x354
289 #define TSI148_LCSR_IT2_ITAT 0x358
291 #define TSI148_LCSR_IT3_ITSAU 0x360
292 #define TSI148_LCSR_IT3_ITSAL 0x364
293 #define TSI148_LCSR_IT3_ITEAU 0x368
294 #define TSI148_LCSR_IT3_ITEAL 0x36C
295 #define TSI148_LCSR_IT3_ITOFU 0x370
296 #define TSI148_LCSR_IT3_ITOFL 0x374
297 #define TSI148_LCSR_IT3_ITAT 0x378
299 #define TSI148_LCSR_IT4_ITSAU 0x380
300 #define TSI148_LCSR_IT4_ITSAL 0x384
301 #define TSI148_LCSR_IT4_ITEAU 0x388
302 #define TSI148_LCSR_IT4_ITEAL 0x38C
303 #define TSI148_LCSR_IT4_ITOFU 0x390
304 #define TSI148_LCSR_IT4_ITOFL 0x394
305 #define TSI148_LCSR_IT4_ITAT 0x398
307 #define TSI148_LCSR_IT5_ITSAU 0x3A0
308 #define TSI148_LCSR_IT5_ITSAL 0x3A4
309 #define TSI148_LCSR_IT5_ITEAU 0x3A8
310 #define TSI148_LCSR_IT5_ITEAL 0x3AC
311 #define TSI148_LCSR_IT5_ITOFU 0x3B0
312 #define TSI148_LCSR_IT5_ITOFL 0x3B4
313 #define TSI148_LCSR_IT5_ITAT 0x3B8
315 #define TSI148_LCSR_IT6_ITSAU 0x3C0
316 #define TSI148_LCSR_IT6_ITSAL 0x3C4
317 #define TSI148_LCSR_IT6_ITEAU 0x3C8
318 #define TSI148_LCSR_IT6_ITEAL 0x3CC
319 #define TSI148_LCSR_IT6_ITOFU 0x3D0
320 #define TSI148_LCSR_IT6_ITOFL 0x3D4
321 #define TSI148_LCSR_IT6_ITAT 0x3D8
323 #define TSI148_LCSR_IT7_ITSAU 0x3E0
324 #define TSI148_LCSR_IT7_ITSAL 0x3E4
325 #define TSI148_LCSR_IT7_ITEAU 0x3E8
326 #define TSI148_LCSR_IT7_ITEAL 0x3EC
327 #define TSI148_LCSR_IT7_ITOFU 0x3F0
328 #define TSI148_LCSR_IT7_ITOFL 0x3F4
329 #define TSI148_LCSR_IT7_ITAT 0x3F8
332 #define TSI148_LCSR_IT0 0x300
333 #define TSI148_LCSR_IT1 0x320
334 #define TSI148_LCSR_IT2 0x340
335 #define TSI148_LCSR_IT3 0x360
336 #define TSI148_LCSR_IT4 0x380
337 #define TSI148_LCSR_IT5 0x3A0
338 #define TSI148_LCSR_IT6 0x3C0
339 #define TSI148_LCSR_IT7 0x3E0
341 static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
342 TSI148_LCSR_IT2, TSI148_LCSR_IT3,
343 TSI148_LCSR_IT4, TSI148_LCSR_IT5,
344 TSI148_LCSR_IT6, TSI148_LCSR_IT7 };
346 #define TSI148_LCSR_OFFSET_ITSAU 0x0
347 #define TSI148_LCSR_OFFSET_ITSAL 0x4
348 #define TSI148_LCSR_OFFSET_ITEAU 0x8
349 #define TSI148_LCSR_OFFSET_ITEAL 0xC
350 #define TSI148_LCSR_OFFSET_ITOFU 0x10
351 #define TSI148_LCSR_OFFSET_ITOFL 0x14
352 #define TSI148_LCSR_OFFSET_ITAT 0x18
355 * Inbound Translation GCSR
358 #define TSI148_LCSR_GBAU 0x400
359 #define TSI148_LCSR_GBAL 0x404
360 #define TSI148_LCSR_GCSRAT 0x408
363 * Inbound Translation CRG
366 #define TSI148_LCSR_CBAU 0x40C
367 #define TSI148_LCSR_CBAL 0x410
368 #define TSI148_LCSR_CSRAT 0x414
371 * Inbound Translation CR/CSR
375 #define TSI148_LCSR_CROU 0x418
376 #define TSI148_LCSR_CROL 0x41C
377 #define TSI148_LCSR_CRAT 0x420
380 * Inbound Translation Location Monitor
383 #define TSI148_LCSR_LMBAU 0x424
384 #define TSI148_LCSR_LMBAL 0x428
385 #define TSI148_LCSR_LMAT 0x42C
388 * VMEbus Interrupt Control.
391 #define TSI148_LCSR_BCU 0x430
392 #define TSI148_LCSR_BCL 0x434
393 #define TSI148_LCSR_BPGTR 0x438
394 #define TSI148_LCSR_BPCTR 0x43C
395 #define TSI148_LCSR_VICR 0x440
398 * Local Bus Interrupt Control.
401 #define TSI148_LCSR_INTEN 0x448
402 #define TSI148_LCSR_INTEO 0x44C
403 #define TSI148_LCSR_INTS 0x450
404 #define TSI148_LCSR_INTC 0x454
405 #define TSI148_LCSR_INTM1 0x458
406 #define TSI148_LCSR_INTM2 0x45C
412 #define TSI148_LCSR_DCTL0 0x500
413 #define TSI148_LCSR_DSTA0 0x504
414 #define TSI148_LCSR_DCSAU0 0x508
415 #define TSI148_LCSR_DCSAL0 0x50C
416 #define TSI148_LCSR_DCDAU0 0x510
417 #define TSI148_LCSR_DCDAL0 0x514
418 #define TSI148_LCSR_DCLAU0 0x518
419 #define TSI148_LCSR_DCLAL0 0x51C
420 #define TSI148_LCSR_DSAU0 0x520
421 #define TSI148_LCSR_DSAL0 0x524
422 #define TSI148_LCSR_DDAU0 0x528
423 #define TSI148_LCSR_DDAL0 0x52C
424 #define TSI148_LCSR_DSAT0 0x530
425 #define TSI148_LCSR_DDAT0 0x534
426 #define TSI148_LCSR_DNLAU0 0x538
427 #define TSI148_LCSR_DNLAL0 0x53C
428 #define TSI148_LCSR_DCNT0 0x540
429 #define TSI148_LCSR_DDBS0 0x544
431 #define TSI148_LCSR_DCTL1 0x580
432 #define TSI148_LCSR_DSTA1 0x584
433 #define TSI148_LCSR_DCSAU1 0x588
434 #define TSI148_LCSR_DCSAL1 0x58C
435 #define TSI148_LCSR_DCDAU1 0x590
436 #define TSI148_LCSR_DCDAL1 0x594
437 #define TSI148_LCSR_DCLAU1 0x598
438 #define TSI148_LCSR_DCLAL1 0x59C
439 #define TSI148_LCSR_DSAU1 0x5A0
440 #define TSI148_LCSR_DSAL1 0x5A4
441 #define TSI148_LCSR_DDAU1 0x5A8
442 #define TSI148_LCSR_DDAL1 0x5AC
443 #define TSI148_LCSR_DSAT1 0x5B0
444 #define TSI148_LCSR_DDAT1 0x5B4
445 #define TSI148_LCSR_DNLAU1 0x5B8
446 #define TSI148_LCSR_DNLAL1 0x5BC
447 #define TSI148_LCSR_DCNT1 0x5C0
448 #define TSI148_LCSR_DDBS1 0x5C4
450 #define TSI148_LCSR_DMA0 0x500
451 #define TSI148_LCSR_DMA1 0x580
454 static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
457 #define TSI148_LCSR_OFFSET_DCTL 0x0
458 #define TSI148_LCSR_OFFSET_DSTA 0x4
459 #define TSI148_LCSR_OFFSET_DCSAU 0x8
460 #define TSI148_LCSR_OFFSET_DCSAL 0xC
461 #define TSI148_LCSR_OFFSET_DCDAU 0x10
462 #define TSI148_LCSR_OFFSET_DCDAL 0x14
463 #define TSI148_LCSR_OFFSET_DCLAU 0x18
464 #define TSI148_LCSR_OFFSET_DCLAL 0x1C
465 #define TSI148_LCSR_OFFSET_DSAU 0x20
466 #define TSI148_LCSR_OFFSET_DSAL 0x24
467 #define TSI148_LCSR_OFFSET_DDAU 0x28
468 #define TSI148_LCSR_OFFSET_DDAL 0x2C
469 #define TSI148_LCSR_OFFSET_DSAT 0x30
470 #define TSI148_LCSR_OFFSET_DDAT 0x34
471 #define TSI148_LCSR_OFFSET_DNLAU 0x38
472 #define TSI148_LCSR_OFFSET_DNLAL 0x3C
473 #define TSI148_LCSR_OFFSET_DCNT 0x40
474 #define TSI148_LCSR_OFFSET_DDBS 0x44
477 * GCSR Register Group
482 * offset 00 600 - DEVI/VENI
483 * offset 04 604 - CTRL/GA/REVID
484 * offset 08 608 - Semaphore3/2/1/0
485 * offset 0C 60C - Seamphore7/6/5/4
487 #define TSI148_GCSR_ID 0x600
488 #define TSI148_GCSR_CSR 0x604
489 #define TSI148_GCSR_SEMA0 0x608
490 #define TSI148_GCSR_SEMA1 0x60C
495 * offset 10 610 - Mailbox0
497 #define TSI148_GCSR_MBOX0 0x610
498 #define TSI148_GCSR_MBOX1 0x614
499 #define TSI148_GCSR_MBOX2 0x618
500 #define TSI148_GCSR_MBOX3 0x61C
502 static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
513 * offset 7FFF4 FF4 - CSRBCR
514 * offset 7FFF8 FF8 - CSRBSR
515 * offset 7FFFC FFC - CBAR
517 #define TSI148_CSRBCR 0xFF4
518 #define TSI148_CSRBSR 0xFF8
519 #define TSI148_CBAR 0xFFC
525 * TSI148 Register Bit Definitions
531 #define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */
532 #define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */
533 #define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */
534 #define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */
535 #define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */
537 #define TSI148_PCFS_STAT_RCPVE (1<<15) /* Detected Parity Error */
538 #define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */
539 #define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */
540 #define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */
541 #define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */
542 #define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */
543 #define TSI148_PCFS_STAT_DPAR (1<<8) /* Data Parity Err Reported */
544 #define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */
545 #define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */
546 #define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */
549 * Revision ID/Class Code Registers (CRG +$008)
551 #define TSI148_PCFS_CLAS_M (0xFF<<24) /* Class ID */
552 #define TSI148_PCFS_SUBCLAS_M (0xFF<<16) /* Sub-Class ID */
553 #define TSI148_PCFS_PROGIF_M (0xFF<<8) /* Sub-Class ID */
554 #define TSI148_PCFS_REVID_M (0xFF<<0) /* Rev ID */
557 * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C)
559 #define TSI148_PCFS_HEAD_M (0xFF<<16) /* Master Lat Timer */
560 #define TSI148_PCFS_MLAT_M (0xFF<<8) /* Master Lat Timer */
561 #define TSI148_PCFS_CLSZ_M (0xFF<<0) /* Cache Line Size */
564 * Memory Base Address Lower Reg (CRG + $010)
566 #define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
567 #define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */
568 #define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */
569 #define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */
572 * Message Signaled Interrupt Capabilities Register (CRG + $040)
574 #define TSI148_PCFS_MSICAP_64BAC (1<<7) /* 64-bit Address Capable */
575 #define TSI148_PCFS_MSICAP_MME_M (7<<4) /* Multiple Msg Enable Mask */
576 #define TSI148_PCFS_MSICAP_MMC_M (7<<1) /* Multiple Msg Capable Mask */
577 #define TSI148_PCFS_MSICAP_MSIEN (1<<0) /* Msg signaled INT Enable */
580 * Message Address Lower Register (CRG +$044)
582 #define TSI148_PCFS_MSIAL_M (0x3FFFFFFF<<2) /* Mask */
585 * Message Data Register (CRG + 4C)
587 #define TSI148_PCFS_MSIMD_M (0xFFFF<<0) /* Mask */
590 * PCI-X Capabilities Register (CRG + $050)
592 #define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */
593 #define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */
594 #define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */
595 #define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */
598 * PCI-X Status Register (CRG +$054)
600 #define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Recieved Split Comp Error */
601 #define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
602 #define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans */
603 #define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
604 #define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */
605 #define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */
606 #define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */
607 #define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */
608 #define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */
609 #define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */
610 #define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */
611 #define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */
618 * Outbound Translation Starting Address Lower
620 #define TSI148_LCSR_OTSAL_M (0xFFFF<<16) /* Mask */
623 * Outbound Translation Ending Address Lower
625 #define TSI148_LCSR_OTEAL_M (0xFFFF<<16) /* Mask */
628 * Outbound Translation Offset Lower
630 #define TSI148_LCSR_OTOFFL_M (0xFFFF<<16) /* Mask */
633 * Outbound Translation 2eSST Broadcast Select
635 #define TSI148_LCSR_OTBS_M (0xFFFFF<<0) /* Mask */
638 * Outbound Translation Attribute
640 #define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */
641 #define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */
643 #define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */
644 #define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */
645 #define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */
646 #define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */
647 #define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */
649 #define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */
650 #define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */
651 #define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */
652 #define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */
654 #define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */
655 #define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */
656 #define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */
657 #define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */
658 #define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */
659 #define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */
660 #define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8) /* 2eSST Bcast Xfer Protocol */
662 #define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */
663 #define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */
664 #define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */
666 #define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */
667 #define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */
669 #define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */
670 #define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */
671 #define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */
672 #define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */
673 #define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */
674 #define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */
675 #define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0) /* User1 Address Space */
676 #define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0) /* User2 Address Space */
677 #define TSI148_LCSR_OTAT_AMODE_USER3 (10<<0) /* User3 Address Space */
678 #define TSI148_LCSR_OTAT_AMODE_USER4 (11<<0) /* User4 Address Space */
681 * VME Master Control Register CRG+$234
683 #define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */
684 #define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */
685 #define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */
686 #define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */
688 #define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */
690 #define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask */
691 #define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */
692 #define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */
693 #define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */
694 #define TSI148_LCSR_VMCTRL_ATO_2M (3<<16) /* 2 ms */
695 #define TSI148_LCSR_VMCTRL_ATO_8M (4<<16) /* 8 ms */
696 #define TSI148_LCSR_VMCTRL_ATO_32M (5<<16) /* 32 ms */
697 #define TSI148_LCSR_VMCTRL_ATO_128M (6<<16) /* 128 ms */
698 #define TSI148_LCSR_VMCTRL_ATO_DIS (7<<16) /* Disabled */
700 #define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */
701 #define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */
702 #define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */
703 #define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */
704 #define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */
705 #define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */
706 #define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */
707 #define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */
708 #define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */
710 #define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */
711 #define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */
712 #define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */
713 #define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */
714 #define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */
715 #define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */
716 #define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */
717 #define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */
718 #define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */
720 #define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask */
721 #define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */
722 #define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */
723 #define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */
724 #define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */
726 #define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */
727 #define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask */
730 * VMEbus Control Register CRG+$238
732 #define TSI148_LCSR_VCTRL_LRE (1<<31) /* Late Retry Enable */
734 #define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */
735 #define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */
736 #define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */
737 #define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */
738 #define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */
739 #define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */
740 #define TSI148_LCSR_VCTRL_DLT_256 (5<<24) /* 256 VCLKS */
741 #define TSI148_LCSR_VCTRL_DLT_512 (6<<24) /* 512 VCLKS */
742 #define TSI148_LCSR_VCTRL_DLT_1024 (7<<24) /* 1024 VCLKS */
743 #define TSI148_LCSR_VCTRL_DLT_2048 (8<<24) /* 2048 VCLKS */
744 #define TSI148_LCSR_VCTRL_DLT_4096 (9<<24) /* 4096 VCLKS */
745 #define TSI148_LCSR_VCTRL_DLT_8192 (0xA<<24) /* 8192 VCLKS */
746 #define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */
747 #define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */
749 #define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy */
751 #define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */
752 #define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */
754 #define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */
755 #define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */
757 #define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */
758 #define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */
760 #define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask */
761 #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
762 #define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
763 #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
764 #define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */
765 #define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */
766 #define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */
767 #define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */
768 #define TSI148_LCSR_VCTRL_GTO_DIS (7<<0) /* Disabled */
771 * VMEbus Status Register CRG + $23C
773 #define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */
774 #define TSI148_LCSR_VSTAT_BRDFL (1<<14) /* Board fail */
775 #define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */
776 #define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */
777 #define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */
778 #define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */
779 #define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */
780 #define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */
781 #define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
784 * PCI Configuration Status Register CRG+$240
786 #define TSI148_LCSR_PSTAT_REQ64S (1<<6) /* Request 64 status set */
787 #define TSI148_LCSR_PSTAT_M66ENS (1<<5) /* M66ENS 66Mhz enable */
788 #define TSI148_LCSR_PSTAT_FRAMES (1<<4) /* Frame Status */
789 #define TSI148_LCSR_PSTAT_IRDYS (1<<3) /* IRDY status */
790 #define TSI148_LCSR_PSTAT_DEVSELS (1<<2) /* DEVL status */
791 #define TSI148_LCSR_PSTAT_STOPS (1<<1) /* STOP status */
792 #define TSI148_LCSR_PSTAT_TRDYS (1<<0) /* TRDY status */
795 * VMEbus Exception Attributes Register CRG + $268
797 #define TSI148_LCSR_VEAT_VES (1<<31) /* Status */
798 #define TSI148_LCSR_VEAT_VEOF (1<<30) /* Overflow */
799 #define TSI148_LCSR_VEAT_VESCL (1<<29) /* Status Clear */
800 #define TSI148_LCSR_VEAT_2EOT (1<<21) /* 2e Odd Termination */
801 #define TSI148_LCSR_VEAT_2EST (1<<20) /* 2e Slave terminated */
802 #define TSI148_LCSR_VEAT_BERR (1<<19) /* Bus Error */
803 #define TSI148_LCSR_VEAT_LWORD (1<<18) /* LWORD_ signal state */
804 #define TSI148_LCSR_VEAT_WRITE (1<<17) /* WRITE_ signal state */
805 #define TSI148_LCSR_VEAT_IACK (1<<16) /* IACK_ signal state */
806 #define TSI148_LCSR_VEAT_DS1 (1<<15) /* DS1_ signal state */
807 #define TSI148_LCSR_VEAT_DS0 (1<<14) /* DS0_ signal state */
808 #define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */
809 #define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */
813 * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280
815 #define TSI148_LCSR_EDPAT_EDPCL (1<<29)
818 * Inbound Translation Starting Address Lower
820 #define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16) /* Mask */
821 #define TSI148_LCSR_ITSAL24_M (0x00FFF<<12) /* Mask */
822 #define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4) /* Mask */
825 * Inbound Translation Ending Address Lower
827 #define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16) /* Mask */
828 #define TSI148_LCSR_ITEAL24_M (0x00FFF<<12) /* Mask */
829 #define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4) /* Mask */
832 * Inbound Translation Offset Lower
834 #define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16) /* Mask */
835 #define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12) /* Mask */
836 #define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4) /* Mask */
839 * Inbound Translation Attribute
841 #define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */
842 #define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */
844 #define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */
845 #define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */
846 #define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */
847 #define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */
848 #define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */
850 #define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */
851 #define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */
852 #define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */
853 #define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */
855 #define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */
856 #define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */
857 #define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */
858 #define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */
859 #define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */
861 #define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */
862 #define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */
863 #define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */
864 #define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */
865 #define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */
867 #define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */
868 #define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */
869 #define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */
870 #define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */
873 * GCSR Base Address Lower Address CRG +$404
875 #define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5) /* Mask */
878 * GCSR Attribute Register CRG + $408
880 #define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */
882 #define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */
883 #define TSI148_LCSR_GCSRAT_AS_A16 (0<<4) /* Address Space 16 */
884 #define TSI148_LCSR_GCSRAT_AS_A24 (1<<4) /* Address Space 24 */
885 #define TSI148_LCSR_GCSRAT_AS_A32 (2<<4) /* Address Space 32 */
886 #define TSI148_LCSR_GCSRAT_AS_A64 (4<<4) /* Address Space 64 */
888 #define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */
889 #define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */
890 #define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */
891 #define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */
894 * CRG Base Address Lower Address CRG + $410
896 #define TSI148_LCSR_CBAL_M (0xFFFFF<<12)
899 * CRG Attribute Register CRG + $414
901 #define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */
903 #define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */
904 #define TSI148_LCSR_CRGAT_AS_A16 (0<<4) /* Address Space 16 */
905 #define TSI148_LCSR_CRGAT_AS_A24 (1<<4) /* Address Space 24 */
906 #define TSI148_LCSR_CRGAT_AS_A32 (2<<4) /* Address Space 32 */
907 #define TSI148_LCSR_CRGAT_AS_A64 (4<<4) /* Address Space 64 */
909 #define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */
910 #define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */
911 #define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */
912 #define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */
915 * CR/CSR Offset Lower Register CRG + $41C
917 #define TSI148_LCSR_CROL_M (0x1FFF<<19) /* Mask */
920 * CR/CSR Attribute register CRG + $420
922 #define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */
925 * Location Monitor base address lower register CRG + $428
927 #define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5) /* Mask */
930 * Location Monitor Attribute Register CRG + $42C
932 #define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */
934 #define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */
935 #define TSI148_LCSR_LMAT_AS_A16 (0<<4) /* A16 */
936 #define TSI148_LCSR_LMAT_AS_A24 (1<<4) /* A24 */
937 #define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */
938 #define TSI148_LCSR_LMAT_AS_A64 (4<<4) /* A64 */
940 #define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */
941 #define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */
942 #define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */
943 #define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */
946 * Broadcast Pulse Generator Timer Register CRG + $438
948 #define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0) /* Mask */
951 * Broadcast Programmable Clock Timer Register CRG + $43C
953 #define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0) /* Mask */
956 * VMEbus Interrupt Control Register CRG + $43C
958 #define TSI148_LCSR_VICR_CNTS_M (3<<22) /* Cntr Source MASK */
959 #define TSI148_LCSR_VICR_CNTS_DIS (1<<22) /* Cntr Disable */
960 #define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */
961 #define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */
963 #define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interupt MASK */
964 #define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interupt Disable */
965 #define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */
966 #define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */
968 #define TSI148_LCSR_VICR_IRQIF_M (3<<18) /* IRQ1* Function MASK */
969 #define TSI148_LCSR_VICR_IRQIF_NORM (1<<18) /* Normal */
970 #define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18) /* Pulse Generator */
971 #define TSI148_LCSR_VICR_IRQIF_PROG (3<<18) /* Programmable Clock */
972 #define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */
974 #define TSI148_LCSR_VICR_IRQ2F_M (3<<16) /* IRQ2* Function MASK */
975 #define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16) /* Normal */
976 #define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16) /* Pulse Generator */
977 #define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16) /* Programmable Clock */
978 #define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */
980 #define TSI148_LCSR_VICR_BIP (1<<15) /* Broadcast Interrupt Pulse */
982 #define TSI148_LCSR_VICR_IRQC (1<<12) /* VMEbus IRQ Clear */
983 #define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */
985 #define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */
986 #define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */
987 #define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */
988 #define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */
989 #define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */
990 #define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */
991 #define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */
992 #define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */
994 static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1,
995 TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3,
996 TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5,
997 TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 };
999 #define TSI148_LCSR_VICR_STID_M (0xFF<<0) /* Status/ID Mask */
1002 * Interrupt Enable Register CRG + $440
1004 #define TSI148_LCSR_INTEN_DMA1EN (1<<25) /* DMAC 1 */
1005 #define TSI148_LCSR_INTEN_DMA0EN (1<<24) /* DMAC 0 */
1006 #define TSI148_LCSR_INTEN_LM3EN (1<<23) /* Location Monitor 3 */
1007 #define TSI148_LCSR_INTEN_LM2EN (1<<22) /* Location Monitor 2 */
1008 #define TSI148_LCSR_INTEN_LM1EN (1<<21) /* Location Monitor 1 */
1009 #define TSI148_LCSR_INTEN_LM0EN (1<<20) /* Location Monitor 0 */
1010 #define TSI148_LCSR_INTEN_MB3EN (1<<19) /* Mail Box 3 */
1011 #define TSI148_LCSR_INTEN_MB2EN (1<<18) /* Mail Box 2 */
1012 #define TSI148_LCSR_INTEN_MB1EN (1<<17) /* Mail Box 1 */
1013 #define TSI148_LCSR_INTEN_MB0EN (1<<16) /* Mail Box 0 */
1014 #define TSI148_LCSR_INTEN_PERREN (1<<13) /* PCI/X Error */
1015 #define TSI148_LCSR_INTEN_VERREN (1<<12) /* VMEbus Error */
1016 #define TSI148_LCSR_INTEN_VIEEN (1<<11) /* VMEbus IRQ Edge */
1017 #define TSI148_LCSR_INTEN_IACKEN (1<<10) /* IACK */
1018 #define TSI148_LCSR_INTEN_SYSFLEN (1<<9) /* System Fail */
1019 #define TSI148_LCSR_INTEN_ACFLEN (1<<8) /* AC Fail */
1020 #define TSI148_LCSR_INTEN_IRQ7EN (1<<7) /* IRQ7 */
1021 #define TSI148_LCSR_INTEN_IRQ6EN (1<<6) /* IRQ6 */
1022 #define TSI148_LCSR_INTEN_IRQ5EN (1<<5) /* IRQ5 */
1023 #define TSI148_LCSR_INTEN_IRQ4EN (1<<4) /* IRQ4 */
1024 #define TSI148_LCSR_INTEN_IRQ3EN (1<<3) /* IRQ3 */
1025 #define TSI148_LCSR_INTEN_IRQ2EN (1<<2) /* IRQ2 */
1026 #define TSI148_LCSR_INTEN_IRQ1EN (1<<1) /* IRQ1 */
1028 static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN,
1029 TSI148_LCSR_INTEN_LM1EN,
1030 TSI148_LCSR_INTEN_LM2EN,
1031 TSI148_LCSR_INTEN_LM3EN };
1033 static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN,
1034 TSI148_LCSR_INTEN_IRQ2EN,
1035 TSI148_LCSR_INTEN_IRQ3EN,
1036 TSI148_LCSR_INTEN_IRQ4EN,
1037 TSI148_LCSR_INTEN_IRQ5EN,
1038 TSI148_LCSR_INTEN_IRQ6EN,
1039 TSI148_LCSR_INTEN_IRQ7EN };
1042 * Interrupt Enable Out Register CRG + $444
1044 #define TSI148_LCSR_INTEO_DMA1EO (1<<25) /* DMAC 1 */
1045 #define TSI148_LCSR_INTEO_DMA0EO (1<<24) /* DMAC 0 */
1046 #define TSI148_LCSR_INTEO_LM3EO (1<<23) /* Loc Monitor 3 */
1047 #define TSI148_LCSR_INTEO_LM2EO (1<<22) /* Loc Monitor 2 */
1048 #define TSI148_LCSR_INTEO_LM1EO (1<<21) /* Loc Monitor 1 */
1049 #define TSI148_LCSR_INTEO_LM0EO (1<<20) /* Location Monitor 0 */
1050 #define TSI148_LCSR_INTEO_MB3EO (1<<19) /* Mail Box 3 */
1051 #define TSI148_LCSR_INTEO_MB2EO (1<<18) /* Mail Box 2 */
1052 #define TSI148_LCSR_INTEO_MB1EO (1<<17) /* Mail Box 1 */
1053 #define TSI148_LCSR_INTEO_MB0EO (1<<16) /* Mail Box 0 */
1054 #define TSI148_LCSR_INTEO_PERREO (1<<13) /* PCI/X Error */
1055 #define TSI148_LCSR_INTEO_VERREO (1<<12) /* VMEbus Error */
1056 #define TSI148_LCSR_INTEO_VIEEO (1<<11) /* VMEbus IRQ Edge */
1057 #define TSI148_LCSR_INTEO_IACKEO (1<<10) /* IACK */
1058 #define TSI148_LCSR_INTEO_SYSFLEO (1<<9) /* System Fail */
1059 #define TSI148_LCSR_INTEO_ACFLEO (1<<8) /* AC Fail */
1060 #define TSI148_LCSR_INTEO_IRQ7EO (1<<7) /* IRQ7 */
1061 #define TSI148_LCSR_INTEO_IRQ6EO (1<<6) /* IRQ6 */
1062 #define TSI148_LCSR_INTEO_IRQ5EO (1<<5) /* IRQ5 */
1063 #define TSI148_LCSR_INTEO_IRQ4EO (1<<4) /* IRQ4 */
1064 #define TSI148_LCSR_INTEO_IRQ3EO (1<<3) /* IRQ3 */
1065 #define TSI148_LCSR_INTEO_IRQ2EO (1<<2) /* IRQ2 */
1066 #define TSI148_LCSR_INTEO_IRQ1EO (1<<1) /* IRQ1 */
1068 static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO,
1069 TSI148_LCSR_INTEO_LM1EO,
1070 TSI148_LCSR_INTEO_LM2EO,
1071 TSI148_LCSR_INTEO_LM3EO };
1073 static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO,
1074 TSI148_LCSR_INTEO_IRQ2EO,
1075 TSI148_LCSR_INTEO_IRQ3EO,
1076 TSI148_LCSR_INTEO_IRQ4EO,
1077 TSI148_LCSR_INTEO_IRQ5EO,
1078 TSI148_LCSR_INTEO_IRQ6EO,
1079 TSI148_LCSR_INTEO_IRQ7EO };
1082 * Interrupt Status Register CRG + $448
1084 #define TSI148_LCSR_INTS_DMA1S (1<<25) /* DMA 1 */
1085 #define TSI148_LCSR_INTS_DMA0S (1<<24) /* DMA 0 */
1086 #define TSI148_LCSR_INTS_LM3S (1<<23) /* Location Monitor 3 */
1087 #define TSI148_LCSR_INTS_LM2S (1<<22) /* Location Monitor 2 */
1088 #define TSI148_LCSR_INTS_LM1S (1<<21) /* Location Monitor 1 */
1089 #define TSI148_LCSR_INTS_LM0S (1<<20) /* Location Monitor 0 */
1090 #define TSI148_LCSR_INTS_MB3S (1<<19) /* Mail Box 3 */
1091 #define TSI148_LCSR_INTS_MB2S (1<<18) /* Mail Box 2 */
1092 #define TSI148_LCSR_INTS_MB1S (1<<17) /* Mail Box 1 */
1093 #define TSI148_LCSR_INTS_MB0S (1<<16) /* Mail Box 0 */
1094 #define TSI148_LCSR_INTS_PERRS (1<<13) /* PCI/X Error */
1095 #define TSI148_LCSR_INTS_VERRS (1<<12) /* VMEbus Error */
1096 #define TSI148_LCSR_INTS_VIES (1<<11) /* VMEbus IRQ Edge */
1097 #define TSI148_LCSR_INTS_IACKS (1<<10) /* IACK */
1098 #define TSI148_LCSR_INTS_SYSFLS (1<<9) /* System Fail */
1099 #define TSI148_LCSR_INTS_ACFLS (1<<8) /* AC Fail */
1100 #define TSI148_LCSR_INTS_IRQ7S (1<<7) /* IRQ7 */
1101 #define TSI148_LCSR_INTS_IRQ6S (1<<6) /* IRQ6 */
1102 #define TSI148_LCSR_INTS_IRQ5S (1<<5) /* IRQ5 */
1103 #define TSI148_LCSR_INTS_IRQ4S (1<<4) /* IRQ4 */
1104 #define TSI148_LCSR_INTS_IRQ3S (1<<3) /* IRQ3 */
1105 #define TSI148_LCSR_INTS_IRQ2S (1<<2) /* IRQ2 */
1106 #define TSI148_LCSR_INTS_IRQ1S (1<<1) /* IRQ1 */
1108 static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S,
1109 TSI148_LCSR_INTS_LM1S,
1110 TSI148_LCSR_INTS_LM2S,
1111 TSI148_LCSR_INTS_LM3S };
1113 static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S,
1114 TSI148_LCSR_INTS_MB1S,
1115 TSI148_LCSR_INTS_MB2S,
1116 TSI148_LCSR_INTS_MB3S };
1119 * Interrupt Clear Register CRG + $44C
1121 #define TSI148_LCSR_INTC_DMA1C (1<<25) /* DMA 1 */
1122 #define TSI148_LCSR_INTC_DMA0C (1<<24) /* DMA 0 */
1123 #define TSI148_LCSR_INTC_LM3C (1<<23) /* Location Monitor 3 */
1124 #define TSI148_LCSR_INTC_LM2C (1<<22) /* Location Monitor 2 */
1125 #define TSI148_LCSR_INTC_LM1C (1<<21) /* Location Monitor 1 */
1126 #define TSI148_LCSR_INTC_LM0C (1<<20) /* Location Monitor 0 */
1127 #define TSI148_LCSR_INTC_MB3C (1<<19) /* Mail Box 3 */
1128 #define TSI148_LCSR_INTC_MB2C (1<<18) /* Mail Box 2 */
1129 #define TSI148_LCSR_INTC_MB1C (1<<17) /* Mail Box 1 */
1130 #define TSI148_LCSR_INTC_MB0C (1<<16) /* Mail Box 0 */
1131 #define TSI148_LCSR_INTC_PERRC (1<<13) /* VMEbus Error */
1132 #define TSI148_LCSR_INTC_VERRC (1<<12) /* VMEbus Access Time-out */
1133 #define TSI148_LCSR_INTC_VIEC (1<<11) /* VMEbus IRQ Edge */
1134 #define TSI148_LCSR_INTC_IACKC (1<<10) /* IACK */
1135 #define TSI148_LCSR_INTC_SYSFLC (1<<9) /* System Fail */
1136 #define TSI148_LCSR_INTC_ACFLC (1<<8) /* AC Fail */
1138 static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C,
1139 TSI148_LCSR_INTC_LM1C,
1140 TSI148_LCSR_INTC_LM2C,
1141 TSI148_LCSR_INTC_LM3C };
1143 static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
1144 TSI148_LCSR_INTC_MB1C,
1145 TSI148_LCSR_INTC_MB2C,
1146 TSI148_LCSR_INTC_MB3C };
1149 * Interrupt Map Register 1 CRG + $458
1151 #define TSI148_LCSR_INTM1_DMA1M_M (3<<18) /* DMA 1 */
1152 #define TSI148_LCSR_INTM1_DMA0M_M (3<<16) /* DMA 0 */
1153 #define TSI148_LCSR_INTM1_LM3M_M (3<<14) /* Location Monitor 3 */
1154 #define TSI148_LCSR_INTM1_LM2M_M (3<<12) /* Location Monitor 2 */
1155 #define TSI148_LCSR_INTM1_LM1M_M (3<<10) /* Location Monitor 1 */
1156 #define TSI148_LCSR_INTM1_LM0M_M (3<<8) /* Location Monitor 0 */
1157 #define TSI148_LCSR_INTM1_MB3M_M (3<<6) /* Mail Box 3 */
1158 #define TSI148_LCSR_INTM1_MB2M_M (3<<4) /* Mail Box 2 */
1159 #define TSI148_LCSR_INTM1_MB1M_M (3<<2) /* Mail Box 1 */
1160 #define TSI148_LCSR_INTM1_MB0M_M (3<<0) /* Mail Box 0 */
1163 * Interrupt Map Register 2 CRG + $45C
1165 #define TSI148_LCSR_INTM2_PERRM_M (3<<26) /* PCI Bus Error */
1166 #define TSI148_LCSR_INTM2_VERRM_M (3<<24) /* VMEbus Error */
1167 #define TSI148_LCSR_INTM2_VIEM_M (3<<22) /* VMEbus IRQ Edge */
1168 #define TSI148_LCSR_INTM2_IACKM_M (3<<20) /* IACK */
1169 #define TSI148_LCSR_INTM2_SYSFLM_M (3<<18) /* System Fail */
1170 #define TSI148_LCSR_INTM2_ACFLM_M (3<<16) /* AC Fail */
1171 #define TSI148_LCSR_INTM2_IRQ7M_M (3<<14) /* IRQ7 */
1172 #define TSI148_LCSR_INTM2_IRQ6M_M (3<<12) /* IRQ6 */
1173 #define TSI148_LCSR_INTM2_IRQ5M_M (3<<10) /* IRQ5 */
1174 #define TSI148_LCSR_INTM2_IRQ4M_M (3<<8) /* IRQ4 */
1175 #define TSI148_LCSR_INTM2_IRQ3M_M (3<<6) /* IRQ3 */
1176 #define TSI148_LCSR_INTM2_IRQ2M_M (3<<4) /* IRQ2 */
1177 #define TSI148_LCSR_INTM2_IRQ1M_M (3<<2) /* IRQ1 */
1180 * DMA Control (0-1) Registers CRG + $500
1182 #define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */
1183 #define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */
1184 #define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */
1186 #define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */
1188 #define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */
1189 #define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */
1190 #define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */
1191 #define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */
1192 #define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */
1193 #define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */
1194 #define TSI148_LCSR_DCTL_VBKS_1024 (5<<12) /* VMEbus block Size 1024 */
1195 #define TSI148_LCSR_DCTL_VBKS_2048 (6<<12) /* VMEbus block Size 2048 */
1196 #define TSI148_LCSR_DCTL_VBKS_4096 (7<<12) /* VMEbus block Size 4096 */
1198 #define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */
1199 #define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */
1200 #define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */
1201 #define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */
1202 #define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */
1203 #define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */
1204 #define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */
1205 #define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */
1206 #define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */
1208 #define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */
1209 #define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */
1210 #define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */
1211 #define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */
1212 #define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */
1213 #define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */
1214 #define TSI148_LCSR_DCTL_PBKS_1024 (5<<4) /* PCI block size 1024 bytes */
1215 #define TSI148_LCSR_DCTL_PBKS_2048 (6<<4) /* PCI block size 2048 bytes */
1216 #define TSI148_LCSR_DCTL_PBKS_4096 (7<<4) /* PCI block size 4096 bytes */
1218 #define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */
1219 #define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */
1220 #define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */
1221 #define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */
1222 #define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */
1223 #define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */
1224 #define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */
1225 #define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */
1226 #define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */
1229 * DMA Status Registers (0-1) CRG + $504
1231 #define TSI148_LCSR_DSTA_SMA (1<<31) /* PCI Signalled Master Abt */
1232 #define TSI148_LCSR_DSTA_RTA (1<<30) /* PCI Received Target Abt */
1233 #define TSI148_LCSR_DSTA_MRC (1<<29) /* PCI Max Retry Count */
1234 #define TSI148_LCSR_DSTA_VBE (1<<28) /* VMEbus error */
1235 #define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */
1236 #define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */
1237 #define TSI148_LCSR_DSTA_DON (1<<25) /* Done */
1238 #define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */
1241 * DMA Current Link Address Lower (0-1)
1243 #define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6) /* Mask */
1246 * DMA Source Attribute (0-1) Reg
1248 #define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */
1249 #define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */
1250 #define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */
1251 #define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */
1253 #define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */
1254 #define TSI148_LCSR_DSAT_NIN (1<<24) /* No Increment */
1256 #define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */
1257 #define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */
1258 #define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */
1259 #define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */
1261 #define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
1262 #define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */
1263 #define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */
1264 #define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */
1265 #define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */
1266 #define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */
1267 #define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
1269 #define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */
1270 #define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */
1271 #define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */
1273 #define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */
1274 #define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */
1276 #define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */
1277 #define TSI148_LCSR_DSAT_AMODE_A16 (0<<0) /* A16 */
1278 #define TSI148_LCSR_DSAT_AMODE_A24 (1<<0) /* A24 */
1279 #define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */
1280 #define TSI148_LCSR_DSAT_AMODE_A64 (4<<0) /* A64 */
1281 #define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */
1282 #define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0) /* User1 */
1283 #define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0) /* User2 */
1284 #define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0) /* User3 */
1285 #define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0) /* User4 */
1288 * DMA Destination Attribute Registers (0-1)
1290 #define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */
1291 #define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */
1293 #define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */
1294 #define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */
1295 #define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */
1296 #define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */
1298 #define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
1299 #define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */
1300 #define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */
1301 #define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */
1302 #define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */
1303 #define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */
1304 #define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
1306 #define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */
1307 #define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */
1308 #define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */
1310 #define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */
1311 #define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */
1313 #define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */
1314 #define TSI148_LCSR_DDAT_AMODE_A16 (0<<0) /* A16 */
1315 #define TSI148_LCSR_DDAT_AMODE_A24 (1<<0) /* A24 */
1316 #define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */
1317 #define TSI148_LCSR_DDAT_AMODE_A64 (4<<0) /* A64 */
1318 #define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */
1319 #define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0) /* User1 */
1320 #define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0) /* User2 */
1321 #define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0) /* User3 */
1322 #define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0) /* User4 */
1325 * DMA Next Link Address Lower
1327 #define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */
1328 #define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
1331 * DMA 2eSST Broadcast Select
1333 #define TSI148_LCSR_DBS_M (0x1FFFFF<<0) /* Mask */
1336 * GCSR Register Group
1340 * GCSR Control and Status Register CRG + $604
1342 #define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */
1343 #define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */
1344 #define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */
1345 #define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */
1346 #define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */
1348 #define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */
1349 #define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */
1350 #define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */
1351 #define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */
1352 #define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */
1353 #define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */
1354 #define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */
1355 #define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */
1357 #define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */
1358 #define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
1361 * CR/CSR Register Group
1365 * CR/CSR Bit Clear Register CRG + $FF4
1367 #define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */
1368 #define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */
1369 #define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */
1370 #define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */
1371 #define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */
1374 * CR/CSR Bit Set Register CRG+$FF8
1376 #define TSI148_CRCSR_CSRBSR_LISTS (1<<7) /* Local Reset Clear */
1377 #define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Clear */
1378 #define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */
1379 #define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Clear */
1380 #define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Clear */
1383 * CR/CSR Base Address Register CRG + FFC
1385 #define TSI148_CRCSR_CBAR_M (0x1F<<3) /* Mask */
1387 #endif /* TSI148_H */
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