drivers/staging/rts5208/spi.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26
  27 #include "rtsx.h"
  28 #include "spi.h"
  29
  30 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
  31 {
  32         struct spi_info *spi = &(chip->spi);
  33
  34         spi->err_code = err_code;
  35 }
  36
  37 static int spi_init(struct rtsx_chip *chip)
  38 {
  39         int retval;
  40
  41         retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
  42                                      CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 | SPI_AUTO);
  43         if (retval) {
  44                 rtsx_trace(chip);
  45                 return retval;
  46         }
  47         retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
  48                                      SAMPLE_DELAY_HALF);
  49         if (retval) {
  50                 rtsx_trace(chip);
  51                 return retval;
  52         }
  53
  54         return STATUS_SUCCESS;
  55 }
  56
  57 static int spi_set_init_para(struct rtsx_chip *chip)
  58 {
  59         struct spi_info *spi = &(chip->spi);
  60         int retval;
  61
  62         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF,
  63                                      (u8)(spi->clk_div >> 8));
  64         if (retval) {
  65                 rtsx_trace(chip);
  66                 return retval;
  67         }
  68         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF,
  69                                      (u8)(spi->clk_div));
  70         if (retval) {
  71                 rtsx_trace(chip);
  72                 return retval;
  73         }
  74
  75         retval = switch_clock(chip, spi->spi_clock);
  76         if (retval != STATUS_SUCCESS) {
  77                 rtsx_trace(chip);
  78                 return STATUS_FAIL;
  79         }
  80
  81         retval = select_card(chip, SPI_CARD);
  82         if (retval != STATUS_SUCCESS) {
  83                 rtsx_trace(chip);
  84                 return STATUS_FAIL;
  85         }
  86
  87         retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
  88                                      SPI_CLK_EN);
  89         if (retval) {
  90                 rtsx_trace(chip);
  91                 return retval;
  92         }
  93         retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
  94                                      SPI_OUTPUT_EN);
  95         if (retval) {
  96                 rtsx_trace(chip);
  97                 return retval;
  98         }
  99
 100         wait_timeout(10);
 101
 102         retval = spi_init(chip);
 103         if (retval != STATUS_SUCCESS) {
 104                 rtsx_trace(chip);
 105                 return STATUS_FAIL;
 106         }
 107
 108         return STATUS_SUCCESS;
 109 }
 110
 111 static int sf_polling_status(struct rtsx_chip *chip, int msec)
 112 {
 113         int retval;
 114
 115         rtsx_init_cmd(chip);
 116
 117         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
 118         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 119                 SPI_TRANSFER0_START | SPI_POLLING_MODE0);
 120         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 121                 SPI_TRANSFER0_END);
 122
 123         retval = rtsx_send_cmd(chip, 0, msec);
 124         if (retval < 0) {
 125                 rtsx_clear_spi_error(chip);
 126                 spi_set_err_code(chip, SPI_BUSY_ERR);
 127                 rtsx_trace(chip);
 128                 return STATUS_FAIL;
 129         }
 130
 131         return STATUS_SUCCESS;
 132 }
 133
 134 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
 135 {
 136         struct spi_info *spi = &(chip->spi);
 137         int retval;
 138
 139         if (!spi->write_en)
 140                 return STATUS_SUCCESS;
 141
 142         rtsx_init_cmd(chip);
 143
 144         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 145         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 146                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 147         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 148                 SPI_TRANSFER0_START | SPI_C_MODE0);
 149         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 150                 SPI_TRANSFER0_END);
 151
 152         retval = rtsx_send_cmd(chip, 0, 100);
 153         if (retval < 0) {
 154                 rtsx_clear_spi_error(chip);
 155                 spi_set_err_code(chip, SPI_HW_ERR);
 156                 rtsx_trace(chip);
 157                 return STATUS_FAIL;
 158         }
 159
 160         return STATUS_SUCCESS;
 161 }
 162
 163 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
 164 {
 165         struct spi_info *spi = &(chip->spi);
 166         int retval;
 167
 168         if (!spi->write_en)
 169                 return STATUS_SUCCESS;
 170
 171         rtsx_init_cmd(chip);
 172
 173         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 174         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 175                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 176         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 177                 SPI_TRANSFER0_START | SPI_C_MODE0);
 178         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 179                 SPI_TRANSFER0_END);
 180
 181         retval = rtsx_send_cmd(chip, 0, 100);
 182         if (retval < 0) {
 183                 rtsx_clear_spi_error(chip);
 184                 spi_set_err_code(chip, SPI_HW_ERR);
 185                 rtsx_trace(chip);
 186                 return STATUS_FAIL;
 187         }
 188
 189         return STATUS_SUCCESS;
 190 }
 191
 192 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
 193                 u16 len)
 194 {
 195         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 196         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 197                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 198         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
 199         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
 200         if (addr_mode) {
 201                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 202                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 203                         (u8)(addr >> 8));
 204                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 205                         (u8)(addr >> 16));
 206                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 207                         SPI_TRANSFER0_START | SPI_CADO_MODE0);
 208         } else {
 209                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 210                         SPI_TRANSFER0_START | SPI_CDO_MODE0);
 211         }
 212         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 213                 SPI_TRANSFER0_END);
 214 }
 215
 216 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
 217 {
 218         int retval;
 219
 220         rtsx_init_cmd(chip);
 221
 222         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 223         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 224                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 225         if (addr_mode) {
 226                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 227                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 228                         (u8)(addr >> 8));
 229                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 230                         (u8)(addr >> 16));
 231                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 232                         SPI_TRANSFER0_START | SPI_CA_MODE0);
 233         } else {
 234                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 235                         SPI_TRANSFER0_START | SPI_C_MODE0);
 236         }
 237         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 238                 SPI_TRANSFER0_END);
 239
 240         retval = rtsx_send_cmd(chip, 0, 100);
 241         if (retval < 0) {
 242                 rtsx_clear_spi_error(chip);
 243                 spi_set_err_code(chip, SPI_HW_ERR);
 244                 rtsx_trace(chip);
 245                 return STATUS_FAIL;
 246         }
 247
 248         return STATUS_SUCCESS;
 249 }
 250
 251 static int spi_init_eeprom(struct rtsx_chip *chip)
 252 {
 253         int retval;
 254         int clk;
 255
 256         if (chip->asic_code)
 257                 clk = 30;
 258         else
 259                 clk = CLK_30;
 260
 261         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
 262         if (retval) {
 263                 rtsx_trace(chip);
 264                 return retval;
 265         }
 266         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
 267         if (retval) {
 268                 rtsx_trace(chip);
 269                 return retval;
 270         }
 271
 272         retval = switch_clock(chip, clk);
 273         if (retval != STATUS_SUCCESS) {
 274                 rtsx_trace(chip);
 275                 return STATUS_FAIL;
 276         }
 277
 278         retval = select_card(chip, SPI_CARD);
 279         if (retval != STATUS_SUCCESS) {
 280                 rtsx_trace(chip);
 281                 return STATUS_FAIL;
 282         }
 283
 284         retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
 285                                      SPI_CLK_EN);
 286         if (retval) {
 287                 rtsx_trace(chip);
 288                 return retval;
 289         }
 290         retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
 291                                      SPI_OUTPUT_EN);
 292         if (retval) {
 293                 rtsx_trace(chip);
 294                 return retval;
 295         }
 296
 297         wait_timeout(10);
 298
 299         retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
 300                                      CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
 301         if (retval) {
 302                 rtsx_trace(chip);
 303                 return retval;
 304         }
 305         retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
 306                                      SAMPLE_DELAY_HALF);
 307         if (retval) {
 308                 rtsx_trace(chip);
 309                 return retval;
 310         }
 311
 312         return STATUS_SUCCESS;
 313 }
 314
 315 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
 316 {
 317         int retval;
 318
 319         rtsx_init_cmd(chip);
 320
 321         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
 322         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
 323         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 324                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 325         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 326                 SPI_TRANSFER0_END);
 327
 328         retval = rtsx_send_cmd(chip, 0, 100);
 329         if (retval < 0) {
 330                 rtsx_trace(chip);
 331                 return STATUS_FAIL;
 332         }
 333
 334         return STATUS_SUCCESS;
 335 }
 336
 337 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
 338 {
 339         int retval;
 340
 341         retval = spi_init_eeprom(chip);
 342         if (retval != STATUS_SUCCESS) {
 343                 rtsx_trace(chip);
 344                 return STATUS_FAIL;
 345         }
 346
 347         retval = spi_eeprom_program_enable(chip);
 348         if (retval != STATUS_SUCCESS) {
 349                 rtsx_trace(chip);
 350                 return STATUS_FAIL;
 351         }
 352
 353         rtsx_init_cmd(chip);
 354
 355         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 356         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 357         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
 358         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
 359         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 360                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 361         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 362                 SPI_TRANSFER0_END);
 363
 364         retval = rtsx_send_cmd(chip, 0, 100);
 365         if (retval < 0) {
 366                 rtsx_trace(chip);
 367                 return STATUS_FAIL;
 368         }
 369
 370         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 371         if (retval) {
 372                 rtsx_trace(chip);
 373                 return retval;
 374         }
 375
 376         return STATUS_SUCCESS;
 377 }
 378
 379 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
 380 {
 381         int retval;
 382
 383         retval = spi_init_eeprom(chip);
 384         if (retval != STATUS_SUCCESS) {
 385                 rtsx_trace(chip);
 386                 return STATUS_FAIL;
 387         }
 388
 389         retval = spi_eeprom_program_enable(chip);
 390         if (retval != STATUS_SUCCESS) {
 391                 rtsx_trace(chip);
 392                 return STATUS_FAIL;
 393         }
 394
 395         rtsx_init_cmd(chip);
 396
 397         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 398         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 399         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
 400         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 401         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
 402         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
 403         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 404                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 405         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 406                 SPI_TRANSFER0_END);
 407
 408         retval = rtsx_send_cmd(chip, 0, 100);
 409         if (retval < 0) {
 410                 rtsx_trace(chip);
 411                 return STATUS_FAIL;
 412         }
 413
 414         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 415         if (retval) {
 416                 rtsx_trace(chip);
 417                 return retval;
 418         }
 419
 420         return STATUS_SUCCESS;
 421 }
 422
 423 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
 424 {
 425         int retval;
 426         u8 data;
 427
 428         retval = spi_init_eeprom(chip);
 429         if (retval != STATUS_SUCCESS) {
 430                 rtsx_trace(chip);
 431                 return STATUS_FAIL;
 432         }
 433
 434         rtsx_init_cmd(chip);
 435
 436         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 437         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 438         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
 439         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 440         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
 441         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
 442         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
 443         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 444                 SPI_TRANSFER0_START | SPI_CADI_MODE0);
 445         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 446                 SPI_TRANSFER0_END);
 447
 448         retval = rtsx_send_cmd(chip, 0, 100);
 449         if (retval < 0) {
 450                 rtsx_trace(chip);
 451                 return STATUS_FAIL;
 452         }
 453
 454         wait_timeout(5);
 455         retval = rtsx_read_register(chip, SPI_DATA, &data);
 456         if (retval) {
 457                 rtsx_trace(chip);
 458                 return retval;
 459         }
 460
 461         if (val)
 462                 *val = data;
 463
 464         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 465         if (retval) {
 466                 rtsx_trace(chip);
 467                 return retval;
 468         }
 469
 470         return STATUS_SUCCESS;
 471 }
 472
 473 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
 474 {
 475         int retval;
 476
 477         retval = spi_init_eeprom(chip);
 478         if (retval != STATUS_SUCCESS) {
 479                 rtsx_trace(chip);
 480                 return STATUS_FAIL;
 481         }
 482
 483         retval = spi_eeprom_program_enable(chip);
 484         if (retval != STATUS_SUCCESS) {
 485                 rtsx_trace(chip);
 486                 return STATUS_FAIL;
 487         }
 488
 489         rtsx_init_cmd(chip);
 490
 491         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 492         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 493         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
 494         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
 495         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
 496         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
 497         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
 498         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 499                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 500         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 501                 SPI_TRANSFER0_END);
 502
 503         retval = rtsx_send_cmd(chip, 0, 100);
 504         if (retval < 0) {
 505                 rtsx_trace(chip);
 506                 return STATUS_FAIL;
 507         }
 508
 509         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 510         if (retval) {
 511                 rtsx_trace(chip);
 512                 return retval;
 513         }
 514
 515         return STATUS_SUCCESS;
 516 }
 517
 518 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 519 {
 520         struct spi_info *spi = &(chip->spi);
 521
 522         dev_dbg(rtsx_dev(chip), "spi_get_status: err_code = 0x%x\n",
 523                 spi->err_code);
 524         rtsx_stor_set_xfer_buf(&(spi->err_code),
 525                         min_t(int, scsi_bufflen(srb), 1), srb);
 526         scsi_set_resid(srb, scsi_bufflen(srb) - 1);
 527
 528         return STATUS_SUCCESS;
 529 }
 530
 531 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 532 {
 533         struct spi_info *spi = &(chip->spi);
 534
 535         spi_set_err_code(chip, SPI_NO_ERR);
 536
 537         if (chip->asic_code)
 538                 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
 539         else
 540                 spi->spi_clock = srb->cmnd[3];
 541
 542         spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
 543         spi->write_en = srb->cmnd[6];
 544
 545         dev_dbg(rtsx_dev(chip), "spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n",
 546                 spi->spi_clock, spi->clk_div, spi->write_en);
 547
 548         return STATUS_SUCCESS;
 549 }
 550
 551 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 552 {
 553         int retval;
 554         u16 len;
 555         u8 *buf;
 556
 557         spi_set_err_code(chip, SPI_NO_ERR);
 558
 559         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 560         if (len > 512) {
 561                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 562                 rtsx_trace(chip);
 563                 return STATUS_FAIL;
 564         }
 565
 566         retval = spi_set_init_para(chip);
 567         if (retval != STATUS_SUCCESS) {
 568                 spi_set_err_code(chip, SPI_HW_ERR);
 569                 rtsx_trace(chip);
 570                 return STATUS_FAIL;
 571         }
 572
 573         rtsx_init_cmd(chip);
 574
 575         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 576                 PINGPONG_BUFFER);
 577
 578         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
 579         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
 580         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
 581         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
 582         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 583                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 584         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
 585         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
 586
 587         if (len == 0) {
 588                 if (srb->cmnd[9]) {
 589                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
 590                                       0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
 591                 } else {
 592                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
 593                                       0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
 594                 }
 595         } else {
 596                 if (srb->cmnd[9]) {
 597                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 598                                 SPI_TRANSFER0_START | SPI_CADI_MODE0);
 599                 } else {
 600                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 601                                 SPI_TRANSFER0_START | SPI_CDI_MODE0);
 602                 }
 603         }
 604
 605         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 606                 SPI_TRANSFER0_END);
 607
 608         retval = rtsx_send_cmd(chip, 0, 100);
 609         if (retval < 0) {
 610                 rtsx_clear_spi_error(chip);
 611                 spi_set_err_code(chip, SPI_HW_ERR);
 612                 rtsx_trace(chip);
 613                 return STATUS_FAIL;
 614         }
 615
 616         if (len) {
 617                 buf = kmalloc(len, GFP_KERNEL);
 618                 if (!buf) {
 619                         rtsx_trace(chip);
 620                         return STATUS_ERROR;
 621                 }
 622
 623                 retval = rtsx_read_ppbuf(chip, buf, len);
 624                 if (retval != STATUS_SUCCESS) {
 625                         spi_set_err_code(chip, SPI_READ_ERR);
 626                         kfree(buf);
 627                         rtsx_trace(chip);
 628                         return STATUS_FAIL;
 629                 }
 630
 631                 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
 632                 scsi_set_resid(srb, 0);
 633
 634                 kfree(buf);
 635         }
 636
 637         return STATUS_SUCCESS;
 638 }
 639
 640 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 641 {
 642         int retval;
 643         unsigned int index = 0, offset = 0;
 644         u8 ins, slow_read;
 645         u32 addr;
 646         u16 len;
 647         u8 *buf;
 648
 649         spi_set_err_code(chip, SPI_NO_ERR);
 650
 651         ins = srb->cmnd[3];
 652         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 653                                         << 8) | srb->cmnd[6];
 654         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 655         slow_read = srb->cmnd[9];
 656
 657         retval = spi_set_init_para(chip);
 658         if (retval != STATUS_SUCCESS) {
 659                 spi_set_err_code(chip, SPI_HW_ERR);
 660                 rtsx_trace(chip);
 661                 return STATUS_FAIL;
 662         }
 663
 664         buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
 665         if (!buf) {
 666                 rtsx_trace(chip);
 667                 return STATUS_ERROR;
 668         }
 669
 670         while (len) {
 671                 u16 pagelen = SF_PAGE_LEN - (u8)addr;
 672
 673                 if (pagelen > len)
 674                         pagelen = len;
 675
 676                 rtsx_init_cmd(chip);
 677
 678                 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
 679
 680                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 681
 682                 if (slow_read) {
 683                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
 684                                 (u8)addr);
 685                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 686                                 (u8)(addr >> 8));
 687                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 688                                 (u8)(addr >> 16));
 689                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 690                                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 691                 } else {
 692                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 693                                 (u8)addr);
 694                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 695                                 (u8)(addr >> 8));
 696                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
 697                                 (u8)(addr >> 16));
 698                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 699                                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
 700                 }
 701
 702                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
 703                         (u8)(pagelen >> 8));
 704                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
 705                         (u8)pagelen);
 706
 707                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 708                         SPI_TRANSFER0_START | SPI_CADI_MODE0);
 709                 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
 710                         SPI_TRANSFER0_END, SPI_TRANSFER0_END);
 711
 712                 rtsx_send_cmd_no_wait(chip);
 713
 714                 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
 715                                         DMA_FROM_DEVICE, 10000);
 716                 if (retval < 0) {
 717                         kfree(buf);
 718                         rtsx_clear_spi_error(chip);
 719                         spi_set_err_code(chip, SPI_HW_ERR);
 720                         rtsx_trace(chip);
 721                         return STATUS_FAIL;
 722                 }
 723
 724                 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
 725                                         TO_XFER_BUF);
 726
 727                 addr += pagelen;
 728                 len -= pagelen;
 729         }
 730
 731         scsi_set_resid(srb, 0);
 732         kfree(buf);
 733
 734         return STATUS_SUCCESS;
 735 }
 736
 737 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 738 {
 739         int retval;
 740         u8 ins, program_mode;
 741         u32 addr;
 742         u16 len;
 743         u8 *buf;
 744         unsigned int index = 0, offset = 0;
 745
 746         spi_set_err_code(chip, SPI_NO_ERR);
 747
 748         ins = srb->cmnd[3];
 749         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 750                                         << 8) | srb->cmnd[6];
 751         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 752         program_mode = srb->cmnd[9];
 753
 754         retval = spi_set_init_para(chip);
 755         if (retval != STATUS_SUCCESS) {
 756                 spi_set_err_code(chip, SPI_HW_ERR);
 757                 rtsx_trace(chip);
 758                 return STATUS_FAIL;
 759         }
 760
 761         if (program_mode == BYTE_PROGRAM) {
 762                 buf = kmalloc(4, GFP_KERNEL);
 763                 if (!buf) {
 764                         rtsx_trace(chip);
 765                         return STATUS_ERROR;
 766                 }
 767
 768                 while (len) {
 769                         retval = sf_enable_write(chip, SPI_WREN);
 770                         if (retval != STATUS_SUCCESS) {
 771                                 kfree(buf);
 772                                 rtsx_trace(chip);
 773                                 return STATUS_FAIL;
 774                         }
 775
 776                         rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
 777                                                 FROM_XFER_BUF);
 778
 779                         rtsx_init_cmd(chip);
 780
 781                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 782                                 0x01, PINGPONG_BUFFER);
 783                         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
 784                                 buf[0]);
 785                         sf_program(chip, ins, 1, addr, 1);
 786
 787                         retval = rtsx_send_cmd(chip, 0, 100);
 788                         if (retval < 0) {
 789                                 kfree(buf);
 790                                 rtsx_clear_spi_error(chip);
 791                                 spi_set_err_code(chip, SPI_HW_ERR);
 792                                 rtsx_trace(chip);
 793                                 return STATUS_FAIL;
 794                         }
 795
 796                         retval = sf_polling_status(chip, 100);
 797                         if (retval != STATUS_SUCCESS) {
 798                                 kfree(buf);
 799                                 rtsx_trace(chip);
 800                                 return STATUS_FAIL;
 801                         }
 802
 803                         addr++;
 804                         len--;
 805                 }
 806
 807                 kfree(buf);
 808
 809         } else if (program_mode == AAI_PROGRAM) {
 810                 int first_byte = 1;
 811
 812                 retval = sf_enable_write(chip, SPI_WREN);
 813                 if (retval != STATUS_SUCCESS) {
 814                         rtsx_trace(chip);
 815                         return STATUS_FAIL;
 816                 }
 817
 818                 buf = kmalloc(4, GFP_KERNEL);
 819                 if (!buf) {
 820                         rtsx_trace(chip);
 821                         return STATUS_ERROR;
 822                 }
 823
 824                 while (len) {
 825                         rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
 826                                                 FROM_XFER_BUF);
 827
 828                         rtsx_init_cmd(chip);
 829
 830                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 831                                 0x01, PINGPONG_BUFFER);
 832                         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
 833                                 buf[0]);
 834                         if (first_byte) {
 835                                 sf_program(chip, ins, 1, addr, 1);
 836                                 first_byte = 0;
 837                         } else {
 838                                 sf_program(chip, ins, 0, 0, 1);
 839                         }
 840
 841                         retval = rtsx_send_cmd(chip, 0, 100);
 842                         if (retval < 0) {
 843                                 kfree(buf);
 844                                 rtsx_clear_spi_error(chip);
 845                                 spi_set_err_code(chip, SPI_HW_ERR);
 846                                 rtsx_trace(chip);
 847                                 return STATUS_FAIL;
 848                         }
 849
 850                         retval = sf_polling_status(chip, 100);
 851                         if (retval != STATUS_SUCCESS) {
 852                                 kfree(buf);
 853                                 rtsx_trace(chip);
 854                                 return STATUS_FAIL;
 855                         }
 856
 857                         len--;
 858                 }
 859
 860                 kfree(buf);
 861
 862                 retval = sf_disable_write(chip, SPI_WRDI);
 863                 if (retval != STATUS_SUCCESS) {
 864                         rtsx_trace(chip);
 865                         return STATUS_FAIL;
 866                 }
 867
 868                 retval = sf_polling_status(chip, 100);
 869                 if (retval != STATUS_SUCCESS) {
 870                         rtsx_trace(chip);
 871                         return STATUS_FAIL;
 872                 }
 873         } else if (program_mode == PAGE_PROGRAM) {
 874                 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
 875                 if (!buf) {
 876                         rtsx_trace(chip);
 877                         return STATUS_NOMEM;
 878                 }
 879
 880                 while (len) {
 881                         u16 pagelen = SF_PAGE_LEN - (u8)addr;
 882
 883                         if (pagelen > len)
 884                                 pagelen = len;
 885
 886                         retval = sf_enable_write(chip, SPI_WREN);
 887                         if (retval != STATUS_SUCCESS) {
 888                                 kfree(buf);
 889                                 rtsx_trace(chip);
 890                                 return STATUS_FAIL;
 891                         }
 892
 893                         rtsx_init_cmd(chip);
 894
 895                         trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
 896                         sf_program(chip, ins, 1, addr, pagelen);
 897
 898                         rtsx_send_cmd_no_wait(chip);
 899
 900                         rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
 901                                                 &offset, FROM_XFER_BUF);
 902
 903                         retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
 904                                                 DMA_TO_DEVICE, 100);
 905                         if (retval < 0) {
 906                                 kfree(buf);
 907                                 rtsx_clear_spi_error(chip);
 908                                 spi_set_err_code(chip, SPI_HW_ERR);
 909                                 rtsx_trace(chip);
 910                                 return STATUS_FAIL;
 911                         }
 912
 913                         retval = sf_polling_status(chip, 100);
 914                         if (retval != STATUS_SUCCESS) {
 915                                 kfree(buf);
 916                                 rtsx_trace(chip);
 917                                 return STATUS_FAIL;
 918                         }
 919
 920                         addr += pagelen;
 921                         len -= pagelen;
 922                 }
 923
 924                 kfree(buf);
 925         } else {
 926                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 927                 rtsx_trace(chip);
 928                 return STATUS_FAIL;
 929         }
 930
 931         return STATUS_SUCCESS;
 932 }
 933
 934 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 935 {
 936         int retval;
 937         u8 ins, erase_mode;
 938         u32 addr;
 939
 940         spi_set_err_code(chip, SPI_NO_ERR);
 941
 942         ins = srb->cmnd[3];
 943         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 944                                         << 8) | srb->cmnd[6];
 945         erase_mode = srb->cmnd[9];
 946
 947         retval = spi_set_init_para(chip);
 948         if (retval != STATUS_SUCCESS) {
 949                 spi_set_err_code(chip, SPI_HW_ERR);
 950                 rtsx_trace(chip);
 951                 return STATUS_FAIL;
 952         }
 953
 954         if (erase_mode == PAGE_ERASE) {
 955                 retval = sf_enable_write(chip, SPI_WREN);
 956                 if (retval != STATUS_SUCCESS) {
 957                         rtsx_trace(chip);
 958                         return STATUS_FAIL;
 959                 }
 960
 961                 retval = sf_erase(chip, ins, 1, addr);
 962                 if (retval != STATUS_SUCCESS) {
 963                         rtsx_trace(chip);
 964                         return STATUS_FAIL;
 965                 }
 966         } else if (erase_mode == CHIP_ERASE) {
 967                 retval = sf_enable_write(chip, SPI_WREN);
 968                 if (retval != STATUS_SUCCESS) {
 969                         rtsx_trace(chip);
 970                         return STATUS_FAIL;
 971                 }
 972
 973                 retval = sf_erase(chip, ins, 0, 0);
 974                 if (retval != STATUS_SUCCESS) {
 975                         rtsx_trace(chip);
 976                         return STATUS_FAIL;
 977                 }
 978         } else {
 979                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 980                 rtsx_trace(chip);
 981                 return STATUS_FAIL;
 982         }
 983
 984         return STATUS_SUCCESS;
 985 }
 986
 987 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 988 {
 989         int retval;
 990         u8 ins, status, ewsr;
 991
 992         ins = srb->cmnd[3];
 993         status = srb->cmnd[4];
 994         ewsr = srb->cmnd[5];
 995
 996         retval = spi_set_init_para(chip);
 997         if (retval != STATUS_SUCCESS) {
 998                 spi_set_err_code(chip, SPI_HW_ERR);
 999                 rtsx_trace(chip);
1000                 return STATUS_FAIL;
1001         }
1002
1003         retval = sf_enable_write(chip, ewsr);
1004         if (retval != STATUS_SUCCESS) {
1005                 rtsx_trace(chip);
1006                 return STATUS_FAIL;
1007         }
1008
1009         rtsx_init_cmd(chip);
1010
1011         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1012                 PINGPONG_BUFFER);
1013
1014         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
1015         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
1016                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
1017         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
1018         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
1019         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
1020         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
1021                 SPI_TRANSFER0_START | SPI_CDO_MODE0);
1022         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
1023                 SPI_TRANSFER0_END);
1024
1025         retval = rtsx_send_cmd(chip, 0, 100);
1026         if (retval != STATUS_SUCCESS) {
1027                 rtsx_clear_spi_error(chip);
1028                 spi_set_err_code(chip, SPI_HW_ERR);
1029                 rtsx_trace(chip);
1030                 return STATUS_FAIL;
1031         }
1032
1033         return STATUS_SUCCESS;
1034 }