drivers/staging/rtl8821ae/rtl8821ae/rf.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "reg.h"
  32 #include "def.h"
  33 #include "phy.h"
  34 #include "rf.h"
  35 #include "dm.h"
  36
  37 static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
  38
  39 void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  40 {
  41         struct rtl_priv *rtlpriv = rtl_priv(hw);
  42
  43         switch (bandwidth) {
  44         case HT_CHANNEL_WIDTH_20:
  45                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
  46                 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
  47                 break;
  48         case HT_CHANNEL_WIDTH_20_40:
  49                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
  50                 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
  51                 break;
  52         case HT_CHANNEL_WIDTH_80:
  53                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
  54                 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
  55                 break;
  56         default:
  57                 RT_TRACE(COMP_ERR, DBG_EMERG,
  58                          ("unknown bandwidth: %#X\n", bandwidth));
  59                 break;
  60         }
  61 }
  62
  63 void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  64                                        u8 *ppowerlevel)
  65 {
  66         struct rtl_priv *rtlpriv = rtl_priv(hw);
  67         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  68         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  69         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  70         u32 tx_agc[2] = {0, 0}, tmpval;
  71         bool turbo_scanoff = false;
  72         u8 idx1, idx2;
  73         u8 *ptr;
  74         u8 direction;
  75         u32 pwrtrac_value;
  76
  77         if (rtlefuse->eeprom_regulatory != 0)
  78                 turbo_scanoff = true;
  79
  80         if (mac->act_scanning == true) {
  81                 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  82                 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  83
  84                 if (turbo_scanoff) {
  85                         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  86                                 tx_agc[idx1] = ppowerlevel[idx1] |
  87                                     (ppowerlevel[idx1] << 8) |
  88                                     (ppowerlevel[idx1] << 16) |
  89                                     (ppowerlevel[idx1] << 24);
  90                         }
  91                 }
  92         } else {
  93                 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  94                         tx_agc[idx1] = ppowerlevel[idx1] |
  95                             (ppowerlevel[idx1] << 8) |
  96                             (ppowerlevel[idx1] << 16) |
  97                             (ppowerlevel[idx1] << 24);
  98                 }
  99
 100                 if (rtlefuse->eeprom_regulatory == 0) {
 101                         tmpval =
 102                             (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
 103                             (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
 104                              8);
 105                         tx_agc[RF90_PATH_A] += tmpval;
 106
 107                         tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
 108                             (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
 109                              24);
 110                         tx_agc[RF90_PATH_B] += tmpval;
 111                 }
 112         }
 113
 114         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
 115                 ptr = (u8 *) (&(tx_agc[idx1]));
 116                 for (idx2 = 0; idx2 < 4; idx2++) {
 117                         if (*ptr > RF6052_MAX_TX_PWR)
 118                                 *ptr = RF6052_MAX_TX_PWR;
 119                         ptr++;
 120                 }
 121         }
 122         rtl8821ae_dm_txpower_track_adjust(hw,1,&direction,&pwrtrac_value);
 123         if (direction ==1){
 124                 tx_agc[0] += pwrtrac_value;
 125                 tx_agc[1] += pwrtrac_value;
 126         } else if (direction == 2){
 127                 tx_agc[0] -= pwrtrac_value;
 128                 tx_agc[1] -= pwrtrac_value;
 129         }
 130         tmpval = tx_agc[RF90_PATH_A] ;
 131         rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
 132
 133         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 134                 ("CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 135                  RTXAGC_A_CCK11_CCK1));
 136
 137         tmpval = tx_agc[RF90_PATH_B] ;
 138         rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
 139
 140         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 141                 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 142                  RTXAGC_B_CCK11_CCK1));
 143 }
 144
 145 static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
 146                                       u8 *ppowerlevel_ofdm, u8 *ppowerlevel_bw20, u8 *ppowerlevel_bw40, u8 channel,
 147                                       u32 *ofdmbase, u32 *mcsbase)
 148 {
 149         struct rtl_priv *rtlpriv = rtl_priv(hw);
 150         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 151         u32 powerBase0, powerBase1;
 152         u8 i, powerlevel[2];
 153
 154         for (i = 0; i < 2; i++) {
 155                 powerBase0 = ppowerlevel_ofdm[i];
 156
 157                 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
 158                     (powerBase0 << 8) | powerBase0;
 159                 *(ofdmbase + i) = powerBase0;
 160                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 161                         (" [OFDM power base index rf(%c) = 0x%x]\n",
 162                          ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
 163         }
 164
 165         for (i = 0; i < 2; i++) {
 166                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
 167                         powerlevel[i] = ppowerlevel_bw20[i];
 168                 }else{
 169                         powerlevel[i] = ppowerlevel_bw40[i];
 170                 }
 171                 powerBase1 = powerlevel[i];
 172                 powerBase1 = (powerBase1 << 24) |
 173                     (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
 174
 175                 *(mcsbase + i) = powerBase1;
 176
 177                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 178                         (" [MCS power base index rf(%c) = 0x%x]\n",
 179                          ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
 180         }
 181 }
 182
 183 static void _rtl8821ae_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
 184                                                        u8 channel, u8 index,
 185                                                        u32 *powerBase0,
 186                                                        u32 *powerBase1,
 187                                                        u32 *p_outwriteval)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 191         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 192         u8 i, chnlgroup = 0, pwr_diff_limit[4],pwr_diff = 0,customer_pwr_diff;
 193         u32 writeVal, customer_limit, rf;
 194
 195         for (rf = 0; rf < 2; rf++) {
 196                 switch (rtlefuse->eeprom_regulatory) {
 197                 case 0:
 198                         chnlgroup = 0;
 199
 200                         writeVal =
 201                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
 202                                                                          (rf ? 8 : 0)]
 203                             + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 204
 205                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 206                                 ("RTK better performance, "
 207                                  "writeVal(%c) = 0x%x\n",
 208                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 209                         break;
 210                 case 1:
 211                         if (rtlphy->pwrgroup_cnt == 1)
 212                                 chnlgroup = 0;
 213                         else {
 214                                 if(channel<3)
 215                                         chnlgroup = 0;
 216                                 else if (channel <6)
 217                                         chnlgroup = 1;
 218                                 else if (channel <9)
 219                                         chnlgroup = 2;
 220                                 else if (channel <12)
 221                                         chnlgroup = 3;
 222                                 else if (channel < 14)
 223                                         chnlgroup = 4;
 224                                 else if (channel == 14)
 225                                         chnlgroup = 5;
 226                         }
 227
 228                         writeVal =
 229                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 230                             [index + (rf ? 8 : 0)] + ((index < 2) ?
 231                                                       powerBase0[rf] :
 232                                                       powerBase1[rf]);
 233
 234                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 235                                 ("Realtek regulatory, 20MHz, "
 236                                  "writeVal(%c) = 0x%x\n",
 237                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 238
 239                         break;
 240                 case 2:
 241                         writeVal =
 242                             ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 243
 244                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 245                                 ("Better regulatory, "
 246                                  "writeVal(%c) = 0x%x\n",
 247                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 248                         break;
 249                 case 3:
 250                         chnlgroup = 0;
 251
 252                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 253                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 254                                         ("customer's limit, 40MHz "
 255                                          "rf(%c) = 0x%x\n",
 256                                          ((rf == 0) ? 'A' : 'B'),
 257                                          rtlefuse->pwrgroup_ht40[rf][channel -
 258                                                                      1]));
 259                         } else {
 260                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 261                                         ("customer's limit, 20MHz "
 262                                          "rf(%c) = 0x%x\n",
 263                                          ((rf == 0) ? 'A' : 'B'),
 264                                          rtlefuse->pwrgroup_ht20[rf][channel -
 265                                                                      1]));
 266                         }
 267
 268                         if (index < 2)
 269                                 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
 270                         else if (rtlphy->current_chan_bw ==  HT_CHANNEL_WIDTH_20)
 271                                 pwr_diff = rtlefuse->txpwr_ht20diff[rf][channel-1];
 272
 273                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
 274                                 customer_pwr_diff = rtlefuse->pwrgroup_ht40[rf][channel-1];
 275                         else
 276                                 customer_pwr_diff = rtlefuse->pwrgroup_ht20[rf][channel-1];
 277
 278                         if (pwr_diff > customer_pwr_diff)
 279                                 pwr_diff = 0;
 280                         else
 281                                 pwr_diff = customer_pwr_diff - pwr_diff;
 282
 283                         for (i = 0; i < 4; i++) {
 284                                 pwr_diff_limit[i] =
 285                                     (u8) ((rtlphy->mcs_txpwrlevel_origoffset
 286                                            [chnlgroup][index + (rf ? 8 : 0)] & (0x7f <<
 287                                                                         (i * 8))) >> (i * 8));
 288
 289                                         if(pwr_diff_limit[i] > pwr_diff)
 290                                                 pwr_diff_limit[i] = pwr_diff;
 291                         }
 292
 293                         customer_limit = (pwr_diff_limit[3] << 24) |
 294                             (pwr_diff_limit[2] << 16) |
 295                             (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
 296
 297                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 298                                 ("Customer's limit rf(%c) = 0x%x\n",
 299                                  ((rf == 0) ? 'A' : 'B'), customer_limit));
 300
 301                         writeVal = customer_limit +
 302                             ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 303
 304                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 305                                 ("Customer, writeVal rf(%c)= 0x%x\n",
 306                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 307                         break;
 308                 default:
 309                         chnlgroup = 0;
 310                         writeVal =
 311                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 312                             [index + (rf ? 8 : 0)]
 313                             + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 314
 315                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 316                                 ("RTK better performance, writeVal "
 317                                  "rf(%c) = 0x%x\n",
 318                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 319                         break;
 320                 }
 321
 322                 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
 323                         writeVal = writeVal - 0x06060606;
 324                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 325                          TXHIGHPWRLEVEL_BT2)
 326                         writeVal = writeVal - 0x0c0c0c0c;
 327                 *(p_outwriteval + rf) = writeVal;
 328         }
 329 }
 330
 331 static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
 332                                          u8 index, u32 *pValue)
 333 {
 334         struct rtl_priv *rtlpriv = rtl_priv(hw);
 335         u16 regoffset_a[6] = {
 336                 RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
 337                 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
 338                 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
 339         };
 340         u16 regoffset_b[6] = {
 341                 RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
 342                 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
 343                 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
 344         };
 345         u8 i, rf, pwr_val[4];
 346         u32 writeVal;
 347         u16 regoffset;
 348
 349         for (rf = 0; rf < 2; rf++) {
 350                 writeVal = pValue[rf];
 351                 for (i = 0; i < 4; i++) {
 352                         pwr_val[i] = (u8) ((writeVal & (0x7f <<
 353                                                         (i * 8))) >> (i * 8));
 354
 355                         if (pwr_val[i] > RF6052_MAX_TX_PWR)
 356                                 pwr_val[i] = RF6052_MAX_TX_PWR;
 357                 }
 358                 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
 359                     (pwr_val[1] << 8) | pwr_val[0];
 360
 361                 if (rf == 0)
 362                         regoffset = regoffset_a[index];
 363                 else
 364                         regoffset = regoffset_b[index];
 365                 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
 366
 367                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 368                         ("Set 0x%x = %08x\n", regoffset, writeVal));
 369         }
 370 }
 371
 372 void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
 373                                               u8 *ppowerlevel_ofdm, u8 *ppowerlevel_bw20, u8 *ppowerlevel_bw40, u8 channel)
 374 {
 375         u32 writeVal[2], powerBase0[2], powerBase1[2];
 376         u8 index;
 377         u8 direction;
 378         u32 pwrtrac_value;
 379
 380         rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm, ppowerlevel_bw20, ppowerlevel_bw40,
 381                                   channel, &powerBase0[0], &powerBase1[0]);
 382
 383         rtl8821ae_dm_txpower_track_adjust(hw,1,&direction,&pwrtrac_value);
 384
 385         for (index = 0; index < 6; index++) {
 386                 _rtl8821ae_get_txpower_writeval_by_regulatory(hw,
 387                                                            channel, index,
 388                                                            &powerBase0[0],
 389                                                            &powerBase1[0],
 390                                                            &writeVal[0]);
 391                 if (direction ==1){
 392                         writeVal[0] += pwrtrac_value;
 393                         writeVal[1] += pwrtrac_value;
 394                 } else if (direction == 2){
 395                         writeVal[0] -= pwrtrac_value;
 396                         writeVal[1] -= pwrtrac_value;
 397                 }
 398                 _rtl8821ae_write_ofdm_power_reg(hw, index, &writeVal[0]);
 399         }
 400 }
 401
 402 bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
 403 {
 404         struct rtl_priv *rtlpriv = rtl_priv(hw);
 405         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 406
 407         if (rtlphy->rf_type == RF_1T1R)
 408                 rtlphy->num_total_rfpath = 1;
 409         else
 410                 rtlphy->num_total_rfpath = 2;
 411
 412         return _rtl8821ae_phy_rf6052_config_parafile(hw);
 413
 414 }
 415
 416 static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
 417 {
 418         struct rtl_priv *rtlpriv = rtl_priv(hw);
 419         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 420         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 421         //u32 u4_regvalue = 0;
 422         u8 rfpath;
 423         bool rtstatus = true;
 424         //struct bb_reg_def *pphyreg;
 425
 426         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
 427                 switch (rfpath) {
 428                 case RF90_PATH_A: {
 429                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 430                                 rtstatus = rtl8812ae_phy_config_rf_with_headerfile(hw,
 431                                                                         (enum radio_path)rfpath);
 432                         else
 433                                 rtstatus = rtl8821ae_phy_config_rf_with_headerfile(hw,
 434                                                                         (enum radio_path)rfpath);
 435                         break;
 436                         }
 437                 case RF90_PATH_B: {
 438                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 439                                 rtstatus = rtl8812ae_phy_config_rf_with_headerfile(hw,
 440                                                                         (enum radio_path)rfpath);
 441                         else
 442                                 rtstatus = rtl8821ae_phy_config_rf_with_headerfile(hw,
 443                                                                         (enum radio_path)rfpath);
 444                         break;
 445                         }
 446                 case RF90_PATH_C:
 447                         break;
 448                 case RF90_PATH_D:
 449                         break;
 450                 }
 451
 452                 if (rtstatus != true) {
 453                         RT_TRACE(COMP_INIT, DBG_TRACE,
 454                                  ("Radio[%d] Fail!!", rfpath));
 455                         return false;
 456                 }
 457
 458         }
 459
 460         /*put arrays in dm.c*/
 461         /*_rtl8821ae_config_rf_txpwr_track_headerfile(hw);*/
 462         RT_TRACE(COMP_INIT, DBG_TRACE, ("\n"));
 463         return rtstatus;
 464 }