drivers/staging/rtl8821ae/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44 #include "pwrseqcmd.h"
  45 #include "pwrseq.h"
  46 #include "btc.h"
  47 #include "../btcoexist/rtl_btc.h"
  48
  49 #define LLT_CONFIG      5
  50
  51 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  52 {
  53         struct rtl_priv *rtlpriv = rtl_priv(hw);
  54         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  55         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  56
  57         while (skb_queue_len(&ring->queue)) {
  58                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  59                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  60
  61                 pci_unmap_single(rtlpci->pdev,
  62                                  le32_to_cpu(rtlpriv->cfg->ops->get_desc(
  63                                  (u8 *) entry, true, HW_DESC_TXBUFF_ADDR)),
  64                                  skb->len, PCI_DMA_TODEVICE);
  65                 kfree_skb(skb);
  66                 ring->idx = (ring->idx + 1) % ring->entries;
  67         }
  68
  69 }
  70
  71 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  72                                       u8 set_bits, u8 clear_bits)
  73 {
  74         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76
  77         rtlpci->reg_bcn_ctrl_val |= set_bits;
  78         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  79
  80         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  81 }
  82
  83 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  84 {
  85         struct rtl_priv *rtlpriv = rtl_priv(hw);
  86         u8 tmp1byte;
  87
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  89         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  91         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  92         tmp1byte &= ~(BIT(0));
  93         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  94 }
  95
  96 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  97 {
  98         struct rtl_priv *rtlpriv = rtl_priv(hw);
  99         u8 tmp1byte;
 100
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 102         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 104         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 105         tmp1byte |= BIT(0);
 106         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 107 }
 108
 109 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 110 {
 111         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 112 }
 113
 114 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 115 {
 116         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 117 }
 118
 119 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 120         u8 rpwm_val, bool b_need_turn_off_ckk)
 121 {
 122         struct rtl_priv *rtlpriv = rtl_priv(hw);
 123         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 124         bool b_support_remote_wake_up;
 125         u32 count = 0,isr_regaddr,content;
 126         bool b_schedule_timer = b_need_turn_off_ckk;
 127         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 128                                         (u8 *) (&b_support_remote_wake_up));
 129
 130         if (!rtlhal->bfw_ready)
 131                 return;
 132         if (!rtlpriv->psc.b_fw_current_inpsmode)
 133                 return;
 134
 135         while (1) {
 136                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 137                 if (rtlhal->bfw_clk_change_in_progress) {
 138                         while (rtlhal->bfw_clk_change_in_progress) {
 139                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 140                                 count++;
 141                                 udelay(100);
 142                                 if (count > 1000)
 143                                         return;
 144                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         }
 146                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 147                 } else {
 148                         rtlhal->bfw_clk_change_in_progress = false;
 149                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 150                 }
 151         }
 152
 153         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 154                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 155                                         (u8 *) (&rpwm_val));
 156                 if (FW_PS_IS_ACK(rpwm_val)) {
 157                         isr_regaddr = REG_HISR;
 158                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 159                         while (!(content & IMR_CPWM) && (count < 500)) {
 160                                 udelay(50);
 161                                 count++;
 162                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 163                         }
 164
 165                         if (content & IMR_CPWM) {
 166                         rtl_write_word(rtlpriv,isr_regaddr, 0x0100);
 167                         rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 168                         RT_TRACE(COMP_POWER, DBG_LOUD, ("Receive CPWM INT!!! Set pHalData->FwPSState = %X\n", rtlhal->fw_ps_state));
 169                         }
 170                 }
 171
 172                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 173                 rtlhal->bfw_clk_change_in_progress = false;
 174                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 175                 if (b_schedule_timer) {
 176                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 177                                   jiffies + MSECS(10));
 178                 }
 179
 180         } else  {
 181                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 182                 rtlhal->bfw_clk_change_in_progress = false;
 183                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 184         }
 185
 186
 187 }
 188
 189 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 190         u8 rpwm_val)
 191 {
 192         struct rtl_priv *rtlpriv = rtl_priv(hw);
 193         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 194         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 195         struct rtl8192_tx_ring *ring;
 196         enum rf_pwrstate rtstate;
 197         bool b_schedule_timer = false;
 198         u8 queue;
 199
 200         if (!rtlhal->bfw_ready)
 201                 return;
 202         if (!rtlpriv->psc.b_fw_current_inpsmode)
 203                 return;
 204         if (!rtlhal->ballow_sw_to_change_hwclc)
 205                 return;
 206         rtlpriv->cfg->ops->get_hw_reg(hw,HW_VAR_RF_STATE,(u8 *)(&rtstate));
 207         if (rtstate == ERFOFF ||rtlpriv->psc.inactive_pwrstate ==ERFOFF)
 208                 return;
 209
 210         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 211                 ring = &rtlpci->tx_ring[queue];
 212                 if (skb_queue_len(&ring->queue)) {
 213                         b_schedule_timer = true;
 214                         break;
 215                 }
 216         }
 217
 218         if (b_schedule_timer) {
 219                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 220                                           jiffies + MSECS(10));
 221                 return;
 222         }
 223
 224         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 225                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 226                 if (!rtlhal->bfw_clk_change_in_progress) {
 227                         rtlhal->bfw_clk_change_in_progress = true;
 228                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 229                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 230                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 231                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 232                                 (u8 *) (&rpwm_val));
 233                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 234                         rtlhal->bfw_clk_change_in_progress = false;
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                 } else {
 237                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 238                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 239                                           jiffies + MSECS(10));
 240                 }
 241         }
 242
 243 }
 244
 245 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 246 {
 247         u8 rpwm_val = 0;
 248         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 249         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 250 }
 251
 252 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 253 {
 254         struct rtl_priv *rtlpriv = rtl_priv(hw);
 255         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 256         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 257         bool b_fw_current_inps = false;
 258         u8 rpwm_val = 0,fw_pwrmode = FW_PS_ACTIVE_MODE;
 259
 260         if (ppsc->b_low_power_enable){
 261                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 262                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 263                 rtlhal->ballow_sw_to_change_hwclc = false;
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 265                                 (u8 *) (&fw_pwrmode));
 266                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 267                                 (u8 *) (&b_fw_current_inps));
 268         } else {
 269                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 271                                 (u8 *) (&rpwm_val));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 273                                 (u8 *) (&fw_pwrmode));
 274                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 275                                 (u8 *) (&b_fw_current_inps));
 276         }
 277
 278 }
 279
 280 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 281 {
 282         struct rtl_priv *rtlpriv = rtl_priv(hw);
 283         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 284         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 285         bool b_fw_current_inps = true;
 286         u8 rpwm_val;
 287
 288         if (ppsc->b_low_power_enable){
 289                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 290                 rtlpriv->cfg->ops->set_hw_reg(hw,
 291                                 HW_VAR_FW_PSMODE_STATUS,
 292                                 (u8 *) (&b_fw_current_inps));
 293                 rtlpriv->cfg->ops->set_hw_reg(hw,
 294                                 HW_VAR_H2C_FW_PWRMODE,
 295                                 (u8 *) (&ppsc->fwctrl_psmode));
 296                 rtlhal->ballow_sw_to_change_hwclc = true;
 297                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 298
 299
 300         } else {
 301                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 302                 rtlpriv->cfg->ops->set_hw_reg(hw,
 303                                 HW_VAR_FW_PSMODE_STATUS,
 304                                 (u8 *) (&b_fw_current_inps));
 305                 rtlpriv->cfg->ops->set_hw_reg(hw,
 306                                 HW_VAR_H2C_FW_PWRMODE,
 307                                 (u8 *) (&ppsc->fwctrl_psmode));
 308                 rtlpriv->cfg->ops->set_hw_reg(hw,
 309                                 HW_VAR_SET_RPWM,
 310                                 (u8 *) (&rpwm_val));
 311         }
 312
 313 }
 314
 315 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 316 {
 317         struct rtl_priv *rtlpriv = rtl_priv(hw);
 318         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 319         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 320         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 321
 322         switch (variable) {
 323         case HW_VAR_ETHER_ADDR:
 324                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 325                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 326                 break;
 327         case HW_VAR_BSSID:
 328                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 329                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 330                 break;
 331         case HW_VAR_MEDIA_STATUS:
 332                 val[0] = rtl_read_byte(rtlpriv, REG_CR+2) & 0x3;
 333                 break;
 334         case HW_VAR_SLOT_TIME:
 335                 *((u8 *)(val)) = mac->slot_time;
 336                 break;
 337         case HW_VAR_BEACON_INTERVAL:
 338                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 339                 break;
 340         case HW_VAR_ATIM_WINDOW:
 341                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 342                 break;
 343         case HW_VAR_RCR:
 344                 *((u32 *) (val)) = rtlpci->receive_config;
 345                 break;
 346         case HW_VAR_RF_STATE:
 347                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 348                 break;
 349         case HW_VAR_FWLPS_RF_ON:{
 350                         enum rf_pwrstate rfState;
 351                         u32 val_rcr;
 352
 353                         rtlpriv->cfg->ops->get_hw_reg(hw,
 354                                                       HW_VAR_RF_STATE,
 355                                                       (u8 *) (&rfState));
 356                         if (rfState == ERFOFF) {
 357                                 *((bool *) (val)) = true;
 358                         } else {
 359                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 360                                 val_rcr &= 0x00070000;
 361                                 if (val_rcr)
 362                                         *((bool *) (val)) = false;
 363                                 else
 364                                         *((bool *) (val)) = true;
 365                         }
 366                         break;
 367                 }
 368         case HW_VAR_FW_PSMODE_STATUS:
 369                 *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
 370                 break;
 371         case HW_VAR_CORRECT_TSF:{
 372                         u64 tsf;
 373                         u32 *ptsf_low = (u32 *) & tsf;
 374                         u32 *ptsf_high = ((u32 *) & tsf) + 1;
 375
 376                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 377                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 378
 379                         *((u64 *) (val)) = tsf;
 380
 381                         break;
 382                 }
 383         default:
 384                 RT_TRACE(COMP_ERR, DBG_EMERG,
 385                          ("switch case not process %x\n",variable));
 386                 break;
 387         }
 388 }
 389
 390
 391 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 392 {
 393         struct rtl_priv *rtlpriv = rtl_priv(hw);
 394         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 395         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 396         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 397         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 398         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 399         u8 idx;
 400
 401         switch (variable) {
 402         case HW_VAR_ETHER_ADDR:{
 403                         for (idx = 0; idx < ETH_ALEN; idx++) {
 404                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 405                                                val[idx]);
 406                         }
 407                         break;
 408                 }
 409         case HW_VAR_BASIC_RATE:{
 410                         u16 b_rate_cfg = ((u16 *) val)[0];
 411                         u8 rate_index = 0;
 412                         b_rate_cfg = b_rate_cfg & 0x15f;
 413                         b_rate_cfg |= 0x01;
 414                         rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 415                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 416                                        (b_rate_cfg >> 8) & 0xff);
 417                         while (b_rate_cfg > 0x1) {
 418                                 b_rate_cfg = (b_rate_cfg >> 1);
 419                                 rate_index++;
 420                         }
 421                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 422                                        rate_index);
 423                         break;
 424                 }
 425         case HW_VAR_BSSID:{
 426                         for (idx = 0; idx < ETH_ALEN; idx++) {
 427                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 428                                                val[idx]);
 429                         }
 430                         break;
 431                 }
 432         case HW_VAR_SIFS:{
 433                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 434                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 435
 436                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 437                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 438
 439                         if (!mac->ht_enable)
 440                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 441                                                0x0e0e);
 442                         else
 443                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 444                                                *((u16 *) val));
 445                         break;
 446                 }
 447         case HW_VAR_SLOT_TIME:{
 448                         u8 e_aci;
 449
 450                         RT_TRACE(COMP_MLME, DBG_LOUD,
 451                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 452
 453                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 454
 455                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 456                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 457                                                               HW_VAR_AC_PARAM,
 458                                                               (u8 *) (&e_aci));
 459                         }
 460                         break;
 461                 }
 462         case HW_VAR_ACK_PREAMBLE:{
 463                         u8 reg_tmp;
 464                         u8 short_preamble = (bool) (*(u8 *) val);
 465                         reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 466                         if (short_preamble){
 467                                 reg_tmp |= BIT(1);
 468                                 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 469                         } else {
 470                                 reg_tmp &= (~BIT(1));
 471                                 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 472                         }
 473                         break;
 474                 }
 475         case HW_VAR_WPA_CONFIG:
 476                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 477                 break;
 478         case HW_VAR_AMPDU_MIN_SPACE:{
 479                         u8 min_spacing_to_set;
 480                         u8 sec_min_space;
 481
 482                         min_spacing_to_set = *((u8 *) val);
 483                         if (min_spacing_to_set <= 7) {
 484                                 sec_min_space = 0;
 485
 486                                 if (min_spacing_to_set < sec_min_space)
 487                                         min_spacing_to_set = sec_min_space;
 488
 489                                 mac->min_space_cfg = ((mac->min_space_cfg &
 490                                                        0xf8) |
 491                                                       min_spacing_to_set);
 492
 493                                 *val = min_spacing_to_set;
 494
 495                                 RT_TRACE(COMP_MLME, DBG_LOUD,
 496                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 497                                           mac->min_space_cfg));
 498
 499                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 500                                                mac->min_space_cfg);
 501                         }
 502                         break;
 503                 }
 504         case HW_VAR_SHORTGI_DENSITY:{
 505                         u8 density_to_set;
 506
 507                         density_to_set = *((u8 *) val);
 508                         mac->min_space_cfg |= (density_to_set << 3);
 509
 510                         RT_TRACE(COMP_MLME, DBG_LOUD,
 511                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 512                                   mac->min_space_cfg));
 513
 514                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 515                                        mac->min_space_cfg);
 516
 517                         break;
 518                 }
 519         case HW_VAR_AMPDU_FACTOR:{
 520                         u32     ampdu_len =  (*((u8 *)val));
 521                         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 522                                 if(ampdu_len < VHT_AGG_SIZE_128K)
 523                                         ampdu_len = (0x2000 << (*((u8 *)val))) -1;
 524                                 else
 525                                         ampdu_len = 0x1ffff;
 526                         } else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 527                                 if(ampdu_len < HT_AGG_SIZE_64K)
 528                                         ampdu_len = (0x2000 << (*((u8 *)val))) -1;
 529                                 else
 530                                         ampdu_len = 0xffff;
 531                         }
 532                         ampdu_len |= BIT(31);
 533
 534                         rtl_write_dword(rtlpriv,
 535                                 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 536                         break;
 537                 }
 538         case HW_VAR_AC_PARAM:{
 539                         u8 e_aci = *((u8 *) val);
 540                         rtl8821ae_dm_init_edca_turbo(hw);
 541
 542                         if (rtlpci->acm_method != eAcmWay2_SW)
 543                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 544                                                               HW_VAR_ACM_CTRL,
 545                                                               (u8 *) (&e_aci));
 546                         break;
 547                 }
 548         case HW_VAR_ACM_CTRL:{
 549                         u8 e_aci = *((u8 *) val);
 550                         union aci_aifsn *p_aci_aifsn =
 551                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 552                         u8 acm = p_aci_aifsn->f.acm;
 553                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 554
 555                         acm_ctrl =
 556                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 557
 558                         if (acm) {
 559                                 switch (e_aci) {
 560                                 case AC0_BE:
 561                                         acm_ctrl |= AcmHw_BeqEn;
 562                                         break;
 563                                 case AC2_VI:
 564                                         acm_ctrl |= AcmHw_ViqEn;
 565                                         break;
 566                                 case AC3_VO:
 567                                         acm_ctrl |= AcmHw_VoqEn;
 568                                         break;
 569                                 default:
 570                                         RT_TRACE(COMP_ERR, DBG_WARNING,
 571                                                  ("HW_VAR_ACM_CTRL acm set "
 572                                                   "failed: eACI is %d\n", acm));
 573                                         break;
 574                                 }
 575                         } else {
 576                                 switch (e_aci) {
 577                                 case AC0_BE:
 578                                         acm_ctrl &= (~AcmHw_BeqEn);
 579                                         break;
 580                                 case AC2_VI:
 581                                         acm_ctrl &= (~AcmHw_ViqEn);
 582                                         break;
 583                                 case AC3_VO:
 584                                         acm_ctrl &= (~AcmHw_BeqEn);
 585                                         break;
 586                                 default:
 587                                         RT_TRACE(COMP_ERR, DBG_EMERG,
 588                                                  ("switch case not process \n"));
 589                                         break;
 590                                 }
 591                         }
 592
 593                         RT_TRACE(COMP_QOS, DBG_TRACE,
 594                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 595                                   "Write 0x%X\n", acm_ctrl));
 596                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 597                         break;
 598                 }
 599         case HW_VAR_RCR:{
 600                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 601                         rtlpci->receive_config = ((u32 *) (val))[0];
 602                         break;
 603                 }
 604         case HW_VAR_RETRY_LIMIT:{
 605                         u8 retry_limit = ((u8 *) (val))[0];
 606
 607                         rtl_write_word(rtlpriv, REG_RL,
 608                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 609                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 610                         break;
 611                 }
 612         case HW_VAR_DUAL_TSF_RST:
 613                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 614                 break;
 615         case HW_VAR_EFUSE_BYTES:
 616                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 617                 break;
 618         case HW_VAR_EFUSE_USAGE:
 619                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 620                 break;
 621         case HW_VAR_IO_CMD:
 622                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 623                 break;
 624         case HW_VAR_SET_RPWM:{
 625                         u8 rpwm_val;
 626
 627                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 628                         udelay(1);
 629
 630                         if (rpwm_val & BIT(7)) {
 631                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 632                                                (*(u8 *) val));
 633                         } else {
 634                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 635                                                ((*(u8 *) val) | BIT(7)));
 636                         }
 637
 638                         break;
 639                 }
 640         case HW_VAR_H2C_FW_PWRMODE:{
 641                         rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 642                         break;
 643                 }
 644         case HW_VAR_FW_PSMODE_STATUS:
 645                 ppsc->b_fw_current_inpsmode = *((bool *) val);
 646                 break;
 647
 648         case HW_VAR_RESUME_CLK_ON:
 649                 _rtl8821ae_set_fw_ps_rf_on(hw);
 650                 break;
 651
 652         case HW_VAR_FW_LPS_ACTION:{
 653                 bool b_enter_fwlps = *((bool *) val);
 654
 655                 if (b_enter_fwlps)
 656                         _rtl8821ae_fwlps_enter(hw);
 657                  else
 658                         _rtl8821ae_fwlps_leave(hw);
 659
 660                  break;
 661                 }
 662
 663         case HW_VAR_H2C_FW_JOINBSSRPT:{
 664                         u8 mstatus = (*(u8 *) val);
 665                         u8 tmp_regcr, tmp_reg422,bcnvalid_reg;
 666                         u8 count = 0, dlbcn_count = 0;
 667                         bool b_recover = false;
 668
 669                         if (mstatus == RT_MEDIA_CONNECT) {
 670                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 671                                                               NULL);
 672
 673                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 674                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 675                                                (tmp_regcr | BIT(0)));
 676
 677                                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 678                                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 679
 680                                 tmp_reg422 =
 681                                     rtl_read_byte(rtlpriv,
 682                                                   REG_FWHW_TXQ_CTRL + 2);
 683                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 684                                                tmp_reg422 & (~BIT(6)));
 685                                 if (tmp_reg422 & BIT(6))
 686                                         b_recover = true;
 687
 688                                 do {
 689                                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 690                                         rtl_write_byte(rtlpriv, REG_TDECTRL+2,(bcnvalid_reg | BIT(0)));
 691                                         _rtl8821ae_return_beacon_queue_skb(hw);
 692
 693                                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 694                                                 rtl8812ae_set_fw_rsvdpagepkt(hw, 0);
 695                                         else
 696                                                 rtl8821ae_set_fw_rsvdpagepkt(hw, 0);
 697                                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 698                                         count = 0;
 699                                         while (!(bcnvalid_reg & BIT(0)) && count <20){
 700                                                 count++;
 701                                                 udelay(10);
 702                                                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 703                                         }
 704                                         dlbcn_count++;
 705                                 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count <5);
 706
 707                                 if (bcnvalid_reg & BIT(0))
 708                                         rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 709
 710                                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 711                                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 712
 713                                 if (b_recover) {
 714                                         rtl_write_byte(rtlpriv,
 715                                                        REG_FWHW_TXQ_CTRL + 2,
 716                                                        tmp_reg422);
 717                                 }
 718
 719                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 720                                                (tmp_regcr & ~(BIT(0))));
 721                         }
 722                         rtl8821ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 723
 724                         break;
 725                 }
 726         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
 727                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *) val));
 728                 break;
 729         }
 730
 731         case HW_VAR_AID:{
 732                         u16 u2btmp;
 733                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 734                         u2btmp &= 0xC000;
 735                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 736                                                 mac->assoc_id));
 737
 738                         break;
 739                 }
 740         case HW_VAR_CORRECT_TSF:{
 741                         u8 btype_ibss = ((u8 *) (val))[0];
 742
 743                         if (btype_ibss == true)
 744                                 _rtl8821ae_stop_tx_beacon(hw);
 745
 746                         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 747
 748                         rtl_write_dword(rtlpriv, REG_TSFTR,
 749                                         (u32) (mac->tsf & 0xffffffff));
 750                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 751                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 752
 753                         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 754
 755                         if (btype_ibss == true)
 756                                 _rtl8821ae_resume_tx_beacon(hw);
 757
 758                         break;
 759
 760                 }
 761         case HW_VAR_NAV_UPPER: {
 762                         u32     us_nav_upper = ((u32)*val);
 763
 764                         if(us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF)
 765                         {
 766                                 RT_TRACE(COMP_INIT , DBG_WARNING,
 767                                         ("The setting value (0x%08X us) of NAV_UPPER"
 768                                          " is larger than (%d * 0xFF)!!!\n",
 769                                          us_nav_upper, HAL_92C_NAV_UPPER_UNIT));
 770                                 break;
 771                         }
 772                         rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 773                                 ((u8)((us_nav_upper + HAL_92C_NAV_UPPER_UNIT - 1) / HAL_92C_NAV_UPPER_UNIT)));
 774                         break;
 775                 }
 776         case HW_VAR_KEEP_ALIVE: {
 777                         u8 array[2];
 778                         array[0] = 0xff;
 779                         array[1] = *((u8 *)val);
 780                         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, array);
 781                 }
 782         default:
 783                 RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case "
 784                                                         "not process %x\n",variable));
 785                 break;
 786         }
 787 }
 788
 789 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 790 {
 791         struct rtl_priv *rtlpriv = rtl_priv(hw);
 792         bool status = true;
 793         long count = 0;
 794         u32 value = _LLT_INIT_ADDR(address) |
 795             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 796
 797         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 798
 799         do {
 800                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 801                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 802                         break;
 803
 804                 if (count > POLLING_LLT_THRESHOLD) {
 805                         RT_TRACE(COMP_ERR, DBG_EMERG,
 806                                  ("Failed to polling write LLT done at "
 807                                   "address %d!\n", address));
 808                         status = false;
 809                         break;
 810                 }
 811         } while (++count);
 812
 813         return status;
 814 }
 815
 816 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 817 {
 818         struct rtl_priv *rtlpriv = rtl_priv(hw);
 819         unsigned short i;
 820         u8 txpktbuf_bndy;
 821         u8 maxPage;
 822         bool status;
 823
 824         maxPage = 255;
 825         txpktbuf_bndy = 0xF8;
 826
 827
 828         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 829         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 830
 831         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 832
 833         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 834         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 835
 836         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 837         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 838
 839         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 840                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 841                 if (true != status)
 842                         return status;
 843         }
 844
 845         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 846         if (true != status)
 847                 return status;
 848
 849         for (i = txpktbuf_bndy; i < maxPage; i++) {
 850                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 851                 if (true != status)
 852                         return status;
 853         }
 854
 855         status = _rtl8821ae_llt_write(hw, maxPage, txpktbuf_bndy);
 856         if (true != status)
 857                 return status;
 858
 859         rtl_write_dword(rtlpriv, REG_RQPN, 0x80e70808);
 860         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 861
 862         return true;
 863 }
 864
 865 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 866 {
 867         struct rtl_priv *rtlpriv = rtl_priv(hw);
 868         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 869         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 870         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 871         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 872
 873         if (rtlpriv->rtlhal.up_first_time)
 874                 return;
 875
 876         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 877                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 878                         rtl8812ae_sw_led_on(hw, pLed0);
 879                 else
 880                         rtl8821ae_sw_led_on(hw, pLed0);
 881         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 882                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 883                         rtl8812ae_sw_led_on(hw, pLed0);
 884                 else
 885                         rtl8821ae_sw_led_on(hw, pLed0);
 886         else
 887                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 888                         rtl8812ae_sw_led_off(hw, pLed0);
 889                 else
 890                         rtl8821ae_sw_led_off(hw, pLed0);
 891 }
 892
 893 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 894 {
 895         struct rtl_priv *rtlpriv = rtl_priv(hw);
 896         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 897         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 898
 899         u8 bytetmp = 0;
 900         u16 wordtmp = 0;
 901         bool b_mac_func_enable = rtlhal->b_mac_func_enable;
 902
 903         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 904
 905         /*Auto Power Down to CHIP-off State*/
 906         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 907         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 908
 909         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 910                 /* HW Power on sequence*/
 911                 if(!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 912                         PWR_INTF_PCI_MSK, RTL8812_NIC_ENABLE_FLOW)) {
 913                                 RT_TRACE(COMP_INIT,DBG_LOUD,("init 8812 MAC Fail as power on failure\n"));
 914                                 return false;
 915                 }
 916         } else {
 917                 /* HW Power on sequence */
 918                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, PWR_FAB_ALL_MSK,
 919                         PWR_INTF_PCI_MSK, RTL8821A_NIC_ENABLE_FLOW)){
 920                         RT_TRACE(COMP_INIT,DBG_LOUD,("init 8821 MAC Fail as power on failure\n"));
 921                         return false;
 922                 }
 923         }
 924
 925         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 926         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 927
 928         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 929         bytetmp = 0xff;
 930         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 931         mdelay(2);
 932
 933         bytetmp |= 0x7f;
 934         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 935         mdelay(2);
 936
 937         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 938                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 939                 if (bytetmp & BIT(0)) {
 940                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 941                         bytetmp |= BIT(6);
 942                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 943                 }
 944         }
 945
 946         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 947         bytetmp &= ~BIT(4);
 948         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 949
 950         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 951
 952         if (!b_mac_func_enable) {
 953                 if (!_rtl8821ae_llt_table_init(hw))
 954                         return false;
 955         }
 956
 957         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 958         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 959
 960         /* Enable FW Beamformer Interrupt */
 961         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 962         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 963
 964         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 965         wordtmp &= 0xf;
 966         wordtmp |= 0xF5B1;
 967         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 968
 969         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 970         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 971         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 972         /*low address*/
 973         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 974                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
 975         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 976                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
 977         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 978                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 979         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 980                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 981         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 982                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 983         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 984                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 985         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 986                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
 987         rtl_write_dword(rtlpriv, REG_RX_DESA,
 988                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
 989
 990         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 991
 992         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 993
 994         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
 995         _rtl8821ae_gen_refresh_led_state(hw);
 996
 997         return true;
 998 }
 999
1000 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1001 {
1002         struct rtl_priv *rtlpriv = rtl_priv(hw);
1003         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1004         u32 reg_rrsr;
1005
1006         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1007
1008         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1009         /* ARFB table 9 for 11ac 5G 2SS */
1010         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1011         /* ARFB table 10 for 11ac 5G 1SS */
1012         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1013         /* ARFB table 11 for 11ac 24G 1SS */
1014         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1015         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1016         /* ARFB table 12 for 11ac 24G 1SS */
1017         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1018         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1019         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1020         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1021         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1022
1023         /*Set retry limit*/
1024         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1025
1026
1027         /* Set Data / Response auto rate fallack retry count*/
1028         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1029         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1030         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1031         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1032
1033         rtlpci->reg_bcn_ctrl_val = 0x1d;
1034         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1035
1036         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1037         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1,0xff); // 8 ms
1038
1039         /* AGGR_BK_TIME Reg51A 0x16 */
1040         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1041
1042         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1043         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1044
1045         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1046         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1047         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1048 }
1049
1050 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1051 {
1052         u16 ret = 0;
1053         u8 tmp = 0, count = 0;
1054
1055         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1056         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6) ;
1057         count = 0;
1058         while (tmp && count < 20) {
1059                 udelay(10);
1060                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1061                 count++;
1062         }
1063         if (0 == tmp)
1064                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1065
1066         return ret;
1067 }
1068
1069 void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1070 {
1071         u8 tmp = 0, count = 0;
1072
1073         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1074         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1075         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5) ;
1076         count = 0;
1077         while (tmp && count < 20) {
1078                 udelay(10);
1079                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1080                 count++;
1081         }
1082 }
1083
1084 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1085 {
1086         u16 read_addr = addr & 0xfffc;
1087         u8 tmp = 0, count = 0, ret = 0;
1088
1089         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1090         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1091         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1092         count = 0;
1093         while (tmp && count < 20) {
1094                 udelay(10);
1095                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1096                 count++;
1097         }
1098         if (0 == tmp) {
1099                 read_addr = REG_DBI_RDATA + addr % 4;
1100                 ret = rtl_read_word(rtlpriv, read_addr);
1101         }
1102         return ret;
1103 }
1104
1105 void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1106 {
1107         u8 tmp = 0, count = 0;
1108         u16 wrtie_addr, remainder = addr % 4;
1109
1110         wrtie_addr = REG_DBI_WDATA + remainder;
1111         rtl_write_byte(rtlpriv, wrtie_addr, data);
1112
1113         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1114         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1115
1116         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1117
1118         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1119         count = 0;
1120         while (tmp && count < 20) {
1121                 udelay(10);
1122                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1123                 count++;
1124         }
1125
1126 }
1127
1128 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1129 {
1130         struct rtl_priv *rtlpriv = rtl_priv(hw);
1131         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1132         u8 tmp;
1133
1134         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1135                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1136                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1137
1138                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1139                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1140         }
1141
1142         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1143         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1144
1145         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1146         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1147
1148         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1149         {
1150                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1151                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1152         }
1153 }
1154
1155 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1156 {
1157         struct rtl_priv *rtlpriv = rtl_priv(hw);
1158         u8 sec_reg_value;
1159         u8 tmp;
1160
1161         RT_TRACE(COMP_INIT, DBG_DMESG,
1162                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1163                   rtlpriv->sec.pairwise_enc_algorithm,
1164                   rtlpriv->sec.group_enc_algorithm));
1165
1166         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1167                 RT_TRACE(COMP_SEC, DBG_DMESG, ("not open hw encryption\n"));
1168                 return;
1169         }
1170
1171         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1172
1173         if (rtlpriv->sec.use_defaultkey) {
1174                 sec_reg_value |= SCR_TxUseDK;
1175                 sec_reg_value |= SCR_RxUseDK;
1176         }
1177
1178         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1179
1180         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1181         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1182
1183         RT_TRACE(COMP_SEC, DBG_DMESG,
1184                  ("The SECR-value %x \n", sec_reg_value));
1185
1186         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1187
1188 }
1189
1190 #if 0
1191 bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1192 {
1193         struct rtl_priv *rtlpriv = rtl_priv(hw);
1194         u8 tmp;
1195         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL+3);
1196         if (!(tmp&BIT(2))) {
1197                 rtl_write_byte(rtlpriv, REG_DBI_CTRL+3, tmp|BIT(2));
1198                 mdelay(100);
1199         }
1200
1201         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL+3);
1202         if (tmp&BIT(0) || tmp&BIT(1)) {
1203                 RT_TRACE(COMP_INIT, DBG_LOUD,
1204                         ("rtl8821ae_check_pcie_dma_hang(): TRUE! Reset PCIE DMA!\n"));
1205                 return true;
1206         } else {
1207                 return false;
1208         }
1209 }
1210
1211 void _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1212                                                                                                         bool mac_power_on, bool watch_dog)
1213 {
1214         struct rtl_priv *rtlpriv = rtl_priv(hw);
1215         u8 tmp;
1216         bool release_mac_rx_pause;
1217         u8 backup_pcie_dma_pause;
1218
1219         RT_TRACE(COMP_INIT, DBG_LOUD, ("_rtl8821ae_reset_pcie_interface_dma()\n"));
1220
1221         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1222         tmp &= ~BIT(1);
1223         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1224         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1225         tmp |= BIT2;
1226         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1227
1228         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1229         if (tmp & BIT(2)) {
1230                 release_mac_rx_pause = false;
1231         } else {
1232                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp | BIT(2));
1233                 release_mac_rx_pause = true;
1234         }
1235         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+1);
1236         if (backup_pcie_dma_pause != 0xFF)
1237                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1238
1239         if (mac_power_on)
1240                 rtl_write_byte(rtlpriv, REG_CR, 0);
1241
1242         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1243         tmp &= ~BIT(0);
1244         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, tmp);
1245
1246         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1247         tmp |= ~BIT(0);
1248         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, tmp);
1249
1250         if (mac_power_on)
1251                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1252
1253         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL+2);
1254         tmp |= BIT1;
1255         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL+2, tmp);
1256
1257         if (watch_dog) {
1258                 u32 rqpn = 0;
1259                 u32 rqpn_npq = 0;
1260                 u8 tx_page_boundary = _RQPN_Init_8812E(Adapter, &rqpn_npq, &rqpn);
1261
1262                 if(LLT_table_init_8812(Adapter, TX_PAGE_BOUNDARY, RQPN, RQPN_NPQ) == RT_STATUS_FAILURE)
1263                         return false;
1264
1265                         PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
1266                         PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
1267
1268                         // <1> Reset Tx descriptor
1269                         Adapter->HalFunc.ResetTxDescHandler(Adapter,Adapter->NumTxDesc);
1270
1271                         // <2> Reset Rx descriptor
1272                         Adapter->HalFunc.ResetRxDescHandler(Adapter,Adapter->NumRxDesc);
1273
1274                         // <3> Reset RFDs
1275                         FreeRFDs( Adapter, TRUE);
1276
1277                         // <4> Reset TCBs
1278                         FreeTCBs( Adapter, TRUE);
1279
1280                         // We should set all Rx desc own bit to 1 to prevent from RDU after enable Rx DMA. 2013.02.18, by tynli.
1281                         PrepareAllRxDescBuffer(Adapter);
1282
1283                         PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
1284                         PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
1285
1286                         //
1287                         // Initialize TRx DMA address.
1288                         //
1289                         // Because set 0x100 to 0x0 will cause the Rx descriptor address 0x340 be cleared to zero on 88EE,
1290                         // we should re-initialize Rx desc. address before enable DMA. 2012.11.07. by tynli.
1291                         InitTRxDescHwAddress8812AE(Adapter);
1292                 }
1293
1294                 // In MAC power on state, BB and RF maybe in ON state, if we release TRx DMA here
1295                 // it will cause packets to be started to Tx/Rx, so we release Tx/Rx DMA later.
1296                 if(!bInMACPowerOn || bInWatchDog)
1297                 {
1298                         // 8. release TRX DMA
1299                         //write 0x284 bit[18] = 1'b0
1300                         //write 0x301 = 0x00
1301                         if(bReleaseMACRxPause)
1302                         {
1303                                 u1Tmp = PlatformEFIORead1Byte(Adapter, REG_RXDMA_CONTROL);
1304                                 PlatformEFIOWrite1Byte(Adapter, REG_RXDMA_CONTROL, (u1Tmp&~BIT2));
1305                         }
1306                         PlatformEFIOWrite1Byte(Adapter,         REG_PCIE_CTRL_REG+1, BackUpPcieDMAPause);
1307                 }
1308
1309                 if(IS_HARDWARE_TYPE_8821E(Adapter))
1310                 {
1311                         //9. lock system register
1312                         //       write 0xCC bit[2] = 1'b0
1313                         u1Tmp = PlatformEFIORead1Byte(Adapter, REG_PMC_DBG_CTRL2_8723B);
1314                         u1Tmp &= ~(BIT2);
1315                         PlatformEFIOWrite1Byte(Adapter, REG_PMC_DBG_CTRL2_8723B, u1Tmp);
1316                 }
1317
1318                 return RT_STATUS_SUCCESS;
1319 }
1320 #endif
1321
1322 // Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ----------
1323 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1324 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1325 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1326 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1327 // -----------------------------------------------------------
1328
1329 void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1330 {
1331         struct rtl_priv *rtlpriv = rtl_priv(hw);
1332         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1, \
1333                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, \
1334                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1335
1336         rtlpriv->cfg->ops->set_hw_reg(hw, \
1337                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1338
1339         RT_TRACE(COMP_INIT,DBG_LOUD, \
1340                 ("Initialize MacId media status: from %d to %d\n", \
1341                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, \
1342                 MAC_ID_STATIC_FOR_BT_CLIENT_END));
1343 }
1344
1345 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1346 {
1347         struct rtl_priv *rtlpriv = rtl_priv(hw);
1348         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1349         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1350         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1351         bool rtstatus = true;
1352         int err;
1353         u8 tmp_u1b;
1354         u32 nav_upper = WIFI_NAV_UPPER_US;
1355
1356         rtlpriv->rtlhal.being_init_adapter = true;
1357         rtlpriv->intf_ops->disable_aspm(hw);
1358
1359         /*YP wowlan not considered*/
1360
1361         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1362         if (tmp_u1b!=0 && tmp_u1b != 0xEA) {
1363                 rtlhal->b_mac_func_enable = true;
1364                 RT_TRACE(COMP_INIT,DBG_LOUD,(" MAC has already power on.\n"));
1365         } else {
1366                 rtlhal->b_mac_func_enable = false;
1367                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1368         }
1369
1370 /*      if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1371                 _rtl8821ae_reset_pcie_interface_dma(hw,rtlhal->b_mac_func_enable,false);
1372                 rtlhal->b_mac_func_enable = false;
1373         } */
1374
1375         rtstatus = _rtl8821ae_init_mac(hw);
1376         if (rtstatus != true) {
1377                 RT_TRACE(COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
1378                 err = 1;
1379                 return err;
1380         }
1381
1382         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1383         tmp_u1b &= 0x7F;
1384         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1385
1386         err = rtl8821ae_download_fw(hw, false);
1387         if (err) {
1388                 RT_TRACE(COMP_ERR, DBG_WARNING,
1389                          ("Failed to download FW. Init HW "
1390                           "without FW now..\n"));
1391                 err = 1;
1392                 rtlhal->bfw_ready = false;
1393                 return err;
1394         } else {
1395                 rtlhal->bfw_ready = true;
1396         }
1397         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1398         rtlhal->bfw_clk_change_in_progress = false;
1399         rtlhal->ballow_sw_to_change_hwclc = false;
1400         rtlhal->last_hmeboxnum = 0;
1401
1402         /*SIC_Init(Adapter);
1403         if(pHalData->AMPDUBurstMode)
1404                 PlatformEFIOWrite1Byte(Adapter,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1405
1406         rtl8821ae_phy_mac_config(hw);
1407         /* because last function modify RCR, so we update
1408          * rcr var here, or TP will unstable for receive_config
1409          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1410          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1411         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1412         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1413         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1414         rtl8821ae_phy_bb_config(hw);
1415
1416         rtl8821ae_phy_rf_config(hw);
1417
1418         _rtl8821ae_hw_configure(hw);
1419
1420         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1421
1422         /*set wireless mode*/
1423
1424         rtlhal->b_mac_func_enable = true;
1425
1426         rtl_cam_reset_all_entry(hw);
1427
1428         rtl8821ae_enable_hw_security_config(hw);
1429
1430         ppsc->rfpwr_state = ERFON;
1431
1432         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1433         _rtl8821ae_enable_aspm_back_door(hw);
1434         rtlpriv->intf_ops->enable_aspm(hw);
1435
1436         //rtl8821ae_bt_hw_init(hw);
1437         rtlpriv->rtlhal.being_init_adapter = false;
1438
1439         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1440
1441         //rtl8821ae_dm_check_txpower_tracking(hw);
1442         //rtl8821ae_phy_lc_calibrate(hw);
1443
1444         /* Release Rx DMA*/
1445         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1446         if (tmp_u1b & BIT(2)) {
1447                 /* Release Rx DMA if needed*/
1448                 tmp_u1b &= ~BIT(2);
1449                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1450         }
1451
1452         /* Release Tx/Rx PCIE DMA if*/
1453         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1454
1455         rtl8821ae_dm_init(hw);
1456         rtl8821ae_macid_initialize_mediastatus(hw);
1457
1458         RT_TRACE(COMP_INIT, DBG_LOUD, ("rtl8821ae_hw_init() <====\n"));
1459         return err;
1460 }
1461
1462 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
1463 {
1464         struct rtl_priv *rtlpriv = rtl_priv(hw);
1465         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1466         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1467         enum version_8821ae version = VERSION_UNKNOWN;
1468         u32 value32;
1469
1470         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1471         RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadChipVersion8812A 0xF0 = 0x%x \n", value32));
1472
1473
1474
1475         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1476                 rtlphy->rf_type = RF_2T2R;
1477         else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1478                 rtlphy->rf_type = RF_1T1R;
1479
1480         RT_TRACE(COMP_INIT, DBG_LOUD, ("RF_Type is %x!!\n", rtlphy->rf_type));
1481
1482
1483         if (value32 & TRP_VAUX_EN)
1484         {
1485                 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1486                 {
1487                         if(rtlphy->rf_type == RF_2T2R)
1488                                 version = VERSION_TEST_CHIP_2T2R_8812;
1489                         else
1490                                 version = VERSION_TEST_CHIP_1T1R_8812;
1491                 }
1492                 else
1493                         version = VERSION_TEST_CHIP_8821;
1494         } else {
1495                 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1496                 {
1497                         u32     rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) +1 ;
1498
1499                         if(rtlphy->rf_type == RF_2T2R)
1500                                 version = (enum version_8821ae)(CHIP_8812 | NORMAL_CHIP | RF_TYPE_2T2R);
1501                         else
1502                                 version = (enum version_8821ae)(CHIP_8812 | NORMAL_CHIP);
1503
1504                         version = (enum version_8821ae)(version| (rtl_id << 12));
1505                 }
1506                 else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1507                 {
1508                         u32     rtl_id = value32 & CHIP_VER_RTL_MASK;
1509
1510                         version = (enum version_8821ae)(CHIP_8821 | NORMAL_CHIP | rtl_id);
1511                 }
1512         }
1513
1514         RT_TRACE(COMP_INIT, DBG_LOUD,
1515                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1516                   "RF_2T2R" : "RF_1T1R"));
1517
1518         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1519         {
1520                 /*WL_HWROF_EN.*/
1521                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1522                 rtlphy->hw_rof_enable= ((value32 & WL_HWROF_EN) ? 1 : 0);
1523         }
1524
1525         switch(version)
1526         {
1527                 case VERSION_TEST_CHIP_1T1R_8812:
1528                         RT_TRACE(COMP_INIT, DBG_LOUD,
1529                                 ("Chip Version ID: VERSION_TEST_CHIP_1T1R_8812.\n"));
1530                         break;
1531                 case VERSION_TEST_CHIP_2T2R_8812:
1532                         RT_TRACE(COMP_INIT, DBG_LOUD,
1533                                 ("Chip Version ID: VERSION_TEST_CHIP_2T2R_8812.\n"));
1534                         break;
1535                 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
1536                         RT_TRACE(COMP_INIT, DBG_LOUD,
1537                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812.\n"));
1538                         break;
1539                 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
1540                         RT_TRACE(COMP_INIT, DBG_LOUD,
1541                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812.\n"));
1542                         break;
1543                 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
1544                         RT_TRACE(COMP_INIT, DBG_LOUD,
1545                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT.\n"));
1546                         break;
1547                 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
1548                         RT_TRACE(COMP_INIT, DBG_LOUD,
1549                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT.\n"));
1550                         break;
1551                 case VERSION_TEST_CHIP_8821:
1552                         RT_TRACE(COMP_INIT, DBG_LOUD,
1553                                 ("Chip Version ID: VERSION_TEST_CHIP_8821.\n"));
1554                         break;
1555                 case VERSION_NORMAL_TSMC_CHIP_8821:
1556                         RT_TRACE(COMP_INIT, DBG_LOUD,
1557                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT.\n"));
1558                         break;
1559                 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
1560                         RT_TRACE(COMP_INIT, DBG_LOUD,
1561                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT.\n"));
1562                         break;
1563                 default:
1564                         RT_TRACE(COMP_INIT, DBG_LOUD,
1565                                 ("Chip Version ID: Unknow (0x%X).\n", version));
1566                         break;
1567         }
1568
1569         return version;
1570 }
1571
1572 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
1573                                      enum nl80211_iftype type)
1574 {
1575         struct rtl_priv *rtlpriv = rtl_priv(hw);
1576         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1577         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1578         bt_msr &= 0xfc;
1579
1580         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1581         RT_TRACE(COMP_BEACON, DBG_LOUD,
1582                 ("clear 0x550 when set HW_VAR_MEDIA_STATUS\n"));
1583
1584         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1585             type == NL80211_IFTYPE_STATION) {
1586                 _rtl8821ae_stop_tx_beacon(hw);
1587                 _rtl8821ae_enable_bcn_sub_func(hw);
1588         } else if (type == NL80211_IFTYPE_ADHOC ||
1589                 type == NL80211_IFTYPE_AP) {
1590                 _rtl8821ae_resume_tx_beacon(hw);
1591                 _rtl8821ae_disable_bcn_sub_func(hw);
1592         } else {
1593                 RT_TRACE(COMP_ERR, DBG_WARNING,("Set HW_VAR_MEDIA_STATUS: "
1594                           "No such media status(%x).\n", type));
1595         }
1596
1597         switch (type) {
1598         case NL80211_IFTYPE_UNSPECIFIED:
1599                 bt_msr |= MSR_NOLINK;
1600                 ledaction = LED_CTL_LINK;
1601                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to NO LINK!\n"));
1602                 break;
1603         case NL80211_IFTYPE_ADHOC:
1604                 bt_msr |= MSR_ADHOC;
1605                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to Ad Hoc!\n"));
1606                 break;
1607         case NL80211_IFTYPE_STATION:
1608                 bt_msr |= MSR_INFRA;
1609                 ledaction = LED_CTL_LINK;
1610                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to STA!\n"));
1611                 break;
1612         case NL80211_IFTYPE_AP:
1613                 bt_msr |= MSR_AP;
1614                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to AP!\n"));
1615                 break;
1616         default:
1617                 RT_TRACE(COMP_ERR, DBG_EMERG, ("Network type %d not support!\n", type));
1618                 return 1;
1619                 break;
1620
1621         }
1622
1623         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1624         rtlpriv->cfg->ops->led_control(hw, ledaction);
1625         if ((bt_msr & 0xfc) == MSR_AP)
1626                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1627         else
1628                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1629
1630         return 0;
1631 }
1632
1633 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1634 {
1635         struct rtl_priv *rtlpriv = rtl_priv(hw);
1636         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1637         u32 reg_rcr = rtlpci->receive_config;
1638
1639         if (rtlpriv->psc.rfpwr_state != ERFON)
1640                 return;
1641
1642         if (check_bssid == true) {
1643                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1644                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1645                                               (u8 *) (&reg_rcr));
1646                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
1647         } else if (check_bssid == false) {
1648                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1649                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
1650                 rtlpriv->cfg->ops->set_hw_reg(hw,
1651                         HW_VAR_RCR, (u8 *) (&reg_rcr));
1652         }
1653
1654 }
1655
1656 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1657 {
1658         struct rtl_priv *rtlpriv = rtl_priv(hw);
1659
1660         RT_TRACE(COMP_INIT, DBG_LOUD, ("rtl8821ae_set_network_type!\n"));
1661
1662         if (_rtl8821ae_set_media_status(hw, type))
1663                 return -EOPNOTSUPP;
1664
1665         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1666                 if (type != NL80211_IFTYPE_AP)
1667                         rtl8821ae_set_check_bssid(hw, true);
1668         } else {
1669                 rtl8821ae_set_check_bssid(hw, false);
1670         }
1671
1672         return 0;
1673 }
1674
1675 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1676 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
1677 {
1678         struct rtl_priv *rtlpriv = rtl_priv(hw);
1679         rtl8821ae_dm_init_edca_turbo(hw);
1680         switch (aci) {
1681         case AC1_BK:
1682                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1683                 break;
1684         case AC0_BE:
1685                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1686                 break;
1687         case AC2_VI:
1688                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1689                 break;
1690         case AC3_VO:
1691                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1692                 break;
1693         default:
1694                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1695                 break;
1696         }
1697 }
1698
1699 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
1700 {
1701         struct rtl_priv *rtlpriv = rtl_priv(hw);
1702         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1703
1704         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1705         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1706         rtlpci->irq_enabled = true;
1707         /* there are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM.
1708         *So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore.
1709         */
1710         //rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1711         /*enable system interrupt*/
1712         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1713 }
1714
1715 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
1716 {
1717         struct rtl_priv *rtlpriv = rtl_priv(hw);
1718         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1719
1720         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1721         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1722         rtlpci->irq_enabled = false;
1723         synchronize_irq(rtlpci->pdev->irq);
1724 }
1725
1726 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1727 {
1728         struct rtl_priv *rtlpriv = rtl_priv(hw);
1729         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1730         u8 u1b_tmp;
1731
1732         rtlhal->b_mac_func_enable = false;
1733
1734         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1735         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1736         /* 1. Run LPS WL RFOFF flow */
1737                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"));
1738                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1739                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1740         }
1741         /* 2. 0x1F[7:0] = 0 */
1742         /* turn off RF */
1743         //rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1744         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1745                 rtlhal->bfw_ready ) {
1746                 rtl8821ae_firmware_selfreset(hw);
1747         }
1748
1749         /* Reset MCU. Suggested by Filen. */
1750         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1751         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1752
1753         /* g.   MCUFWDL 0x80[1:0]=0      */
1754         /* reset MCU ready status */
1755         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1756
1757         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1758                 /* HW card disable configuration. */
1759                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1760                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1761         } else {
1762                 /* HW card disable configuration. */
1763                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1764                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1765         }
1766
1767         /* Reset MCU IO Wrapper */
1768         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1769         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1770         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1771         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1772
1773         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1774         /* lock ISO/CLK/Power control register */
1775         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1776 }
1777
1778 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
1779 {
1780         struct rtl_priv *rtlpriv = rtl_priv(hw);
1781         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1782         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1783         enum nl80211_iftype opmode;
1784
1785         RT_TRACE(COMP_INIT, DBG_LOUD,
1786                  ("rtl8821ae_card_disable.\n"));
1787
1788         mac->link_state = MAC80211_NOLINK;
1789         opmode = NL80211_IFTYPE_UNSPECIFIED;
1790         _rtl8821ae_set_media_status(hw, opmode);
1791         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1792             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1793                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1794         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1795         _rtl8821ae_poweroff_adapter(hw);
1796
1797         /* after power off we should do iqk again */
1798         rtlpriv->phy.iqk_initialized = false;
1799 }
1800
1801 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
1802                                   u32 *p_inta, u32 *p_intb)
1803 {
1804         struct rtl_priv *rtlpriv = rtl_priv(hw);
1805         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1806
1807         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1808         rtl_write_dword(rtlpriv, ISR, *p_inta);
1809
1810
1811         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1812         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1813
1814 }
1815
1816
1817 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1818 {
1819
1820         struct rtl_priv *rtlpriv = rtl_priv(hw);
1821         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1822         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1823         u16 bcn_interval, atim_window;
1824
1825         bcn_interval = mac->beacon_interval;
1826         atim_window = 2;        /*FIX MERGE */
1827         rtl8821ae_disable_interrupt(hw);
1828         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1829         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1830         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1831         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1832         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1833         rtl_write_byte(rtlpriv, 0x606, 0x30);
1834         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1835         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1836         rtl8821ae_enable_interrupt(hw);
1837 }
1838
1839 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
1840 {
1841         struct rtl_priv *rtlpriv = rtl_priv(hw);
1842         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1843         u16 bcn_interval = mac->beacon_interval;
1844
1845         RT_TRACE(COMP_BEACON, DBG_DMESG,
1846                  ("beacon_interval:%d\n", bcn_interval));
1847         rtl8821ae_disable_interrupt(hw);
1848         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1849         rtl8821ae_enable_interrupt(hw);
1850 }
1851
1852 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
1853                                    u32 add_msr, u32 rm_msr)
1854 {
1855         struct rtl_priv *rtlpriv = rtl_priv(hw);
1856         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1857
1858         RT_TRACE(COMP_INTR, DBG_LOUD,
1859                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1860
1861         if (add_msr)
1862                 rtlpci->irq_mask[0] |= add_msr;
1863         if (rm_msr)
1864                 rtlpci->irq_mask[0] &= (~rm_msr);
1865         rtl8821ae_disable_interrupt(hw);
1866         rtl8821ae_enable_interrupt(hw);
1867 }
1868
1869 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
1870 {
1871         u8 group = 0;
1872
1873         if (chnl <= 14) {
1874                 if (1 <= chnl && chnl <= 2 )
1875                         group = 0;
1876         else if (3 <= chnl && chnl <= 5 )
1877                         group = 1;
1878         else if (6 <= chnl && chnl <= 8 )
1879                         group = 2;
1880         else if (9 <= chnl && chnl <= 11)
1881                         group = 3;
1882         else /*if (12 <= chnl && chnl <= 14)*/
1883                         group = 4;
1884         } else {
1885                 if (36 <= chnl && chnl <= 42)
1886                         group = 0;
1887         else if (44 <= chnl && chnl <= 48)
1888                         group = 1;
1889         else if (50 <= chnl && chnl <= 58)
1890                         group = 2;
1891         else if (60 <= chnl && chnl <= 64)
1892                         group = 3;
1893         else if (100 <= chnl && chnl <= 106)
1894                         group = 4;
1895         else if (108 <= chnl && chnl <= 114)
1896                         group = 5;
1897         else if (116 <= chnl && chnl <= 122)
1898                         group = 6;
1899         else if (124 <= chnl && chnl <= 130)
1900                         group = 7;
1901         else if (132 <= chnl && chnl <= 138)
1902                         group = 8;
1903         else if (140 <= chnl && chnl <= 144)
1904                         group = 9;
1905         else if (149 <= chnl && chnl <= 155)
1906                         group = 10;
1907         else if (157 <= chnl && chnl <= 161)
1908                         group = 11;
1909         else if (165 <= chnl && chnl <= 171)
1910                         group = 12;
1911         else if (173 <= chnl && chnl <= 177)
1912                         group = 13;
1913                 else
1914                         /*RT_TRACE(COMP_EFUSE,DBG_LOUD,
1915                                 ("5G, Channel %d in Group not found \n",chnl));*/
1916                         RT_ASSERT(!COMP_EFUSE,
1917                                 ("5G, Channel %d in Group not found \n",chnl));
1918         }
1919         return group;
1920 }
1921
1922 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
1923         struct txpower_info_2g *pwrinfo24g,
1924         struct txpower_info_5g *pwrinfo5g,
1925         bool autoload_fail,
1926         u8 *hwinfo)
1927 {
1928         struct rtl_priv *rtlpriv = rtl_priv(hw);
1929         u32 rfPath, eeAddr=EEPROM_TX_PWR_INX, group,TxCount=0;
1930
1931         RT_TRACE(COMP_INIT, DBG_LOUD, ("hal_ReadPowerValueFromPROM8821ae(): PROMContent[0x%x]=0x%x\n", (eeAddr+1), hwinfo[eeAddr+1]));
1932         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
1933                 autoload_fail = true;
1934
1935         if (autoload_fail)
1936         {
1937                 RT_TRACE(COMP_INIT, DBG_LOUD, ("auto load fail : Use Default value!\n"));
1938                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1939                         /*2.4G default value*/
1940                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1941                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
1942                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
1943                         }
1944                         for (TxCount = 0;TxCount < MAX_TX_COUNT;TxCount++) {
1945                                 if (TxCount == 0) {
1946                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
1947                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
1948                                 } else {
1949                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
1950                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
1951                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
1952                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
1953                                 }
1954                         }
1955                         /*5G default value*/
1956                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1957                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
1958
1959                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1960                                 if (TxCount == 0) {
1961                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
1962                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
1963                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
1964                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
1965                                 } else {
1966                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
1967                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
1968                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
1969                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
1970                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
1971                                 }
1972                         }
1973                 }
1974                 return;
1975         }
1976
1977         rtl_priv(hw)->efuse.b_txpwr_fromeprom = true;
1978
1979         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1980                 /*2.4G default value*/
1981                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1982                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
1983                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
1984                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
1985                 }
1986                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1987                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
1988                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
1989                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
1990                 }
1991                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount ++) {
1992                         if (TxCount == 0) {
1993                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
1994                                 if (hwinfo[eeAddr] == 0xFF) {
1995                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0x02;
1996                                 } else {
1997                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
1998                                         if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))    /*bit sign number to 8 bit sign number*/
1999                                                 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2000                                 }
2001
2002                                 if (hwinfo[eeAddr] == 0xFF) {
2003                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0x04;
2004                                 } else {
2005                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2006                                         if(pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))             /*bit sign number to 8 bit sign number*/
2007                                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2008                                 }
2009                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2010                                 eeAddr++;
2011                         } else {
2012                                 if (hwinfo[eeAddr] == 0xFF) {
2013                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2014                                 } else {
2015                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2016                                         if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2017                                                 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2018                                 }
2019
2020                                 if (hwinfo[eeAddr] == 0xFF) {
2021                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2022                                 } else {
2023                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2024                                         if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2025                                                 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2026                                 }
2027
2028                                 eeAddr++;
2029
2030                                 if (hwinfo[eeAddr] == 0xFF) {
2031                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2032                                 } else {
2033                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2034                                         if(pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2035                                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2036                                 }
2037
2038                                 if (hwinfo[eeAddr] == 0xFF) {
2039                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2040                                 } else {
2041                                         pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2042                                         if(pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2043                                                 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2044                                 }
2045                                 eeAddr++;
2046                         }
2047                 }
2048
2049                 /*5G default value*/
2050                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group ++) {
2051                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2052                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2053                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2054                 }
2055
2056                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2057                         if (TxCount == 0) {
2058                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2059                                 if (hwinfo[eeAddr] == 0xFF) {
2060                                         pwrinfo5g->bw20_diff[rfPath][TxCount] = 0x0;
2061                                 } else {
2062                                         pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2063                                         if(pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2064                                                 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2065                                 }
2066
2067                                 if (hwinfo[eeAddr] == 0xFF) {
2068                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] = 0x4;
2069                                 } else {
2070                                         pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2071                                         if(pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2072                                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2073                                 }
2074                                 eeAddr++;
2075                         } else {
2076                                 if (hwinfo[eeAddr] == 0xFF) {
2077                                         pwrinfo5g->bw40_diff[rfPath][TxCount] = 0xFE;
2078                                 } else {
2079                                         pwrinfo5g->bw40_diff[rfPath][TxCount]= (hwinfo[eeAddr] & 0xf0) >> 4;
2080                                         if(pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2081                                                 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2082                                 }
2083
2084                                 if (hwinfo[eeAddr] == 0xFF) {
2085                                         pwrinfo5g->bw20_diff[rfPath][TxCount] = 0xFE;
2086                                 } else {
2087                                         pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2088                                         if(pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2089                                                 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2090                                 }
2091                                 eeAddr++;
2092                         }
2093                 }
2094
2095                 if (hwinfo[eeAddr] == 0xFF) {
2096                         pwrinfo5g->ofdm_diff[rfPath][1] = 0xFE;
2097                         pwrinfo5g->ofdm_diff[rfPath][2] = 0xFE;
2098                 } else {
2099                         pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2100                         pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2101                 }
2102                 eeAddr++;
2103                 if (hwinfo[eeAddr] == 0xFF)
2104                         pwrinfo5g->ofdm_diff[rfPath][3] = 0xFE;
2105                 else
2106                         pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2107
2108                 eeAddr++;
2109
2110                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2111                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] == 0xFF)
2112                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] = 0xFE;
2113                         else if(pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2114                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2115                 }
2116                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2117                         if (hwinfo[eeAddr] == 0xFF) {
2118                                 pwrinfo5g->bw80_diff[rfPath][TxCount] = 0xFE;
2119                         } else {
2120                                 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2121                                 if(pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))              //4bit sign number to 8 bit sign number
2122                                         pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2123                         }
2124
2125                         if (hwinfo[eeAddr] == 0xFF) {
2126                                 pwrinfo5g->bw160_diff[rfPath][TxCount] = 0xFE;
2127                         } else {
2128                                 pwrinfo5g->bw160_diff[rfPath][TxCount]= (hwinfo[eeAddr] & 0x0f);
2129                                 if(pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))             //4bit sign number to 8 bit sign number
2130                                         pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2131                         }
2132                         eeAddr++;
2133                 }
2134         }
2135 }
2136
2137 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2138                                                  bool autoload_fail,
2139                                                  u8 *hwinfo)
2140 {
2141         struct rtl_priv *rtlpriv = rtl_priv(hw);
2142         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2143         struct txpower_info_2g pwrinfo24g;
2144         struct txpower_info_5g pwrinfo5g;
2145         u8 channel5g[CHANNEL_MAX_NUMBER_5G] =
2146                                  {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
2147                           114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
2148                           153,155,157,159,161,163,165,167,168,169,171,173,175,177};
2149         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2150         u8 rf_path, index;
2151         u8 i;
2152
2153         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g, autoload_fail, hwinfo);
2154
2155         for (rf_path = 0; rf_path < 2; rf_path++) {
2156                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2157                         index = _rtl8821ae_get_chnl_group(i + 1);
2158
2159                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2160                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2161                                         pwrinfo24g.index_cck_base[rf_path][5];
2162                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2163                                         pwrinfo24g.index_bw40_base[rf_path][index];
2164                         } else {
2165                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2166                                         pwrinfo24g.index_cck_base[rf_path][index];
2167                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2168                                         pwrinfo24g.index_bw40_base[rf_path][index];
2169                         }
2170                 }
2171
2172                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2173                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2174                         rtlefuse->txpwr_5g_bw40base[rf_path][i] = pwrinfo5g.index_bw40_base[rf_path][index];
2175                 }
2176                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2177                         u8 upper, lower;
2178                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2179                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2180                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2181
2182                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2183                 }
2184                 for (i = 0; i < MAX_TX_COUNT; i++) {
2185                         rtlefuse->txpwr_cckdiff[rf_path][i] = pwrinfo24g.cck_diff[rf_path][i];
2186                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] = pwrinfo24g.ofdm_diff[rf_path][i];
2187                         rtlefuse->txpwr_ht20diff[rf_path][i] = pwrinfo24g.bw20_diff[rf_path][i];
2188                         rtlefuse->txpwr_ht40diff[rf_path][i] = pwrinfo24g.bw40_diff[rf_path][i];
2189
2190                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = pwrinfo5g.ofdm_diff[rf_path][i];
2191                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] = pwrinfo5g.bw20_diff[rf_path][i];
2192                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] = pwrinfo5g.bw40_diff[rf_path][i];
2193                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] = pwrinfo5g.bw80_diff[rf_path][i];
2194                 }
2195         }
2196
2197         if (!autoload_fail){
2198                 rtlefuse->eeprom_regulatory =
2199                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2200                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2201                         rtlefuse->eeprom_regulatory = 0;
2202         } else {
2203                 rtlefuse->eeprom_regulatory = 0;
2204         }
2205
2206         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
2207         ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory ));
2208 }
2209
2210 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2211                                                  bool autoload_fail,
2212                                                  u8 *hwinfo)
2213 {
2214         struct rtl_priv *rtlpriv = rtl_priv(hw);
2215         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2216         struct txpower_info_2g pwrinfo24g;
2217         struct txpower_info_5g pwrinfo5g;
2218         u8 channel5g[CHANNEL_MAX_NUMBER_5G] =
2219                                 {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
2220                  114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
2221                  153,155,157,159,161,163,165,167,168,169,171,173,175,177};
2222         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2223         u8 rf_path, index;
2224         u8 i;
2225
2226         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g, autoload_fail, hwinfo);
2227
2228         for (rf_path = 0; rf_path < 2; rf_path++) {
2229                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2230                         index = _rtl8821ae_get_chnl_group(i + 1);
2231
2232                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2233                                 rtlefuse->txpwrlevel_cck[rf_path][i] = pwrinfo24g.index_cck_base[rf_path][5];
2234                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = pwrinfo24g.index_bw40_base[rf_path][index];
2235                         } else {
2236                                 rtlefuse->txpwrlevel_cck[rf_path][i] = pwrinfo24g.index_cck_base[rf_path][index];
2237                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = pwrinfo24g.index_bw40_base[rf_path][index];
2238                         }
2239                 }
2240
2241                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2242                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2243                         rtlefuse->txpwr_5g_bw40base[rf_path][i] = pwrinfo5g.index_bw40_base[rf_path][index];
2244                 }
2245                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2246                         u8 upper, lower;
2247                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2248                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2249                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2250
2251                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2252                 }
2253                 for (i = 0; i < MAX_TX_COUNT; i++) {
2254                         rtlefuse->txpwr_cckdiff[rf_path][i] = pwrinfo24g.cck_diff[rf_path][i];
2255                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] = pwrinfo24g.ofdm_diff[rf_path][i];
2256                         rtlefuse->txpwr_ht20diff[rf_path][i] = pwrinfo24g.bw20_diff[rf_path][i];
2257                         rtlefuse->txpwr_ht40diff[rf_path][i] = pwrinfo24g.bw40_diff[rf_path][i];
2258
2259                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = pwrinfo5g.ofdm_diff[rf_path][i];
2260                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] = pwrinfo5g.bw20_diff[rf_path][i];
2261                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] = pwrinfo5g.bw40_diff[rf_path][i];
2262                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] = pwrinfo5g.bw80_diff[rf_path][i];
2263                 }
2264         }
2265
2266         if (!autoload_fail){
2267                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2268                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2269                         rtlefuse->eeprom_regulatory = 0;
2270         } else {
2271                 rtlefuse->eeprom_regulatory = 0;
2272         }
2273
2274         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
2275         ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory ));
2276 }
2277
2278 static void _rtl8812ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test )
2279 {
2280         struct rtl_priv *rtlpriv = rtl_priv(hw);
2281         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2282         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2283         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2284         u16 i, usvalue;
2285         u8 hwinfo[HWSET_MAX_SIZE];
2286         u16 eeprom_id;
2287
2288         if (b_pseudo_test) {
2289                 /* need add */
2290         }
2291
2292         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2293                 rtl_efuse_shadow_map_update(hw);
2294                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2295                        HWSET_MAX_SIZE);
2296         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2297                 RT_TRACE(COMP_ERR, DBG_EMERG,
2298                          ("RTL819X Not boot from eeprom, check it !!"));
2299         }
2300
2301         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP \n"),
2302                       hwinfo, HWSET_MAX_SIZE);
2303
2304         eeprom_id = *((u16 *) & hwinfo[0]);
2305         if (eeprom_id != RTL_EEPROM_ID) {
2306                 RT_TRACE(COMP_ERR, DBG_WARNING,
2307                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
2308                 rtlefuse->autoload_failflag = true;
2309         } else {
2310                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2311                 rtlefuse->autoload_failflag = false;
2312         }
2313
2314         if (rtlefuse->autoload_failflag == true) {
2315                 RT_TRACE(COMP_ERR, DBG_EMERG,
2316                          ("RTL8812AE autoload_failflag, check it !!"));
2317                 return;
2318         }
2319
2320         rtlefuse->eeprom_version = *(u8 *) & hwinfo[EEPROM_VERSION];
2321         if (rtlefuse->eeprom_version == 0xff)
2322                         rtlefuse->eeprom_version = 0;
2323
2324         RT_TRACE(COMP_INIT, DBG_LOUD,
2325                  ("EEPROM version: 0x%2x\n", rtlefuse->eeprom_version));
2326
2327         rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2328         rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2329         rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2330         rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2331         RT_TRACE(COMP_INIT, DBG_LOUD,
2332                  ("EEPROMId = 0x%4x\n", eeprom_id));
2333         RT_TRACE(COMP_INIT, DBG_LOUD,
2334                  ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
2335         RT_TRACE(COMP_INIT, DBG_LOUD,
2336                  ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
2337         RT_TRACE(COMP_INIT, DBG_LOUD,
2338                  ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
2339         RT_TRACE(COMP_INIT, DBG_LOUD,
2340                  ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
2341
2342         /*customer ID*/
2343         rtlefuse->eeprom_oemid = *(u8 *) & hwinfo[EEPROM_CUSTOMER_ID];
2344         if (rtlefuse->eeprom_oemid == 0xFF)
2345                 rtlefuse->eeprom_oemid = 0;
2346
2347         RT_TRACE(COMP_INIT, DBG_LOUD,
2348                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
2349
2350         for (i = 0; i < 6; i += 2) {
2351                 usvalue = *(u16 *) & hwinfo[EEPROM_MAC_ADDR + i];
2352                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2353         }
2354
2355         RT_TRACE(COMP_INIT, DBG_DMESG,
2356                  ("dev_addr: %pM\n", rtlefuse->dev_addr));
2357
2358         _rtl8812ae_read_txpower_info_from_hwpg(hw,
2359                 rtlefuse->autoload_failflag, hwinfo);
2360
2361         /*board type*/
2362         rtlefuse->board_type = (((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) & 0xE0 ) >> 5);
2363         if ((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) == 0xff )
2364                 rtlefuse->board_type = 0;
2365         rtlhal->boad_type = rtlefuse->board_type;
2366
2367         rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
2368                         rtlefuse->autoload_failflag, hwinfo);
2369
2370         rtlefuse->eeprom_channelplan = *(u8 *) & hwinfo[EEPROM_CHANNELPLAN];
2371         if (rtlefuse->eeprom_channelplan == 0xff)
2372                 rtlefuse->eeprom_channelplan = 0x7F;
2373
2374         /* set channel paln to world wide 13 */
2375         //rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
2376
2377         /*parse xtal*/
2378         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
2379         if ( rtlefuse->crystalcap == 0xFF )
2380                 rtlefuse->crystalcap = 0x20;
2381
2382         rtlefuse->eeprom_thermalmeter = *(u8 *) & hwinfo[EEPROM_THERMAL_METER];
2383         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||rtlefuse->autoload_failflag )
2384         {
2385                 rtlefuse->b_apk_thermalmeterignore = true;
2386                 rtlefuse->eeprom_thermalmeter = 0xff;
2387         }
2388
2389         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2390         RT_TRACE(COMP_INIT, DBG_LOUD,
2391                  ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
2392
2393         if (rtlefuse->autoload_failflag == false) {
2394                 rtlefuse->antenna_div_cfg = *(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18 >> 3;
2395                 if (*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
2396                         rtlefuse->antenna_div_cfg = 0x00;
2397                 /*if (BT_1ant())
2398                         rtlefuse->antenna_div_cfg = 0;*/
2399                 rtlefuse->antenna_div_type = *(u8 *) & hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
2400                 if (rtlefuse->antenna_div_type == 0xFF)
2401                 {
2402                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
2403                 }
2404         } else {
2405                 rtlefuse->antenna_div_cfg = 0;
2406                 rtlefuse->antenna_div_type = 0;
2407         }
2408
2409         RT_TRACE(COMP_INIT, DBG_LOUD,
2410                 ("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
2411                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type));
2412
2413         /*Hal_ReadPAType_8821A()*/
2414         /*Hal_EfuseParseRateIndicationOption8821A()*/
2415         /*Hal_ReadEfusePCIeCap8821AE()*/
2416
2417         pcipriv->ledctl.bled_opendrain = true;
2418
2419         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2420                 switch (rtlefuse->eeprom_oemid) {
2421                 case RT_CID_DEFAULT:
2422                         break;
2423                 case EEPROM_CID_TOSHIBA:
2424                         rtlhal->oem_id = RT_CID_TOSHIBA;
2425                         break;
2426                 case EEPROM_CID_CCX:
2427                         rtlhal->oem_id = RT_CID_CCX;
2428                         break;
2429                 case EEPROM_CID_QMI:
2430                         rtlhal->oem_id = RT_CID_819x_QMI;
2431                         break;
2432                 case EEPROM_CID_WHQL:
2433                         break;
2434                 default:
2435                         break;
2436
2437                 }
2438         }
2439 }
2440
2441 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test )
2442 {
2443         struct rtl_priv *rtlpriv = rtl_priv(hw);
2444         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2445         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2446         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2447         u16 i, usvalue;
2448         u8 hwinfo[HWSET_MAX_SIZE];
2449         u16 eeprom_id;
2450
2451         if (b_pseudo_test) {
2452                 /* need add */
2453         }
2454
2455         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2456                 rtl_efuse_shadow_map_update(hw);
2457                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2458                        HWSET_MAX_SIZE);
2459         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2460                 RT_TRACE(COMP_ERR, DBG_EMERG,
2461                          ("RTL819X Not boot from eeprom, check it !!"));
2462         }
2463
2464         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP \n"),
2465                       hwinfo, HWSET_MAX_SIZE);
2466
2467         eeprom_id = *((u16 *) & hwinfo[0]);
2468         if (eeprom_id != RTL_EEPROM_ID) {
2469                 RT_TRACE(COMP_ERR, DBG_WARNING,
2470                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
2471                 rtlefuse->autoload_failflag = true;
2472         } else {
2473                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2474                 rtlefuse->autoload_failflag = false;
2475         }
2476
2477         if (rtlefuse->autoload_failflag == true) {
2478                 RT_TRACE(COMP_ERR, DBG_EMERG,
2479                          ("RTL8812AE autoload_failflag, check it !!"));
2480                 return;
2481         }
2482
2483         rtlefuse->eeprom_version = *(u8 *) & hwinfo[EEPROM_VERSION];
2484         if (rtlefuse->eeprom_version == 0xff)
2485                         rtlefuse->eeprom_version = 0;
2486
2487         RT_TRACE(COMP_INIT, DBG_LOUD,
2488                  ("EEPROM version: 0x%2x\n", rtlefuse->eeprom_version));
2489
2490         rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2491         rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2492         rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2493         rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2494         RT_TRACE(COMP_INIT, DBG_LOUD,
2495                  ("EEPROMId = 0x%4x\n", eeprom_id));
2496         RT_TRACE(COMP_INIT, DBG_LOUD,
2497                  ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
2498         RT_TRACE(COMP_INIT, DBG_LOUD,
2499                  ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
2500         RT_TRACE(COMP_INIT, DBG_LOUD,
2501                  ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
2502         RT_TRACE(COMP_INIT, DBG_LOUD,
2503                  ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
2504
2505         /*customer ID*/
2506         rtlefuse->eeprom_oemid = *(u8 *) & hwinfo[EEPROM_CUSTOMER_ID];
2507         if (rtlefuse->eeprom_oemid == 0xFF)
2508                 rtlefuse->eeprom_oemid = 0;
2509
2510         RT_TRACE(COMP_INIT, DBG_LOUD,
2511                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
2512
2513         for (i = 0; i < 6; i += 2) {
2514                 usvalue = *(u16 *) & hwinfo[EEPROM_MAC_ADDR + i];
2515                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2516         }
2517
2518         RT_TRACE(COMP_INIT, DBG_DMESG,
2519                  ("dev_addr: %pM\n", rtlefuse->dev_addr));
2520
2521         _rtl8821ae_read_txpower_info_from_hwpg(hw,
2522                 rtlefuse->autoload_failflag, hwinfo);
2523
2524         /*board type*/
2525         rtlefuse->board_type = (((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) & 0xE0 ) >> 5);
2526         if ((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) == 0xff )
2527                 rtlefuse->board_type = 0;
2528         rtlhal->boad_type = rtlefuse->board_type;
2529
2530         rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
2531                         rtlefuse->autoload_failflag, hwinfo);
2532
2533         rtlefuse->eeprom_channelplan = *(u8 *) & hwinfo[EEPROM_CHANNELPLAN];
2534         if (rtlefuse->eeprom_channelplan == 0xff)
2535                 rtlefuse->eeprom_channelplan = 0x7F;
2536
2537         /* set channel paln to world wide 13 */
2538         //rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
2539
2540         /*parse xtal*/
2541         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
2542         if ( rtlefuse->crystalcap == 0xFF )
2543                 rtlefuse->crystalcap = 0x20;
2544
2545         rtlefuse->eeprom_thermalmeter = *(u8 *) & hwinfo[EEPROM_THERMAL_METER];
2546         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||rtlefuse->autoload_failflag )
2547         {
2548                 rtlefuse->b_apk_thermalmeterignore = true;
2549                 rtlefuse->eeprom_thermalmeter = 0x18;
2550         }
2551
2552         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2553         RT_TRACE(COMP_INIT, DBG_LOUD,
2554                  ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
2555
2556         if (rtlefuse->autoload_failflag == false) {
2557                 rtlefuse->antenna_div_cfg = (*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] & BIT(3))?true:false;
2558                 /*if (BT_1ant())
2559                         rtlefuse->antenna_div_cfg = 0;*/
2560
2561                 rtlefuse->antenna_div_type = CG_TRX_HW_ANTDIV;
2562         } else {
2563                 rtlefuse->antenna_div_cfg = 0;
2564                 rtlefuse->antenna_div_type = 0;
2565         }
2566
2567         RT_TRACE(COMP_INIT, DBG_LOUD,
2568                 ("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
2569                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type));
2570
2571         pcipriv->ledctl.bled_opendrain = true;
2572
2573         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2574                 switch (rtlefuse->eeprom_oemid) {
2575                 case RT_CID_DEFAULT:
2576                         break;
2577                 case EEPROM_CID_TOSHIBA:
2578                         rtlhal->oem_id = RT_CID_TOSHIBA;
2579                         break;
2580                 case EEPROM_CID_CCX:
2581                         rtlhal->oem_id = RT_CID_CCX;
2582                         break;
2583                 case EEPROM_CID_QMI:
2584                         rtlhal->oem_id = RT_CID_819x_QMI;
2585                         break;
2586                 case EEPROM_CID_WHQL:
2587                         break;
2588                 default:
2589                         break;
2590                 }
2591         }
2592 }
2593
2594
2595 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
2596 {
2597         struct rtl_priv *rtlpriv = rtl_priv(hw);
2598         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2599         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2600
2601         pcipriv->ledctl.bled_opendrain = true;
2602         switch (rtlhal->oem_id) {
2603         case RT_CID_819x_HP:
2604                 pcipriv->ledctl.bled_opendrain = true;
2605                 break;
2606         case RT_CID_819x_Lenovo:
2607         case RT_CID_DEFAULT:
2608         case RT_CID_TOSHIBA:
2609         case RT_CID_CCX:
2610         case RT_CID_819x_Acer:
2611         case RT_CID_WHQL:
2612         default:
2613                 break;
2614         }
2615         RT_TRACE(COMP_INIT, DBG_DMESG,
2616                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
2617 }*/
2618
2619 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
2620 {
2621         struct rtl_priv *rtlpriv = rtl_priv(hw);
2622         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2623         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2624         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2625         u8 tmp_u1b;
2626
2627         rtlhal->version = _rtl8821ae_read_chip_version(hw);
2628
2629         if (get_rf_type(rtlphy) == RF_1T1R)
2630                 rtlpriv->dm.brfpath_rxenable[0] = true;
2631         else
2632                 rtlpriv->dm.brfpath_rxenable[0] =
2633                     rtlpriv->dm.brfpath_rxenable[1] = true;
2634         RT_TRACE(COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
2635                                                 rtlhal->version));
2636
2637         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2638         if (tmp_u1b & BIT(4)) {
2639                 RT_TRACE(COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
2640                 rtlefuse->epromtype = EEPROM_93C46;
2641         } else {
2642                 RT_TRACE(COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
2643                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2644         }
2645
2646         if (tmp_u1b & BIT(5)) {
2647                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2648                 rtlefuse->autoload_failflag = false;
2649                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2650                         _rtl8812ae_read_adapter_info(hw, false);
2651                 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2652                         _rtl8821ae_read_adapter_info(hw, false);
2653         } else {
2654                         RT_TRACE(COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
2655         }
2656         /*hal_ReadRFType_8812A()*/
2657         //_rtl8821ae_hal_customized_behavior(hw);
2658 }
2659
2660 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
2661                 struct ieee80211_sta *sta)
2662 {
2663         struct rtl_priv *rtlpriv = rtl_priv(hw);
2664         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2665         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2666         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2667         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2668         u32 ratr_value;
2669         u8 ratr_index = 0;
2670         u8 b_nmode = mac->ht_enable;
2671         u8 mimo_ps = IEEE80211_SMPS_OFF;
2672         u16 shortgi_rate;
2673         u32 tmp_ratr_value;
2674         u8 b_curtxbw_40mhz = mac->bw_40;
2675         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2676                                 1 : 0;
2677         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2678                                 1 : 0;
2679         enum wireless_mode wirelessmode = mac->mode;
2680
2681         if (rtlhal->current_bandtype == BAND_ON_5G)
2682                 ratr_value = sta->supp_rates[1] << 4;
2683         else
2684                 ratr_value = sta->supp_rates[0];
2685         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2686                 ratr_value = 0xfff;
2687         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2688                         sta->ht_cap.mcs.rx_mask[0] << 12);
2689         switch (wirelessmode) {
2690         case WIRELESS_MODE_B:
2691                 if (ratr_value & 0x0000000c)
2692                         ratr_value &= 0x0000000d;
2693                 else
2694                         ratr_value &= 0x0000000f;
2695                 break;
2696         case WIRELESS_MODE_G:
2697                 ratr_value &= 0x00000FF5;
2698                 break;
2699         case WIRELESS_MODE_N_24G:
2700         case WIRELESS_MODE_N_5G:
2701                 b_nmode = 1;
2702                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2703                         ratr_value &= 0x0007F005;
2704                 } else {
2705                         u32 ratr_mask;
2706
2707                         if (get_rf_type(rtlphy) == RF_1T2R ||
2708                             get_rf_type(rtlphy) == RF_1T1R)
2709                                 ratr_mask = 0x000ff005;
2710                         else
2711                                 ratr_mask = 0x0f0ff005;
2712
2713                         ratr_value &= ratr_mask;
2714                 }
2715                 break;
2716         default:
2717                 if (rtlphy->rf_type == RF_1T2R)
2718                         ratr_value &= 0x000ff0ff;
2719                 else
2720                         ratr_value &= 0x0f0ff0ff;
2721
2722                 break;
2723         }
2724
2725         if ( (rtlpcipriv->btcoexist.bt_coexistence) &&
2726              (rtlpcipriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2727              (rtlpcipriv->btcoexist.bt_cur_state) &&
2728              (rtlpcipriv->btcoexist.bt_ant_isolation) &&
2729              ((rtlpcipriv->btcoexist.bt_service == BT_SCO)||
2730              (rtlpcipriv->btcoexist.bt_service == BT_BUSY)) )
2731                 ratr_value &= 0x0fffcfc0;
2732         else
2733                 ratr_value &= 0x0FFFFFFF;
2734
2735         if (b_nmode && ((b_curtxbw_40mhz &&
2736                          b_curshortgi_40mhz) || (!b_curtxbw_40mhz &&
2737                                                  b_curshortgi_20mhz))) {
2738
2739                 ratr_value |= 0x10000000;
2740                 tmp_ratr_value = (ratr_value >> 12);
2741
2742                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2743                         if ((1 << shortgi_rate) & tmp_ratr_value)
2744                                 break;
2745                 }
2746
2747                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2748                     (shortgi_rate << 4) | (shortgi_rate);
2749         }
2750
2751         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2752
2753         RT_TRACE(COMP_RATR, DBG_DMESG,
2754                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
2755 }
2756
2757
2758 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
2759         struct ieee80211_hw *hw, u8 rate_index,
2760         enum wireless_mode wirelessmode)
2761 {
2762         struct rtl_priv *rtlpriv = rtl_priv(hw);
2763         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2764         u8 ret = 0;
2765         switch(rate_index){
2766                 case RATR_INX_WIRELESS_NGB:
2767                         if(rtlphy->rf_type == RF_1T1R)
2768                                 ret = 1;
2769                         else
2770                                 ret = 0;
2771                         ;break;
2772                 case RATR_INX_WIRELESS_N:
2773                 case RATR_INX_WIRELESS_NG:
2774                         if(rtlphy->rf_type == RF_1T1R)
2775                                 ret = 5;
2776                         else
2777                                 ret = 4;
2778                         ;break;
2779                 case RATR_INX_WIRELESS_NB:
2780                         if(rtlphy->rf_type == RF_1T1R)
2781                                 ret = 3;
2782                         else
2783                                 ret = 2;
2784                         ;break;
2785                 case RATR_INX_WIRELESS_GB:
2786                         ret = 6;
2787                         break;
2788                 case RATR_INX_WIRELESS_G:
2789                         ret = 7;
2790                         break;
2791                 case RATR_INX_WIRELESS_B:
2792                         ret = 8;
2793                         break;
2794                 case RATR_INX_WIRELESS_MC:
2795                         if ((wirelessmode == WIRELESS_MODE_B)
2796                                 || (wirelessmode == WIRELESS_MODE_G)
2797                                 || (wirelessmode == WIRELESS_MODE_N_24G)
2798                                 || (wirelessmode == WIRELESS_MODE_AC_24G))
2799                                 ret = 6;
2800                         else
2801                                 ret = 7;
2802                 case RATR_INX_WIRELESS_AC_5N:
2803                         if(rtlphy->rf_type == RF_1T1R)
2804                                 ret = 10;
2805                         else
2806                                 ret = 9;
2807                         break;
2808                 case RATR_INX_WIRELESS_AC_24N:
2809                         if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
2810                         {
2811                                 if(rtlphy->rf_type == RF_1T1R)
2812                                         ret = 10;
2813                                 else
2814                                         ret = 9;
2815                         } else {
2816                                 if(rtlphy->rf_type == RF_1T1R)
2817                                         ret = 11;
2818                                 else
2819                                         ret = 12;
2820                         }
2821                         break;
2822                 default:
2823                         ret = 0;break;
2824         }
2825         return ret;
2826 }
2827
2828 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
2829                 struct ieee80211_sta *sta, u8 rssi_level)
2830 {
2831         struct rtl_priv *rtlpriv = rtl_priv(hw);
2832         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2833         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2834         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2835         struct rtl_sta_info * sta_entry = NULL;
2836         u32 ratr_bitmap;
2837         u8 ratr_index;
2838         u8 b_curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2839                                 ? 1 : 0;
2840         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2841                                 1 : 0;
2842         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2843                                 1 : 0;
2844         enum wireless_mode wirelessmode = 0;
2845         bool b_shortgi = false;
2846         u8 rate_mask[7];
2847         u8 macid = 0;
2848         u8 mimo_ps = IEEE80211_SMPS_OFF;
2849
2850         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2851         wirelessmode = sta_entry->wireless_mode;
2852         if (mac->opmode == NL80211_IFTYPE_STATION ||
2853                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2854                 b_curtxbw_40mhz = mac->bw_40;
2855         else if (mac->opmode == NL80211_IFTYPE_AP ||
2856                 mac->opmode == NL80211_IFTYPE_ADHOC)
2857                 macid = sta->aid + 1;
2858
2859         ratr_bitmap = sta->supp_rates[0];
2860
2861         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2862                 ratr_bitmap = 0xfff;
2863
2864         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2865                         sta->ht_cap.mcs.rx_mask[0] << 12);
2866 /*mac id owner*/
2867         switch (wirelessmode) {
2868         case WIRELESS_MODE_B:
2869                 ratr_index = RATR_INX_WIRELESS_B;
2870                 if (ratr_bitmap & 0x0000000c)
2871                         ratr_bitmap &= 0x0000000d;
2872                 else
2873                         ratr_bitmap &= 0x0000000f;
2874                 break;
2875         case WIRELESS_MODE_G:
2876                 ratr_index = RATR_INX_WIRELESS_GB;
2877
2878                 if (rssi_level == 1)
2879                         ratr_bitmap &= 0x00000f00;
2880                 else if (rssi_level == 2)
2881                         ratr_bitmap &= 0x00000ff0;
2882                 else
2883                         ratr_bitmap &= 0x00000ff5;
2884                 break;
2885         case WIRELESS_MODE_A:
2886                 ratr_index = RATR_INX_WIRELESS_G;
2887                 ratr_bitmap &= 0x00000ff0;
2888                 break;
2889         case WIRELESS_MODE_N_24G:
2890         case WIRELESS_MODE_N_5G:
2891                 if (wirelessmode == WIRELESS_MODE_N_24G)
2892                         ratr_index = RATR_INX_WIRELESS_NGB;
2893                 else
2894                         ratr_index = RATR_INX_WIRELESS_NG;
2895
2896                 if (mimo_ps == IEEE80211_SMPS_STATIC  || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
2897                         if (rssi_level == 1)
2898                                 ratr_bitmap &= 0x00070000;
2899                         else if (rssi_level == 2)
2900                                 ratr_bitmap &= 0x0007f000;
2901                         else
2902                                 ratr_bitmap &= 0x0007f005;
2903                 } else {
2904                         if ( rtlphy->rf_type == RF_1T1R) {
2905                                 if (b_curtxbw_40mhz) {
2906                                         if (rssi_level == 1)
2907                                                 ratr_bitmap &= 0x000f0000;
2908                                         else if (rssi_level == 2)
2909                                                 ratr_bitmap &= 0x000ff000;
2910                                         else
2911                                                 ratr_bitmap &= 0x000ff015;
2912                                 } else {
2913                                         if (rssi_level == 1)
2914                                                 ratr_bitmap &= 0x000f0000;
2915                                         else if (rssi_level == 2)
2916                                                 ratr_bitmap &= 0x000ff000;
2917                                         else
2918                                                 ratr_bitmap &= 0x000ff005;
2919                                 }
2920                         } else {
2921                                 if (b_curtxbw_40mhz) {
2922                                         if (rssi_level == 1)
2923                                                 ratr_bitmap &= 0x0fff0000;
2924                                         else if (rssi_level == 2)
2925                                                 ratr_bitmap &= 0x0ffff000;
2926                                         else
2927                                                 ratr_bitmap &= 0x0ffff015;
2928                                 } else {
2929                                         if (rssi_level == 1)
2930                                                 ratr_bitmap &= 0x0fff0000;
2931                                         else if (rssi_level == 2)
2932                                                 ratr_bitmap &= 0x0ffff000;
2933                                         else
2934                                                 ratr_bitmap &= 0x0ffff005;
2935                                 }
2936                         }
2937                 }
2938                 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
2939                     (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
2940
2941                         if (macid == 0)
2942                                 b_shortgi = true;
2943                         else if (macid == 1)
2944                                 b_shortgi = false;
2945                 }
2946                 break;
2947
2948         case WIRELESS_MODE_AC_24G:
2949                 ratr_index = RATR_INX_WIRELESS_AC_24N;
2950                 if(rssi_level == 1)
2951                         ratr_bitmap &= 0xfc3f0000;
2952                 else if(rssi_level == 2)
2953                         ratr_bitmap &= 0xfffff000;
2954                 else
2955                         ratr_bitmap &= 0xffffffff;
2956                 break;
2957
2958         case WIRELESS_MODE_AC_5G:
2959                 ratr_index = RATR_INX_WIRELESS_AC_5N;
2960
2961                 if (rtlphy->rf_type == RF_1T1R)
2962                 {
2963                         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2964                         {
2965                                 if(rssi_level == 1)                             /*add by Gary for ac-series*/
2966                                         ratr_bitmap &= 0x003f8000;
2967                                 else if (rssi_level == 2)
2968                                         ratr_bitmap &= 0x003ff000;
2969                                 else
2970                                         ratr_bitmap &= 0x003ff010;
2971                         }
2972                         else
2973                                 ratr_bitmap &= 0x000ff010;
2974                 }
2975                 else
2976                 {
2977                         if(rssi_level == 1)                             /* add by Gary for ac-series*/
2978                                 ratr_bitmap &= 0xfe3f8000;       /*VHT 2SS MCS3~9*/
2979                         else if (rssi_level == 2)
2980                                 ratr_bitmap &= 0xfffff000;       /*VHT 2SS MCS0~9*/
2981                         else
2982                                 ratr_bitmap &= 0xfffff010;       /*All*/
2983                 }
2984                 break;
2985
2986         default:
2987                 ratr_index = RATR_INX_WIRELESS_NGB;
2988
2989                 if (rtlphy->rf_type == RF_1T2R)
2990                         ratr_bitmap &= 0x000ff0ff;
2991                 else
2992                         ratr_bitmap &= 0x0f0ff0ff;
2993                 break;
2994
2995         }
2996
2997         sta_entry->ratr_index = ratr_index;
2998
2999         RT_TRACE(COMP_RATR, DBG_DMESG,
3000                  ("ratr_bitmap :%x\n", ratr_bitmap));
3001         *(u32 *) & rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3002                                        (ratr_index << 28));
3003         rate_mask[0] = macid;
3004         rate_mask[1] = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode) | (b_shortgi ? 0x80 : 0x00);
3005         rate_mask[2] = b_curtxbw_40mhz;
3006         /* if (prox_priv->proxim_modeinfo->power_output > 0)
3007                 rate_mask[2] |= BIT(6); */
3008
3009         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3010         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >>8);
3011         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3012         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3013
3014         RT_TRACE(COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
3015                                                  "ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3016                                                  ratr_index, ratr_bitmap,
3017                                                  rate_mask[0], rate_mask[1],
3018                                                  rate_mask[2], rate_mask[3],
3019                                                  rate_mask[4], rate_mask[5],
3020                                                  rate_mask[6]));
3021         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3022         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3023 }
3024
3025 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3026                 struct ieee80211_sta *sta, u8 rssi_level)
3027 {
3028         struct rtl_priv *rtlpriv = rtl_priv(hw);
3029         if (rtlpriv->dm.b_useramask)
3030                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3031         else
3032                 /*RT_TRACE(COMP_RATR,DBG_LOUD,("rtl8821ae_update_hal_rate_tbl(): Error! 8821ae FW RA Only"));*/
3033                 rtl8821ae_update_hal_rate_table(hw, sta);
3034 }
3035
3036 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3037 {
3038         struct rtl_priv *rtlpriv = rtl_priv(hw);
3039         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3040         u16 sifs_timer;
3041
3042         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3043                                       (u8 *) & mac->slot_time);
3044         if (!mac->ht_enable)
3045                 sifs_timer = 0x0a0a;
3046         else
3047                 sifs_timer = 0x0e0e;
3048         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *) & sifs_timer);
3049 }
3050
3051 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
3052 {
3053         struct rtl_priv *rtlpriv = rtl_priv(hw);
3054         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3055         struct rtl_phy *rtlphy = &(rtlpriv->phy);
3056         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3057         u8 u1tmp = 0;
3058         bool b_actuallyset = false;
3059
3060         if (rtlpriv->rtlhal.being_init_adapter)
3061                 return false;
3062
3063         if (ppsc->b_swrf_processing)
3064                 return false;
3065
3066         spin_lock(&rtlpriv->locks.rf_ps_lock);
3067         if (ppsc->rfchange_inprogress) {
3068                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3069                 return false;
3070         } else {
3071                 ppsc->rfchange_inprogress = true;
3072                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3073         }
3074
3075         cur_rfstate = ppsc->rfpwr_state;
3076
3077         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3078                                         rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3079
3080         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3081
3082         if (rtlphy->polarity_ctl) {
3083                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3084         } else {
3085                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3086         }
3087
3088         if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
3089                 RT_TRACE(COMP_RF, DBG_DMESG,
3090                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
3091
3092                 e_rfpowerstate_toset = ERFON;
3093                 ppsc->b_hwradiooff = false;
3094                 b_actuallyset = true;
3095         } else if ((ppsc->b_hwradiooff == false)
3096                    && (e_rfpowerstate_toset == ERFOFF)) {
3097                 RT_TRACE(COMP_RF, DBG_DMESG,
3098                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
3099
3100                 e_rfpowerstate_toset = ERFOFF;
3101                 ppsc->b_hwradiooff = true;
3102                 b_actuallyset = true;
3103         }
3104
3105         if (b_actuallyset) {
3106                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3107                 ppsc->rfchange_inprogress = false;
3108                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3109         } else {
3110                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3111                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3112
3113                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3114                 ppsc->rfchange_inprogress = false;
3115                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3116         }
3117
3118         *valid = 1;
3119         return !ppsc->b_hwradiooff;
3120
3121 }
3122
3123 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3124                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3125                      bool is_wepkey, bool clear_all)
3126 {
3127         struct rtl_priv *rtlpriv = rtl_priv(hw);
3128         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3129         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3130         u8 *macaddr = p_macaddr;
3131         u32 entry_id = 0;
3132         bool is_pairwise = false;
3133
3134         static u8 cam_const_addr[4][6] = {
3135                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3136                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3137                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3138                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3139         };
3140         static u8 cam_const_broad[] = {
3141                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3142         };
3143
3144         if (clear_all) {
3145                 u8 idx = 0;
3146                 u8 cam_offset = 0;
3147                 u8 clear_number = 5;
3148
3149                 RT_TRACE(COMP_SEC, DBG_DMESG, ("clear_all\n"));
3150
3151                 for (idx = 0; idx < clear_number; idx++) {
3152                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3153                         rtl_cam_empty_entry(hw, cam_offset + idx);
3154
3155                         if (idx < 5) {
3156                                 memset(rtlpriv->sec.key_buf[idx], 0,
3157                                        MAX_KEY_LEN);
3158                                 rtlpriv->sec.key_len[idx] = 0;
3159                         }
3160                 }
3161
3162         } else {
3163                 switch (enc_algo) {
3164                 case WEP40_ENCRYPTION:
3165                         enc_algo = CAM_WEP40;
3166                         break;
3167                 case WEP104_ENCRYPTION:
3168                         enc_algo = CAM_WEP104;
3169                         break;
3170                 case TKIP_ENCRYPTION:
3171                         enc_algo = CAM_TKIP;
3172                         break;
3173                 case AESCCMP_ENCRYPTION:
3174                         enc_algo = CAM_AES;
3175                         break;
3176                 default:
3177                         RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case "
3178                                                                 "not process \n"));
3179                         enc_algo = CAM_TKIP;
3180                         break;
3181                 }
3182
3183                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3184                         macaddr = cam_const_addr[key_index];
3185                         entry_id = key_index;
3186                 } else {
3187                         if (is_group) {
3188                                 macaddr = cam_const_broad;
3189                                 entry_id = key_index;
3190                         } else {
3191                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3192                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3193                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3194                                                 RT_TRACE(COMP_SEC, DBG_EMERG,
3195                                                                 ("Can not find free hw security cam entry\n"));
3196                                                 return;
3197                                         }
3198                                 } else {
3199                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3200                                 }
3201
3202                                 key_index = PAIRWISE_KEYIDX;
3203                                 is_pairwise = true;
3204                         }
3205                 }
3206
3207                 if (rtlpriv->sec.key_len[key_index] == 0) {
3208                         RT_TRACE(COMP_SEC, DBG_DMESG,
3209                                  ("delete one entry, entry_id is %d\n",entry_id));
3210                         if (mac->opmode == NL80211_IFTYPE_AP)
3211                                 rtl_cam_del_entry(hw, p_macaddr);
3212                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3213                 } else {
3214                         RT_TRACE(COMP_SEC, DBG_DMESG, ("add one entry\n"));
3215                         if (is_pairwise) {
3216                                 RT_TRACE(COMP_SEC, DBG_DMESG, ("set Pairwiase key\n"));
3217
3218                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3219                                                       entry_id, enc_algo,
3220                                                       CAM_CONFIG_NO_USEDK,
3221                                                       rtlpriv->sec.key_buf[key_index]);
3222                         } else {
3223                                 RT_TRACE(COMP_SEC, DBG_DMESG, ("set group key\n"));
3224
3225                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3226                                         rtl_cam_add_one_entry(hw,
3227                                                         rtlefuse->dev_addr,
3228                                                         PAIRWISE_KEYIDX,
3229                                                         CAM_PAIRWISE_KEY_POSITION,
3230                                                         enc_algo,
3231                                                         CAM_CONFIG_NO_USEDK,
3232                                                         rtlpriv->sec.key_buf
3233                                                         [entry_id]);
3234                                 }
3235
3236                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3237                                                 entry_id, enc_algo,
3238                                                 CAM_CONFIG_NO_USEDK,
3239                                                 rtlpriv->sec.key_buf[entry_id]);
3240                         }
3241
3242                 }
3243         }
3244 }
3245
3246
3247 void rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3248                                               bool auto_load_fail, u8 *hwinfo)
3249 {
3250         struct rtl_priv *rtlpriv = rtl_priv(hw);
3251         u8 value;
3252
3253         if (!auto_load_fail) {
3254                 value = *(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION];
3255                 if (((value & 0xe0) >> 5) == 0x1)
3256                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3257                 else
3258                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3259                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3260
3261                 value = hwinfo[EEPROM_RF_BT_SETTING];
3262                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3263         } else {
3264                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3265                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3266                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3267         }
3268         /*move BT_InitHalVars() to init_sw_vars*/
3269 }
3270
3271 void rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3272                                               bool auto_load_fail, u8 *hwinfo)
3273 {
3274         struct rtl_priv *rtlpriv = rtl_priv(hw);
3275         u8 value;
3276         u32 tmpu_32;
3277
3278         if (!auto_load_fail) {
3279                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3280                 if(tmpu_32 & BIT(18))
3281                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3282                 else
3283                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3284                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3285
3286                 value = hwinfo[EEPROM_RF_BT_SETTING];
3287                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3288         } else {
3289                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3290                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3291                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3292         }
3293         /*move BT_InitHalVars() to init_sw_vars*/
3294 }
3295
3296 void rtl8821ae_bt_reg_init(struct ieee80211_hw* hw)
3297 {
3298         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
3299
3300         /* 0:Low, 1:High, 2:From Efuse. */
3301         rtlpcipriv->btcoexist.b_reg_bt_iso = 2;
3302         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3303         rtlpcipriv->btcoexist.b_reg_bt_sco= 3;
3304         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3305         rtlpcipriv->btcoexist.b_reg_bt_sco= 0;
3306 }
3307
3308
3309 void rtl8821ae_bt_hw_init(struct ieee80211_hw* hw)
3310 {
3311         struct rtl_priv *rtlpriv = rtl_priv(hw);
3312
3313         if (rtlpriv->cfg->ops->get_btc_status()){
3314                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3315         }
3316 }
3317
3318 void rtl8821ae_suspend(struct ieee80211_hw *hw)
3319 {
3320 }
3321
3322 void rtl8821ae_resume(struct ieee80211_hw *hw)
3323 {
3324 }
3325
3326 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
3327 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3328         bool allow_all_da, bool write_into_reg)
3329 {
3330         struct rtl_priv *rtlpriv = rtl_priv(hw);
3331         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3332
3333         if (allow_all_da) /* Set BIT0 */
3334                 rtlpci->receive_config |= RCR_AAP;
3335         else /* Clear BIT0 */
3336                 rtlpci->receive_config &= ~RCR_AAP;
3337
3338         if(write_into_reg)
3339                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
3340
3341
3342         RT_TRACE(COMP_TURBO | COMP_INIT, DBG_LOUD,
3343                 ("receive_config=0x%08X, write_into_reg=%d\n",
3344                 rtlpci->receive_config, write_into_reg ));
3345 }
3346