drivers/staging/rtl8821ae/rtl8821ae/dm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL8821AE_DM_H__
  31 #define __RTL8821AE_DM_H__
  32
  33 #define MAIN_ANT        0
  34 #define AUX_ANT 1
  35 #define MAIN_ANT_CG_TRX 1
  36 #define AUX_ANT_CG_TRX  0
  37 #define MAIN_ANT_CGCS_RX        0
  38 #define AUX_ANT_CGCS_RX 1
  39
  40 #define TXSCALE_TABLE_SIZE 37
  41
  42 /*RF REG LIST*/
  43 #define DM_REG_RF_MODE_11N                              0x00
  44 #define DM_REG_RF_0B_11N                                0x0B
  45 #define DM_REG_CHNBW_11N                                0x18
  46 #define DM_REG_T_METER_11N                              0x24
  47 #define DM_REG_RF_25_11N                                0x25
  48 #define DM_REG_RF_26_11N                                0x26
  49 #define DM_REG_RF_27_11N                                0x27
  50 #define DM_REG_RF_2B_11N                                0x2B
  51 #define DM_REG_RF_2C_11N                                0x2C
  52 #define DM_REG_RXRF_A3_11N                              0x3C
  53 #define DM_REG_T_METER_92D_11N                  0x42
  54 #define DM_REG_T_METER_88E_11N                  0x42
  55
  56
  57
  58 /*BB REG LIST*/
  59 /*PAGE 8 */
  60 #define DM_REG_BB_CTRL_11N                              0x800
  61 #define DM_REG_RF_PIN_11N                               0x804
  62 #define DM_REG_PSD_CTRL_11N                             0x808
  63 #define DM_REG_TX_ANT_CTRL_11N                  0x80C
  64 #define DM_REG_BB_PWR_SAV5_11N                  0x818
  65 #define DM_REG_CCK_RPT_FORMAT_11N               0x824
  66 #define DM_REG_RX_DEFUALT_A_11N         0x858
  67 #define DM_REG_RX_DEFUALT_B_11N         0x85A
  68 #define DM_REG_BB_PWR_SAV3_11N                  0x85C
  69 #define DM_REG_ANTSEL_CTRL_11N                  0x860
  70 #define DM_REG_RX_ANT_CTRL_11N                  0x864
  71 #define DM_REG_PIN_CTRL_11N                             0x870
  72 #define DM_REG_BB_PWR_SAV1_11N                  0x874
  73 #define DM_REG_ANTSEL_PATH_11N                  0x878
  74 #define DM_REG_BB_3WIRE_11N                     0x88C
  75 #define DM_REG_SC_CNT_11N                               0x8C4
  76 #define DM_REG_PSD_DATA_11N                     0x8B4
  77 /*PAGE 9*/
  78 #define DM_REG_ANT_MAPPING1_11N         0x914
  79 #define DM_REG_ANT_MAPPING2_11N         0x918
  80 /*PAGE A*/
  81 #define DM_REG_CCK_ANTDIV_PARA1_11N     0xA00
  82 #define DM_REG_CCK_CCA_11N                      0xA0A
  83 #define DM_REG_CCK_CCA_11AC                     0xA0A
  84 #define DM_REG_CCK_ANTDIV_PARA2_11N     0xA0C
  85 #define DM_REG_CCK_ANTDIV_PARA3_11N     0xA10
  86 #define DM_REG_CCK_ANTDIV_PARA4_11N     0xA14
  87 #define DM_REG_CCK_FILTER_PARA1_11N     0xA22
  88 #define DM_REG_CCK_FILTER_PARA2_11N     0xA23
  89 #define DM_REG_CCK_FILTER_PARA3_11N     0xA24
  90 #define DM_REG_CCK_FILTER_PARA4_11N     0xA25
  91 #define DM_REG_CCK_FILTER_PARA5_11N     0xA26
  92 #define DM_REG_CCK_FILTER_PARA6_11N     0xA27
  93 #define DM_REG_CCK_FILTER_PARA7_11N     0xA28
  94 #define DM_REG_CCK_FILTER_PARA8_11N     0xA29
  95 #define DM_REG_CCK_FA_RST_11N                   0xA2C
  96 #define DM_REG_CCK_FA_MSB_11N                   0xA58
  97 #define DM_REG_CCK_FA_LSB_11N                   0xA5C
  98 #define DM_REG_CCK_CCA_CNT_11N                  0xA60
  99 #define DM_REG_BB_PWR_SAV4_11N                  0xA74
 100 /*PAGE B */
 101 #define DM_REG_LNA_SWITCH_11N                   0xB2C
 102 #define DM_REG_PATH_SWITCH_11N                  0xB30
 103 #define DM_REG_RSSI_CTRL_11N                    0xB38
 104 #define DM_REG_CONFIG_ANTA_11N                  0xB68
 105 #define DM_REG_RSSI_BT_11N                              0xB9C
 106 /*PAGE C */
 107 #define DM_REG_OFDM_FA_HOLDC_11N                0xC00
 108 #define DM_REG_RX_PATH_11N                              0xC04
 109 #define DM_REG_TRMUX_11N                                0xC08
 110 #define DM_REG_OFDM_FA_RSTC_11N         0xC0C
 111 #define DM_REG_RXIQI_MATRIX_11N         0xC14
 112 #define DM_REG_TXIQK_MATRIX_LSB1_11N    0xC4C
 113 #define DM_REG_IGI_A_11N                                0xC50
 114 #define DM_REG_IGI_A_11AC                               0xC50
 115 #define DM_REG_ANTDIV_PARA2_11N         0xC54
 116 #define DM_REG_IGI_B_11N                                        0xC58
 117 #define DM_REG_IGI_B_11AC                                       0xE50
 118 #define DM_REG_ANTDIV_PARA3_11N         0xC5C
 119 #define DM_REG_BB_PWR_SAV2_11N                  0xC70
 120 #define DM_REG_RX_OFF_11N                               0xC7C
 121 #define DM_REG_TXIQK_MATRIXA_11N                0xC80
 122 #define DM_REG_TXIQK_MATRIXB_11N                0xC88
 123 #define DM_REG_TXIQK_MATRIXA_LSB2_11N   0xC94
 124 #define DM_REG_TXIQK_MATRIXB_LSB2_11N   0xC9C
 125 #define DM_REG_RXIQK_MATRIX_LSB_11N     0xCA0
 126 #define DM_REG_ANTDIV_PARA1_11N         0xCA4
 127 #define DM_REG_OFDM_FA_TYPE1_11N                0xCF0
 128 /*PAGE D */
 129 #define DM_REG_OFDM_FA_RSTD_11N         0xD00
 130 #define DM_REG_OFDM_FA_TYPE2_11N                0xDA0
 131 #define DM_REG_OFDM_FA_TYPE3_11N                0xDA4
 132 #define DM_REG_OFDM_FA_TYPE4_11N                0xDA8
 133 /*PAGE E */
 134 #define DM_REG_TXAGC_A_6_18_11N         0xE00
 135 #define DM_REG_TXAGC_A_24_54_11N                0xE04
 136 #define DM_REG_TXAGC_A_1_MCS32_11N      0xE08
 137 #define DM_REG_TXAGC_A_MCS0_3_11N               0xE10
 138 #define DM_REG_TXAGC_A_MCS4_7_11N               0xE14
 139 #define DM_REG_TXAGC_A_MCS8_11_11N      0xE18
 140 #define DM_REG_TXAGC_A_MCS12_15_11N     0xE1C
 141 #define DM_REG_FPGA0_IQK_11N                    0xE28
 142 #define DM_REG_TXIQK_TONE_A_11N         0xE30
 143 #define DM_REG_RXIQK_TONE_A_11N         0xE34
 144 #define DM_REG_TXIQK_PI_A_11N                   0xE38
 145 #define DM_REG_RXIQK_PI_A_11N                   0xE3C
 146 #define DM_REG_TXIQK_11N                                0xE40
 147 #define DM_REG_RXIQK_11N                                0xE44
 148 #define DM_REG_IQK_AGC_PTS_11N                  0xE48
 149 #define DM_REG_IQK_AGC_RSP_11N                  0xE4C
 150 #define DM_REG_BLUETOOTH_11N                    0xE6C
 151 #define DM_REG_RX_WAIT_CCA_11N                  0xE70
 152 #define DM_REG_TX_CCK_RFON_11N                  0xE74
 153 #define DM_REG_TX_CCK_BBON_11N                  0xE78
 154 #define DM_REG_OFDM_RFON_11N                    0xE7C
 155 #define DM_REG_OFDM_BBON_11N                    0xE80
 156 #define DM_REG_TX2RX_11N                                0xE84
 157 #define DM_REG_TX2TX_11N                                0xE88
 158 #define DM_REG_RX_CCK_11N                               0xE8C
 159 #define DM_REG_RX_OFDM_11N                              0xED0
 160 #define DM_REG_RX_WAIT_RIFS_11N         0xED4
 161 #define DM_REG_RX2RX_11N                                0xED8
 162 #define DM_REG_STANDBY_11N                              0xEDC
 163 #define DM_REG_SLEEP_11N                                0xEE0
 164 #define DM_REG_PMPD_ANAEN_11N                   0xEEC
 165
 166
 167 /*MAC REG LIST*/
 168 #define DM_REG_BB_RST_11N                               0x02
 169 #define DM_REG_ANTSEL_PIN_11N                   0x4C
 170 #define DM_REG_EARLY_MODE_11N                   0x4D0
 171 #define DM_REG_RSSI_MONITOR_11N         0x4FE
 172 #define DM_REG_EDCA_VO_11N                              0x500
 173 #define DM_REG_EDCA_VI_11N                              0x504
 174 #define DM_REG_EDCA_BE_11N                              0x508
 175 #define DM_REG_EDCA_BK_11N                              0x50C
 176 #define DM_REG_TXPAUSE_11N                              0x522
 177 #define DM_REG_RESP_TX_11N                              0x6D8
 178 #define DM_REG_ANT_TRAIN_PARA1_11N      0x7b0
 179 #define DM_REG_ANT_TRAIN_PARA2_11N      0x7b4
 180
 181
 182 /*DIG Related*/
 183 #define DM_BIT_IGI_11N                                  0x0000007F
 184 #define DM_BIT_IGI_11AC                                 0xFFFFFFFF
 185
 186
 187
 188 #define HAL_DM_DIG_DISABLE                      BIT(0)
 189 #define HAL_DM_HIPWR_DISABLE            BIT(1)
 190
 191 #define OFDM_TABLE_LENGTH                       43
 192 #define CCK_TABLE_LENGTH                        33
 193
 194 #define OFDM_TABLE_SIZE                         37
 195 #define CCK_TABLE_SIZE                          33
 196
 197 #define BW_AUTO_SWITCH_HIGH_LOW         25
 198 #define BW_AUTO_SWITCH_LOW_HIGH         30
 199
 200 #define DM_DIG_THRESH_HIGH                      40
 201 #define DM_DIG_THRESH_LOW                       35
 202
 203 #define DM_FALSEALARM_THRESH_LOW        400
 204 #define DM_FALSEALARM_THRESH_HIGH       1000
 205
 206 #define DM_DIG_MAX                                      0x3e
 207 #define DM_DIG_MIN                                      0x1e
 208
 209 #define DM_DIG_MAX_AP                           0x32
 210 #define DM_DIG_MIN_AP                           0x20
 211
 212 #define DM_DIG_FA_UPPER                         0x3e
 213 #define DM_DIG_FA_LOWER                         0x1e
 214 #define DM_DIG_FA_TH0                           0x200
 215 #define DM_DIG_FA_TH1                           0x300
 216 #define DM_DIG_FA_TH2                           0x400
 217
 218 #define DM_DIG_BACKOFF_MAX                      12
 219 #define DM_DIG_BACKOFF_MIN                      -4
 220 #define DM_DIG_BACKOFF_DEFAULT          10
 221
 222 #define RXPATHSELECTION_SS_TH_lOW       30
 223 #define RXPATHSELECTION_DIFF_TH         18
 224
 225 #define DM_RATR_STA_INIT                        0
 226 #define DM_RATR_STA_HIGH                        1
 227 #define DM_RATR_STA_MIDDLE                      2
 228 #define DM_RATR_STA_LOW                         3
 229
 230 #define CTS2SELF_THVAL                          30
 231 #define REGC38_TH                                       20
 232
 233 #define WAIOTTHVal                                      25
 234
 235 #define TXHIGHPWRLEVEL_NORMAL           0
 236 #define TXHIGHPWRLEVEL_LEVEL1           1
 237 #define TXHIGHPWRLEVEL_LEVEL2           2
 238 #define TXHIGHPWRLEVEL_BT1                      3
 239 #define TXHIGHPWRLEVEL_BT2                      4
 240
 241 #define DM_TYPE_BYFW                            0
 242 #define DM_TYPE_BYDRIVER                        1
 243
 244 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
 245 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
 246 #define TXPWRTRACK_MAX_IDX 6
 247
 248 /* Dynamic ATC switch */
 249 #define ATC_STATUS_OFF                          0x0                     /* enable */
 250 #define ATC_STATUS_ON                           0x1                     /* disable */
 251 #define CFO_THRESHOLD_XTAL                      10                      /* kHz */
 252 #define CFO_THRESHOLD_ATC                       80                      /* kHz */
 253
 254 #define AVG_THERMAL_NUM_8812A   4
 255 #define TXPWR_TRACK_TABLE_SIZE  30
 256 #define MAX_PATH_NUM_8812A              2
 257 #define MAX_PATH_NUM_8821A              1
 258
 259
 260 struct ps_t {
 261         u8 pre_ccastate;
 262         u8 cur_ccasate;
 263         u8 pre_rfstate;
 264         u8 cur_rfstate;
 265         u8 initialize;
 266         long rssi_val_min;
 267
 268 };
 269
 270 struct dig_t {
 271         u8 dig_enable_flag;
 272         u8 dig_ext_port_stage;
 273         u32 rssi_lowthresh;
 274         u32 rssi_highthresh;
 275
 276         u32 fa_lowthresh;
 277         u32 fa_highthresh;
 278
 279         u8 cursta_connectctate;
 280         u8 presta_connectstate;
 281         u8 curmultista_connectstate;
 282
 283         u8 pre_igvalue;
 284         u8 cur_igvalue;
 285         u8 bt30_cur_igi;
 286         u8 backup_igvalue;
 287         u8 stop_dig;
 288
 289         char backoff_val;
 290         char backoff_val_range_max;
 291         char backoff_val_range_min;
 292         u8 rx_gain_range_max;
 293         u8 rx_gain_range_min;
 294         u8 rssi_val_min;
 295
 296         u8 pre_cck_cca_thres;
 297         u8 cur_cck_cca_thres;
 298         u8 pre_cck_pd_state;
 299         u8 cur_cck_pd_state;
 300
 301         u8 large_fa_hit;
 302         u8 forbidden_igi;
 303         u32 recover_cnt;
 304
 305         u8 dig_dynamic_min_0;
 306         u8 dig_dynamic_min_1;
 307         bool b_media_connect_0;
 308         bool b_media_connect_1;
 309
 310         u32 antdiv_rssi_max;
 311         u32 rssi_max;
 312 };
 313
 314
 315 enum FAT_STATE {
 316         FAT_NORMAL_STATE        = 0,
 317         FAT_TRAINING_STATE = 1,
 318 };
 319
 320 enum tag_dynamic_init_gain_operation_type_definition {
 321         DIG_TYPE_THRESH_HIGH = 0,
 322         DIG_TYPE_THRESH_LOW = 1,
 323         DIG_TYPE_BACKOFF = 2,
 324         DIG_TYPE_RX_GAIN_MIN = 3,
 325         DIG_TYPE_RX_GAIN_MAX = 4,
 326         DIG_TYPE_ENABLE = 5,
 327         DIG_TYPE_DISABLE = 6,
 328         DIG_OP_TYPE_MAX
 329 };
 330
 331 enum tag_cck_packet_detection_threshold_type_definition {
 332         CCK_PD_STAGE_LowRssi = 0,
 333         CCK_PD_STAGE_HighRssi = 1,
 334         CCK_FA_STAGE_Low = 2,
 335         CCK_FA_STAGE_High = 3,
 336         CCK_PD_STAGE_MAX = 4,
 337 };
 338
 339 enum dm_1r_cca_e {
 340         CCA_1R = 0,
 341         CCA_2R = 1,
 342         CCA_MAX = 2,
 343 };
 344
 345 enum dm_rf_e {
 346         RF_SAVE = 0,
 347         RF_NORMAL = 1,
 348         RF_MAX = 2,
 349 };
 350
 351 enum dm_sw_ant_switch_e {
 352         ANS_ANTENNA_B = 1,
 353         ANS_ANTENNA_A = 2,
 354         ANS_ANTENNA_MAX = 3,
 355 };
 356
 357 enum dm_dig_ext_port_alg_e {
 358         DIG_EXT_PORT_STAGE_0 = 0,
 359         DIG_EXT_PORT_STAGE_1 = 1,
 360         DIG_EXT_PORT_STAGE_2 = 2,
 361         DIG_EXT_PORT_STAGE_3 = 3,
 362         DIG_EXT_PORT_STAGE_MAX = 4,
 363 };
 364
 365 enum dm_dig_connect_e {
 366         DIG_STA_DISCONNECT = 0,
 367         DIG_STA_CONNECT = 1,
 368         DIG_STA_BEFORE_CONNECT = 2,
 369         DIG_MULTISTA_DISCONNECT = 3,
 370         DIG_MULTISTA_CONNECT = 4,
 371         DIG_CONNECT_MAX
 372 };
 373
 374 enum pwr_track_control_method {
 375         BBSWING,
 376         TXAGC,
 377         MIX_MODE
 378 };
 379
 380 #define BT_RSSI_STATE_NORMAL_POWER      BIT_OFFSET_LEN_MASK_32(0, 1)
 381 #define BT_RSSI_STATE_AMDPU_OFF         BIT_OFFSET_LEN_MASK_32(1, 1)
 382 #define BT_RSSI_STATE_SPECIAL_LOW       BIT_OFFSET_LEN_MASK_32(2, 1)
 383 #define BT_RSSI_STATE_BG_EDCA_LOW       BIT_OFFSET_LEN_MASK_32(3, 1)
 384 #define BT_RSSI_STATE_TXPOWER_LOW       BIT_OFFSET_LEN_MASK_32(4, 1)
 385 #define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
 386         (((struct rtl_priv *)(_priv))->mac80211.opmode == NL80211_IFTYPE_ADHOC)?  \
 387         (((struct rtl_priv *)(_priv))->dm.entry_min_undecoratedsmoothed_pwdb):  \
 388         (((struct rtl_priv *)(_priv))->dm.undecorated_smoothed_pwdb)
 389
 390 extern struct dig_t dm_digtable;
 391 void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
 392                                                                                                    u8 *pdesc, u32 mac_id);
 393 void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,
 394                                                                                           u8 antsel_tr_mux, u32 mac_id,
 395                                                                                           u32 rx_pwdb_all);
 396 void rtl8821ae_dm_fast_antenna_trainning_callback(unsigned long data);
 397 void rtl8821ae_dm_init(struct ieee80211_hw *hw);
 398 void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);
 399 void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
 400 void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
 401 void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
 402 void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
 403 void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
 404                                                                                                    u8 type,u8 *pdirection,
 405                                                                                                    u32 *poutwrite_val);
 406 void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);
 407 void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);
 408 void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
 409 void rtl8812ae_dm_path_diversity(struct ieee80211_hw *hw);
 410 void rtl8812ae_dm_path_diversity_init(struct ieee80211_hw *hw);
 411 void rtl8812ae_dm_path_statistics(struct ieee80211_hw *hw,
 412         u32 rssi_a, u32 rssi_b);
 413 void rtl812ae_dm_set_txpath_by_txinfo(struct ieee80211_hw *hw,
 414         u8 *pdesc);
 415 void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
 416                                                                                                 enum pwr_track_control_method method,
 417                                                                                                 u8 rf_path,
 418                                                                                                 u8 channel_mapped_index);
 419 void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
 420         enum pwr_track_control_method method, u8 rf_path, u8 channel_mapped_index);
 421
 422 void rtl8812ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);
 423 u8 rtl8812ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);
 424 void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
 425 void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
 426 #endif