1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
16 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
22 Implement HW Power sequence configuration CMD handling routine for
27 ---------- --------------- -------------------------------
28 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
29 2011-07-07 Roger Create.
32 #include <HalPwrSeqCmd.h>
33 #include <usb_ops_linux.h>
37 /* This routine deal with the Power Configuration CMDs parsing
38 for RTL8723/RTL8188E Series IC. */
41 /* We should follow specific format which was released from
44 /* 2011.07.07, added by Roger. */
46 u8 HalPwrSeqCmdParsing23a(struct rtw_adapter *padapter, u8 CutVersion,
47 u8 FabVersion, u8 InterfaceType,
48 struct wlan_pwr_cfg PwrSeqCmd[])
50 struct wlan_pwr_cfg PwrCfgCmd = { 0 };
51 u8 bPollingBit = false;
55 u32 pollingCount = 0; /* polling autoload done. */
56 u32 maxPollingCnt = 5000;
59 PwrCfgCmd = PwrSeqCmd[AryIdx];
61 RT_TRACE(_module_hal_init_c_, _drv_info_,
62 ("HalPwrSeqCmdParsing23a: offset(%#x) cut_msk(%#x) "
63 "fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) "
64 "msk(%#x) value(%#x)\n",
65 GET_PWR_CFG_OFFSET(PwrCfgCmd),
66 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
67 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
68 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
69 GET_PWR_CFG_BASE(PwrCfgCmd),
70 GET_PWR_CFG_CMD(PwrCfgCmd),
71 GET_PWR_CFG_MASK(PwrCfgCmd),
72 GET_PWR_CFG_VALUE(PwrCfgCmd)));
74 /* 2 Only Handle the command whose FAB, CUT, and Interface are
76 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
77 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
78 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
79 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
81 RT_TRACE(_module_hal_init_c_, _drv_info_,
82 ("HalPwrSeqCmdParsing23a: "
87 RT_TRACE(_module_hal_init_c_, _drv_info_,
88 ("HalPwrSeqCmdParsing23a: "
90 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
92 /* Read the value from system register */
93 value = rtl8723au_read8(padapter, offset);
95 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
96 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) &
97 GET_PWR_CFG_MASK(PwrCfgCmd));
99 /* Write the value back to sytem register */
100 rtl8723au_write8(padapter, offset, value);
103 case PWR_CMD_POLLING:
104 RT_TRACE(_module_hal_init_c_, _drv_info_,
105 ("HalPwrSeqCmdParsing23a: "
106 "PWR_CMD_POLLING\n"));
109 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
111 value = rtl8723au_read8(padapter,
114 value &= GET_PWR_CFG_MASK(PwrCfgCmd);
116 (GET_PWR_CFG_VALUE(PwrCfgCmd) &
117 GET_PWR_CFG_MASK(PwrCfgCmd)))
122 if (pollingCount++ > maxPollingCnt) {
123 DBG_8723A("Fail to polling "
128 } while (!bPollingBit);
133 RT_TRACE(_module_hal_init_c_, _drv_info_,
134 ("HalPwrSeqCmdParsing23a: "
136 if (GET_PWR_CFG_VALUE(PwrCfgCmd) ==
138 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
140 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd) *
145 /* When this command is parsed, end
147 RT_TRACE(_module_hal_init_c_, _drv_info_,
148 ("HalPwrSeqCmdParsing23a: "
154 RT_TRACE(_module_hal_init_c_, _drv_err_,
155 ("HalPwrSeqCmdParsing23a: "
161 AryIdx++; /* Add Array Index */