drivers/staging/rtl8192u/r8190_rtl8256.c

   1 /*
   2  * This is part of the rtl8192 driver
   3  * released under the GPL (See file COPYING for details).
   4  *
   5  * This files contains programming code for the rtl8256
   6  * radio frontend.
   7  *
   8  * *Many* thanks to Realtek Corp. for their great support!
   9  */
  10
  11 #include "r8192U.h"
  12 #include "r8192U_hw.h"
  13 #include "r819xU_phyreg.h"
  14 #include "r819xU_phy.h"
  15 #include "r8190_rtl8256.h"
  16
  17 /*--------------------------------------------------------------------------
  18  * Overview:    set RF band width (20M or 40M)
  19  * Input:       struct net_device*      dev
  20  *              WIRELESS_BANDWIDTH_E    Bandwidth       //20M or 40M
  21  * Output:      NONE
  22  * Return:      NONE
  23  * Note:        8226 support both 20M  and 40 MHz
  24  *--------------------------------------------------------------------------
  25  */
  26 void PHY_SetRF8256Bandwidth(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth)
  27 {
  28         u8      eRFPath;
  29         struct r8192_priv *priv = ieee80211_priv(dev);
  30
  31         /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath;
  32          *  eRFPath++)
  33          */
  34         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
  35                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  36                         continue;
  37
  38                 switch (Bandwidth) {
  39                 case HT_CHANNEL_WIDTH_20:
  40                                 if (priv->card_8192_version == VERSION_819xU_A
  41                                         || priv->card_8192_version
  42                                         == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
  43                                         rtl8192_phy_SetRFReg(dev,
  44                                                 (RF90_RADIO_PATH_E)eRFPath,
  45                                                 0x0b, bMask12Bits, 0x100); /* phy para:1ba */
  46                                         rtl8192_phy_SetRFReg(dev,
  47                                                 (RF90_RADIO_PATH_E)eRFPath,
  48                                                 0x2c, bMask12Bits, 0x3d7);
  49                                         rtl8192_phy_SetRFReg(dev,
  50                                                 (RF90_RADIO_PATH_E)eRFPath,
  51                                                 0x0e, bMask12Bits, 0x021);
  52                                         rtl8192_phy_SetRFReg(dev,
  53                                                 (RF90_RADIO_PATH_E)eRFPath,
  54                                                 0x14, bMask12Bits, 0x5ab);
  55                                 } else {
  56                                         RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  57                                         }
  58                                 break;
  59                 case HT_CHANNEL_WIDTH_20_40:
  60                                 if (priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
  61                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */
  62                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
  63                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
  64
  65                                         if (priv->chan == 3 || priv->chan == 9)
  66                                                 /* I need to set priv->chan whenever current channel changes */
  67                                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
  68                                         else
  69                                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
  70                                 } else {
  71                                         RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  72                                         }
  73                                 break;
  74                 default:
  75                                 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth);
  76                                 break;
  77
  78                 }
  79         }
  80 }
  81 /*--------------------------------------------------------------------------
  82  * Overview:    Interface to config 8256
  83  * Input:       struct net_device*      dev
  84  * Output:      NONE
  85  * Return:      NONE
  86  *--------------------------------------------------------------------------
  87  */
  88 void PHY_RF8256_Config(struct net_device *dev)
  89 {
  90         struct r8192_priv *priv = ieee80211_priv(dev);
  91         /* Initialize general global value
  92          *
  93          * TODO: Extend RF_PATH_C and RF_PATH_D in the future
  94          */
  95         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
  96         /* Config BB and RF */
  97         phy_RF8256_Config_ParaFile(dev);
  98 }
  99 /*--------------------------------------------------------------------------
 100  * Overview:    Interface to config 8256
 101  * Input:       struct net_device*      dev
 102  * Output:      NONE
 103  * Return:      NONE
 104  *--------------------------------------------------------------------------
 105  */
 106 void phy_RF8256_Config_ParaFile(struct net_device *dev)
 107 {
 108         u32     u4RegValue = 0;
 109         u8      eRFPath;
 110         BB_REGISTER_DEFINITION_T        *pPhyReg;
 111         struct r8192_priv *priv = ieee80211_priv(dev);
 112         u32     RegOffSetToBeCheck = 0x3;
 113         u32     RegValueToBeCheck = 0x7f1;
 114         u32     RF3_Final_Value = 0;
 115         u8      ConstRetryTimes = 5, RetryTimes = 5;
 116         u8 ret = 0;
 117         /* Initialize RF */
 118         for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
 119                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 120                         continue;
 121
 122                 pPhyReg = &priv->PHYRegDef[eRFPath];
 123
 124                 /* Joseph test for shorten RF config
 125                  * pHalData->RfReg0Value[eRFPath] =  rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
 126                  * ----Store original RFENV control type
 127                  */
 128                 switch (eRFPath) {
 129                 case RF90_PATH_A:
 130                 case RF90_PATH_C:
 131                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
 132                         break;
 133                 case RF90_PATH_B:
 134                 case RF90_PATH_D:
 135                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 136                         break;
 137                 }
 138
 139                 /*----Set RF_ENV enable----*/
 140                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 141
 142                 /*----Set RF_ENV output high----*/
 143                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 144
 145                 /* Set bit number of Address and Data for RF register */
 146                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
 147                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
 148
 149                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
 150
 151                 /* Check RF block (for FPGA platform only)----
 152                  * TODO: this function should be removed on ASIC , Emily 2007.2.2
 153                  */
 154                 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) {
 155                         RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
 156                         goto phy_RF8256_Config_ParaFile_Fail;
 157                 }
 158
 159                 RetryTimes = ConstRetryTimes;
 160                 RF3_Final_Value = 0;
 161                 /*----Initialize RF fom connfiguration file----*/
 162                 switch (eRFPath) {
 163                 case RF90_PATH_A:
 164                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 165                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 166                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 167                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 168                                 RetryTimes--;
 169                         }
 170                         break;
 171                 case RF90_PATH_B:
 172                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 173                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 174                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 175                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 176                                 RetryTimes--;
 177                         }
 178                         break;
 179                 case RF90_PATH_C:
 180                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 181                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 182                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 183                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 184                                 RetryTimes--;
 185                         }
 186                         break;
 187                 case RF90_PATH_D:
 188                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 189                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 190                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 191                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 192                                 RetryTimes--;
 193                         }
 194                         break;
 195                 }
 196
 197                 /*----Restore RFENV control type----*/
 198                 switch (eRFPath) {
 199                 case RF90_PATH_A:
 200                 case RF90_PATH_C:
 201                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 202                         break;
 203                 case RF90_PATH_B:
 204                 case RF90_PATH_D:
 205                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 206                         break;
 207                 }
 208
 209                 if (ret) {
 210                         RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
 211                         goto phy_RF8256_Config_ParaFile_Fail;
 212                 }
 213
 214         }
 215
 216         RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
 217         return;
 218
 219 phy_RF8256_Config_ParaFile_Fail:
 220         RT_TRACE(COMP_ERR, "PHY Initialization failed\n");
 221 }
 222
 223
 224 void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
 225 {
 226         u32     TxAGC = 0;
 227         struct r8192_priv *priv = ieee80211_priv(dev);
 228         TxAGC = powerlevel;
 229
 230         if (priv->bDynamicTxLowPower) {
 231                 if (priv->CustomerID == RT_CID_819x_Netcore)
 232                         TxAGC = 0x22;
 233                 else
 234                         TxAGC += priv->CckPwEnl;
 235         }
 236
 237         if (TxAGC > 0x24)
 238                 TxAGC = 0x24;
 239         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 240 }
 241
 242
 243 void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
 244 {
 245         struct r8192_priv *priv = ieee80211_priv(dev);
 246         /* Joseph TxPower for 8192 testing */
 247         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 248         u8 index = 0;
 249         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 250         u8 byte0, byte1, byte2, byte3;
 251
 252         powerBase0 = powerlevel + priv->TxPowerDiff;    /* OFDM rates */
 253         powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
 254         powerBase1 = powerlevel;                                                        /* MCS rates */
 255         powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
 256
 257         for (index = 0; index < 6; index++) {
 258                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2)?powerBase0:powerBase1);
 259                 byte0 = (u8)(writeVal & 0x7f);
 260                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 261                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 262                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 263
 264                 if (byte0 > 0x24)
 265                         /* Max power index = 0x24 */
 266                         byte0 = 0x24;
 267                 if (byte1 > 0x24)
 268                         byte1 = 0x24;
 269                 if (byte2 > 0x24)
 270                         byte2 = 0x24;
 271                 if (byte3 > 0x24)
 272                         byte3 = 0x24;
 273
 274                 /* for tx power track */
 275                 if (index == 3) {
 276                         writeVal_tmp = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
 277                         priv->Pwr_Track = writeVal_tmp;
 278                 }
 279
 280                 if (priv->bDynamicTxHighPower) {
 281                         /*Add by Jacken 2008/03/06
 282                          *Emily, 20080613. Set low tx power for both MCS and legacy OFDM
 283                          */
 284                         writeVal = 0x03030303;
 285                 } else {
 286                         writeVal = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
 287                         }
 288                         rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 289         }
 290         return;
 291
 292 }