drivers/staging/rtl8192u/r8190_rtl8256.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This is part of the rtl8192 driver
   4  *
   5  * This files contains programming code for the rtl8256
   6  * radio frontend.
   7  *
   8  * *Many* thanks to Realtek Corp. for their great support!
   9  */
  10
  11 #include "r8192U.h"
  12 #include "r8192U_hw.h"
  13 #include "r819xU_phyreg.h"
  14 #include "r819xU_phy.h"
  15 #include "r8190_rtl8256.h"
  16
  17 /*
  18  * Forward declaration of local functions
  19  */
  20 static void phy_rf8256_config_para_file(struct net_device *dev);
  21
  22 /*--------------------------------------------------------------------------
  23  * Overview:    set RF band width (20M or 40M)
  24  * Input:       struct net_device*      dev
  25  *              WIRELESS_BANDWIDTH_E    Bandwidth       //20M or 40M
  26  * Output:      NONE
  27  * Return:      NONE
  28  * Note:        8226 support both 20M  and 40 MHz
  29  *--------------------------------------------------------------------------
  30  */
  31 void phy_set_rf8256_bandwidth(struct net_device *dev, enum ht_channel_width Bandwidth)
  32 {
  33         u8      eRFPath;
  34         struct r8192_priv *priv = ieee80211_priv(dev);
  35
  36         /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath;
  37          *  eRFPath++)
  38          */
  39         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
  40                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  41                         continue;
  42
  43                 switch (Bandwidth) {
  44                 case HT_CHANNEL_WIDTH_20:
  45                                 if (priv->card_8192_version == VERSION_819XU_A ||
  46                                         priv->card_8192_version ==
  47                                         VERSION_819XU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
  48                                         rtl8192_phy_SetRFReg(dev,
  49                                                 (enum rf90_radio_path_e)eRFPath,
  50                                                 0x0b, bMask12Bits, 0x100); /* phy para:1ba */
  51                                         rtl8192_phy_SetRFReg(dev,
  52                                                 (enum rf90_radio_path_e)eRFPath,
  53                                                 0x2c, bMask12Bits, 0x3d7);
  54                                         rtl8192_phy_SetRFReg(dev,
  55                                                 (enum rf90_radio_path_e)eRFPath,
  56                                                 0x0e, bMask12Bits, 0x021);
  57                                         rtl8192_phy_SetRFReg(dev,
  58                                                 (enum rf90_radio_path_e)eRFPath,
  59                                                 0x14, bMask12Bits, 0x5ab);
  60                                 } else {
  61                                         RT_TRACE(COMP_ERR, "phy_set_rf8256_bandwidth(): unknown hardware version\n");
  62                                         }
  63                                 break;
  64                 case HT_CHANNEL_WIDTH_20_40:
  65                                 if (priv->card_8192_version == VERSION_819XU_A || priv->card_8192_version == VERSION_819XU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
  66                                         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */
  67                                         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x2c, bMask12Bits, 0x3df);
  68                                         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0e, bMask12Bits, 0x0a1);
  69
  70                                         if (priv->chan == 3 || priv->chan == 9)
  71                                                 /* I need to set priv->chan whenever current channel changes */
  72                                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x14, bMask12Bits, 0x59b);
  73                                         else
  74                                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x14, bMask12Bits, 0x5ab);
  75                                 } else {
  76                                         RT_TRACE(COMP_ERR, "phy_set_rf8256_bandwidth(): unknown hardware version\n");
  77                                         }
  78                                 break;
  79                 default:
  80                                 RT_TRACE(COMP_ERR, "phy_set_rf8256_bandwidth(): unknown Bandwidth: %#X\n", Bandwidth);
  81                                 break;
  82                 }
  83         }
  84 }
  85
  86 /*--------------------------------------------------------------------------
  87  * Overview:    Interface to config 8256
  88  * Input:       struct net_device*      dev
  89  * Output:      NONE
  90  * Return:      NONE
  91  *--------------------------------------------------------------------------
  92  */
  93 void phy_rf8256_config(struct net_device *dev)
  94 {
  95         struct r8192_priv *priv = ieee80211_priv(dev);
  96         /* Initialize general global value
  97          *
  98          * TODO: Extend RF_PATH_C and RF_PATH_D in the future
  99          */
 100         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
 101         /* Config BB and RF */
 102         phy_rf8256_config_para_file(dev);
 103 }
 104
 105 /*--------------------------------------------------------------------------
 106  * Overview:    Interface to config 8256
 107  * Input:       struct net_device*      dev
 108  * Output:      NONE
 109  * Return:      NONE
 110  *--------------------------------------------------------------------------
 111  */
 112 static void phy_rf8256_config_para_file(struct net_device *dev)
 113 {
 114         u32     u4RegValue = 0;
 115         u8      eRFPath;
 116         BB_REGISTER_DEFINITION_T        *pPhyReg;
 117         struct r8192_priv *priv = ieee80211_priv(dev);
 118         u32     RegOffSetToBeCheck = 0x3;
 119         u32     RegValueToBeCheck = 0x7f1;
 120         u32     RF3_Final_Value = 0;
 121         u8      ConstRetryTimes = 5, RetryTimes = 5;
 122         u8 ret = 0;
 123         /* Initialize RF */
 124         for (eRFPath = (enum rf90_radio_path_e)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
 125                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 126                         continue;
 127
 128                 pPhyReg = &priv->PHYRegDef[eRFPath];
 129
 130                 /* Joseph test for shorten RF config
 131                  * pHalData->RfReg0Value[eRFPath] =  rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, rGlobalCtrl, bMaskDWord);
 132                  * ----Store original RFENV control type
 133                  */
 134                 switch (eRFPath) {
 135                 case RF90_PATH_A:
 136                 case RF90_PATH_C:
 137                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
 138                         break;
 139                 case RF90_PATH_B:
 140                 case RF90_PATH_D:
 141                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV << 16);
 142                         break;
 143                 }
 144
 145                 /*----Set RF_ENV enable----*/
 146                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
 147
 148                 /*----Set RF_ENV output high----*/
 149                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 150
 151                 /* Set bit number of Address and Data for RF register */
 152                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
 153                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
 154
 155                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0, bMask12Bits, 0xbf);
 156
 157                 /* Check RF block (for FPGA platform only)----
 158                  * TODO: this function should be removed on ASIC , Emily 2007.2.2
 159                  */
 160                 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path_e)eRFPath)) {
 161                         RT_TRACE(COMP_ERR, "phy_rf8256_config():Check Radio[%d] Fail!!\n", eRFPath);
 162                         goto phy_RF8256_Config_ParaFile_Fail;
 163                 }
 164
 165                 RetryTimes = ConstRetryTimes;
 166                 RF3_Final_Value = 0;
 167                 /*----Initialize RF fom connfiguration file----*/
 168                 switch (eRFPath) {
 169                 case RF90_PATH_A:
 170                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 171                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
 172                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 173                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 174                                 RetryTimes--;
 175                         }
 176                         break;
 177                 case RF90_PATH_B:
 178                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 179                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
 180                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 181                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 182                                 RetryTimes--;
 183                         }
 184                         break;
 185                 case RF90_PATH_C:
 186                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 187                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
 188                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 189                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 190                                 RetryTimes--;
 191                         }
 192                         break;
 193                 case RF90_PATH_D:
 194                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 195                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
 196                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 197                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 198                                 RetryTimes--;
 199                         }
 200                         break;
 201                 }
 202
 203                 /*----Restore RFENV control type----*/
 204                 switch (eRFPath) {
 205                 case RF90_PATH_A:
 206                 case RF90_PATH_C:
 207                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 208                         break;
 209                 case RF90_PATH_B:
 210                 case RF90_PATH_D:
 211                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
 212                         break;
 213                 }
 214
 215                 if (ret) {
 216                         RT_TRACE(COMP_ERR, "phy_rf8256_config_para_file():Radio[%d] Fail!!", eRFPath);
 217                         goto phy_RF8256_Config_ParaFile_Fail;
 218                 }
 219         }
 220
 221         RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
 222         return;
 223
 224 phy_RF8256_Config_ParaFile_Fail:
 225         RT_TRACE(COMP_ERR, "PHY Initialization failed\n");
 226 }
 227
 228 void phy_set_rf8256_cck_tx_power(struct net_device *dev, u8 powerlevel)
 229 {
 230         u32     TxAGC = 0;
 231         struct r8192_priv *priv = ieee80211_priv(dev);
 232
 233         TxAGC = powerlevel;
 234
 235         if (priv->bDynamicTxLowPower) {
 236                 if (priv->CustomerID == RT_CID_819x_Netcore)
 237                         TxAGC = 0x22;
 238                 else
 239                         TxAGC += priv->CckPwEnl;
 240         }
 241
 242         if (TxAGC > 0x24)
 243                 TxAGC = 0x24;
 244         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 245 }
 246
 247 void phy_set_rf8256_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
 248 {
 249         struct r8192_priv *priv = ieee80211_priv(dev);
 250         /* Joseph TxPower for 8192 testing */
 251         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 252         u8 index = 0;
 253         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 254         u8 byte0, byte1, byte2, byte3;
 255
 256         powerBase0 = powerlevel + priv->TxPowerDiff;    /* OFDM rates */
 257         powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0;
 258         powerBase1 = powerlevel;                                                        /* MCS rates */
 259         powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
 260
 261         for (index = 0; index < 6; index++) {
 262                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2) ? powerBase0 : powerBase1);
 263                 byte0 = (u8)(writeVal & 0x7f);
 264                 byte1 = (u8)((writeVal & 0x7f00) >> 8);
 265                 byte2 = (u8)((writeVal & 0x7f0000) >> 16);
 266                 byte3 = (u8)((writeVal & 0x7f000000) >> 24);
 267
 268                 if (byte0 > 0x24)
 269                         /* Max power index = 0x24 */
 270                         byte0 = 0x24;
 271                 if (byte1 > 0x24)
 272                         byte1 = 0x24;
 273                 if (byte2 > 0x24)
 274                         byte2 = 0x24;
 275                 if (byte3 > 0x24)
 276                         byte3 = 0x24;
 277
 278                 /* for tx power track */
 279                 if (index == 3) {
 280                         writeVal_tmp = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
 281                         priv->Pwr_Track = writeVal_tmp;
 282                 }
 283
 284                 if (priv->bDynamicTxHighPower) {
 285                         /*Add by Jacken 2008/03/06
 286                          *Emily, 20080613. Set low tx power for both MCS and legacy OFDM
 287                          */
 288                         writeVal = 0x03030303;
 289                 } else {
 290                         writeVal = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
 291                 }
 292                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 293         }
 294         return;
 295 }