drivers/staging/rtl8188eu/include/rtl8188e_hal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #ifndef __RTL8188E_HAL_H__
  16 #define __RTL8188E_HAL_H__
  17
  18
  19 /* include HAL Related header after HAL Related compiling flags */
  20 #include "rtl8188e_spec.h"
  21 #include "Hal8188EPhyReg.h"
  22 #include "Hal8188EPhyCfg.h"
  23 #include "rtl8188e_dm.h"
  24 #include "rtl8188e_recv.h"
  25 #include "rtl8188e_xmit.h"
  26 #include "rtl8188e_cmd.h"
  27 #include "pwrseq.h"
  28 #include "rtw_efuse.h"
  29 #include "rtw_sreset.h"
  30 #include "odm_precomp.h"
  31
  32 /*  Fw Array */
  33 #define Rtl8188E_FwImageArray           Rtl8188EFwImgArray
  34 #define Rtl8188E_FWImgArrayLength       Rtl8188EFWImgArrayLength
  35
  36 #define RTL8188E_FW_UMC_IMG                     "/*(DEBLOBBED)*/"
  37 #define RTL8188E_PHY_REG                        "rtl8188E\\PHY_REG_1T.txt"
  38 #define RTL8188E_PHY_RADIO_A                    "rtl8188E\\radio_a_1T.txt"
  39 #define RTL8188E_PHY_RADIO_B                    "rtl8188E\\radio_b_1T.txt"
  40 #define RTL8188E_AGC_TAB                        "rtl8188E\\AGC_TAB_1T.txt"
  41 #define RTL8188E_PHY_MACREG                     "rtl8188E\\MAC_REG.txt"
  42 #define RTL8188E_PHY_REG_PG                     "rtl8188E\\PHY_REG_PG.txt"
  43 #define RTL8188E_PHY_REG_MP                     "rtl8188E\\PHY_REG_MP.txt"
  44
  45 /*              RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  46 #define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  47 #define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  48 #define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  49 #define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  50 #define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  51 #define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  52 #define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  53 #define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  54 #define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  55
  56 #define DRVINFO_SZ      4 /*  unit is 8bytes */
  57 #define PageNum_128(_Len)       (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
  58
  59 /*  download firmware related data structure */
  60 #define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  61 #define FW_8188E_START_ADDRESS          0x1000
  62 #define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  63
  64 #define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  65
  66 #define IS_FW_HEADER_EXIST(_pFwHdr)                             \
  67         ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 ||  \
  68         (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 ||   \
  69         (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 ||   \
  70         (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0)
  71
  72 #define DRIVER_EARLY_INT_TIME           0x05
  73 #define BCN_DMA_ATIME_INT_TIME          0x02
  74
  75 enum usb_rx_agg_mode {
  76         USB_RX_AGG_DISABLE,
  77         USB_RX_AGG_DMA,
  78         USB_RX_AGG_USB,
  79         USB_RX_AGG_MIX
  80 };
  81
  82 #define MAX_RX_DMA_BUFFER_SIZE_88E                              \
  83       0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
  84               * WOLPattern(16*24)) */
  85
  86 #define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
  87
  88
  89 /*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
  90 #define MAX_TX_QUEUE                    9
  91
  92 #define TX_SELE_HQ                      BIT(0)          /*  High Queue */
  93 #define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
  94 #define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
  95
  96 /*  Note: We will divide number of page equally for each queue other
  97  *  than public queue! */
  98 /*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
  99 /*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
 100 /*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
 101  *  null-data */
 102
 103 #define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
 104
 105 #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
 106
 107 /* Note: For Normal Chip Setting ,modify later */
 108 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 109         TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 110 #define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 111         (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 112
 113 /*      Chip specific */
 114 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 115 #define CHIP_BONDING_92C_1T2R   0x1
 116 #define CHIP_BONDING_88C_USB_MCARD      0x2
 117 #define CHIP_BONDING_88C_USB_HP 0x1
 118 #include "HalVerDef.h"
 119 #include "hal_com.h"
 120
 121 /*      Channel Plan */
 122 enum ChannelPlan {
 123         CHPL_FCC        = 0,
 124         CHPL_IC         = 1,
 125         CHPL_ETSI       = 2,
 126         CHPL_SPA        = 3,
 127         CHPL_FRANCE     = 4,
 128         CHPL_MKK        = 5,
 129         CHPL_MKK1       = 6,
 130         CHPL_ISRAEL     = 7,
 131         CHPL_TELEC      = 8,
 132         CHPL_GLOBAL     = 9,
 133         CHPL_WORLD      = 10,
 134 };
 135
 136 struct txpowerinfo24g {
 137         u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 138         u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 139         /* If only one tx, only BW20 and OFDM are used. */
 140         s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 141         s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 142         s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 143         s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 144 };
 145
 146 #define EFUSE_REAL_CONTENT_LEN          512
 147 #define EFUSE_MAX_SECTION               16
 148 #define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 149 #define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 150 /*  To prevent out of boundary programming case, */
 151 /*  leave 1byte and program full section */
 152 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 153 /*  For worst case: */
 154 /*  | 1byte|----8bytes----|1byte|--5bytes--| */
 155 /*  |         |            Reserved(14bytes)          | */
 156
 157 /*  PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
 158 #define EFUSE_OOB_PROTECT_BYTES                 15
 159
 160 #define         HWSET_MAX_SIZE_88E              512
 161
 162 #define         EFUSE_REAL_CONTENT_LEN_88E      256
 163 #define         EFUSE_MAP_LEN_88E               512
 164 #define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 165 #define         EFUSE_MAX_SECTION_88E           64
 166 #define         EFUSE_MAX_WORD_UNIT_88E         4
 167 #define         EFUSE_IC_ID_OFFSET_88E          506
 168 #define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 169         (addr < EFUSE_REAL_CONTENT_LEN_88E)
 170 /*  To prevent out of boundary programming case, leave 1byte and program
 171  *  full section */
 172 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 173 /*  For worst case: */
 174 /*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 175 /*  PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
 176 #define         EFUSE_OOB_PROTECT_BYTES_88E     18
 177 #define         EFUSE_PROTECT_BYTES_BANK_88E    16
 178
 179 /*                      EFUSE for BT definition */
 180 #define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 181 #define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 182 #define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 183
 184 #define EFUSE_PROTECT_BYTES_BANK        16
 185
 186 struct hal_data_8188e {
 187         struct HAL_VERSION      VersionID;
 188         u16     CustomerID;
 189         u16     FirmwareVersion;
 190         u16     FirmwareVersionRev;
 191         u16     FirmwareSubVersion;
 192         u16     FirmwareSignature;
 193         u8      PGMaxGroup;
 194         /* current WIFI_PHY values */
 195         u32     ReceiveConfig;
 196         enum wireless_mode CurrentWirelessMode;
 197         enum ht_channel_width CurrentChannelBW;
 198         u8      CurrentChannel;
 199         u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 200
 201         u16     BasicRateSet;
 202
 203         u8      BoardType;
 204
 205         /*  EEPROM setting. */
 206         u16     EEPROMVID;
 207         u16     EEPROMPID;
 208         u16     EEPROMSVID;
 209         u16     EEPROMSDID;
 210         u8      EEPROMCustomerID;
 211         u8      EEPROMSubCustomerID;
 212         u8      EEPROMVersion;
 213         u8      EEPROMRegulatory;
 214
 215         u8      bTXPowerDataReadFromEEPORM;
 216         u8      EEPROMThermalMeter;
 217         u8      bAPKThermalMeterIgnore;
 218
 219         bool    EepromOrEfuse;
 220         /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
 221         u8      EfuseMap[2][HWSET_MAX_SIZE_512];
 222         u8      EfuseUsedPercentage;
 223         struct efuse_hal        EfuseHal;
 224
 225         u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 226         u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 227         /* If only one tx, only BW20 and OFDM are used. */
 228         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 229         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 230         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 231         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 232
 233         u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 234         /*  For HT 40MHZ pwr */
 235         u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 236         /*  For HT 40MHZ pwr */
 237         u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 238         /*  HT 20<->40 Pwr diff */
 239         u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 240         /*  For HT<->legacy pwr diff */
 241         u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 242         /*  For power group */
 243         u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 244         u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 245
 246         u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 247         /*  The current Tx Power Level */
 248         u8      CurrentCckTxPwrIdx;
 249         u8      CurrentOfdm24GTxPwrIdx;
 250         u8      CurrentBW2024GTxPwrIdx;
 251         u8      CurrentBW4024GTxPwrIdx;
 252
 253
 254         /*  Read/write are allow for following hardware information variables */
 255         u8      framesync;
 256         u32     framesyncC34;
 257         u8      framesyncMonitor;
 258         u8      DefaultInitialGain[4];
 259         u8      pwrGroupCnt;
 260         u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 261         u32     CCKTxPowerLevelOriginalOffset;
 262
 263         u8      CrystalCap;
 264
 265         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 266
 267         struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 268
 269         u32     RfRegChnlVal[2];
 270
 271         /* RDG enable */
 272         bool     bRDGEnable;
 273
 274         /* for host message to fw */
 275         u8      LastHMEBoxNum;
 276
 277         u8      RegTxPause;
 278         /*  Beacon function related global variable. */
 279         u32     RegBcnCtrlVal;
 280         u8      RegFwHwTxQCtrl;
 281         u8      RegReg542;
 282         u8      RegCR_1;
 283
 284         struct dm_priv  dmpriv;
 285         struct odm_dm_struct odmpriv;
 286         struct sreset_priv srestpriv;
 287
 288         u8      CurAntenna;
 289         u8      AntDivCfg;
 290         u8      TRxAntDivType;
 291
 292
 293         u8      bDumpRxPkt;/* for debug */
 294         u8      bDumpTxPkt;/* for debug */
 295         u8      FwRsvdPageStartOffset; /* Reserve page start offset except
 296                                         *  beacon in TxQ. */
 297
 298         /*  2010/08/09 MH Add CU power down mode. */
 299         bool            pwrdown;
 300
 301         /*  Add for dual MAC  0--Mac0 1--Mac1 */
 302         u32     interfaceIndex;
 303
 304         u8      OutEpQueueSel;
 305         u8      OutEpNumber;
 306
 307         u16     EfuseUsedBytes;
 308
 309         /*  Auto FSM to Turn On, include clock, isolation, power control
 310          *  for MAC only */
 311         u8      bMacPwrCtrlOn;
 312
 313         u32     UsbBulkOutSize;
 314
 315         /*  Interrupt relatd register information. */
 316         u32     IntArray[3];/* HISR0,HISR1,HSISR */
 317         u32     IntrMask[3];
 318         u8      C2hArray[16];
 319         u8      UsbTxAggMode;
 320         u8      UsbTxAggDescNum;
 321         u16     HwRxPageSize;           /*  Hardware setting */
 322         u32     MaxUsbRxAggBlock;
 323
 324         enum usb_rx_agg_mode UsbRxAggMode;
 325         u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 326                                          * 512-byte in high speed and 64-byte
 327                                          * in full speed */
 328         u8      UsbRxAggBlockTimeout;
 329         u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 330         u8      UsbRxAggPageTimeout;
 331 };
 332
 333 /*  rtl8188e_hal_init.c */
 334 void _8051Reset88E(struct adapter *padapter);
 335 void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 336
 337
 338 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 339
 340 /*  EFuse */
 341 void Hal_InitPGData88E(struct adapter *padapter);
 342 void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 343 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 344                             bool AutoLoadFail);
 345
 346 void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 347                                 bool AutoLoadFail);
 348 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 349                                  bool AutoLoadFail);
 350 void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 351                                  bool AutoLoadFail);
 352 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
 353                                  bool AutoLoadFail);
 354 void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
 355                               bool AutoloadFail);
 356 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 357                               bool AutoLoadFail);
 358 void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 359                                 bool AutoLoadFail);
 360 void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 361                                 bool AutoLoadFail);
 362
 363 /*  register */
 364
 365 void rtl8188e_start_thread(struct adapter *padapter);
 366 void rtl8188e_stop_thread(struct adapter *padapter);
 367
 368 s32 iol_execute(struct adapter *padapter, u8 control);
 369 void iol_mode_enable(struct adapter *padapter, u8 enable);
 370 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 371 void rtw_cancel_all_timer(struct adapter *padapter);
 372
 373 #endif /* __RTL8188E_HAL_H__ */